4 * Copyright Red Hat, Inc. 2013-2014
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
10 * This work is licensed under the terms of the GNU GPL, version 2.
11 * See the COPYING file in the top-level directory.
14 #ifndef HW_VIRTIO_GPU_H
15 #define HW_VIRTIO_GPU_H
17 #include "qemu/queue.h"
18 #include "ui/qemu-pixman.h"
19 #include "ui/console.h"
20 #include "hw/virtio/virtio.h"
22 #include "sysemu/vhost-user-backend.h"
24 #include "standard-headers/linux/virtio_gpu.h"
25 #include "standard-headers/linux/virtio_ids.h"
26 #include "qom/object.h"
28 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
29 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
32 #define TYPE_VIRTIO_GPU "virtio-gpu-device"
33 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU)
35 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device"
36 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL)
38 #define TYPE_VHOST_USER_GPU "vhost-user-gpu"
39 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
41 struct virtio_gpu_simple_resource {
49 uint32_t scanout_bitmask;
50 pixman_image_t *image;
61 QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
64 struct virtio_gpu_framebuffer {
65 pixman_format_code_t format;
67 uint32_t width, height;
72 struct virtio_gpu_scanout {
75 uint32_t width, height;
79 struct virtio_gpu_update_cursor cursor;
80 QEMUCursor *current_cursor;
83 struct virtio_gpu_requested_state {
84 uint16_t width_mm, height_mm;
85 uint32_t width, height;
86 uint32_t refresh_rate;
90 enum virtio_gpu_base_conf_flags {
91 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
92 VIRTIO_GPU_FLAG_STATS_ENABLED,
93 VIRTIO_GPU_FLAG_EDID_ENABLED,
94 VIRTIO_GPU_FLAG_DMABUF_ENABLED,
95 VIRTIO_GPU_FLAG_BLOB_ENABLED,
96 VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED,
99 #define virtio_gpu_virgl_enabled(_cfg) \
100 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
101 #define virtio_gpu_stats_enabled(_cfg) \
102 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
103 #define virtio_gpu_edid_enabled(_cfg) \
104 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
105 #define virtio_gpu_dmabuf_enabled(_cfg) \
106 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED))
107 #define virtio_gpu_blob_enabled(_cfg) \
108 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED))
109 #define virtio_gpu_context_init_enabled(_cfg) \
110 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED))
111 #define virtio_gpu_hostmem_enabled(_cfg) \
114 struct virtio_gpu_base_conf {
115 uint32_t max_outputs;
122 struct virtio_gpu_ctrl_command {
123 VirtQueueElement elem;
125 struct virtio_gpu_ctrl_hdr cmd_hdr;
128 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
131 struct VirtIOGPUBase {
132 VirtIODevice parent_obj;
134 Error *migration_blocker;
136 struct virtio_gpu_base_conf conf;
137 struct virtio_gpu_config virtio_config;
138 const GraphicHwOps *hw_ops;
140 int renderer_blocked;
143 MemoryRegion hostmem;
145 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
147 int enabled_output_bitmask;
148 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
151 struct VirtIOGPUBaseClass {
152 VirtioDeviceClass parent;
154 void (*gl_flushed)(VirtIOGPUBase *g);
157 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \
158 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \
159 DEFINE_PROP_BIT("edid", _state, _conf.flags, \
160 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
161 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1280), \
162 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 800)
164 typedef struct VGPUDMABuf {
167 QTAILQ_ENTRY(VGPUDMABuf) next;
171 VirtIOGPUBase parent_obj;
173 uint64_t conf_max_hostmem;
176 VirtQueue *cursor_vq;
184 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
185 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
186 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
190 bool processing_cmdq;
191 QEMUTimer *fence_poll;
192 QEMUTimer *print_stats;
196 uint32_t max_inflight;
203 QTAILQ_HEAD(, VGPUDMABuf) bufs;
204 VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS];
208 struct VirtIOGPUClass {
209 VirtIOGPUBaseClass parent;
211 void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq);
212 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
213 void (*update_cursor_data)(VirtIOGPU *g,
214 struct virtio_gpu_scanout *s,
215 uint32_t resource_id);
219 struct VirtIOGPU parent_obj;
221 bool renderer_inited;
225 struct VhostUserGPU {
226 VirtIOGPUBase parent_obj;
228 VhostUserBackend *vhost;
229 int vhost_gpu_fd; /* closed by the chardev */
230 CharBackend vhost_chr;
231 QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
232 bool backend_blocked;
235 #define VIRTIO_GPU_FILL_CMD(out) do { \
237 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
238 &out, sizeof(out)); \
239 if (s != sizeof(out)) { \
240 qemu_log_mask(LOG_GUEST_ERROR, \
241 "%s: command size incorrect %zu vs %zu\n", \
242 __func__, s, sizeof(out)); \
247 /* virtio-gpu-base.c */
248 bool virtio_gpu_base_device_realize(DeviceState *qdev,
249 VirtIOHandleOutput ctrl_cb,
250 VirtIOHandleOutput cursor_cb,
252 void virtio_gpu_base_device_unrealize(DeviceState *qdev);
253 void virtio_gpu_base_reset(VirtIOGPUBase *g);
254 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
255 struct virtio_gpu_resp_display_info *dpy_info);
257 void virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout,
258 struct virtio_gpu_resp_edid *edid);
260 void virtio_gpu_ctrl_response(VirtIOGPU *g,
261 struct virtio_gpu_ctrl_command *cmd,
262 struct virtio_gpu_ctrl_hdr *resp,
264 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
265 struct virtio_gpu_ctrl_command *cmd,
266 enum virtio_gpu_ctrl_type type);
267 void virtio_gpu_get_display_info(VirtIOGPU *g,
268 struct virtio_gpu_ctrl_command *cmd);
269 void virtio_gpu_get_edid(VirtIOGPU *g,
270 struct virtio_gpu_ctrl_command *cmd);
271 int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
272 uint32_t nr_entries, uint32_t offset,
273 struct virtio_gpu_ctrl_command *cmd,
274 uint64_t **addr, struct iovec **iov,
276 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
277 struct iovec *iov, uint32_t count);
278 void virtio_gpu_process_cmdq(VirtIOGPU *g);
279 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp);
280 void virtio_gpu_reset(VirtIODevice *vdev);
281 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
282 void virtio_gpu_update_cursor_data(VirtIOGPU *g,
283 struct virtio_gpu_scanout *s,
284 uint32_t resource_id);
286 /* virtio-gpu-udmabuf.c */
287 bool virtio_gpu_have_udmabuf(void);
288 void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res);
289 void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res);
290 int virtio_gpu_update_dmabuf(VirtIOGPU *g,
292 struct virtio_gpu_simple_resource *res,
293 struct virtio_gpu_framebuffer *fb,
294 struct virtio_gpu_rect *r);
296 /* virtio-gpu-3d.c */
297 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
298 struct virtio_gpu_ctrl_command *cmd);
299 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
300 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g);
301 void virtio_gpu_virgl_reset(VirtIOGPU *g);
302 int virtio_gpu_virgl_init(VirtIOGPU *g);
303 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);