include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  76 };
  77
  78 enum {
  79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
  80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_UCTX = 0x0004,
  85         MLX5_OBJ_TYPE_UMEM = 0x0005,
  86 };
  87
  88 enum {
  89         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  90         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  91         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  92         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  93         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  94         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  95         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  96         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  97         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  98         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  99         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 100         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 107         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 108         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 109         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 110         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 111         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 112         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 113         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 114         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 115         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 116         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 117         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 118         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 119         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 120         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 121         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 122         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 123         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 124         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 125         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 126         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 127         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 128         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 129         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 130         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 131         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 132         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 133         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 134         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 135         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 136         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 137         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 138         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 139         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 140         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 141         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 142         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 143         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 144         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 145         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 146         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 147         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 148         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 149         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 150         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 151         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 152         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 153         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 154         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 155         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 156         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 157         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 158         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 159         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 160         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 161         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 162         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 163         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 164         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 165         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 166         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 167         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 168         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 169         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 170         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 171         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 172         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 173         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 174         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 175         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 176         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 177         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 178         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 179         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 180         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 181         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 182         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 183         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 184         MLX5_CMD_OP_NOP                           = 0x80d,
 185         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 186         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 217         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 218         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 219         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 220         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 221         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 222         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 223         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 224         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 225         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 226         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 227         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 228         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 229         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 230         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 231         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 232         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 233         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 234         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 235         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 236         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 237         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 238         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 239         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 240         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 241         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 242         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 243         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 244         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 245         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 246         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 247         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 248         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 249         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 250         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 260         MLX5_CMD_OP_MAX
 261 };
 262
 263 struct mlx5_ifc_flow_table_fields_supported_bits {
 264         u8         outer_dmac[0x1];
 265         u8         outer_smac[0x1];
 266         u8         outer_ether_type[0x1];
 267         u8         outer_ip_version[0x1];
 268         u8         outer_first_prio[0x1];
 269         u8         outer_first_cfi[0x1];
 270         u8         outer_first_vid[0x1];
 271         u8         outer_ipv4_ttl[0x1];
 272         u8         outer_second_prio[0x1];
 273         u8         outer_second_cfi[0x1];
 274         u8         outer_second_vid[0x1];
 275         u8         reserved_at_b[0x1];
 276         u8         outer_sip[0x1];
 277         u8         outer_dip[0x1];
 278         u8         outer_frag[0x1];
 279         u8         outer_ip_protocol[0x1];
 280         u8         outer_ip_ecn[0x1];
 281         u8         outer_ip_dscp[0x1];
 282         u8         outer_udp_sport[0x1];
 283         u8         outer_udp_dport[0x1];
 284         u8         outer_tcp_sport[0x1];
 285         u8         outer_tcp_dport[0x1];
 286         u8         outer_tcp_flags[0x1];
 287         u8         outer_gre_protocol[0x1];
 288         u8         outer_gre_key[0x1];
 289         u8         outer_vxlan_vni[0x1];
 290         u8         reserved_at_1a[0x5];
 291         u8         source_eswitch_port[0x1];
 292
 293         u8         inner_dmac[0x1];
 294         u8         inner_smac[0x1];
 295         u8         inner_ether_type[0x1];
 296         u8         inner_ip_version[0x1];
 297         u8         inner_first_prio[0x1];
 298         u8         inner_first_cfi[0x1];
 299         u8         inner_first_vid[0x1];
 300         u8         reserved_at_27[0x1];
 301         u8         inner_second_prio[0x1];
 302         u8         inner_second_cfi[0x1];
 303         u8         inner_second_vid[0x1];
 304         u8         reserved_at_2b[0x1];
 305         u8         inner_sip[0x1];
 306         u8         inner_dip[0x1];
 307         u8         inner_frag[0x1];
 308         u8         inner_ip_protocol[0x1];
 309         u8         inner_ip_ecn[0x1];
 310         u8         inner_ip_dscp[0x1];
 311         u8         inner_udp_sport[0x1];
 312         u8         inner_udp_dport[0x1];
 313         u8         inner_tcp_sport[0x1];
 314         u8         inner_tcp_dport[0x1];
 315         u8         inner_tcp_flags[0x1];
 316         u8         reserved_at_37[0x9];
 317
 318         u8         reserved_at_40[0x5];
 319         u8         outer_first_mpls_over_udp[0x4];
 320         u8         outer_first_mpls_over_gre[0x4];
 321         u8         inner_first_mpls[0x4];
 322         u8         outer_first_mpls[0x4];
 323         u8         reserved_at_55[0x2];
 324         u8         outer_esp_spi[0x1];
 325         u8         reserved_at_58[0x2];
 326         u8         bth_dst_qp[0x1];
 327
 328         u8         reserved_at_5b[0x25];
 329 };
 330
 331 struct mlx5_ifc_flow_table_prop_layout_bits {
 332         u8         ft_support[0x1];
 333         u8         reserved_at_1[0x1];
 334         u8         flow_counter[0x1];
 335         u8         flow_modify_en[0x1];
 336         u8         modify_root[0x1];
 337         u8         identified_miss_table_mode[0x1];
 338         u8         flow_table_modify[0x1];
 339         u8         reformat[0x1];
 340         u8         decap[0x1];
 341         u8         reserved_at_9[0x1];
 342         u8         pop_vlan[0x1];
 343         u8         push_vlan[0x1];
 344         u8         reserved_at_c[0x1];
 345         u8         pop_vlan_2[0x1];
 346         u8         push_vlan_2[0x1];
 347         u8         reformat_and_vlan_action[0x1];
 348         u8         reserved_at_10[0x2];
 349         u8         reformat_l3_tunnel_to_l2[0x1];
 350         u8         reformat_l2_to_l3_tunnel[0x1];
 351         u8         reformat_and_modify_action[0x1];
 352         u8         reserved_at_14[0xb];
 353         u8         reserved_at_20[0x2];
 354         u8         log_max_ft_size[0x6];
 355         u8         log_max_modify_header_context[0x8];
 356         u8         max_modify_header_actions[0x8];
 357         u8         max_ft_level[0x8];
 358
 359         u8         reserved_at_40[0x20];
 360
 361         u8         reserved_at_60[0x18];
 362         u8         log_max_ft_num[0x8];
 363
 364         u8         reserved_at_80[0x18];
 365         u8         log_max_destination[0x8];
 366
 367         u8         log_max_flow_counter[0x8];
 368         u8         reserved_at_a8[0x10];
 369         u8         log_max_flow[0x8];
 370
 371         u8         reserved_at_c0[0x40];
 372
 373         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 374
 375         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 376 };
 377
 378 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 379         u8         send[0x1];
 380         u8         receive[0x1];
 381         u8         write[0x1];
 382         u8         read[0x1];
 383         u8         atomic[0x1];
 384         u8         srq_receive[0x1];
 385         u8         reserved_at_6[0x1a];
 386 };
 387
 388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 389         u8         smac_47_16[0x20];
 390
 391         u8         smac_15_0[0x10];
 392         u8         ethertype[0x10];
 393
 394         u8         dmac_47_16[0x20];
 395
 396         u8         dmac_15_0[0x10];
 397         u8         first_prio[0x3];
 398         u8         first_cfi[0x1];
 399         u8         first_vid[0xc];
 400
 401         u8         ip_protocol[0x8];
 402         u8         ip_dscp[0x6];
 403         u8         ip_ecn[0x2];
 404         u8         cvlan_tag[0x1];
 405         u8         svlan_tag[0x1];
 406         u8         frag[0x1];
 407         u8         ip_version[0x4];
 408         u8         tcp_flags[0x9];
 409
 410         u8         tcp_sport[0x10];
 411         u8         tcp_dport[0x10];
 412
 413         u8         reserved_at_c0[0x18];
 414         u8         ttl_hoplimit[0x8];
 415
 416         u8         udp_sport[0x10];
 417         u8         udp_dport[0x10];
 418
 419         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 420
 421         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 422 };
 423
 424 struct mlx5_ifc_fte_match_set_misc_bits {
 425         u8         reserved_at_0[0x8];
 426         u8         source_sqn[0x18];
 427
 428         u8         source_eswitch_owner_vhca_id[0x10];
 429         u8         source_port[0x10];
 430
 431         u8         outer_second_prio[0x3];
 432         u8         outer_second_cfi[0x1];
 433         u8         outer_second_vid[0xc];
 434         u8         inner_second_prio[0x3];
 435         u8         inner_second_cfi[0x1];
 436         u8         inner_second_vid[0xc];
 437
 438         u8         outer_second_cvlan_tag[0x1];
 439         u8         inner_second_cvlan_tag[0x1];
 440         u8         outer_second_svlan_tag[0x1];
 441         u8         inner_second_svlan_tag[0x1];
 442         u8         reserved_at_64[0xc];
 443         u8         gre_protocol[0x10];
 444
 445         u8         gre_key_h[0x18];
 446         u8         gre_key_l[0x8];
 447
 448         u8         vxlan_vni[0x18];
 449         u8         reserved_at_b8[0x8];
 450
 451         u8         reserved_at_c0[0x20];
 452
 453         u8         reserved_at_e0[0xc];
 454         u8         outer_ipv6_flow_label[0x14];
 455
 456         u8         reserved_at_100[0xc];
 457         u8         inner_ipv6_flow_label[0x14];
 458
 459         u8         reserved_at_120[0x28];
 460         u8         bth_dst_qp[0x18];
 461         u8         reserved_at_160[0x20];
 462         u8         outer_esp_spi[0x20];
 463         u8         reserved_at_1a0[0x60];
 464 };
 465
 466 struct mlx5_ifc_fte_match_mpls_bits {
 467         u8         mpls_label[0x14];
 468         u8         mpls_exp[0x3];
 469         u8         mpls_s_bos[0x1];
 470         u8         mpls_ttl[0x8];
 471 };
 472
 473 struct mlx5_ifc_fte_match_set_misc2_bits {
 474         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 475
 476         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 477
 478         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 479
 480         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 481
 482         u8         reserved_at_80[0x100];
 483
 484         u8         metadata_reg_a[0x20];
 485
 486         u8         reserved_at_1a0[0x60];
 487 };
 488
 489 struct mlx5_ifc_cmd_pas_bits {
 490         u8         pa_h[0x20];
 491
 492         u8         pa_l[0x14];
 493         u8         reserved_at_34[0xc];
 494 };
 495
 496 struct mlx5_ifc_uint64_bits {
 497         u8         hi[0x20];
 498
 499         u8         lo[0x20];
 500 };
 501
 502 enum {
 503         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 504         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 505         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 506         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 507         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 508         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 509         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 510         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 511         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 512         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 513 };
 514
 515 struct mlx5_ifc_ads_bits {
 516         u8         fl[0x1];
 517         u8         free_ar[0x1];
 518         u8         reserved_at_2[0xe];
 519         u8         pkey_index[0x10];
 520
 521         u8         reserved_at_20[0x8];
 522         u8         grh[0x1];
 523         u8         mlid[0x7];
 524         u8         rlid[0x10];
 525
 526         u8         ack_timeout[0x5];
 527         u8         reserved_at_45[0x3];
 528         u8         src_addr_index[0x8];
 529         u8         reserved_at_50[0x4];
 530         u8         stat_rate[0x4];
 531         u8         hop_limit[0x8];
 532
 533         u8         reserved_at_60[0x4];
 534         u8         tclass[0x8];
 535         u8         flow_label[0x14];
 536
 537         u8         rgid_rip[16][0x8];
 538
 539         u8         reserved_at_100[0x4];
 540         u8         f_dscp[0x1];
 541         u8         f_ecn[0x1];
 542         u8         reserved_at_106[0x1];
 543         u8         f_eth_prio[0x1];
 544         u8         ecn[0x2];
 545         u8         dscp[0x6];
 546         u8         udp_sport[0x10];
 547
 548         u8         dei_cfi[0x1];
 549         u8         eth_prio[0x3];
 550         u8         sl[0x4];
 551         u8         vhca_port_num[0x8];
 552         u8         rmac_47_32[0x10];
 553
 554         u8         rmac_31_0[0x20];
 555 };
 556
 557 struct mlx5_ifc_flow_table_nic_cap_bits {
 558         u8         nic_rx_multi_path_tirs[0x1];
 559         u8         nic_rx_multi_path_tirs_fts[0x1];
 560         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 561         u8         reserved_at_3[0x1d];
 562         u8         encap_general_header[0x1];
 563         u8         reserved_at_21[0xa];
 564         u8         log_max_packet_reformat_context[0x5];
 565         u8         reserved_at_30[0x6];
 566         u8         max_encap_header_size[0xa];
 567         u8         reserved_at_40[0x1c0];
 568
 569         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 570
 571         u8         reserved_at_400[0x200];
 572
 573         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 574
 575         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 576
 577         u8         reserved_at_a00[0x200];
 578
 579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 580
 581         u8         reserved_at_e00[0x7200];
 582 };
 583
 584 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 585         u8      reserved_at_0[0x1c];
 586         u8      fdb_multi_path_to_table[0x1];
 587         u8      reserved_at_1d[0x1e3];
 588
 589         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 590
 591         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 592
 593         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 594
 595         u8      reserved_at_800[0x7800];
 596 };
 597
 598 struct mlx5_ifc_e_switch_cap_bits {
 599         u8         vport_svlan_strip[0x1];
 600         u8         vport_cvlan_strip[0x1];
 601         u8         vport_svlan_insert[0x1];
 602         u8         vport_cvlan_insert_if_not_exist[0x1];
 603         u8         vport_cvlan_insert_overwrite[0x1];
 604         u8         reserved_at_5[0x18];
 605         u8         merged_eswitch[0x1];
 606         u8         nic_vport_node_guid_modify[0x1];
 607         u8         nic_vport_port_guid_modify[0x1];
 608
 609         u8         vxlan_encap_decap[0x1];
 610         u8         nvgre_encap_decap[0x1];
 611         u8         reserved_at_22[0x9];
 612         u8         log_max_packet_reformat_context[0x5];
 613         u8         reserved_2b[0x6];
 614         u8         max_encap_header_size[0xa];
 615
 616         u8         reserved_40[0x7c0];
 617
 618 };
 619
 620 struct mlx5_ifc_qos_cap_bits {
 621         u8         packet_pacing[0x1];
 622         u8         esw_scheduling[0x1];
 623         u8         esw_bw_share[0x1];
 624         u8         esw_rate_limit[0x1];
 625         u8         reserved_at_4[0x1];
 626         u8         packet_pacing_burst_bound[0x1];
 627         u8         packet_pacing_typical_size[0x1];
 628         u8         reserved_at_7[0x19];
 629
 630         u8         reserved_at_20[0x20];
 631
 632         u8         packet_pacing_max_rate[0x20];
 633
 634         u8         packet_pacing_min_rate[0x20];
 635
 636         u8         reserved_at_80[0x10];
 637         u8         packet_pacing_rate_table_size[0x10];
 638
 639         u8         esw_element_type[0x10];
 640         u8         esw_tsar_type[0x10];
 641
 642         u8         reserved_at_c0[0x10];
 643         u8         max_qos_para_vport[0x10];
 644
 645         u8         max_tsar_bw_share[0x20];
 646
 647         u8         reserved_at_100[0x700];
 648 };
 649
 650 struct mlx5_ifc_debug_cap_bits {
 651         u8         reserved_at_0[0x20];
 652
 653         u8         reserved_at_20[0x2];
 654         u8         stall_detect[0x1];
 655         u8         reserved_at_23[0x1d];
 656
 657         u8         reserved_at_40[0x7c0];
 658 };
 659
 660 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 661         u8         csum_cap[0x1];
 662         u8         vlan_cap[0x1];
 663         u8         lro_cap[0x1];
 664         u8         lro_psh_flag[0x1];
 665         u8         lro_time_stamp[0x1];
 666         u8         reserved_at_5[0x2];
 667         u8         wqe_vlan_insert[0x1];
 668         u8         self_lb_en_modifiable[0x1];
 669         u8         reserved_at_9[0x2];
 670         u8         max_lso_cap[0x5];
 671         u8         multi_pkt_send_wqe[0x2];
 672         u8         wqe_inline_mode[0x2];
 673         u8         rss_ind_tbl_cap[0x4];
 674         u8         reg_umr_sq[0x1];
 675         u8         scatter_fcs[0x1];
 676         u8         enhanced_multi_pkt_send_wqe[0x1];
 677         u8         tunnel_lso_const_out_ip_id[0x1];
 678         u8         reserved_at_1c[0x2];
 679         u8         tunnel_stateless_gre[0x1];
 680         u8         tunnel_stateless_vxlan[0x1];
 681
 682         u8         swp[0x1];
 683         u8         swp_csum[0x1];
 684         u8         swp_lso[0x1];
 685         u8         reserved_at_23[0xd];
 686         u8         max_vxlan_udp_ports[0x8];
 687         u8         reserved_at_38[0x6];
 688         u8         max_geneve_opt_len[0x1];
 689         u8         tunnel_stateless_geneve_rx[0x1];
 690
 691         u8         reserved_at_40[0x10];
 692         u8         lro_min_mss_size[0x10];
 693
 694         u8         reserved_at_60[0x120];
 695
 696         u8         lro_timer_supported_periods[4][0x20];
 697
 698         u8         reserved_at_200[0x600];
 699 };
 700
 701 struct mlx5_ifc_roce_cap_bits {
 702         u8         roce_apm[0x1];
 703         u8         reserved_at_1[0x1f];
 704
 705         u8         reserved_at_20[0x60];
 706
 707         u8         reserved_at_80[0xc];
 708         u8         l3_type[0x4];
 709         u8         reserved_at_90[0x8];
 710         u8         roce_version[0x8];
 711
 712         u8         reserved_at_a0[0x10];
 713         u8         r_roce_dest_udp_port[0x10];
 714
 715         u8         r_roce_max_src_udp_port[0x10];
 716         u8         r_roce_min_src_udp_port[0x10];
 717
 718         u8         reserved_at_e0[0x10];
 719         u8         roce_address_table_size[0x10];
 720
 721         u8         reserved_at_100[0x700];
 722 };
 723
 724 struct mlx5_ifc_device_mem_cap_bits {
 725         u8         memic[0x1];
 726         u8         reserved_at_1[0x1f];
 727
 728         u8         reserved_at_20[0xb];
 729         u8         log_min_memic_alloc_size[0x5];
 730         u8         reserved_at_30[0x8];
 731         u8         log_max_memic_addr_alignment[0x8];
 732
 733         u8         memic_bar_start_addr[0x40];
 734
 735         u8         memic_bar_size[0x20];
 736
 737         u8         max_memic_size[0x20];
 738
 739         u8         reserved_at_c0[0x740];
 740 };
 741
 742 enum {
 743         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 744         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 745         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 746         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 747         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 748         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 749         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 750         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 751         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 752 };
 753
 754 enum {
 755         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 756         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 757         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 758         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 759         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 760         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 761         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 762         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 763         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 764 };
 765
 766 struct mlx5_ifc_atomic_caps_bits {
 767         u8         reserved_at_0[0x40];
 768
 769         u8         atomic_req_8B_endianness_mode[0x2];
 770         u8         reserved_at_42[0x4];
 771         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 772
 773         u8         reserved_at_47[0x19];
 774
 775         u8         reserved_at_60[0x20];
 776
 777         u8         reserved_at_80[0x10];
 778         u8         atomic_operations[0x10];
 779
 780         u8         reserved_at_a0[0x10];
 781         u8         atomic_size_qp[0x10];
 782
 783         u8         reserved_at_c0[0x10];
 784         u8         atomic_size_dc[0x10];
 785
 786         u8         reserved_at_e0[0x720];
 787 };
 788
 789 struct mlx5_ifc_odp_cap_bits {
 790         u8         reserved_at_0[0x40];
 791
 792         u8         sig[0x1];
 793         u8         reserved_at_41[0x1f];
 794
 795         u8         reserved_at_60[0x20];
 796
 797         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 798
 799         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 800
 801         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 802
 803         u8         reserved_at_e0[0x720];
 804 };
 805
 806 struct mlx5_ifc_calc_op {
 807         u8        reserved_at_0[0x10];
 808         u8        reserved_at_10[0x9];
 809         u8        op_swap_endianness[0x1];
 810         u8        op_min[0x1];
 811         u8        op_xor[0x1];
 812         u8        op_or[0x1];
 813         u8        op_and[0x1];
 814         u8        op_max[0x1];
 815         u8        op_add[0x1];
 816 };
 817
 818 struct mlx5_ifc_vector_calc_cap_bits {
 819         u8         calc_matrix[0x1];
 820         u8         reserved_at_1[0x1f];
 821         u8         reserved_at_20[0x8];
 822         u8         max_vec_count[0x8];
 823         u8         reserved_at_30[0xd];
 824         u8         max_chunk_size[0x3];
 825         struct mlx5_ifc_calc_op calc0;
 826         struct mlx5_ifc_calc_op calc1;
 827         struct mlx5_ifc_calc_op calc2;
 828         struct mlx5_ifc_calc_op calc3;
 829
 830         u8         reserved_at_e0[0x720];
 831 };
 832
 833 enum {
 834         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 835         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 836         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 837         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 838 };
 839
 840 enum {
 841         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 842         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 843 };
 844
 845 enum {
 846         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 847         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 848         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 849         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 850         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 851 };
 852
 853 enum {
 854         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 855         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 856         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 857         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 858         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 859         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 860 };
 861
 862 enum {
 863         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 864         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 865 };
 866
 867 enum {
 868         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 869         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 870         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 871 };
 872
 873 enum {
 874         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 875         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 876 };
 877
 878 enum {
 879         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 880         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 881         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 882 };
 883
 884 struct mlx5_ifc_cmd_hca_cap_bits {
 885         u8         reserved_at_0[0x30];
 886         u8         vhca_id[0x10];
 887
 888         u8         reserved_at_40[0x40];
 889
 890         u8         log_max_srq_sz[0x8];
 891         u8         log_max_qp_sz[0x8];
 892         u8         reserved_at_90[0xb];
 893         u8         log_max_qp[0x5];
 894
 895         u8         reserved_at_a0[0xb];
 896         u8         log_max_srq[0x5];
 897         u8         reserved_at_b0[0x10];
 898
 899         u8         reserved_at_c0[0x8];
 900         u8         log_max_cq_sz[0x8];
 901         u8         reserved_at_d0[0xb];
 902         u8         log_max_cq[0x5];
 903
 904         u8         log_max_eq_sz[0x8];
 905         u8         reserved_at_e8[0x2];
 906         u8         log_max_mkey[0x6];
 907         u8         reserved_at_f0[0x8];
 908         u8         dump_fill_mkey[0x1];
 909         u8         reserved_at_f9[0x3];
 910         u8         log_max_eq[0x4];
 911
 912         u8         max_indirection[0x8];
 913         u8         fixed_buffer_size[0x1];
 914         u8         log_max_mrw_sz[0x7];
 915         u8         force_teardown[0x1];
 916         u8         reserved_at_111[0x1];
 917         u8         log_max_bsf_list_size[0x6];
 918         u8         umr_extended_translation_offset[0x1];
 919         u8         null_mkey[0x1];
 920         u8         log_max_klm_list_size[0x6];
 921
 922         u8         reserved_at_120[0xa];
 923         u8         log_max_ra_req_dc[0x6];
 924         u8         reserved_at_130[0xa];
 925         u8         log_max_ra_res_dc[0x6];
 926
 927         u8         reserved_at_140[0xa];
 928         u8         log_max_ra_req_qp[0x6];
 929         u8         reserved_at_150[0xa];
 930         u8         log_max_ra_res_qp[0x6];
 931
 932         u8         end_pad[0x1];
 933         u8         cc_query_allowed[0x1];
 934         u8         cc_modify_allowed[0x1];
 935         u8         start_pad[0x1];
 936         u8         cache_line_128byte[0x1];
 937         u8         reserved_at_165[0xa];
 938         u8         qcam_reg[0x1];
 939         u8         gid_table_size[0x10];
 940
 941         u8         out_of_seq_cnt[0x1];
 942         u8         vport_counters[0x1];
 943         u8         retransmission_q_counters[0x1];
 944         u8         debug[0x1];
 945         u8         modify_rq_counter_set_id[0x1];
 946         u8         rq_delay_drop[0x1];
 947         u8         max_qp_cnt[0xa];
 948         u8         pkey_table_size[0x10];
 949
 950         u8         vport_group_manager[0x1];
 951         u8         vhca_group_manager[0x1];
 952         u8         ib_virt[0x1];
 953         u8         eth_virt[0x1];
 954         u8         vnic_env_queue_counters[0x1];
 955         u8         ets[0x1];
 956         u8         nic_flow_table[0x1];
 957         u8         eswitch_manager[0x1];
 958         u8         device_memory[0x1];
 959         u8         mcam_reg[0x1];
 960         u8         pcam_reg[0x1];
 961         u8         local_ca_ack_delay[0x5];
 962         u8         port_module_event[0x1];
 963         u8         enhanced_error_q_counters[0x1];
 964         u8         ports_check[0x1];
 965         u8         reserved_at_1b3[0x1];
 966         u8         disable_link_up[0x1];
 967         u8         beacon_led[0x1];
 968         u8         port_type[0x2];
 969         u8         num_ports[0x8];
 970
 971         u8         reserved_at_1c0[0x1];
 972         u8         pps[0x1];
 973         u8         pps_modify[0x1];
 974         u8         log_max_msg[0x5];
 975         u8         reserved_at_1c8[0x4];
 976         u8         max_tc[0x4];
 977         u8         temp_warn_event[0x1];
 978         u8         dcbx[0x1];
 979         u8         general_notification_event[0x1];
 980         u8         reserved_at_1d3[0x2];
 981         u8         fpga[0x1];
 982         u8         rol_s[0x1];
 983         u8         rol_g[0x1];
 984         u8         reserved_at_1d8[0x1];
 985         u8         wol_s[0x1];
 986         u8         wol_g[0x1];
 987         u8         wol_a[0x1];
 988         u8         wol_b[0x1];
 989         u8         wol_m[0x1];
 990         u8         wol_u[0x1];
 991         u8         wol_p[0x1];
 992
 993         u8         stat_rate_support[0x10];
 994         u8         reserved_at_1f0[0xc];
 995         u8         cqe_version[0x4];
 996
 997         u8         compact_address_vector[0x1];
 998         u8         striding_rq[0x1];
 999         u8         reserved_at_202[0x1];
1000         u8         ipoib_enhanced_offloads[0x1];
1001         u8         ipoib_basic_offloads[0x1];
1002         u8         reserved_at_205[0x1];
1003         u8         repeated_block_disabled[0x1];
1004         u8         umr_modify_entity_size_disabled[0x1];
1005         u8         umr_modify_atomic_disabled[0x1];
1006         u8         umr_indirect_mkey_disabled[0x1];
1007         u8         umr_fence[0x2];
1008         u8         reserved_at_20c[0x3];
1009         u8         drain_sigerr[0x1];
1010         u8         cmdif_checksum[0x2];
1011         u8         sigerr_cqe[0x1];
1012         u8         reserved_at_213[0x1];
1013         u8         wq_signature[0x1];
1014         u8         sctr_data_cqe[0x1];
1015         u8         reserved_at_216[0x1];
1016         u8         sho[0x1];
1017         u8         tph[0x1];
1018         u8         rf[0x1];
1019         u8         dct[0x1];
1020         u8         qos[0x1];
1021         u8         eth_net_offloads[0x1];
1022         u8         roce[0x1];
1023         u8         atomic[0x1];
1024         u8         reserved_at_21f[0x1];
1025
1026         u8         cq_oi[0x1];
1027         u8         cq_resize[0x1];
1028         u8         cq_moderation[0x1];
1029         u8         reserved_at_223[0x3];
1030         u8         cq_eq_remap[0x1];
1031         u8         pg[0x1];
1032         u8         block_lb_mc[0x1];
1033         u8         reserved_at_229[0x1];
1034         u8         scqe_break_moderation[0x1];
1035         u8         cq_period_start_from_cqe[0x1];
1036         u8         cd[0x1];
1037         u8         reserved_at_22d[0x1];
1038         u8         apm[0x1];
1039         u8         vector_calc[0x1];
1040         u8         umr_ptr_rlky[0x1];
1041         u8         imaicl[0x1];
1042         u8         reserved_at_232[0x4];
1043         u8         qkv[0x1];
1044         u8         pkv[0x1];
1045         u8         set_deth_sqpn[0x1];
1046         u8         reserved_at_239[0x3];
1047         u8         xrc[0x1];
1048         u8         ud[0x1];
1049         u8         uc[0x1];
1050         u8         rc[0x1];
1051
1052         u8         uar_4k[0x1];
1053         u8         reserved_at_241[0x9];
1054         u8         uar_sz[0x6];
1055         u8         reserved_at_250[0x8];
1056         u8         log_pg_sz[0x8];
1057
1058         u8         bf[0x1];
1059         u8         driver_version[0x1];
1060         u8         pad_tx_eth_packet[0x1];
1061         u8         reserved_at_263[0x8];
1062         u8         log_bf_reg_size[0x5];
1063
1064         u8         reserved_at_270[0xb];
1065         u8         lag_master[0x1];
1066         u8         num_lag_ports[0x4];
1067
1068         u8         reserved_at_280[0x10];
1069         u8         max_wqe_sz_sq[0x10];
1070
1071         u8         reserved_at_2a0[0x10];
1072         u8         max_wqe_sz_rq[0x10];
1073
1074         u8         max_flow_counter_31_16[0x10];
1075         u8         max_wqe_sz_sq_dc[0x10];
1076
1077         u8         reserved_at_2e0[0x7];
1078         u8         max_qp_mcg[0x19];
1079
1080         u8         reserved_at_300[0x18];
1081         u8         log_max_mcg[0x8];
1082
1083         u8         reserved_at_320[0x3];
1084         u8         log_max_transport_domain[0x5];
1085         u8         reserved_at_328[0x3];
1086         u8         log_max_pd[0x5];
1087         u8         reserved_at_330[0xb];
1088         u8         log_max_xrcd[0x5];
1089
1090         u8         nic_receive_steering_discard[0x1];
1091         u8         receive_discard_vport_down[0x1];
1092         u8         transmit_discard_vport_down[0x1];
1093         u8         reserved_at_343[0x5];
1094         u8         log_max_flow_counter_bulk[0x8];
1095         u8         max_flow_counter_15_0[0x10];
1096
1097
1098         u8         reserved_at_360[0x3];
1099         u8         log_max_rq[0x5];
1100         u8         reserved_at_368[0x3];
1101         u8         log_max_sq[0x5];
1102         u8         reserved_at_370[0x3];
1103         u8         log_max_tir[0x5];
1104         u8         reserved_at_378[0x3];
1105         u8         log_max_tis[0x5];
1106
1107         u8         basic_cyclic_rcv_wqe[0x1];
1108         u8         reserved_at_381[0x2];
1109         u8         log_max_rmp[0x5];
1110         u8         reserved_at_388[0x3];
1111         u8         log_max_rqt[0x5];
1112         u8         reserved_at_390[0x3];
1113         u8         log_max_rqt_size[0x5];
1114         u8         reserved_at_398[0x3];
1115         u8         log_max_tis_per_sq[0x5];
1116
1117         u8         ext_stride_num_range[0x1];
1118         u8         reserved_at_3a1[0x2];
1119         u8         log_max_stride_sz_rq[0x5];
1120         u8         reserved_at_3a8[0x3];
1121         u8         log_min_stride_sz_rq[0x5];
1122         u8         reserved_at_3b0[0x3];
1123         u8         log_max_stride_sz_sq[0x5];
1124         u8         reserved_at_3b8[0x3];
1125         u8         log_min_stride_sz_sq[0x5];
1126
1127         u8         hairpin[0x1];
1128         u8         reserved_at_3c1[0x2];
1129         u8         log_max_hairpin_queues[0x5];
1130         u8         reserved_at_3c8[0x3];
1131         u8         log_max_hairpin_wq_data_sz[0x5];
1132         u8         reserved_at_3d0[0x3];
1133         u8         log_max_hairpin_num_packets[0x5];
1134         u8         reserved_at_3d8[0x3];
1135         u8         log_max_wq_sz[0x5];
1136
1137         u8         nic_vport_change_event[0x1];
1138         u8         disable_local_lb_uc[0x1];
1139         u8         disable_local_lb_mc[0x1];
1140         u8         log_min_hairpin_wq_data_sz[0x5];
1141         u8         reserved_at_3e8[0x3];
1142         u8         log_max_vlan_list[0x5];
1143         u8         reserved_at_3f0[0x3];
1144         u8         log_max_current_mc_list[0x5];
1145         u8         reserved_at_3f8[0x3];
1146         u8         log_max_current_uc_list[0x5];
1147
1148         u8         general_obj_types[0x40];
1149
1150         u8         reserved_at_440[0x20];
1151
1152         u8         reserved_at_460[0x10];
1153         u8         max_num_eqs[0x10];
1154
1155         u8         reserved_at_480[0x3];
1156         u8         log_max_l2_table[0x5];
1157         u8         reserved_at_488[0x8];
1158         u8         log_uar_page_sz[0x10];
1159
1160         u8         reserved_at_4a0[0x20];
1161         u8         device_frequency_mhz[0x20];
1162         u8         device_frequency_khz[0x20];
1163
1164         u8         reserved_at_500[0x20];
1165         u8         num_of_uars_per_page[0x20];
1166
1167         u8         flex_parser_protocols[0x20];
1168         u8         reserved_at_560[0x20];
1169
1170         u8         reserved_at_580[0x3c];
1171         u8         mini_cqe_resp_stride_index[0x1];
1172         u8         cqe_128_always[0x1];
1173         u8         cqe_compression_128[0x1];
1174         u8         cqe_compression[0x1];
1175
1176         u8         cqe_compression_timeout[0x10];
1177         u8         cqe_compression_max_num[0x10];
1178
1179         u8         reserved_at_5e0[0x10];
1180         u8         tag_matching[0x1];
1181         u8         rndv_offload_rc[0x1];
1182         u8         rndv_offload_dc[0x1];
1183         u8         log_tag_matching_list_sz[0x5];
1184         u8         reserved_at_5f8[0x3];
1185         u8         log_max_xrq[0x5];
1186
1187         u8         affiliate_nic_vport_criteria[0x8];
1188         u8         native_port_num[0x8];
1189         u8         num_vhca_ports[0x8];
1190         u8         reserved_at_618[0x6];
1191         u8         sw_owner_id[0x1];
1192         u8         reserved_at_61f[0x1e1];
1193 };
1194
1195 enum mlx5_flow_destination_type {
1196         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1197         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1198         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1199
1200         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1201         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1202         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1203 };
1204
1205 struct mlx5_ifc_dest_format_struct_bits {
1206         u8         destination_type[0x8];
1207         u8         destination_id[0x18];
1208         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1209         u8         reserved_at_21[0xf];
1210         u8         destination_eswitch_owner_vhca_id[0x10];
1211 };
1212
1213 struct mlx5_ifc_flow_counter_list_bits {
1214         u8         flow_counter_id[0x20];
1215
1216         u8         reserved_at_20[0x20];
1217 };
1218
1219 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1220         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1221         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1222         u8         reserved_at_0[0x40];
1223 };
1224
1225 struct mlx5_ifc_fte_match_param_bits {
1226         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1227
1228         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1229
1230         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1231
1232         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1233
1234         u8         reserved_at_800[0x800];
1235 };
1236
1237 enum {
1238         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1239         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1240         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1241         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1242         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1243 };
1244
1245 struct mlx5_ifc_rx_hash_field_select_bits {
1246         u8         l3_prot_type[0x1];
1247         u8         l4_prot_type[0x1];
1248         u8         selected_fields[0x1e];
1249 };
1250
1251 enum {
1252         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1253         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1254 };
1255
1256 enum {
1257         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1258         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1259 };
1260
1261 struct mlx5_ifc_wq_bits {
1262         u8         wq_type[0x4];
1263         u8         wq_signature[0x1];
1264         u8         end_padding_mode[0x2];
1265         u8         cd_slave[0x1];
1266         u8         reserved_at_8[0x18];
1267
1268         u8         hds_skip_first_sge[0x1];
1269         u8         log2_hds_buf_size[0x3];
1270         u8         reserved_at_24[0x7];
1271         u8         page_offset[0x5];
1272         u8         lwm[0x10];
1273
1274         u8         reserved_at_40[0x8];
1275         u8         pd[0x18];
1276
1277         u8         reserved_at_60[0x8];
1278         u8         uar_page[0x18];
1279
1280         u8         dbr_addr[0x40];
1281
1282         u8         hw_counter[0x20];
1283
1284         u8         sw_counter[0x20];
1285
1286         u8         reserved_at_100[0xc];
1287         u8         log_wq_stride[0x4];
1288         u8         reserved_at_110[0x3];
1289         u8         log_wq_pg_sz[0x5];
1290         u8         reserved_at_118[0x3];
1291         u8         log_wq_sz[0x5];
1292
1293         u8         reserved_at_120[0x3];
1294         u8         log_hairpin_num_packets[0x5];
1295         u8         reserved_at_128[0x3];
1296         u8         log_hairpin_data_sz[0x5];
1297
1298         u8         reserved_at_130[0x4];
1299         u8         log_wqe_num_of_strides[0x4];
1300         u8         two_byte_shift_en[0x1];
1301         u8         reserved_at_139[0x4];
1302         u8         log_wqe_stride_size[0x3];
1303
1304         u8         reserved_at_140[0x4c0];
1305
1306         struct mlx5_ifc_cmd_pas_bits pas[0];
1307 };
1308
1309 struct mlx5_ifc_rq_num_bits {
1310         u8         reserved_at_0[0x8];
1311         u8         rq_num[0x18];
1312 };
1313
1314 struct mlx5_ifc_mac_address_layout_bits {
1315         u8         reserved_at_0[0x10];
1316         u8         mac_addr_47_32[0x10];
1317
1318         u8         mac_addr_31_0[0x20];
1319 };
1320
1321 struct mlx5_ifc_vlan_layout_bits {
1322         u8         reserved_at_0[0x14];
1323         u8         vlan[0x0c];
1324
1325         u8         reserved_at_20[0x20];
1326 };
1327
1328 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1329         u8         reserved_at_0[0xa0];
1330
1331         u8         min_time_between_cnps[0x20];
1332
1333         u8         reserved_at_c0[0x12];
1334         u8         cnp_dscp[0x6];
1335         u8         reserved_at_d8[0x4];
1336         u8         cnp_prio_mode[0x1];
1337         u8         cnp_802p_prio[0x3];
1338
1339         u8         reserved_at_e0[0x720];
1340 };
1341
1342 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1343         u8         reserved_at_0[0x60];
1344
1345         u8         reserved_at_60[0x4];
1346         u8         clamp_tgt_rate[0x1];
1347         u8         reserved_at_65[0x3];
1348         u8         clamp_tgt_rate_after_time_inc[0x1];
1349         u8         reserved_at_69[0x17];
1350
1351         u8         reserved_at_80[0x20];
1352
1353         u8         rpg_time_reset[0x20];
1354
1355         u8         rpg_byte_reset[0x20];
1356
1357         u8         rpg_threshold[0x20];
1358
1359         u8         rpg_max_rate[0x20];
1360
1361         u8         rpg_ai_rate[0x20];
1362
1363         u8         rpg_hai_rate[0x20];
1364
1365         u8         rpg_gd[0x20];
1366
1367         u8         rpg_min_dec_fac[0x20];
1368
1369         u8         rpg_min_rate[0x20];
1370
1371         u8         reserved_at_1c0[0xe0];
1372
1373         u8         rate_to_set_on_first_cnp[0x20];
1374
1375         u8         dce_tcp_g[0x20];
1376
1377         u8         dce_tcp_rtt[0x20];
1378
1379         u8         rate_reduce_monitor_period[0x20];
1380
1381         u8         reserved_at_320[0x20];
1382
1383         u8         initial_alpha_value[0x20];
1384
1385         u8         reserved_at_360[0x4a0];
1386 };
1387
1388 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1389         u8         reserved_at_0[0x80];
1390
1391         u8         rppp_max_rps[0x20];
1392
1393         u8         rpg_time_reset[0x20];
1394
1395         u8         rpg_byte_reset[0x20];
1396
1397         u8         rpg_threshold[0x20];
1398
1399         u8         rpg_max_rate[0x20];
1400
1401         u8         rpg_ai_rate[0x20];
1402
1403         u8         rpg_hai_rate[0x20];
1404
1405         u8         rpg_gd[0x20];
1406
1407         u8         rpg_min_dec_fac[0x20];
1408
1409         u8         rpg_min_rate[0x20];
1410
1411         u8         reserved_at_1c0[0x640];
1412 };
1413
1414 enum {
1415         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1416         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1417         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1418 };
1419
1420 struct mlx5_ifc_resize_field_select_bits {
1421         u8         resize_field_select[0x20];
1422 };
1423
1424 enum {
1425         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1426         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1427         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1428         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1429 };
1430
1431 struct mlx5_ifc_modify_field_select_bits {
1432         u8         modify_field_select[0x20];
1433 };
1434
1435 struct mlx5_ifc_field_select_r_roce_np_bits {
1436         u8         field_select_r_roce_np[0x20];
1437 };
1438
1439 struct mlx5_ifc_field_select_r_roce_rp_bits {
1440         u8         field_select_r_roce_rp[0x20];
1441 };
1442
1443 enum {
1444         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1445         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1446         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1447         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1448         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1449         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1450         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1451         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1452         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1453         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1454 };
1455
1456 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1457         u8         field_select_8021qaurp[0x20];
1458 };
1459
1460 struct mlx5_ifc_phys_layer_cntrs_bits {
1461         u8         time_since_last_clear_high[0x20];
1462
1463         u8         time_since_last_clear_low[0x20];
1464
1465         u8         symbol_errors_high[0x20];
1466
1467         u8         symbol_errors_low[0x20];
1468
1469         u8         sync_headers_errors_high[0x20];
1470
1471         u8         sync_headers_errors_low[0x20];
1472
1473         u8         edpl_bip_errors_lane0_high[0x20];
1474
1475         u8         edpl_bip_errors_lane0_low[0x20];
1476
1477         u8         edpl_bip_errors_lane1_high[0x20];
1478
1479         u8         edpl_bip_errors_lane1_low[0x20];
1480
1481         u8         edpl_bip_errors_lane2_high[0x20];
1482
1483         u8         edpl_bip_errors_lane2_low[0x20];
1484
1485         u8         edpl_bip_errors_lane3_high[0x20];
1486
1487         u8         edpl_bip_errors_lane3_low[0x20];
1488
1489         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1490
1491         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1492
1493         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1494
1495         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1496
1497         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1498
1499         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1500
1501         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1502
1503         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1504
1505         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1506
1507         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1508
1509         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1510
1511         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1512
1513         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1514
1515         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1516
1517         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1518
1519         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1520
1521         u8         rs_fec_corrected_blocks_high[0x20];
1522
1523         u8         rs_fec_corrected_blocks_low[0x20];
1524
1525         u8         rs_fec_uncorrectable_blocks_high[0x20];
1526
1527         u8         rs_fec_uncorrectable_blocks_low[0x20];
1528
1529         u8         rs_fec_no_errors_blocks_high[0x20];
1530
1531         u8         rs_fec_no_errors_blocks_low[0x20];
1532
1533         u8         rs_fec_single_error_blocks_high[0x20];
1534
1535         u8         rs_fec_single_error_blocks_low[0x20];
1536
1537         u8         rs_fec_corrected_symbols_total_high[0x20];
1538
1539         u8         rs_fec_corrected_symbols_total_low[0x20];
1540
1541         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1542
1543         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1544
1545         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1546
1547         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1548
1549         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1550
1551         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1552
1553         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1554
1555         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1556
1557         u8         link_down_events[0x20];
1558
1559         u8         successful_recovery_events[0x20];
1560
1561         u8         reserved_at_640[0x180];
1562 };
1563
1564 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1565         u8         time_since_last_clear_high[0x20];
1566
1567         u8         time_since_last_clear_low[0x20];
1568
1569         u8         phy_received_bits_high[0x20];
1570
1571         u8         phy_received_bits_low[0x20];
1572
1573         u8         phy_symbol_errors_high[0x20];
1574
1575         u8         phy_symbol_errors_low[0x20];
1576
1577         u8         phy_corrected_bits_high[0x20];
1578
1579         u8         phy_corrected_bits_low[0x20];
1580
1581         u8         phy_corrected_bits_lane0_high[0x20];
1582
1583         u8         phy_corrected_bits_lane0_low[0x20];
1584
1585         u8         phy_corrected_bits_lane1_high[0x20];
1586
1587         u8         phy_corrected_bits_lane1_low[0x20];
1588
1589         u8         phy_corrected_bits_lane2_high[0x20];
1590
1591         u8         phy_corrected_bits_lane2_low[0x20];
1592
1593         u8         phy_corrected_bits_lane3_high[0x20];
1594
1595         u8         phy_corrected_bits_lane3_low[0x20];
1596
1597         u8         reserved_at_200[0x5c0];
1598 };
1599
1600 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1601         u8         symbol_error_counter[0x10];
1602
1603         u8         link_error_recovery_counter[0x8];
1604
1605         u8         link_downed_counter[0x8];
1606
1607         u8         port_rcv_errors[0x10];
1608
1609         u8         port_rcv_remote_physical_errors[0x10];
1610
1611         u8         port_rcv_switch_relay_errors[0x10];
1612
1613         u8         port_xmit_discards[0x10];
1614
1615         u8         port_xmit_constraint_errors[0x8];
1616
1617         u8         port_rcv_constraint_errors[0x8];
1618
1619         u8         reserved_at_70[0x8];
1620
1621         u8         link_overrun_errors[0x8];
1622
1623         u8         reserved_at_80[0x10];
1624
1625         u8         vl_15_dropped[0x10];
1626
1627         u8         reserved_at_a0[0x80];
1628
1629         u8         port_xmit_wait[0x20];
1630 };
1631
1632 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1633         u8         transmit_queue_high[0x20];
1634
1635         u8         transmit_queue_low[0x20];
1636
1637         u8         reserved_at_40[0x780];
1638 };
1639
1640 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1641         u8         rx_octets_high[0x20];
1642
1643         u8         rx_octets_low[0x20];
1644
1645         u8         reserved_at_40[0xc0];
1646
1647         u8         rx_frames_high[0x20];
1648
1649         u8         rx_frames_low[0x20];
1650
1651         u8         tx_octets_high[0x20];
1652
1653         u8         tx_octets_low[0x20];
1654
1655         u8         reserved_at_180[0xc0];
1656
1657         u8         tx_frames_high[0x20];
1658
1659         u8         tx_frames_low[0x20];
1660
1661         u8         rx_pause_high[0x20];
1662
1663         u8         rx_pause_low[0x20];
1664
1665         u8         rx_pause_duration_high[0x20];
1666
1667         u8         rx_pause_duration_low[0x20];
1668
1669         u8         tx_pause_high[0x20];
1670
1671         u8         tx_pause_low[0x20];
1672
1673         u8         tx_pause_duration_high[0x20];
1674
1675         u8         tx_pause_duration_low[0x20];
1676
1677         u8         rx_pause_transition_high[0x20];
1678
1679         u8         rx_pause_transition_low[0x20];
1680
1681         u8         reserved_at_3c0[0x40];
1682
1683         u8         device_stall_minor_watermark_cnt_high[0x20];
1684
1685         u8         device_stall_minor_watermark_cnt_low[0x20];
1686
1687         u8         device_stall_critical_watermark_cnt_high[0x20];
1688
1689         u8         device_stall_critical_watermark_cnt_low[0x20];
1690
1691         u8         reserved_at_480[0x340];
1692 };
1693
1694 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1695         u8         port_transmit_wait_high[0x20];
1696
1697         u8         port_transmit_wait_low[0x20];
1698
1699         u8         reserved_at_40[0x100];
1700
1701         u8         rx_buffer_almost_full_high[0x20];
1702
1703         u8         rx_buffer_almost_full_low[0x20];
1704
1705         u8         rx_buffer_full_high[0x20];
1706
1707         u8         rx_buffer_full_low[0x20];
1708
1709         u8         rx_icrc_encapsulated_high[0x20];
1710
1711         u8         rx_icrc_encapsulated_low[0x20];
1712
1713         u8         reserved_at_200[0x5c0];
1714 };
1715
1716 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1717         u8         dot3stats_alignment_errors_high[0x20];
1718
1719         u8         dot3stats_alignment_errors_low[0x20];
1720
1721         u8         dot3stats_fcs_errors_high[0x20];
1722
1723         u8         dot3stats_fcs_errors_low[0x20];
1724
1725         u8         dot3stats_single_collision_frames_high[0x20];
1726
1727         u8         dot3stats_single_collision_frames_low[0x20];
1728
1729         u8         dot3stats_multiple_collision_frames_high[0x20];
1730
1731         u8         dot3stats_multiple_collision_frames_low[0x20];
1732
1733         u8         dot3stats_sqe_test_errors_high[0x20];
1734
1735         u8         dot3stats_sqe_test_errors_low[0x20];
1736
1737         u8         dot3stats_deferred_transmissions_high[0x20];
1738
1739         u8         dot3stats_deferred_transmissions_low[0x20];
1740
1741         u8         dot3stats_late_collisions_high[0x20];
1742
1743         u8         dot3stats_late_collisions_low[0x20];
1744
1745         u8         dot3stats_excessive_collisions_high[0x20];
1746
1747         u8         dot3stats_excessive_collisions_low[0x20];
1748
1749         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1750
1751         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1752
1753         u8         dot3stats_carrier_sense_errors_high[0x20];
1754
1755         u8         dot3stats_carrier_sense_errors_low[0x20];
1756
1757         u8         dot3stats_frame_too_longs_high[0x20];
1758
1759         u8         dot3stats_frame_too_longs_low[0x20];
1760
1761         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1762
1763         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1764
1765         u8         dot3stats_symbol_errors_high[0x20];
1766
1767         u8         dot3stats_symbol_errors_low[0x20];
1768
1769         u8         dot3control_in_unknown_opcodes_high[0x20];
1770
1771         u8         dot3control_in_unknown_opcodes_low[0x20];
1772
1773         u8         dot3in_pause_frames_high[0x20];
1774
1775         u8         dot3in_pause_frames_low[0x20];
1776
1777         u8         dot3out_pause_frames_high[0x20];
1778
1779         u8         dot3out_pause_frames_low[0x20];
1780
1781         u8         reserved_at_400[0x3c0];
1782 };
1783
1784 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1785         u8         ether_stats_drop_events_high[0x20];
1786
1787         u8         ether_stats_drop_events_low[0x20];
1788
1789         u8         ether_stats_octets_high[0x20];
1790
1791         u8         ether_stats_octets_low[0x20];
1792
1793         u8         ether_stats_pkts_high[0x20];
1794
1795         u8         ether_stats_pkts_low[0x20];
1796
1797         u8         ether_stats_broadcast_pkts_high[0x20];
1798
1799         u8         ether_stats_broadcast_pkts_low[0x20];
1800
1801         u8         ether_stats_multicast_pkts_high[0x20];
1802
1803         u8         ether_stats_multicast_pkts_low[0x20];
1804
1805         u8         ether_stats_crc_align_errors_high[0x20];
1806
1807         u8         ether_stats_crc_align_errors_low[0x20];
1808
1809         u8         ether_stats_undersize_pkts_high[0x20];
1810
1811         u8         ether_stats_undersize_pkts_low[0x20];
1812
1813         u8         ether_stats_oversize_pkts_high[0x20];
1814
1815         u8         ether_stats_oversize_pkts_low[0x20];
1816
1817         u8         ether_stats_fragments_high[0x20];
1818
1819         u8         ether_stats_fragments_low[0x20];
1820
1821         u8         ether_stats_jabbers_high[0x20];
1822
1823         u8         ether_stats_jabbers_low[0x20];
1824
1825         u8         ether_stats_collisions_high[0x20];
1826
1827         u8         ether_stats_collisions_low[0x20];
1828
1829         u8         ether_stats_pkts64octets_high[0x20];
1830
1831         u8         ether_stats_pkts64octets_low[0x20];
1832
1833         u8         ether_stats_pkts65to127octets_high[0x20];
1834
1835         u8         ether_stats_pkts65to127octets_low[0x20];
1836
1837         u8         ether_stats_pkts128to255octets_high[0x20];
1838
1839         u8         ether_stats_pkts128to255octets_low[0x20];
1840
1841         u8         ether_stats_pkts256to511octets_high[0x20];
1842
1843         u8         ether_stats_pkts256to511octets_low[0x20];
1844
1845         u8         ether_stats_pkts512to1023octets_high[0x20];
1846
1847         u8         ether_stats_pkts512to1023octets_low[0x20];
1848
1849         u8         ether_stats_pkts1024to1518octets_high[0x20];
1850
1851         u8         ether_stats_pkts1024to1518octets_low[0x20];
1852
1853         u8         ether_stats_pkts1519to2047octets_high[0x20];
1854
1855         u8         ether_stats_pkts1519to2047octets_low[0x20];
1856
1857         u8         ether_stats_pkts2048to4095octets_high[0x20];
1858
1859         u8         ether_stats_pkts2048to4095octets_low[0x20];
1860
1861         u8         ether_stats_pkts4096to8191octets_high[0x20];
1862
1863         u8         ether_stats_pkts4096to8191octets_low[0x20];
1864
1865         u8         ether_stats_pkts8192to10239octets_high[0x20];
1866
1867         u8         ether_stats_pkts8192to10239octets_low[0x20];
1868
1869         u8         reserved_at_540[0x280];
1870 };
1871
1872 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1873         u8         if_in_octets_high[0x20];
1874
1875         u8         if_in_octets_low[0x20];
1876
1877         u8         if_in_ucast_pkts_high[0x20];
1878
1879         u8         if_in_ucast_pkts_low[0x20];
1880
1881         u8         if_in_discards_high[0x20];
1882
1883         u8         if_in_discards_low[0x20];
1884
1885         u8         if_in_errors_high[0x20];
1886
1887         u8         if_in_errors_low[0x20];
1888
1889         u8         if_in_unknown_protos_high[0x20];
1890
1891         u8         if_in_unknown_protos_low[0x20];
1892
1893         u8         if_out_octets_high[0x20];
1894
1895         u8         if_out_octets_low[0x20];
1896
1897         u8         if_out_ucast_pkts_high[0x20];
1898
1899         u8         if_out_ucast_pkts_low[0x20];
1900
1901         u8         if_out_discards_high[0x20];
1902
1903         u8         if_out_discards_low[0x20];
1904
1905         u8         if_out_errors_high[0x20];
1906
1907         u8         if_out_errors_low[0x20];
1908
1909         u8         if_in_multicast_pkts_high[0x20];
1910
1911         u8         if_in_multicast_pkts_low[0x20];
1912
1913         u8         if_in_broadcast_pkts_high[0x20];
1914
1915         u8         if_in_broadcast_pkts_low[0x20];
1916
1917         u8         if_out_multicast_pkts_high[0x20];
1918
1919         u8         if_out_multicast_pkts_low[0x20];
1920
1921         u8         if_out_broadcast_pkts_high[0x20];
1922
1923         u8         if_out_broadcast_pkts_low[0x20];
1924
1925         u8         reserved_at_340[0x480];
1926 };
1927
1928 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1929         u8         a_frames_transmitted_ok_high[0x20];
1930
1931         u8         a_frames_transmitted_ok_low[0x20];
1932
1933         u8         a_frames_received_ok_high[0x20];
1934
1935         u8         a_frames_received_ok_low[0x20];
1936
1937         u8         a_frame_check_sequence_errors_high[0x20];
1938
1939         u8         a_frame_check_sequence_errors_low[0x20];
1940
1941         u8         a_alignment_errors_high[0x20];
1942
1943         u8         a_alignment_errors_low[0x20];
1944
1945         u8         a_octets_transmitted_ok_high[0x20];
1946
1947         u8         a_octets_transmitted_ok_low[0x20];
1948
1949         u8         a_octets_received_ok_high[0x20];
1950
1951         u8         a_octets_received_ok_low[0x20];
1952
1953         u8         a_multicast_frames_xmitted_ok_high[0x20];
1954
1955         u8         a_multicast_frames_xmitted_ok_low[0x20];
1956
1957         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1958
1959         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1960
1961         u8         a_multicast_frames_received_ok_high[0x20];
1962
1963         u8         a_multicast_frames_received_ok_low[0x20];
1964
1965         u8         a_broadcast_frames_received_ok_high[0x20];
1966
1967         u8         a_broadcast_frames_received_ok_low[0x20];
1968
1969         u8         a_in_range_length_errors_high[0x20];
1970
1971         u8         a_in_range_length_errors_low[0x20];
1972
1973         u8         a_out_of_range_length_field_high[0x20];
1974
1975         u8         a_out_of_range_length_field_low[0x20];
1976
1977         u8         a_frame_too_long_errors_high[0x20];
1978
1979         u8         a_frame_too_long_errors_low[0x20];
1980
1981         u8         a_symbol_error_during_carrier_high[0x20];
1982
1983         u8         a_symbol_error_during_carrier_low[0x20];
1984
1985         u8         a_mac_control_frames_transmitted_high[0x20];
1986
1987         u8         a_mac_control_frames_transmitted_low[0x20];
1988
1989         u8         a_mac_control_frames_received_high[0x20];
1990
1991         u8         a_mac_control_frames_received_low[0x20];
1992
1993         u8         a_unsupported_opcodes_received_high[0x20];
1994
1995         u8         a_unsupported_opcodes_received_low[0x20];
1996
1997         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1998
1999         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2000
2001         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2002
2003         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2004
2005         u8         reserved_at_4c0[0x300];
2006 };
2007
2008 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2009         u8         life_time_counter_high[0x20];
2010
2011         u8         life_time_counter_low[0x20];
2012
2013         u8         rx_errors[0x20];
2014
2015         u8         tx_errors[0x20];
2016
2017         u8         l0_to_recovery_eieos[0x20];
2018
2019         u8         l0_to_recovery_ts[0x20];
2020
2021         u8         l0_to_recovery_framing[0x20];
2022
2023         u8         l0_to_recovery_retrain[0x20];
2024
2025         u8         crc_error_dllp[0x20];
2026
2027         u8         crc_error_tlp[0x20];
2028
2029         u8         tx_overflow_buffer_pkt_high[0x20];
2030
2031         u8         tx_overflow_buffer_pkt_low[0x20];
2032
2033         u8         outbound_stalled_reads[0x20];
2034
2035         u8         outbound_stalled_writes[0x20];
2036
2037         u8         outbound_stalled_reads_events[0x20];
2038
2039         u8         outbound_stalled_writes_events[0x20];
2040
2041         u8         reserved_at_200[0x5c0];
2042 };
2043
2044 struct mlx5_ifc_cmd_inter_comp_event_bits {
2045         u8         command_completion_vector[0x20];
2046
2047         u8         reserved_at_20[0xc0];
2048 };
2049
2050 struct mlx5_ifc_stall_vl_event_bits {
2051         u8         reserved_at_0[0x18];
2052         u8         port_num[0x1];
2053         u8         reserved_at_19[0x3];
2054         u8         vl[0x4];
2055
2056         u8         reserved_at_20[0xa0];
2057 };
2058
2059 struct mlx5_ifc_db_bf_congestion_event_bits {
2060         u8         event_subtype[0x8];
2061         u8         reserved_at_8[0x8];
2062         u8         congestion_level[0x8];
2063         u8         reserved_at_18[0x8];
2064
2065         u8         reserved_at_20[0xa0];
2066 };
2067
2068 struct mlx5_ifc_gpio_event_bits {
2069         u8         reserved_at_0[0x60];
2070
2071         u8         gpio_event_hi[0x20];
2072
2073         u8         gpio_event_lo[0x20];
2074
2075         u8         reserved_at_a0[0x40];
2076 };
2077
2078 struct mlx5_ifc_port_state_change_event_bits {
2079         u8         reserved_at_0[0x40];
2080
2081         u8         port_num[0x4];
2082         u8         reserved_at_44[0x1c];
2083
2084         u8         reserved_at_60[0x80];
2085 };
2086
2087 struct mlx5_ifc_dropped_packet_logged_bits {
2088         u8         reserved_at_0[0xe0];
2089 };
2090
2091 enum {
2092         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2093         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2094 };
2095
2096 struct mlx5_ifc_cq_error_bits {
2097         u8         reserved_at_0[0x8];
2098         u8         cqn[0x18];
2099
2100         u8         reserved_at_20[0x20];
2101
2102         u8         reserved_at_40[0x18];
2103         u8         syndrome[0x8];
2104
2105         u8         reserved_at_60[0x80];
2106 };
2107
2108 struct mlx5_ifc_rdma_page_fault_event_bits {
2109         u8         bytes_committed[0x20];
2110
2111         u8         r_key[0x20];
2112
2113         u8         reserved_at_40[0x10];
2114         u8         packet_len[0x10];
2115
2116         u8         rdma_op_len[0x20];
2117
2118         u8         rdma_va[0x40];
2119
2120         u8         reserved_at_c0[0x5];
2121         u8         rdma[0x1];
2122         u8         write[0x1];
2123         u8         requestor[0x1];
2124         u8         qp_number[0x18];
2125 };
2126
2127 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2128         u8         bytes_committed[0x20];
2129
2130         u8         reserved_at_20[0x10];
2131         u8         wqe_index[0x10];
2132
2133         u8         reserved_at_40[0x10];
2134         u8         len[0x10];
2135
2136         u8         reserved_at_60[0x60];
2137
2138         u8         reserved_at_c0[0x5];
2139         u8         rdma[0x1];
2140         u8         write_read[0x1];
2141         u8         requestor[0x1];
2142         u8         qpn[0x18];
2143 };
2144
2145 struct mlx5_ifc_qp_events_bits {
2146         u8         reserved_at_0[0xa0];
2147
2148         u8         type[0x8];
2149         u8         reserved_at_a8[0x18];
2150
2151         u8         reserved_at_c0[0x8];
2152         u8         qpn_rqn_sqn[0x18];
2153 };
2154
2155 struct mlx5_ifc_dct_events_bits {
2156         u8         reserved_at_0[0xc0];
2157
2158         u8         reserved_at_c0[0x8];
2159         u8         dct_number[0x18];
2160 };
2161
2162 struct mlx5_ifc_comp_event_bits {
2163         u8         reserved_at_0[0xc0];
2164
2165         u8         reserved_at_c0[0x8];
2166         u8         cq_number[0x18];
2167 };
2168
2169 enum {
2170         MLX5_QPC_STATE_RST        = 0x0,
2171         MLX5_QPC_STATE_INIT       = 0x1,
2172         MLX5_QPC_STATE_RTR        = 0x2,
2173         MLX5_QPC_STATE_RTS        = 0x3,
2174         MLX5_QPC_STATE_SQER       = 0x4,
2175         MLX5_QPC_STATE_ERR        = 0x6,
2176         MLX5_QPC_STATE_SQD        = 0x7,
2177         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2178 };
2179
2180 enum {
2181         MLX5_QPC_ST_RC            = 0x0,
2182         MLX5_QPC_ST_UC            = 0x1,
2183         MLX5_QPC_ST_UD            = 0x2,
2184         MLX5_QPC_ST_XRC           = 0x3,
2185         MLX5_QPC_ST_DCI           = 0x5,
2186         MLX5_QPC_ST_QP0           = 0x7,
2187         MLX5_QPC_ST_QP1           = 0x8,
2188         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2189         MLX5_QPC_ST_REG_UMR       = 0xc,
2190 };
2191
2192 enum {
2193         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2194         MLX5_QPC_PM_STATE_REARM     = 0x1,
2195         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2196         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2197 };
2198
2199 enum {
2200         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2201 };
2202
2203 enum {
2204         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2205         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2206 };
2207
2208 enum {
2209         MLX5_QPC_MTU_256_BYTES        = 0x1,
2210         MLX5_QPC_MTU_512_BYTES        = 0x2,
2211         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2212         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2213         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2214         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2215 };
2216
2217 enum {
2218         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2219         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2220         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2221         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2222         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2223         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2224         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2225         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2226 };
2227
2228 enum {
2229         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2230         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2231         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2232 };
2233
2234 enum {
2235         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2236         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2237         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2238 };
2239
2240 struct mlx5_ifc_qpc_bits {
2241         u8         state[0x4];
2242         u8         lag_tx_port_affinity[0x4];
2243         u8         st[0x8];
2244         u8         reserved_at_10[0x3];
2245         u8         pm_state[0x2];
2246         u8         reserved_at_15[0x3];
2247         u8         offload_type[0x4];
2248         u8         end_padding_mode[0x2];
2249         u8         reserved_at_1e[0x2];
2250
2251         u8         wq_signature[0x1];
2252         u8         block_lb_mc[0x1];
2253         u8         atomic_like_write_en[0x1];
2254         u8         latency_sensitive[0x1];
2255         u8         reserved_at_24[0x1];
2256         u8         drain_sigerr[0x1];
2257         u8         reserved_at_26[0x2];
2258         u8         pd[0x18];
2259
2260         u8         mtu[0x3];
2261         u8         log_msg_max[0x5];
2262         u8         reserved_at_48[0x1];
2263         u8         log_rq_size[0x4];
2264         u8         log_rq_stride[0x3];
2265         u8         no_sq[0x1];
2266         u8         log_sq_size[0x4];
2267         u8         reserved_at_55[0x6];
2268         u8         rlky[0x1];
2269         u8         ulp_stateless_offload_mode[0x4];
2270
2271         u8         counter_set_id[0x8];
2272         u8         uar_page[0x18];
2273
2274         u8         reserved_at_80[0x8];
2275         u8         user_index[0x18];
2276
2277         u8         reserved_at_a0[0x3];
2278         u8         log_page_size[0x5];
2279         u8         remote_qpn[0x18];
2280
2281         struct mlx5_ifc_ads_bits primary_address_path;
2282
2283         struct mlx5_ifc_ads_bits secondary_address_path;
2284
2285         u8         log_ack_req_freq[0x4];
2286         u8         reserved_at_384[0x4];
2287         u8         log_sra_max[0x3];
2288         u8         reserved_at_38b[0x2];
2289         u8         retry_count[0x3];
2290         u8         rnr_retry[0x3];
2291         u8         reserved_at_393[0x1];
2292         u8         fre[0x1];
2293         u8         cur_rnr_retry[0x3];
2294         u8         cur_retry_count[0x3];
2295         u8         reserved_at_39b[0x5];
2296
2297         u8         reserved_at_3a0[0x20];
2298
2299         u8         reserved_at_3c0[0x8];
2300         u8         next_send_psn[0x18];
2301
2302         u8         reserved_at_3e0[0x8];
2303         u8         cqn_snd[0x18];
2304
2305         u8         reserved_at_400[0x8];
2306         u8         deth_sqpn[0x18];
2307
2308         u8         reserved_at_420[0x20];
2309
2310         u8         reserved_at_440[0x8];
2311         u8         last_acked_psn[0x18];
2312
2313         u8         reserved_at_460[0x8];
2314         u8         ssn[0x18];
2315
2316         u8         reserved_at_480[0x8];
2317         u8         log_rra_max[0x3];
2318         u8         reserved_at_48b[0x1];
2319         u8         atomic_mode[0x4];
2320         u8         rre[0x1];
2321         u8         rwe[0x1];
2322         u8         rae[0x1];
2323         u8         reserved_at_493[0x1];
2324         u8         page_offset[0x6];
2325         u8         reserved_at_49a[0x3];
2326         u8         cd_slave_receive[0x1];
2327         u8         cd_slave_send[0x1];
2328         u8         cd_master[0x1];
2329
2330         u8         reserved_at_4a0[0x3];
2331         u8         min_rnr_nak[0x5];
2332         u8         next_rcv_psn[0x18];
2333
2334         u8         reserved_at_4c0[0x8];
2335         u8         xrcd[0x18];
2336
2337         u8         reserved_at_4e0[0x8];
2338         u8         cqn_rcv[0x18];
2339
2340         u8         dbr_addr[0x40];
2341
2342         u8         q_key[0x20];
2343
2344         u8         reserved_at_560[0x5];
2345         u8         rq_type[0x3];
2346         u8         srqn_rmpn_xrqn[0x18];
2347
2348         u8         reserved_at_580[0x8];
2349         u8         rmsn[0x18];
2350
2351         u8         hw_sq_wqebb_counter[0x10];
2352         u8         sw_sq_wqebb_counter[0x10];
2353
2354         u8         hw_rq_counter[0x20];
2355
2356         u8         sw_rq_counter[0x20];
2357
2358         u8         reserved_at_600[0x20];
2359
2360         u8         reserved_at_620[0xf];
2361         u8         cgs[0x1];
2362         u8         cs_req[0x8];
2363         u8         cs_res[0x8];
2364
2365         u8         dc_access_key[0x40];
2366
2367         u8         reserved_at_680[0xc0];
2368 };
2369
2370 struct mlx5_ifc_roce_addr_layout_bits {
2371         u8         source_l3_address[16][0x8];
2372
2373         u8         reserved_at_80[0x3];
2374         u8         vlan_valid[0x1];
2375         u8         vlan_id[0xc];
2376         u8         source_mac_47_32[0x10];
2377
2378         u8         source_mac_31_0[0x20];
2379
2380         u8         reserved_at_c0[0x14];
2381         u8         roce_l3_type[0x4];
2382         u8         roce_version[0x8];
2383
2384         u8         reserved_at_e0[0x20];
2385 };
2386
2387 union mlx5_ifc_hca_cap_union_bits {
2388         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2389         struct mlx5_ifc_odp_cap_bits odp_cap;
2390         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2391         struct mlx5_ifc_roce_cap_bits roce_cap;
2392         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2393         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2394         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2395         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2396         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2397         struct mlx5_ifc_qos_cap_bits qos_cap;
2398         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2399         u8         reserved_at_0[0x8000];
2400 };
2401
2402 enum {
2403         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2404         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2405         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2406         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2407         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2408         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2409         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2410         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2411         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2412         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2413         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2414 };
2415
2416 struct mlx5_ifc_vlan_bits {
2417         u8         ethtype[0x10];
2418         u8         prio[0x3];
2419         u8         cfi[0x1];
2420         u8         vid[0xc];
2421 };
2422
2423 struct mlx5_ifc_flow_context_bits {
2424         struct mlx5_ifc_vlan_bits push_vlan;
2425
2426         u8         group_id[0x20];
2427
2428         u8         reserved_at_40[0x8];
2429         u8         flow_tag[0x18];
2430
2431         u8         reserved_at_60[0x10];
2432         u8         action[0x10];
2433
2434         u8         reserved_at_80[0x8];
2435         u8         destination_list_size[0x18];
2436
2437         u8         reserved_at_a0[0x8];
2438         u8         flow_counter_list_size[0x18];
2439
2440         u8         packet_reformat_id[0x20];
2441
2442         u8         modify_header_id[0x20];
2443
2444         struct mlx5_ifc_vlan_bits push_vlan_2;
2445
2446         u8         reserved_at_120[0xe0];
2447
2448         struct mlx5_ifc_fte_match_param_bits match_value;
2449
2450         u8         reserved_at_1200[0x600];
2451
2452         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2453 };
2454
2455 enum {
2456         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2457         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2458 };
2459
2460 struct mlx5_ifc_xrc_srqc_bits {
2461         u8         state[0x4];
2462         u8         log_xrc_srq_size[0x4];
2463         u8         reserved_at_8[0x18];
2464
2465         u8         wq_signature[0x1];
2466         u8         cont_srq[0x1];
2467         u8         reserved_at_22[0x1];
2468         u8         rlky[0x1];
2469         u8         basic_cyclic_rcv_wqe[0x1];
2470         u8         log_rq_stride[0x3];
2471         u8         xrcd[0x18];
2472
2473         u8         page_offset[0x6];
2474         u8         reserved_at_46[0x2];
2475         u8         cqn[0x18];
2476
2477         u8         reserved_at_60[0x20];
2478
2479         u8         user_index_equal_xrc_srqn[0x1];
2480         u8         reserved_at_81[0x1];
2481         u8         log_page_size[0x6];
2482         u8         user_index[0x18];
2483
2484         u8         reserved_at_a0[0x20];
2485
2486         u8         reserved_at_c0[0x8];
2487         u8         pd[0x18];
2488
2489         u8         lwm[0x10];
2490         u8         wqe_cnt[0x10];
2491
2492         u8         reserved_at_100[0x40];
2493
2494         u8         db_record_addr_h[0x20];
2495
2496         u8         db_record_addr_l[0x1e];
2497         u8         reserved_at_17e[0x2];
2498
2499         u8         reserved_at_180[0x80];
2500 };
2501
2502 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2503         u8         counter_error_queues[0x20];
2504
2505         u8         total_error_queues[0x20];
2506
2507         u8         send_queue_priority_update_flow[0x20];
2508
2509         u8         reserved_at_60[0x20];
2510
2511         u8         nic_receive_steering_discard[0x40];
2512
2513         u8         receive_discard_vport_down[0x40];
2514
2515         u8         transmit_discard_vport_down[0x40];
2516
2517         u8         reserved_at_140[0xec0];
2518 };
2519
2520 struct mlx5_ifc_traffic_counter_bits {
2521         u8         packets[0x40];
2522
2523         u8         octets[0x40];
2524 };
2525
2526 struct mlx5_ifc_tisc_bits {
2527         u8         strict_lag_tx_port_affinity[0x1];
2528         u8         reserved_at_1[0x3];
2529         u8         lag_tx_port_affinity[0x04];
2530
2531         u8         reserved_at_8[0x4];
2532         u8         prio[0x4];
2533         u8         reserved_at_10[0x10];
2534
2535         u8         reserved_at_20[0x100];
2536
2537         u8         reserved_at_120[0x8];
2538         u8         transport_domain[0x18];
2539
2540         u8         reserved_at_140[0x8];
2541         u8         underlay_qpn[0x18];
2542         u8         reserved_at_160[0x3a0];
2543 };
2544
2545 enum {
2546         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2547         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2548 };
2549
2550 enum {
2551         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2552         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2553 };
2554
2555 enum {
2556         MLX5_RX_HASH_FN_NONE           = 0x0,
2557         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2558         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2559 };
2560
2561 enum {
2562         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2563         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2564 };
2565
2566 struct mlx5_ifc_tirc_bits {
2567         u8         reserved_at_0[0x20];
2568
2569         u8         disp_type[0x4];
2570         u8         reserved_at_24[0x1c];
2571
2572         u8         reserved_at_40[0x40];
2573
2574         u8         reserved_at_80[0x4];
2575         u8         lro_timeout_period_usecs[0x10];
2576         u8         lro_enable_mask[0x4];
2577         u8         lro_max_ip_payload_size[0x8];
2578
2579         u8         reserved_at_a0[0x40];
2580
2581         u8         reserved_at_e0[0x8];
2582         u8         inline_rqn[0x18];
2583
2584         u8         rx_hash_symmetric[0x1];
2585         u8         reserved_at_101[0x1];
2586         u8         tunneled_offload_en[0x1];
2587         u8         reserved_at_103[0x5];
2588         u8         indirect_table[0x18];
2589
2590         u8         rx_hash_fn[0x4];
2591         u8         reserved_at_124[0x2];
2592         u8         self_lb_block[0x2];
2593         u8         transport_domain[0x18];
2594
2595         u8         rx_hash_toeplitz_key[10][0x20];
2596
2597         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2598
2599         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2600
2601         u8         reserved_at_2c0[0x4c0];
2602 };
2603
2604 enum {
2605         MLX5_SRQC_STATE_GOOD   = 0x0,
2606         MLX5_SRQC_STATE_ERROR  = 0x1,
2607 };
2608
2609 struct mlx5_ifc_srqc_bits {
2610         u8         state[0x4];
2611         u8         log_srq_size[0x4];
2612         u8         reserved_at_8[0x18];
2613
2614         u8         wq_signature[0x1];
2615         u8         cont_srq[0x1];
2616         u8         reserved_at_22[0x1];
2617         u8         rlky[0x1];
2618         u8         reserved_at_24[0x1];
2619         u8         log_rq_stride[0x3];
2620         u8         xrcd[0x18];
2621
2622         u8         page_offset[0x6];
2623         u8         reserved_at_46[0x2];
2624         u8         cqn[0x18];
2625
2626         u8         reserved_at_60[0x20];
2627
2628         u8         reserved_at_80[0x2];
2629         u8         log_page_size[0x6];
2630         u8         reserved_at_88[0x18];
2631
2632         u8         reserved_at_a0[0x20];
2633
2634         u8         reserved_at_c0[0x8];
2635         u8         pd[0x18];
2636
2637         u8         lwm[0x10];
2638         u8         wqe_cnt[0x10];
2639
2640         u8         reserved_at_100[0x40];
2641
2642         u8         dbr_addr[0x40];
2643
2644         u8         reserved_at_180[0x80];
2645 };
2646
2647 enum {
2648         MLX5_SQC_STATE_RST  = 0x0,
2649         MLX5_SQC_STATE_RDY  = 0x1,
2650         MLX5_SQC_STATE_ERR  = 0x3,
2651 };
2652
2653 struct mlx5_ifc_sqc_bits {
2654         u8         rlky[0x1];
2655         u8         cd_master[0x1];
2656         u8         fre[0x1];
2657         u8         flush_in_error_en[0x1];
2658         u8         allow_multi_pkt_send_wqe[0x1];
2659         u8         min_wqe_inline_mode[0x3];
2660         u8         state[0x4];
2661         u8         reg_umr[0x1];
2662         u8         allow_swp[0x1];
2663         u8         hairpin[0x1];
2664         u8         reserved_at_f[0x11];
2665
2666         u8         reserved_at_20[0x8];
2667         u8         user_index[0x18];
2668
2669         u8         reserved_at_40[0x8];
2670         u8         cqn[0x18];
2671
2672         u8         reserved_at_60[0x8];
2673         u8         hairpin_peer_rq[0x18];
2674
2675         u8         reserved_at_80[0x10];
2676         u8         hairpin_peer_vhca[0x10];
2677
2678         u8         reserved_at_a0[0x50];
2679
2680         u8         packet_pacing_rate_limit_index[0x10];
2681         u8         tis_lst_sz[0x10];
2682         u8         reserved_at_110[0x10];
2683
2684         u8         reserved_at_120[0x40];
2685
2686         u8         reserved_at_160[0x8];
2687         u8         tis_num_0[0x18];
2688
2689         struct mlx5_ifc_wq_bits wq;
2690 };
2691
2692 enum {
2693         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2694         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2695         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2696         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2697 };
2698
2699 struct mlx5_ifc_scheduling_context_bits {
2700         u8         element_type[0x8];
2701         u8         reserved_at_8[0x18];
2702
2703         u8         element_attributes[0x20];
2704
2705         u8         parent_element_id[0x20];
2706
2707         u8         reserved_at_60[0x40];
2708
2709         u8         bw_share[0x20];
2710
2711         u8         max_average_bw[0x20];
2712
2713         u8         reserved_at_e0[0x120];
2714 };
2715
2716 struct mlx5_ifc_rqtc_bits {
2717         u8         reserved_at_0[0xa0];
2718
2719         u8         reserved_at_a0[0x10];
2720         u8         rqt_max_size[0x10];
2721
2722         u8         reserved_at_c0[0x10];
2723         u8         rqt_actual_size[0x10];
2724
2725         u8         reserved_at_e0[0x6a0];
2726
2727         struct mlx5_ifc_rq_num_bits rq_num[0];
2728 };
2729
2730 enum {
2731         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2732         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2733 };
2734
2735 enum {
2736         MLX5_RQC_STATE_RST  = 0x0,
2737         MLX5_RQC_STATE_RDY  = 0x1,
2738         MLX5_RQC_STATE_ERR  = 0x3,
2739 };
2740
2741 struct mlx5_ifc_rqc_bits {
2742         u8         rlky[0x1];
2743         u8         delay_drop_en[0x1];
2744         u8         scatter_fcs[0x1];
2745         u8         vsd[0x1];
2746         u8         mem_rq_type[0x4];
2747         u8         state[0x4];
2748         u8         reserved_at_c[0x1];
2749         u8         flush_in_error_en[0x1];
2750         u8         hairpin[0x1];
2751         u8         reserved_at_f[0x11];
2752
2753         u8         reserved_at_20[0x8];
2754         u8         user_index[0x18];
2755
2756         u8         reserved_at_40[0x8];
2757         u8         cqn[0x18];
2758
2759         u8         counter_set_id[0x8];
2760         u8         reserved_at_68[0x18];
2761
2762         u8         reserved_at_80[0x8];
2763         u8         rmpn[0x18];
2764
2765         u8         reserved_at_a0[0x8];
2766         u8         hairpin_peer_sq[0x18];
2767
2768         u8         reserved_at_c0[0x10];
2769         u8         hairpin_peer_vhca[0x10];
2770
2771         u8         reserved_at_e0[0xa0];
2772
2773         struct mlx5_ifc_wq_bits wq;
2774 };
2775
2776 enum {
2777         MLX5_RMPC_STATE_RDY  = 0x1,
2778         MLX5_RMPC_STATE_ERR  = 0x3,
2779 };
2780
2781 struct mlx5_ifc_rmpc_bits {
2782         u8         reserved_at_0[0x8];
2783         u8         state[0x4];
2784         u8         reserved_at_c[0x14];
2785
2786         u8         basic_cyclic_rcv_wqe[0x1];
2787         u8         reserved_at_21[0x1f];
2788
2789         u8         reserved_at_40[0x140];
2790
2791         struct mlx5_ifc_wq_bits wq;
2792 };
2793
2794 struct mlx5_ifc_nic_vport_context_bits {
2795         u8         reserved_at_0[0x5];
2796         u8         min_wqe_inline_mode[0x3];
2797         u8         reserved_at_8[0x15];
2798         u8         disable_mc_local_lb[0x1];
2799         u8         disable_uc_local_lb[0x1];
2800         u8         roce_en[0x1];
2801
2802         u8         arm_change_event[0x1];
2803         u8         reserved_at_21[0x1a];
2804         u8         event_on_mtu[0x1];
2805         u8         event_on_promisc_change[0x1];
2806         u8         event_on_vlan_change[0x1];
2807         u8         event_on_mc_address_change[0x1];
2808         u8         event_on_uc_address_change[0x1];
2809
2810         u8         reserved_at_40[0xc];
2811
2812         u8         affiliation_criteria[0x4];
2813         u8         affiliated_vhca_id[0x10];
2814
2815         u8         reserved_at_60[0xd0];
2816
2817         u8         mtu[0x10];
2818
2819         u8         system_image_guid[0x40];
2820         u8         port_guid[0x40];
2821         u8         node_guid[0x40];
2822
2823         u8         reserved_at_200[0x140];
2824         u8         qkey_violation_counter[0x10];
2825         u8         reserved_at_350[0x430];
2826
2827         u8         promisc_uc[0x1];
2828         u8         promisc_mc[0x1];
2829         u8         promisc_all[0x1];
2830         u8         reserved_at_783[0x2];
2831         u8         allowed_list_type[0x3];
2832         u8         reserved_at_788[0xc];
2833         u8         allowed_list_size[0xc];
2834
2835         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2836
2837         u8         reserved_at_7e0[0x20];
2838
2839         u8         current_uc_mac_address[0][0x40];
2840 };
2841
2842 enum {
2843         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2844         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2845         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2846         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2847         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2848 };
2849
2850 struct mlx5_ifc_mkc_bits {
2851         u8         reserved_at_0[0x1];
2852         u8         free[0x1];
2853         u8         reserved_at_2[0x1];
2854         u8         access_mode_4_2[0x3];
2855         u8         reserved_at_6[0x7];
2856         u8         relaxed_ordering_write[0x1];
2857         u8         reserved_at_e[0x1];
2858         u8         small_fence_on_rdma_read_response[0x1];
2859         u8         umr_en[0x1];
2860         u8         a[0x1];
2861         u8         rw[0x1];
2862         u8         rr[0x1];
2863         u8         lw[0x1];
2864         u8         lr[0x1];
2865         u8         access_mode_1_0[0x2];
2866         u8         reserved_at_18[0x8];
2867
2868         u8         qpn[0x18];
2869         u8         mkey_7_0[0x8];
2870
2871         u8         reserved_at_40[0x20];
2872
2873         u8         length64[0x1];
2874         u8         bsf_en[0x1];
2875         u8         sync_umr[0x1];
2876         u8         reserved_at_63[0x2];
2877         u8         expected_sigerr_count[0x1];
2878         u8         reserved_at_66[0x1];
2879         u8         en_rinval[0x1];
2880         u8         pd[0x18];
2881
2882         u8         start_addr[0x40];
2883
2884         u8         len[0x40];
2885
2886         u8         bsf_octword_size[0x20];
2887
2888         u8         reserved_at_120[0x80];
2889
2890         u8         translations_octword_size[0x20];
2891
2892         u8         reserved_at_1c0[0x1b];
2893         u8         log_page_size[0x5];
2894
2895         u8         reserved_at_1e0[0x20];
2896 };
2897
2898 struct mlx5_ifc_pkey_bits {
2899         u8         reserved_at_0[0x10];
2900         u8         pkey[0x10];
2901 };
2902
2903 struct mlx5_ifc_array128_auto_bits {
2904         u8         array128_auto[16][0x8];
2905 };
2906
2907 struct mlx5_ifc_hca_vport_context_bits {
2908         u8         field_select[0x20];
2909
2910         u8         reserved_at_20[0xe0];
2911
2912         u8         sm_virt_aware[0x1];
2913         u8         has_smi[0x1];
2914         u8         has_raw[0x1];
2915         u8         grh_required[0x1];
2916         u8         reserved_at_104[0xc];
2917         u8         port_physical_state[0x4];
2918         u8         vport_state_policy[0x4];
2919         u8         port_state[0x4];
2920         u8         vport_state[0x4];
2921
2922         u8         reserved_at_120[0x20];
2923
2924         u8         system_image_guid[0x40];
2925
2926         u8         port_guid[0x40];
2927
2928         u8         node_guid[0x40];
2929
2930         u8         cap_mask1[0x20];
2931
2932         u8         cap_mask1_field_select[0x20];
2933
2934         u8         cap_mask2[0x20];
2935
2936         u8         cap_mask2_field_select[0x20];
2937
2938         u8         reserved_at_280[0x80];
2939
2940         u8         lid[0x10];
2941         u8         reserved_at_310[0x4];
2942         u8         init_type_reply[0x4];
2943         u8         lmc[0x3];
2944         u8         subnet_timeout[0x5];
2945
2946         u8         sm_lid[0x10];
2947         u8         sm_sl[0x4];
2948         u8         reserved_at_334[0xc];
2949
2950         u8         qkey_violation_counter[0x10];
2951         u8         pkey_violation_counter[0x10];
2952
2953         u8         reserved_at_360[0xca0];
2954 };
2955
2956 struct mlx5_ifc_esw_vport_context_bits {
2957         u8         reserved_at_0[0x3];
2958         u8         vport_svlan_strip[0x1];
2959         u8         vport_cvlan_strip[0x1];
2960         u8         vport_svlan_insert[0x1];
2961         u8         vport_cvlan_insert[0x2];
2962         u8         reserved_at_8[0x18];
2963
2964         u8         reserved_at_20[0x20];
2965
2966         u8         svlan_cfi[0x1];
2967         u8         svlan_pcp[0x3];
2968         u8         svlan_id[0xc];
2969         u8         cvlan_cfi[0x1];
2970         u8         cvlan_pcp[0x3];
2971         u8         cvlan_id[0xc];
2972
2973         u8         reserved_at_60[0x7a0];
2974 };
2975
2976 enum {
2977         MLX5_EQC_STATUS_OK                = 0x0,
2978         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2979 };
2980
2981 enum {
2982         MLX5_EQC_ST_ARMED  = 0x9,
2983         MLX5_EQC_ST_FIRED  = 0xa,
2984 };
2985
2986 struct mlx5_ifc_eqc_bits {
2987         u8         status[0x4];
2988         u8         reserved_at_4[0x9];
2989         u8         ec[0x1];
2990         u8         oi[0x1];
2991         u8         reserved_at_f[0x5];
2992         u8         st[0x4];
2993         u8         reserved_at_18[0x8];
2994
2995         u8         reserved_at_20[0x20];
2996
2997         u8         reserved_at_40[0x14];
2998         u8         page_offset[0x6];
2999         u8         reserved_at_5a[0x6];
3000
3001         u8         reserved_at_60[0x3];
3002         u8         log_eq_size[0x5];
3003         u8         uar_page[0x18];
3004
3005         u8         reserved_at_80[0x20];
3006
3007         u8         reserved_at_a0[0x18];
3008         u8         intr[0x8];
3009
3010         u8         reserved_at_c0[0x3];
3011         u8         log_page_size[0x5];
3012         u8         reserved_at_c8[0x18];
3013
3014         u8         reserved_at_e0[0x60];
3015
3016         u8         reserved_at_140[0x8];
3017         u8         consumer_counter[0x18];
3018
3019         u8         reserved_at_160[0x8];
3020         u8         producer_counter[0x18];
3021
3022         u8         reserved_at_180[0x80];
3023 };
3024
3025 enum {
3026         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3027         MLX5_DCTC_STATE_DRAINING  = 0x1,
3028         MLX5_DCTC_STATE_DRAINED   = 0x2,
3029 };
3030
3031 enum {
3032         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3033         MLX5_DCTC_CS_RES_NA         = 0x1,
3034         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3035 };
3036
3037 enum {
3038         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3039         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3040         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3041         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3042         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3043 };
3044
3045 struct mlx5_ifc_dctc_bits {
3046         u8         reserved_at_0[0x4];
3047         u8         state[0x4];
3048         u8         reserved_at_8[0x18];
3049
3050         u8         reserved_at_20[0x8];
3051         u8         user_index[0x18];
3052
3053         u8         reserved_at_40[0x8];
3054         u8         cqn[0x18];
3055
3056         u8         counter_set_id[0x8];
3057         u8         atomic_mode[0x4];
3058         u8         rre[0x1];
3059         u8         rwe[0x1];
3060         u8         rae[0x1];
3061         u8         atomic_like_write_en[0x1];
3062         u8         latency_sensitive[0x1];
3063         u8         rlky[0x1];
3064         u8         free_ar[0x1];
3065         u8         reserved_at_73[0xd];
3066
3067         u8         reserved_at_80[0x8];
3068         u8         cs_res[0x8];
3069         u8         reserved_at_90[0x3];
3070         u8         min_rnr_nak[0x5];
3071         u8         reserved_at_98[0x8];
3072
3073         u8         reserved_at_a0[0x8];
3074         u8         srqn_xrqn[0x18];
3075
3076         u8         reserved_at_c0[0x8];
3077         u8         pd[0x18];
3078
3079         u8         tclass[0x8];
3080         u8         reserved_at_e8[0x4];
3081         u8         flow_label[0x14];
3082
3083         u8         dc_access_key[0x40];
3084
3085         u8         reserved_at_140[0x5];
3086         u8         mtu[0x3];
3087         u8         port[0x8];
3088         u8         pkey_index[0x10];
3089
3090         u8         reserved_at_160[0x8];
3091         u8         my_addr_index[0x8];
3092         u8         reserved_at_170[0x8];
3093         u8         hop_limit[0x8];
3094
3095         u8         dc_access_key_violation_count[0x20];
3096
3097         u8         reserved_at_1a0[0x14];
3098         u8         dei_cfi[0x1];
3099         u8         eth_prio[0x3];
3100         u8         ecn[0x2];
3101         u8         dscp[0x6];
3102
3103         u8         reserved_at_1c0[0x40];
3104 };
3105
3106 enum {
3107         MLX5_CQC_STATUS_OK             = 0x0,
3108         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3109         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3110 };
3111
3112 enum {
3113         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3114         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3115 };
3116
3117 enum {
3118         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3119         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3120         MLX5_CQC_ST_FIRED                                 = 0xa,
3121 };
3122
3123 enum {
3124         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3125         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3126         MLX5_CQ_PERIOD_NUM_MODES
3127 };
3128
3129 struct mlx5_ifc_cqc_bits {
3130         u8         status[0x4];
3131         u8         reserved_at_4[0x4];
3132         u8         cqe_sz[0x3];
3133         u8         cc[0x1];
3134         u8         reserved_at_c[0x1];
3135         u8         scqe_break_moderation_en[0x1];
3136         u8         oi[0x1];
3137         u8         cq_period_mode[0x2];
3138         u8         cqe_comp_en[0x1];
3139         u8         mini_cqe_res_format[0x2];
3140         u8         st[0x4];
3141         u8         reserved_at_18[0x8];
3142
3143         u8         reserved_at_20[0x20];
3144
3145         u8         reserved_at_40[0x14];
3146         u8         page_offset[0x6];
3147         u8         reserved_at_5a[0x6];
3148
3149         u8         reserved_at_60[0x3];
3150         u8         log_cq_size[0x5];
3151         u8         uar_page[0x18];
3152
3153         u8         reserved_at_80[0x4];
3154         u8         cq_period[0xc];
3155         u8         cq_max_count[0x10];
3156
3157         u8         reserved_at_a0[0x18];
3158         u8         c_eqn[0x8];
3159
3160         u8         reserved_at_c0[0x3];
3161         u8         log_page_size[0x5];
3162         u8         reserved_at_c8[0x18];
3163
3164         u8         reserved_at_e0[0x20];
3165
3166         u8         reserved_at_100[0x8];
3167         u8         last_notified_index[0x18];
3168
3169         u8         reserved_at_120[0x8];
3170         u8         last_solicit_index[0x18];
3171
3172         u8         reserved_at_140[0x8];
3173         u8         consumer_counter[0x18];
3174
3175         u8         reserved_at_160[0x8];
3176         u8         producer_counter[0x18];
3177
3178         u8         reserved_at_180[0x40];
3179
3180         u8         dbr_addr[0x40];
3181 };
3182
3183 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3184         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3185         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3186         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3187         u8         reserved_at_0[0x800];
3188 };
3189
3190 struct mlx5_ifc_query_adapter_param_block_bits {
3191         u8         reserved_at_0[0xc0];
3192
3193         u8         reserved_at_c0[0x8];
3194         u8         ieee_vendor_id[0x18];
3195
3196         u8         reserved_at_e0[0x10];
3197         u8         vsd_vendor_id[0x10];
3198
3199         u8         vsd[208][0x8];
3200
3201         u8         vsd_contd_psid[16][0x8];
3202 };
3203
3204 enum {
3205         MLX5_XRQC_STATE_GOOD   = 0x0,
3206         MLX5_XRQC_STATE_ERROR  = 0x1,
3207 };
3208
3209 enum {
3210         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3211         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3212 };
3213
3214 enum {
3215         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3216 };
3217
3218 struct mlx5_ifc_tag_matching_topology_context_bits {
3219         u8         log_matching_list_sz[0x4];
3220         u8         reserved_at_4[0xc];
3221         u8         append_next_index[0x10];
3222
3223         u8         sw_phase_cnt[0x10];
3224         u8         hw_phase_cnt[0x10];
3225
3226         u8         reserved_at_40[0x40];
3227 };
3228
3229 struct mlx5_ifc_xrqc_bits {
3230         u8         state[0x4];
3231         u8         rlkey[0x1];
3232         u8         reserved_at_5[0xf];
3233         u8         topology[0x4];
3234         u8         reserved_at_18[0x4];
3235         u8         offload[0x4];
3236
3237         u8         reserved_at_20[0x8];
3238         u8         user_index[0x18];
3239
3240         u8         reserved_at_40[0x8];
3241         u8         cqn[0x18];
3242
3243         u8         reserved_at_60[0xa0];
3244
3245         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3246
3247         u8         reserved_at_180[0x280];
3248
3249         struct mlx5_ifc_wq_bits wq;
3250 };
3251
3252 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3253         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3254         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3255         u8         reserved_at_0[0x20];
3256 };
3257
3258 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3259         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3260         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3261         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3262         u8         reserved_at_0[0x20];
3263 };
3264
3265 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3266         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3267         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3268         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3269         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3270         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3271         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3272         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3273         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3274         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3275         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3276         u8         reserved_at_0[0x7c0];
3277 };
3278
3279 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3280         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3281         u8         reserved_at_0[0x7c0];
3282 };
3283
3284 union mlx5_ifc_event_auto_bits {
3285         struct mlx5_ifc_comp_event_bits comp_event;
3286         struct mlx5_ifc_dct_events_bits dct_events;
3287         struct mlx5_ifc_qp_events_bits qp_events;
3288         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3289         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3290         struct mlx5_ifc_cq_error_bits cq_error;
3291         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3292         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3293         struct mlx5_ifc_gpio_event_bits gpio_event;
3294         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3295         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3296         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3297         u8         reserved_at_0[0xe0];
3298 };
3299
3300 struct mlx5_ifc_health_buffer_bits {
3301         u8         reserved_at_0[0x100];
3302
3303         u8         assert_existptr[0x20];
3304
3305         u8         assert_callra[0x20];
3306
3307         u8         reserved_at_140[0x40];
3308
3309         u8         fw_version[0x20];
3310
3311         u8         hw_id[0x20];
3312
3313         u8         reserved_at_1c0[0x20];
3314
3315         u8         irisc_index[0x8];
3316         u8         synd[0x8];
3317         u8         ext_synd[0x10];
3318 };
3319
3320 struct mlx5_ifc_register_loopback_control_bits {
3321         u8         no_lb[0x1];
3322         u8         reserved_at_1[0x7];
3323         u8         port[0x8];
3324         u8         reserved_at_10[0x10];
3325
3326         u8         reserved_at_20[0x60];
3327 };
3328
3329 struct mlx5_ifc_vport_tc_element_bits {
3330         u8         traffic_class[0x4];
3331         u8         reserved_at_4[0xc];
3332         u8         vport_number[0x10];
3333 };
3334
3335 struct mlx5_ifc_vport_element_bits {
3336         u8         reserved_at_0[0x10];
3337         u8         vport_number[0x10];
3338 };
3339
3340 enum {
3341         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3342         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3343         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3344 };
3345
3346 struct mlx5_ifc_tsar_element_bits {
3347         u8         reserved_at_0[0x8];
3348         u8         tsar_type[0x8];
3349         u8         reserved_at_10[0x10];
3350 };
3351
3352 enum {
3353         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3354         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3355 };
3356
3357 struct mlx5_ifc_teardown_hca_out_bits {
3358         u8         status[0x8];
3359         u8         reserved_at_8[0x18];
3360
3361         u8         syndrome[0x20];
3362
3363         u8         reserved_at_40[0x3f];
3364
3365         u8         force_state[0x1];
3366 };
3367
3368 enum {
3369         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3370         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3371 };
3372
3373 struct mlx5_ifc_teardown_hca_in_bits {
3374         u8         opcode[0x10];
3375         u8         reserved_at_10[0x10];
3376
3377         u8         reserved_at_20[0x10];
3378         u8         op_mod[0x10];
3379
3380         u8         reserved_at_40[0x10];
3381         u8         profile[0x10];
3382
3383         u8         reserved_at_60[0x20];
3384 };
3385
3386 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3387         u8         status[0x8];
3388         u8         reserved_at_8[0x18];
3389
3390         u8         syndrome[0x20];
3391
3392         u8         reserved_at_40[0x40];
3393 };
3394
3395 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3396         u8         opcode[0x10];
3397         u8         uid[0x10];
3398
3399         u8         reserved_at_20[0x10];
3400         u8         op_mod[0x10];
3401
3402         u8         reserved_at_40[0x8];
3403         u8         qpn[0x18];
3404
3405         u8         reserved_at_60[0x20];
3406
3407         u8         opt_param_mask[0x20];
3408
3409         u8         reserved_at_a0[0x20];
3410
3411         struct mlx5_ifc_qpc_bits qpc;
3412
3413         u8         reserved_at_800[0x80];
3414 };
3415
3416 struct mlx5_ifc_sqd2rts_qp_out_bits {
3417         u8         status[0x8];
3418         u8         reserved_at_8[0x18];
3419
3420         u8         syndrome[0x20];
3421
3422         u8         reserved_at_40[0x40];
3423 };
3424
3425 struct mlx5_ifc_sqd2rts_qp_in_bits {
3426         u8         opcode[0x10];
3427         u8         uid[0x10];
3428
3429         u8         reserved_at_20[0x10];
3430         u8         op_mod[0x10];
3431
3432         u8         reserved_at_40[0x8];
3433         u8         qpn[0x18];
3434
3435         u8         reserved_at_60[0x20];
3436
3437         u8         opt_param_mask[0x20];
3438
3439         u8         reserved_at_a0[0x20];
3440
3441         struct mlx5_ifc_qpc_bits qpc;
3442
3443         u8         reserved_at_800[0x80];
3444 };
3445
3446 struct mlx5_ifc_set_roce_address_out_bits {
3447         u8         status[0x8];
3448         u8         reserved_at_8[0x18];
3449
3450         u8         syndrome[0x20];
3451
3452         u8         reserved_at_40[0x40];
3453 };
3454
3455 struct mlx5_ifc_set_roce_address_in_bits {
3456         u8         opcode[0x10];
3457         u8         reserved_at_10[0x10];
3458
3459         u8         reserved_at_20[0x10];
3460         u8         op_mod[0x10];
3461
3462         u8         roce_address_index[0x10];
3463         u8         reserved_at_50[0xc];
3464         u8         vhca_port_num[0x4];
3465
3466         u8         reserved_at_60[0x20];
3467
3468         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3469 };
3470
3471 struct mlx5_ifc_set_mad_demux_out_bits {
3472         u8         status[0x8];
3473         u8         reserved_at_8[0x18];
3474
3475         u8         syndrome[0x20];
3476
3477         u8         reserved_at_40[0x40];
3478 };
3479
3480 enum {
3481         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3482         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3483 };
3484
3485 struct mlx5_ifc_set_mad_demux_in_bits {
3486         u8         opcode[0x10];
3487         u8         reserved_at_10[0x10];
3488
3489         u8         reserved_at_20[0x10];
3490         u8         op_mod[0x10];
3491
3492         u8         reserved_at_40[0x20];
3493
3494         u8         reserved_at_60[0x6];
3495         u8         demux_mode[0x2];
3496         u8         reserved_at_68[0x18];
3497 };
3498
3499 struct mlx5_ifc_set_l2_table_entry_out_bits {
3500         u8         status[0x8];
3501         u8         reserved_at_8[0x18];
3502
3503         u8         syndrome[0x20];
3504
3505         u8         reserved_at_40[0x40];
3506 };
3507
3508 struct mlx5_ifc_set_l2_table_entry_in_bits {
3509         u8         opcode[0x10];
3510         u8         reserved_at_10[0x10];
3511
3512         u8         reserved_at_20[0x10];
3513         u8         op_mod[0x10];
3514
3515         u8         reserved_at_40[0x60];
3516
3517         u8         reserved_at_a0[0x8];
3518         u8         table_index[0x18];
3519
3520         u8         reserved_at_c0[0x20];
3521
3522         u8         reserved_at_e0[0x13];
3523         u8         vlan_valid[0x1];
3524         u8         vlan[0xc];
3525
3526         struct mlx5_ifc_mac_address_layout_bits mac_address;
3527
3528         u8         reserved_at_140[0xc0];
3529 };
3530
3531 struct mlx5_ifc_set_issi_out_bits {
3532         u8         status[0x8];
3533         u8         reserved_at_8[0x18];
3534
3535         u8         syndrome[0x20];
3536
3537         u8         reserved_at_40[0x40];
3538 };
3539
3540 struct mlx5_ifc_set_issi_in_bits {
3541         u8         opcode[0x10];
3542         u8         reserved_at_10[0x10];
3543
3544         u8         reserved_at_20[0x10];
3545         u8         op_mod[0x10];
3546
3547         u8         reserved_at_40[0x10];
3548         u8         current_issi[0x10];
3549
3550         u8         reserved_at_60[0x20];
3551 };
3552
3553 struct mlx5_ifc_set_hca_cap_out_bits {
3554         u8         status[0x8];
3555         u8         reserved_at_8[0x18];
3556
3557         u8         syndrome[0x20];
3558
3559         u8         reserved_at_40[0x40];
3560 };
3561
3562 struct mlx5_ifc_set_hca_cap_in_bits {
3563         u8         opcode[0x10];
3564         u8         reserved_at_10[0x10];
3565
3566         u8         reserved_at_20[0x10];
3567         u8         op_mod[0x10];
3568
3569         u8         reserved_at_40[0x40];
3570
3571         union mlx5_ifc_hca_cap_union_bits capability;
3572 };
3573
3574 enum {
3575         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3576         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3577         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3578         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3579 };
3580
3581 struct mlx5_ifc_set_fte_out_bits {
3582         u8         status[0x8];
3583         u8         reserved_at_8[0x18];
3584
3585         u8         syndrome[0x20];
3586
3587         u8         reserved_at_40[0x40];
3588 };
3589
3590 struct mlx5_ifc_set_fte_in_bits {
3591         u8         opcode[0x10];
3592         u8         reserved_at_10[0x10];
3593
3594         u8         reserved_at_20[0x10];
3595         u8         op_mod[0x10];
3596
3597         u8         other_vport[0x1];
3598         u8         reserved_at_41[0xf];
3599         u8         vport_number[0x10];
3600
3601         u8         reserved_at_60[0x20];
3602
3603         u8         table_type[0x8];
3604         u8         reserved_at_88[0x18];
3605
3606         u8         reserved_at_a0[0x8];
3607         u8         table_id[0x18];
3608
3609         u8         reserved_at_c0[0x18];
3610         u8         modify_enable_mask[0x8];
3611
3612         u8         reserved_at_e0[0x20];
3613
3614         u8         flow_index[0x20];
3615
3616         u8         reserved_at_120[0xe0];
3617
3618         struct mlx5_ifc_flow_context_bits flow_context;
3619 };
3620
3621 struct mlx5_ifc_rts2rts_qp_out_bits {
3622         u8         status[0x8];
3623         u8         reserved_at_8[0x18];
3624
3625         u8         syndrome[0x20];
3626
3627         u8         reserved_at_40[0x40];
3628 };
3629
3630 struct mlx5_ifc_rts2rts_qp_in_bits {
3631         u8         opcode[0x10];
3632         u8         uid[0x10];
3633
3634         u8         reserved_at_20[0x10];
3635         u8         op_mod[0x10];
3636
3637         u8         reserved_at_40[0x8];
3638         u8         qpn[0x18];
3639
3640         u8         reserved_at_60[0x20];
3641
3642         u8         opt_param_mask[0x20];
3643
3644         u8         reserved_at_a0[0x20];
3645
3646         struct mlx5_ifc_qpc_bits qpc;
3647
3648         u8         reserved_at_800[0x80];
3649 };
3650
3651 struct mlx5_ifc_rtr2rts_qp_out_bits {
3652         u8         status[0x8];
3653         u8         reserved_at_8[0x18];
3654
3655         u8         syndrome[0x20];
3656
3657         u8         reserved_at_40[0x40];
3658 };
3659
3660 struct mlx5_ifc_rtr2rts_qp_in_bits {
3661         u8         opcode[0x10];
3662         u8         uid[0x10];
3663
3664         u8         reserved_at_20[0x10];
3665         u8         op_mod[0x10];
3666
3667         u8         reserved_at_40[0x8];
3668         u8         qpn[0x18];
3669
3670         u8         reserved_at_60[0x20];
3671
3672         u8         opt_param_mask[0x20];
3673
3674         u8         reserved_at_a0[0x20];
3675
3676         struct mlx5_ifc_qpc_bits qpc;
3677
3678         u8         reserved_at_800[0x80];
3679 };
3680
3681 struct mlx5_ifc_rst2init_qp_out_bits {
3682         u8         status[0x8];
3683         u8         reserved_at_8[0x18];
3684
3685         u8         syndrome[0x20];
3686
3687         u8         reserved_at_40[0x40];
3688 };
3689
3690 struct mlx5_ifc_rst2init_qp_in_bits {
3691         u8         opcode[0x10];
3692         u8         uid[0x10];
3693
3694         u8         reserved_at_20[0x10];
3695         u8         op_mod[0x10];
3696
3697         u8         reserved_at_40[0x8];
3698         u8         qpn[0x18];
3699
3700         u8         reserved_at_60[0x20];
3701
3702         u8         opt_param_mask[0x20];
3703
3704         u8         reserved_at_a0[0x20];
3705
3706         struct mlx5_ifc_qpc_bits qpc;
3707
3708         u8         reserved_at_800[0x80];
3709 };
3710
3711 struct mlx5_ifc_query_xrq_out_bits {
3712         u8         status[0x8];
3713         u8         reserved_at_8[0x18];
3714
3715         u8         syndrome[0x20];
3716
3717         u8         reserved_at_40[0x40];
3718
3719         struct mlx5_ifc_xrqc_bits xrq_context;
3720 };
3721
3722 struct mlx5_ifc_query_xrq_in_bits {
3723         u8         opcode[0x10];
3724         u8         reserved_at_10[0x10];
3725
3726         u8         reserved_at_20[0x10];
3727         u8         op_mod[0x10];
3728
3729         u8         reserved_at_40[0x8];
3730         u8         xrqn[0x18];
3731
3732         u8         reserved_at_60[0x20];
3733 };
3734
3735 struct mlx5_ifc_query_xrc_srq_out_bits {
3736         u8         status[0x8];
3737         u8         reserved_at_8[0x18];
3738
3739         u8         syndrome[0x20];
3740
3741         u8         reserved_at_40[0x40];
3742
3743         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3744
3745         u8         reserved_at_280[0x600];
3746
3747         u8         pas[0][0x40];
3748 };
3749
3750 struct mlx5_ifc_query_xrc_srq_in_bits {
3751         u8         opcode[0x10];
3752         u8         reserved_at_10[0x10];
3753
3754         u8         reserved_at_20[0x10];
3755         u8         op_mod[0x10];
3756
3757         u8         reserved_at_40[0x8];
3758         u8         xrc_srqn[0x18];
3759
3760         u8         reserved_at_60[0x20];
3761 };
3762
3763 enum {
3764         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3765         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3766 };
3767
3768 struct mlx5_ifc_query_vport_state_out_bits {
3769         u8         status[0x8];
3770         u8         reserved_at_8[0x18];
3771
3772         u8         syndrome[0x20];
3773
3774         u8         reserved_at_40[0x20];
3775
3776         u8         reserved_at_60[0x18];
3777         u8         admin_state[0x4];
3778         u8         state[0x4];
3779 };
3780
3781 enum {
3782         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
3783         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
3784 };
3785
3786 struct mlx5_ifc_query_vport_state_in_bits {
3787         u8         opcode[0x10];
3788         u8         reserved_at_10[0x10];
3789
3790         u8         reserved_at_20[0x10];
3791         u8         op_mod[0x10];
3792
3793         u8         other_vport[0x1];
3794         u8         reserved_at_41[0xf];
3795         u8         vport_number[0x10];
3796
3797         u8         reserved_at_60[0x20];
3798 };
3799
3800 struct mlx5_ifc_query_vnic_env_out_bits {
3801         u8         status[0x8];
3802         u8         reserved_at_8[0x18];
3803
3804         u8         syndrome[0x20];
3805
3806         u8         reserved_at_40[0x40];
3807
3808         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3809 };
3810
3811 enum {
3812         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3813 };
3814
3815 struct mlx5_ifc_query_vnic_env_in_bits {
3816         u8         opcode[0x10];
3817         u8         reserved_at_10[0x10];
3818
3819         u8         reserved_at_20[0x10];
3820         u8         op_mod[0x10];
3821
3822         u8         other_vport[0x1];
3823         u8         reserved_at_41[0xf];
3824         u8         vport_number[0x10];
3825
3826         u8         reserved_at_60[0x20];
3827 };
3828
3829 struct mlx5_ifc_query_vport_counter_out_bits {
3830         u8         status[0x8];
3831         u8         reserved_at_8[0x18];
3832
3833         u8         syndrome[0x20];
3834
3835         u8         reserved_at_40[0x40];
3836
3837         struct mlx5_ifc_traffic_counter_bits received_errors;
3838
3839         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3840
3841         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3842
3843         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3844
3845         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3846
3847         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3848
3849         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3850
3851         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3852
3853         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3854
3855         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3856
3857         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3858
3859         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3860
3861         u8         reserved_at_680[0xa00];
3862 };
3863
3864 enum {
3865         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3866 };
3867
3868 struct mlx5_ifc_query_vport_counter_in_bits {
3869         u8         opcode[0x10];
3870         u8         reserved_at_10[0x10];
3871
3872         u8         reserved_at_20[0x10];
3873         u8         op_mod[0x10];
3874
3875         u8         other_vport[0x1];
3876         u8         reserved_at_41[0xb];
3877         u8         port_num[0x4];
3878         u8         vport_number[0x10];
3879
3880         u8         reserved_at_60[0x60];
3881
3882         u8         clear[0x1];
3883         u8         reserved_at_c1[0x1f];
3884
3885         u8         reserved_at_e0[0x20];
3886 };
3887
3888 struct mlx5_ifc_query_tis_out_bits {
3889         u8         status[0x8];
3890         u8         reserved_at_8[0x18];
3891
3892         u8         syndrome[0x20];
3893
3894         u8         reserved_at_40[0x40];
3895
3896         struct mlx5_ifc_tisc_bits tis_context;
3897 };
3898
3899 struct mlx5_ifc_query_tis_in_bits {
3900         u8         opcode[0x10];
3901         u8         reserved_at_10[0x10];
3902
3903         u8         reserved_at_20[0x10];
3904         u8         op_mod[0x10];
3905
3906         u8         reserved_at_40[0x8];
3907         u8         tisn[0x18];
3908
3909         u8         reserved_at_60[0x20];
3910 };
3911
3912 struct mlx5_ifc_query_tir_out_bits {
3913         u8         status[0x8];
3914         u8         reserved_at_8[0x18];
3915
3916         u8         syndrome[0x20];
3917
3918         u8         reserved_at_40[0xc0];
3919
3920         struct mlx5_ifc_tirc_bits tir_context;
3921 };
3922
3923 struct mlx5_ifc_query_tir_in_bits {
3924         u8         opcode[0x10];
3925         u8         reserved_at_10[0x10];
3926
3927         u8         reserved_at_20[0x10];
3928         u8         op_mod[0x10];
3929
3930         u8         reserved_at_40[0x8];
3931         u8         tirn[0x18];
3932
3933         u8         reserved_at_60[0x20];
3934 };
3935
3936 struct mlx5_ifc_query_srq_out_bits {
3937         u8         status[0x8];
3938         u8         reserved_at_8[0x18];
3939
3940         u8         syndrome[0x20];
3941
3942         u8         reserved_at_40[0x40];
3943
3944         struct mlx5_ifc_srqc_bits srq_context_entry;
3945
3946         u8         reserved_at_280[0x600];
3947
3948         u8         pas[0][0x40];
3949 };
3950
3951 struct mlx5_ifc_query_srq_in_bits {
3952         u8         opcode[0x10];
3953         u8         reserved_at_10[0x10];
3954
3955         u8         reserved_at_20[0x10];
3956         u8         op_mod[0x10];
3957
3958         u8         reserved_at_40[0x8];
3959         u8         srqn[0x18];
3960
3961         u8         reserved_at_60[0x20];
3962 };
3963
3964 struct mlx5_ifc_query_sq_out_bits {
3965         u8         status[0x8];
3966         u8         reserved_at_8[0x18];
3967
3968         u8         syndrome[0x20];
3969
3970         u8         reserved_at_40[0xc0];
3971
3972         struct mlx5_ifc_sqc_bits sq_context;
3973 };
3974
3975 struct mlx5_ifc_query_sq_in_bits {
3976         u8         opcode[0x10];
3977         u8         reserved_at_10[0x10];
3978
3979         u8         reserved_at_20[0x10];
3980         u8         op_mod[0x10];
3981
3982         u8         reserved_at_40[0x8];
3983         u8         sqn[0x18];
3984
3985         u8         reserved_at_60[0x20];
3986 };
3987
3988 struct mlx5_ifc_query_special_contexts_out_bits {
3989         u8         status[0x8];
3990         u8         reserved_at_8[0x18];
3991
3992         u8         syndrome[0x20];
3993
3994         u8         dump_fill_mkey[0x20];
3995
3996         u8         resd_lkey[0x20];
3997
3998         u8         null_mkey[0x20];
3999
4000         u8         reserved_at_a0[0x60];
4001 };
4002
4003 struct mlx5_ifc_query_special_contexts_in_bits {
4004         u8         opcode[0x10];
4005         u8         reserved_at_10[0x10];
4006
4007         u8         reserved_at_20[0x10];
4008         u8         op_mod[0x10];
4009
4010         u8         reserved_at_40[0x40];
4011 };
4012
4013 struct mlx5_ifc_query_scheduling_element_out_bits {
4014         u8         opcode[0x10];
4015         u8         reserved_at_10[0x10];
4016
4017         u8         reserved_at_20[0x10];
4018         u8         op_mod[0x10];
4019
4020         u8         reserved_at_40[0xc0];
4021
4022         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4023
4024         u8         reserved_at_300[0x100];
4025 };
4026
4027 enum {
4028         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4029 };
4030
4031 struct mlx5_ifc_query_scheduling_element_in_bits {
4032         u8         opcode[0x10];
4033         u8         reserved_at_10[0x10];
4034
4035         u8         reserved_at_20[0x10];
4036         u8         op_mod[0x10];
4037
4038         u8         scheduling_hierarchy[0x8];
4039         u8         reserved_at_48[0x18];
4040
4041         u8         scheduling_element_id[0x20];
4042
4043         u8         reserved_at_80[0x180];
4044 };
4045
4046 struct mlx5_ifc_query_rqt_out_bits {
4047         u8         status[0x8];
4048         u8         reserved_at_8[0x18];
4049
4050         u8         syndrome[0x20];
4051
4052         u8         reserved_at_40[0xc0];
4053
4054         struct mlx5_ifc_rqtc_bits rqt_context;
4055 };
4056
4057 struct mlx5_ifc_query_rqt_in_bits {
4058         u8         opcode[0x10];
4059         u8         reserved_at_10[0x10];
4060
4061         u8         reserved_at_20[0x10];
4062         u8         op_mod[0x10];
4063
4064         u8         reserved_at_40[0x8];
4065         u8         rqtn[0x18];
4066
4067         u8         reserved_at_60[0x20];
4068 };
4069
4070 struct mlx5_ifc_query_rq_out_bits {
4071         u8         status[0x8];
4072         u8         reserved_at_8[0x18];
4073
4074         u8         syndrome[0x20];
4075
4076         u8         reserved_at_40[0xc0];
4077
4078         struct mlx5_ifc_rqc_bits rq_context;
4079 };
4080
4081 struct mlx5_ifc_query_rq_in_bits {
4082         u8         opcode[0x10];
4083         u8         reserved_at_10[0x10];
4084
4085         u8         reserved_at_20[0x10];
4086         u8         op_mod[0x10];
4087
4088         u8         reserved_at_40[0x8];
4089         u8         rqn[0x18];
4090
4091         u8         reserved_at_60[0x20];
4092 };
4093
4094 struct mlx5_ifc_query_roce_address_out_bits {
4095         u8         status[0x8];
4096         u8         reserved_at_8[0x18];
4097
4098         u8         syndrome[0x20];
4099
4100         u8         reserved_at_40[0x40];
4101
4102         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4103 };
4104
4105 struct mlx5_ifc_query_roce_address_in_bits {
4106         u8         opcode[0x10];
4107         u8         reserved_at_10[0x10];
4108
4109         u8         reserved_at_20[0x10];
4110         u8         op_mod[0x10];
4111
4112         u8         roce_address_index[0x10];
4113         u8         reserved_at_50[0xc];
4114         u8         vhca_port_num[0x4];
4115
4116         u8         reserved_at_60[0x20];
4117 };
4118
4119 struct mlx5_ifc_query_rmp_out_bits {
4120         u8         status[0x8];
4121         u8         reserved_at_8[0x18];
4122
4123         u8         syndrome[0x20];
4124
4125         u8         reserved_at_40[0xc0];
4126
4127         struct mlx5_ifc_rmpc_bits rmp_context;
4128 };
4129
4130 struct mlx5_ifc_query_rmp_in_bits {
4131         u8         opcode[0x10];
4132         u8         reserved_at_10[0x10];
4133
4134         u8         reserved_at_20[0x10];
4135         u8         op_mod[0x10];
4136
4137         u8         reserved_at_40[0x8];
4138         u8         rmpn[0x18];
4139
4140         u8         reserved_at_60[0x20];
4141 };
4142
4143 struct mlx5_ifc_query_qp_out_bits {
4144         u8         status[0x8];
4145         u8         reserved_at_8[0x18];
4146
4147         u8         syndrome[0x20];
4148
4149         u8         reserved_at_40[0x40];
4150
4151         u8         opt_param_mask[0x20];
4152
4153         u8         reserved_at_a0[0x20];
4154
4155         struct mlx5_ifc_qpc_bits qpc;
4156
4157         u8         reserved_at_800[0x80];
4158
4159         u8         pas[0][0x40];
4160 };
4161
4162 struct mlx5_ifc_query_qp_in_bits {
4163         u8         opcode[0x10];
4164         u8         reserved_at_10[0x10];
4165
4166         u8         reserved_at_20[0x10];
4167         u8         op_mod[0x10];
4168
4169         u8         reserved_at_40[0x8];
4170         u8         qpn[0x18];
4171
4172         u8         reserved_at_60[0x20];
4173 };
4174
4175 struct mlx5_ifc_query_q_counter_out_bits {
4176         u8         status[0x8];
4177         u8         reserved_at_8[0x18];
4178
4179         u8         syndrome[0x20];
4180
4181         u8         reserved_at_40[0x40];
4182
4183         u8         rx_write_requests[0x20];
4184
4185         u8         reserved_at_a0[0x20];
4186
4187         u8         rx_read_requests[0x20];
4188
4189         u8         reserved_at_e0[0x20];
4190
4191         u8         rx_atomic_requests[0x20];
4192
4193         u8         reserved_at_120[0x20];
4194
4195         u8         rx_dct_connect[0x20];
4196
4197         u8         reserved_at_160[0x20];
4198
4199         u8         out_of_buffer[0x20];
4200
4201         u8         reserved_at_1a0[0x20];
4202
4203         u8         out_of_sequence[0x20];
4204
4205         u8         reserved_at_1e0[0x20];
4206
4207         u8         duplicate_request[0x20];
4208
4209         u8         reserved_at_220[0x20];
4210
4211         u8         rnr_nak_retry_err[0x20];
4212
4213         u8         reserved_at_260[0x20];
4214
4215         u8         packet_seq_err[0x20];
4216
4217         u8         reserved_at_2a0[0x20];
4218
4219         u8         implied_nak_seq_err[0x20];
4220
4221         u8         reserved_at_2e0[0x20];
4222
4223         u8         local_ack_timeout_err[0x20];
4224
4225         u8         reserved_at_320[0xa0];
4226
4227         u8         resp_local_length_error[0x20];
4228
4229         u8         req_local_length_error[0x20];
4230
4231         u8         resp_local_qp_error[0x20];
4232
4233         u8         local_operation_error[0x20];
4234
4235         u8         resp_local_protection[0x20];
4236
4237         u8         req_local_protection[0x20];
4238
4239         u8         resp_cqe_error[0x20];
4240
4241         u8         req_cqe_error[0x20];
4242
4243         u8         req_mw_binding[0x20];
4244
4245         u8         req_bad_response[0x20];
4246
4247         u8         req_remote_invalid_request[0x20];
4248
4249         u8         resp_remote_invalid_request[0x20];
4250
4251         u8         req_remote_access_errors[0x20];
4252
4253         u8         resp_remote_access_errors[0x20];
4254
4255         u8         req_remote_operation_errors[0x20];
4256
4257         u8         req_transport_retries_exceeded[0x20];
4258
4259         u8         cq_overflow[0x20];
4260
4261         u8         resp_cqe_flush_error[0x20];
4262
4263         u8         req_cqe_flush_error[0x20];
4264
4265         u8         reserved_at_620[0x1e0];
4266 };
4267
4268 struct mlx5_ifc_query_q_counter_in_bits {
4269         u8         opcode[0x10];
4270         u8         reserved_at_10[0x10];
4271
4272         u8         reserved_at_20[0x10];
4273         u8         op_mod[0x10];
4274
4275         u8         reserved_at_40[0x80];
4276
4277         u8         clear[0x1];
4278         u8         reserved_at_c1[0x1f];
4279
4280         u8         reserved_at_e0[0x18];
4281         u8         counter_set_id[0x8];
4282 };
4283
4284 struct mlx5_ifc_query_pages_out_bits {
4285         u8         status[0x8];
4286         u8         reserved_at_8[0x18];
4287
4288         u8         syndrome[0x20];
4289
4290         u8         reserved_at_40[0x10];
4291         u8         function_id[0x10];
4292
4293         u8         num_pages[0x20];
4294 };
4295
4296 enum {
4297         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4298         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4299         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4300 };
4301
4302 struct mlx5_ifc_query_pages_in_bits {
4303         u8         opcode[0x10];
4304         u8         reserved_at_10[0x10];
4305
4306         u8         reserved_at_20[0x10];
4307         u8         op_mod[0x10];
4308
4309         u8         reserved_at_40[0x10];
4310         u8         function_id[0x10];
4311
4312         u8         reserved_at_60[0x20];
4313 };
4314
4315 struct mlx5_ifc_query_nic_vport_context_out_bits {
4316         u8         status[0x8];
4317         u8         reserved_at_8[0x18];
4318
4319         u8         syndrome[0x20];
4320
4321         u8         reserved_at_40[0x40];
4322
4323         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4324 };
4325
4326 struct mlx5_ifc_query_nic_vport_context_in_bits {
4327         u8         opcode[0x10];
4328         u8         reserved_at_10[0x10];
4329
4330         u8         reserved_at_20[0x10];
4331         u8         op_mod[0x10];
4332
4333         u8         other_vport[0x1];
4334         u8         reserved_at_41[0xf];
4335         u8         vport_number[0x10];
4336
4337         u8         reserved_at_60[0x5];
4338         u8         allowed_list_type[0x3];
4339         u8         reserved_at_68[0x18];
4340 };
4341
4342 struct mlx5_ifc_query_mkey_out_bits {
4343         u8         status[0x8];
4344         u8         reserved_at_8[0x18];
4345
4346         u8         syndrome[0x20];
4347
4348         u8         reserved_at_40[0x40];
4349
4350         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4351
4352         u8         reserved_at_280[0x600];
4353
4354         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4355
4356         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4357 };
4358
4359 struct mlx5_ifc_query_mkey_in_bits {
4360         u8         opcode[0x10];
4361         u8         reserved_at_10[0x10];
4362
4363         u8         reserved_at_20[0x10];
4364         u8         op_mod[0x10];
4365
4366         u8         reserved_at_40[0x8];
4367         u8         mkey_index[0x18];
4368
4369         u8         pg_access[0x1];
4370         u8         reserved_at_61[0x1f];
4371 };
4372
4373 struct mlx5_ifc_query_mad_demux_out_bits {
4374         u8         status[0x8];
4375         u8         reserved_at_8[0x18];
4376
4377         u8         syndrome[0x20];
4378
4379         u8         reserved_at_40[0x40];
4380
4381         u8         mad_dumux_parameters_block[0x20];
4382 };
4383
4384 struct mlx5_ifc_query_mad_demux_in_bits {
4385         u8         opcode[0x10];
4386         u8         reserved_at_10[0x10];
4387
4388         u8         reserved_at_20[0x10];
4389         u8         op_mod[0x10];
4390
4391         u8         reserved_at_40[0x40];
4392 };
4393
4394 struct mlx5_ifc_query_l2_table_entry_out_bits {
4395         u8         status[0x8];
4396         u8         reserved_at_8[0x18];
4397
4398         u8         syndrome[0x20];
4399
4400         u8         reserved_at_40[0xa0];
4401
4402         u8         reserved_at_e0[0x13];
4403         u8         vlan_valid[0x1];
4404         u8         vlan[0xc];
4405
4406         struct mlx5_ifc_mac_address_layout_bits mac_address;
4407
4408         u8         reserved_at_140[0xc0];
4409 };
4410
4411 struct mlx5_ifc_query_l2_table_entry_in_bits {
4412         u8         opcode[0x10];
4413         u8         reserved_at_10[0x10];
4414
4415         u8         reserved_at_20[0x10];
4416         u8         op_mod[0x10];
4417
4418         u8         reserved_at_40[0x60];
4419
4420         u8         reserved_at_a0[0x8];
4421         u8         table_index[0x18];
4422
4423         u8         reserved_at_c0[0x140];
4424 };
4425
4426 struct mlx5_ifc_query_issi_out_bits {
4427         u8         status[0x8];
4428         u8         reserved_at_8[0x18];
4429
4430         u8         syndrome[0x20];
4431
4432         u8         reserved_at_40[0x10];
4433         u8         current_issi[0x10];
4434
4435         u8         reserved_at_60[0xa0];
4436
4437         u8         reserved_at_100[76][0x8];
4438         u8         supported_issi_dw0[0x20];
4439 };
4440
4441 struct mlx5_ifc_query_issi_in_bits {
4442         u8         opcode[0x10];
4443         u8         reserved_at_10[0x10];
4444
4445         u8         reserved_at_20[0x10];
4446         u8         op_mod[0x10];
4447
4448         u8         reserved_at_40[0x40];
4449 };
4450
4451 struct mlx5_ifc_set_driver_version_out_bits {
4452         u8         status[0x8];
4453         u8         reserved_0[0x18];
4454
4455         u8         syndrome[0x20];
4456         u8         reserved_1[0x40];
4457 };
4458
4459 struct mlx5_ifc_set_driver_version_in_bits {
4460         u8         opcode[0x10];
4461         u8         reserved_0[0x10];
4462
4463         u8         reserved_1[0x10];
4464         u8         op_mod[0x10];
4465
4466         u8         reserved_2[0x40];
4467         u8         driver_version[64][0x8];
4468 };
4469
4470 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4471         u8         status[0x8];
4472         u8         reserved_at_8[0x18];
4473
4474         u8         syndrome[0x20];
4475
4476         u8         reserved_at_40[0x40];
4477
4478         struct mlx5_ifc_pkey_bits pkey[0];
4479 };
4480
4481 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4482         u8         opcode[0x10];
4483         u8         reserved_at_10[0x10];
4484
4485         u8         reserved_at_20[0x10];
4486         u8         op_mod[0x10];
4487
4488         u8         other_vport[0x1];
4489         u8         reserved_at_41[0xb];
4490         u8         port_num[0x4];
4491         u8         vport_number[0x10];
4492
4493         u8         reserved_at_60[0x10];
4494         u8         pkey_index[0x10];
4495 };
4496
4497 enum {
4498         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4499         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4500         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4501 };
4502
4503 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4504         u8         status[0x8];
4505         u8         reserved_at_8[0x18];
4506
4507         u8         syndrome[0x20];
4508
4509         u8         reserved_at_40[0x20];
4510
4511         u8         gids_num[0x10];
4512         u8         reserved_at_70[0x10];
4513
4514         struct mlx5_ifc_array128_auto_bits gid[0];
4515 };
4516
4517 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4518         u8         opcode[0x10];
4519         u8         reserved_at_10[0x10];
4520
4521         u8         reserved_at_20[0x10];
4522         u8         op_mod[0x10];
4523
4524         u8         other_vport[0x1];
4525         u8         reserved_at_41[0xb];
4526         u8         port_num[0x4];
4527         u8         vport_number[0x10];
4528
4529         u8         reserved_at_60[0x10];
4530         u8         gid_index[0x10];
4531 };
4532
4533 struct mlx5_ifc_query_hca_vport_context_out_bits {
4534         u8         status[0x8];
4535         u8         reserved_at_8[0x18];
4536
4537         u8         syndrome[0x20];
4538
4539         u8         reserved_at_40[0x40];
4540
4541         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4542 };
4543
4544 struct mlx5_ifc_query_hca_vport_context_in_bits {
4545         u8         opcode[0x10];
4546         u8         reserved_at_10[0x10];
4547
4548         u8         reserved_at_20[0x10];
4549         u8         op_mod[0x10];
4550
4551         u8         other_vport[0x1];
4552         u8         reserved_at_41[0xb];
4553         u8         port_num[0x4];
4554         u8         vport_number[0x10];
4555
4556         u8         reserved_at_60[0x20];
4557 };
4558
4559 struct mlx5_ifc_query_hca_cap_out_bits {
4560         u8         status[0x8];
4561         u8         reserved_at_8[0x18];
4562
4563         u8         syndrome[0x20];
4564
4565         u8         reserved_at_40[0x40];
4566
4567         union mlx5_ifc_hca_cap_union_bits capability;
4568 };
4569
4570 struct mlx5_ifc_query_hca_cap_in_bits {
4571         u8         opcode[0x10];
4572         u8         reserved_at_10[0x10];
4573
4574         u8         reserved_at_20[0x10];
4575         u8         op_mod[0x10];
4576
4577         u8         reserved_at_40[0x40];
4578 };
4579
4580 struct mlx5_ifc_query_flow_table_out_bits {
4581         u8         status[0x8];
4582         u8         reserved_at_8[0x18];
4583
4584         u8         syndrome[0x20];
4585
4586         u8         reserved_at_40[0x80];
4587
4588         u8         reserved_at_c0[0x8];
4589         u8         level[0x8];
4590         u8         reserved_at_d0[0x8];
4591         u8         log_size[0x8];
4592
4593         u8         reserved_at_e0[0x120];
4594 };
4595
4596 struct mlx5_ifc_query_flow_table_in_bits {
4597         u8         opcode[0x10];
4598         u8         reserved_at_10[0x10];
4599
4600         u8         reserved_at_20[0x10];
4601         u8         op_mod[0x10];
4602
4603         u8         reserved_at_40[0x40];
4604
4605         u8         table_type[0x8];
4606         u8         reserved_at_88[0x18];
4607
4608         u8         reserved_at_a0[0x8];
4609         u8         table_id[0x18];
4610
4611         u8         reserved_at_c0[0x140];
4612 };
4613
4614 struct mlx5_ifc_query_fte_out_bits {
4615         u8         status[0x8];
4616         u8         reserved_at_8[0x18];
4617
4618         u8         syndrome[0x20];
4619
4620         u8         reserved_at_40[0x1c0];
4621
4622         struct mlx5_ifc_flow_context_bits flow_context;
4623 };
4624
4625 struct mlx5_ifc_query_fte_in_bits {
4626         u8         opcode[0x10];
4627         u8         reserved_at_10[0x10];
4628
4629         u8         reserved_at_20[0x10];
4630         u8         op_mod[0x10];
4631
4632         u8         reserved_at_40[0x40];
4633
4634         u8         table_type[0x8];
4635         u8         reserved_at_88[0x18];
4636
4637         u8         reserved_at_a0[0x8];
4638         u8         table_id[0x18];
4639
4640         u8         reserved_at_c0[0x40];
4641
4642         u8         flow_index[0x20];
4643
4644         u8         reserved_at_120[0xe0];
4645 };
4646
4647 enum {
4648         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4649         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4650         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4651         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4652 };
4653
4654 struct mlx5_ifc_query_flow_group_out_bits {
4655         u8         status[0x8];
4656         u8         reserved_at_8[0x18];
4657
4658         u8         syndrome[0x20];
4659
4660         u8         reserved_at_40[0xa0];
4661
4662         u8         start_flow_index[0x20];
4663
4664         u8         reserved_at_100[0x20];
4665
4666         u8         end_flow_index[0x20];
4667
4668         u8         reserved_at_140[0xa0];
4669
4670         u8         reserved_at_1e0[0x18];
4671         u8         match_criteria_enable[0x8];
4672
4673         struct mlx5_ifc_fte_match_param_bits match_criteria;
4674
4675         u8         reserved_at_1200[0xe00];
4676 };
4677
4678 struct mlx5_ifc_query_flow_group_in_bits {
4679         u8         opcode[0x10];
4680         u8         reserved_at_10[0x10];
4681
4682         u8         reserved_at_20[0x10];
4683         u8         op_mod[0x10];
4684
4685         u8         reserved_at_40[0x40];
4686
4687         u8         table_type[0x8];
4688         u8         reserved_at_88[0x18];
4689
4690         u8         reserved_at_a0[0x8];
4691         u8         table_id[0x18];
4692
4693         u8         group_id[0x20];
4694
4695         u8         reserved_at_e0[0x120];
4696 };
4697
4698 struct mlx5_ifc_query_flow_counter_out_bits {
4699         u8         status[0x8];
4700         u8         reserved_at_8[0x18];
4701
4702         u8         syndrome[0x20];
4703
4704         u8         reserved_at_40[0x40];
4705
4706         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4707 };
4708
4709 struct mlx5_ifc_query_flow_counter_in_bits {
4710         u8         opcode[0x10];
4711         u8         reserved_at_10[0x10];
4712
4713         u8         reserved_at_20[0x10];
4714         u8         op_mod[0x10];
4715
4716         u8         reserved_at_40[0x80];
4717
4718         u8         clear[0x1];
4719         u8         reserved_at_c1[0xf];
4720         u8         num_of_counters[0x10];
4721
4722         u8         flow_counter_id[0x20];
4723 };
4724
4725 struct mlx5_ifc_query_esw_vport_context_out_bits {
4726         u8         status[0x8];
4727         u8         reserved_at_8[0x18];
4728
4729         u8         syndrome[0x20];
4730
4731         u8         reserved_at_40[0x40];
4732
4733         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4734 };
4735
4736 struct mlx5_ifc_query_esw_vport_context_in_bits {
4737         u8         opcode[0x10];
4738         u8         reserved_at_10[0x10];
4739
4740         u8         reserved_at_20[0x10];
4741         u8         op_mod[0x10];
4742
4743         u8         other_vport[0x1];
4744         u8         reserved_at_41[0xf];
4745         u8         vport_number[0x10];
4746
4747         u8         reserved_at_60[0x20];
4748 };
4749
4750 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4751         u8         status[0x8];
4752         u8         reserved_at_8[0x18];
4753
4754         u8         syndrome[0x20];
4755
4756         u8         reserved_at_40[0x40];
4757 };
4758
4759 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4760         u8         reserved_at_0[0x1c];
4761         u8         vport_cvlan_insert[0x1];
4762         u8         vport_svlan_insert[0x1];
4763         u8         vport_cvlan_strip[0x1];
4764         u8         vport_svlan_strip[0x1];
4765 };
4766
4767 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4768         u8         opcode[0x10];
4769         u8         reserved_at_10[0x10];
4770
4771         u8         reserved_at_20[0x10];
4772         u8         op_mod[0x10];
4773
4774         u8         other_vport[0x1];
4775         u8         reserved_at_41[0xf];
4776         u8         vport_number[0x10];
4777
4778         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4779
4780         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4781 };
4782
4783 struct mlx5_ifc_query_eq_out_bits {
4784         u8         status[0x8];
4785         u8         reserved_at_8[0x18];
4786
4787         u8         syndrome[0x20];
4788
4789         u8         reserved_at_40[0x40];
4790
4791         struct mlx5_ifc_eqc_bits eq_context_entry;
4792
4793         u8         reserved_at_280[0x40];
4794
4795         u8         event_bitmask[0x40];
4796
4797         u8         reserved_at_300[0x580];
4798
4799         u8         pas[0][0x40];
4800 };
4801
4802 struct mlx5_ifc_query_eq_in_bits {
4803         u8         opcode[0x10];
4804         u8         reserved_at_10[0x10];
4805
4806         u8         reserved_at_20[0x10];
4807         u8         op_mod[0x10];
4808
4809         u8         reserved_at_40[0x18];
4810         u8         eq_number[0x8];
4811
4812         u8         reserved_at_60[0x20];
4813 };
4814
4815 struct mlx5_ifc_packet_reformat_context_in_bits {
4816         u8         reserved_at_0[0x5];
4817         u8         reformat_type[0x3];
4818         u8         reserved_at_8[0xe];
4819         u8         reformat_data_size[0xa];
4820
4821         u8         reserved_at_20[0x10];
4822         u8         reformat_data[2][0x8];
4823
4824         u8         more_reformat_data[0][0x8];
4825 };
4826
4827 struct mlx5_ifc_query_packet_reformat_context_out_bits {
4828         u8         status[0x8];
4829         u8         reserved_at_8[0x18];
4830
4831         u8         syndrome[0x20];
4832
4833         u8         reserved_at_40[0xa0];
4834
4835         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
4836 };
4837
4838 struct mlx5_ifc_query_packet_reformat_context_in_bits {
4839         u8         opcode[0x10];
4840         u8         reserved_at_10[0x10];
4841
4842         u8         reserved_at_20[0x10];
4843         u8         op_mod[0x10];
4844
4845         u8         packet_reformat_id[0x20];
4846
4847         u8         reserved_at_60[0xa0];
4848 };
4849
4850 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
4851         u8         status[0x8];
4852         u8         reserved_at_8[0x18];
4853
4854         u8         syndrome[0x20];
4855
4856         u8         packet_reformat_id[0x20];
4857
4858         u8         reserved_at_60[0x20];
4859 };
4860
4861 enum {
4862         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
4863         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
4864         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
4865         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
4866         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
4867 };
4868
4869 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
4870         u8         opcode[0x10];
4871         u8         reserved_at_10[0x10];
4872
4873         u8         reserved_at_20[0x10];
4874         u8         op_mod[0x10];
4875
4876         u8         reserved_at_40[0xa0];
4877
4878         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
4879 };
4880
4881 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
4882         u8         status[0x8];
4883         u8         reserved_at_8[0x18];
4884
4885         u8         syndrome[0x20];
4886
4887         u8         reserved_at_40[0x40];
4888 };
4889
4890 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
4891         u8         opcode[0x10];
4892         u8         reserved_at_10[0x10];
4893
4894         u8         reserved_20[0x10];
4895         u8         op_mod[0x10];
4896
4897         u8         packet_reformat_id[0x20];
4898
4899         u8         reserved_60[0x20];
4900 };
4901
4902 struct mlx5_ifc_set_action_in_bits {
4903         u8         action_type[0x4];
4904         u8         field[0xc];
4905         u8         reserved_at_10[0x3];
4906         u8         offset[0x5];
4907         u8         reserved_at_18[0x3];
4908         u8         length[0x5];
4909
4910         u8         data[0x20];
4911 };
4912
4913 struct mlx5_ifc_add_action_in_bits {
4914         u8         action_type[0x4];
4915         u8         field[0xc];
4916         u8         reserved_at_10[0x10];
4917
4918         u8         data[0x20];
4919 };
4920
4921 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4922         struct mlx5_ifc_set_action_in_bits set_action_in;
4923         struct mlx5_ifc_add_action_in_bits add_action_in;
4924         u8         reserved_at_0[0x40];
4925 };
4926
4927 enum {
4928         MLX5_ACTION_TYPE_SET   = 0x1,
4929         MLX5_ACTION_TYPE_ADD   = 0x2,
4930 };
4931
4932 enum {
4933         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4934         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4935         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4936         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4937         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4938         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4939         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4940         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4941         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4942         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4943         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4944         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4945         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4946         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4947         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4948         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4949         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4950         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4951         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4952         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4953         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4954         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4955         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4956 };
4957
4958 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4959         u8         status[0x8];
4960         u8         reserved_at_8[0x18];
4961
4962         u8         syndrome[0x20];
4963
4964         u8         modify_header_id[0x20];
4965
4966         u8         reserved_at_60[0x20];
4967 };
4968
4969 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4970         u8         opcode[0x10];
4971         u8         reserved_at_10[0x10];
4972
4973         u8         reserved_at_20[0x10];
4974         u8         op_mod[0x10];
4975
4976         u8         reserved_at_40[0x20];
4977
4978         u8         table_type[0x8];
4979         u8         reserved_at_68[0x10];
4980         u8         num_of_actions[0x8];
4981
4982         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4983 };
4984
4985 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4986         u8         status[0x8];
4987         u8         reserved_at_8[0x18];
4988
4989         u8         syndrome[0x20];
4990
4991         u8         reserved_at_40[0x40];
4992 };
4993
4994 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4995         u8         opcode[0x10];
4996         u8         reserved_at_10[0x10];
4997
4998         u8         reserved_at_20[0x10];
4999         u8         op_mod[0x10];
5000
5001         u8         modify_header_id[0x20];
5002
5003         u8         reserved_at_60[0x20];
5004 };
5005
5006 struct mlx5_ifc_query_dct_out_bits {
5007         u8         status[0x8];
5008         u8         reserved_at_8[0x18];
5009
5010         u8         syndrome[0x20];
5011
5012         u8         reserved_at_40[0x40];
5013
5014         struct mlx5_ifc_dctc_bits dct_context_entry;
5015
5016         u8         reserved_at_280[0x180];
5017 };
5018
5019 struct mlx5_ifc_query_dct_in_bits {
5020         u8         opcode[0x10];
5021         u8         reserved_at_10[0x10];
5022
5023         u8         reserved_at_20[0x10];
5024         u8         op_mod[0x10];
5025
5026         u8         reserved_at_40[0x8];
5027         u8         dctn[0x18];
5028
5029         u8         reserved_at_60[0x20];
5030 };
5031
5032 struct mlx5_ifc_query_cq_out_bits {
5033         u8         status[0x8];
5034         u8         reserved_at_8[0x18];
5035
5036         u8         syndrome[0x20];
5037
5038         u8         reserved_at_40[0x40];
5039
5040         struct mlx5_ifc_cqc_bits cq_context;
5041
5042         u8         reserved_at_280[0x600];
5043
5044         u8         pas[0][0x40];
5045 };
5046
5047 struct mlx5_ifc_query_cq_in_bits {
5048         u8         opcode[0x10];
5049         u8         reserved_at_10[0x10];
5050
5051         u8         reserved_at_20[0x10];
5052         u8         op_mod[0x10];
5053
5054         u8         reserved_at_40[0x8];
5055         u8         cqn[0x18];
5056
5057         u8         reserved_at_60[0x20];
5058 };
5059
5060 struct mlx5_ifc_query_cong_status_out_bits {
5061         u8         status[0x8];
5062         u8         reserved_at_8[0x18];
5063
5064         u8         syndrome[0x20];
5065
5066         u8         reserved_at_40[0x20];
5067
5068         u8         enable[0x1];
5069         u8         tag_enable[0x1];
5070         u8         reserved_at_62[0x1e];
5071 };
5072
5073 struct mlx5_ifc_query_cong_status_in_bits {
5074         u8         opcode[0x10];
5075         u8         reserved_at_10[0x10];
5076
5077         u8         reserved_at_20[0x10];
5078         u8         op_mod[0x10];
5079
5080         u8         reserved_at_40[0x18];
5081         u8         priority[0x4];
5082         u8         cong_protocol[0x4];
5083
5084         u8         reserved_at_60[0x20];
5085 };
5086
5087 struct mlx5_ifc_query_cong_statistics_out_bits {
5088         u8         status[0x8];
5089         u8         reserved_at_8[0x18];
5090
5091         u8         syndrome[0x20];
5092
5093         u8         reserved_at_40[0x40];
5094
5095         u8         rp_cur_flows[0x20];
5096
5097         u8         sum_flows[0x20];
5098
5099         u8         rp_cnp_ignored_high[0x20];
5100
5101         u8         rp_cnp_ignored_low[0x20];
5102
5103         u8         rp_cnp_handled_high[0x20];
5104
5105         u8         rp_cnp_handled_low[0x20];
5106
5107         u8         reserved_at_140[0x100];
5108
5109         u8         time_stamp_high[0x20];
5110
5111         u8         time_stamp_low[0x20];
5112
5113         u8         accumulators_period[0x20];
5114
5115         u8         np_ecn_marked_roce_packets_high[0x20];
5116
5117         u8         np_ecn_marked_roce_packets_low[0x20];
5118
5119         u8         np_cnp_sent_high[0x20];
5120
5121         u8         np_cnp_sent_low[0x20];
5122
5123         u8         reserved_at_320[0x560];
5124 };
5125
5126 struct mlx5_ifc_query_cong_statistics_in_bits {
5127         u8         opcode[0x10];
5128         u8         reserved_at_10[0x10];
5129
5130         u8         reserved_at_20[0x10];
5131         u8         op_mod[0x10];
5132
5133         u8         clear[0x1];
5134         u8         reserved_at_41[0x1f];
5135
5136         u8         reserved_at_60[0x20];
5137 };
5138
5139 struct mlx5_ifc_query_cong_params_out_bits {
5140         u8         status[0x8];
5141         u8         reserved_at_8[0x18];
5142
5143         u8         syndrome[0x20];
5144
5145         u8         reserved_at_40[0x40];
5146
5147         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5148 };
5149
5150 struct mlx5_ifc_query_cong_params_in_bits {
5151         u8         opcode[0x10];
5152         u8         reserved_at_10[0x10];
5153
5154         u8         reserved_at_20[0x10];
5155         u8         op_mod[0x10];
5156
5157         u8         reserved_at_40[0x1c];
5158         u8         cong_protocol[0x4];
5159
5160         u8         reserved_at_60[0x20];
5161 };
5162
5163 struct mlx5_ifc_query_adapter_out_bits {
5164         u8         status[0x8];
5165         u8         reserved_at_8[0x18];
5166
5167         u8         syndrome[0x20];
5168
5169         u8         reserved_at_40[0x40];
5170
5171         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5172 };
5173
5174 struct mlx5_ifc_query_adapter_in_bits {
5175         u8         opcode[0x10];
5176         u8         reserved_at_10[0x10];
5177
5178         u8         reserved_at_20[0x10];
5179         u8         op_mod[0x10];
5180
5181         u8         reserved_at_40[0x40];
5182 };
5183
5184 struct mlx5_ifc_qp_2rst_out_bits {
5185         u8         status[0x8];
5186         u8         reserved_at_8[0x18];
5187
5188         u8         syndrome[0x20];
5189
5190         u8         reserved_at_40[0x40];
5191 };
5192
5193 struct mlx5_ifc_qp_2rst_in_bits {
5194         u8         opcode[0x10];
5195         u8         uid[0x10];
5196
5197         u8         reserved_at_20[0x10];
5198         u8         op_mod[0x10];
5199
5200         u8         reserved_at_40[0x8];
5201         u8         qpn[0x18];
5202
5203         u8         reserved_at_60[0x20];
5204 };
5205
5206 struct mlx5_ifc_qp_2err_out_bits {
5207         u8         status[0x8];
5208         u8         reserved_at_8[0x18];
5209
5210         u8         syndrome[0x20];
5211
5212         u8         reserved_at_40[0x40];
5213 };
5214
5215 struct mlx5_ifc_qp_2err_in_bits {
5216         u8         opcode[0x10];
5217         u8         uid[0x10];
5218
5219         u8         reserved_at_20[0x10];
5220         u8         op_mod[0x10];
5221
5222         u8         reserved_at_40[0x8];
5223         u8         qpn[0x18];
5224
5225         u8         reserved_at_60[0x20];
5226 };
5227
5228 struct mlx5_ifc_page_fault_resume_out_bits {
5229         u8         status[0x8];
5230         u8         reserved_at_8[0x18];
5231
5232         u8         syndrome[0x20];
5233
5234         u8         reserved_at_40[0x40];
5235 };
5236
5237 struct mlx5_ifc_page_fault_resume_in_bits {
5238         u8         opcode[0x10];
5239         u8         reserved_at_10[0x10];
5240
5241         u8         reserved_at_20[0x10];
5242         u8         op_mod[0x10];
5243
5244         u8         error[0x1];
5245         u8         reserved_at_41[0x4];
5246         u8         page_fault_type[0x3];
5247         u8         wq_number[0x18];
5248
5249         u8         reserved_at_60[0x8];
5250         u8         token[0x18];
5251 };
5252
5253 struct mlx5_ifc_nop_out_bits {
5254         u8         status[0x8];
5255         u8         reserved_at_8[0x18];
5256
5257         u8         syndrome[0x20];
5258
5259         u8         reserved_at_40[0x40];
5260 };
5261
5262 struct mlx5_ifc_nop_in_bits {
5263         u8         opcode[0x10];
5264         u8         reserved_at_10[0x10];
5265
5266         u8         reserved_at_20[0x10];
5267         u8         op_mod[0x10];
5268
5269         u8         reserved_at_40[0x40];
5270 };
5271
5272 struct mlx5_ifc_modify_vport_state_out_bits {
5273         u8         status[0x8];
5274         u8         reserved_at_8[0x18];
5275
5276         u8         syndrome[0x20];
5277
5278         u8         reserved_at_40[0x40];
5279 };
5280
5281 struct mlx5_ifc_modify_vport_state_in_bits {
5282         u8         opcode[0x10];
5283         u8         reserved_at_10[0x10];
5284
5285         u8         reserved_at_20[0x10];
5286         u8         op_mod[0x10];
5287
5288         u8         other_vport[0x1];
5289         u8         reserved_at_41[0xf];
5290         u8         vport_number[0x10];
5291
5292         u8         reserved_at_60[0x18];
5293         u8         admin_state[0x4];
5294         u8         reserved_at_7c[0x4];
5295 };
5296
5297 struct mlx5_ifc_modify_tis_out_bits {
5298         u8         status[0x8];
5299         u8         reserved_at_8[0x18];
5300
5301         u8         syndrome[0x20];
5302
5303         u8         reserved_at_40[0x40];
5304 };
5305
5306 struct mlx5_ifc_modify_tis_bitmask_bits {
5307         u8         reserved_at_0[0x20];
5308
5309         u8         reserved_at_20[0x1d];
5310         u8         lag_tx_port_affinity[0x1];
5311         u8         strict_lag_tx_port_affinity[0x1];
5312         u8         prio[0x1];
5313 };
5314
5315 struct mlx5_ifc_modify_tis_in_bits {
5316         u8         opcode[0x10];
5317         u8         reserved_at_10[0x10];
5318
5319         u8         reserved_at_20[0x10];
5320         u8         op_mod[0x10];
5321
5322         u8         reserved_at_40[0x8];
5323         u8         tisn[0x18];
5324
5325         u8         reserved_at_60[0x20];
5326
5327         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5328
5329         u8         reserved_at_c0[0x40];
5330
5331         struct mlx5_ifc_tisc_bits ctx;
5332 };
5333
5334 struct mlx5_ifc_modify_tir_bitmask_bits {
5335         u8         reserved_at_0[0x20];
5336
5337         u8         reserved_at_20[0x1b];
5338         u8         self_lb_en[0x1];
5339         u8         reserved_at_3c[0x1];
5340         u8         hash[0x1];
5341         u8         reserved_at_3e[0x1];
5342         u8         lro[0x1];
5343 };
5344
5345 struct mlx5_ifc_modify_tir_out_bits {
5346         u8         status[0x8];
5347         u8         reserved_at_8[0x18];
5348
5349         u8         syndrome[0x20];
5350
5351         u8         reserved_at_40[0x40];
5352 };
5353
5354 struct mlx5_ifc_modify_tir_in_bits {
5355         u8         opcode[0x10];
5356         u8         reserved_at_10[0x10];
5357
5358         u8         reserved_at_20[0x10];
5359         u8         op_mod[0x10];
5360
5361         u8         reserved_at_40[0x8];
5362         u8         tirn[0x18];
5363
5364         u8         reserved_at_60[0x20];
5365
5366         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5367
5368         u8         reserved_at_c0[0x40];
5369
5370         struct mlx5_ifc_tirc_bits ctx;
5371 };
5372
5373 struct mlx5_ifc_modify_sq_out_bits {
5374         u8         status[0x8];
5375         u8         reserved_at_8[0x18];
5376
5377         u8         syndrome[0x20];
5378
5379         u8         reserved_at_40[0x40];
5380 };
5381
5382 struct mlx5_ifc_modify_sq_in_bits {
5383         u8         opcode[0x10];
5384         u8         reserved_at_10[0x10];
5385
5386         u8         reserved_at_20[0x10];
5387         u8         op_mod[0x10];
5388
5389         u8         sq_state[0x4];
5390         u8         reserved_at_44[0x4];
5391         u8         sqn[0x18];
5392
5393         u8         reserved_at_60[0x20];
5394
5395         u8         modify_bitmask[0x40];
5396
5397         u8         reserved_at_c0[0x40];
5398
5399         struct mlx5_ifc_sqc_bits ctx;
5400 };
5401
5402 struct mlx5_ifc_modify_scheduling_element_out_bits {
5403         u8         status[0x8];
5404         u8         reserved_at_8[0x18];
5405
5406         u8         syndrome[0x20];
5407
5408         u8         reserved_at_40[0x1c0];
5409 };
5410
5411 enum {
5412         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5413         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5414 };
5415
5416 struct mlx5_ifc_modify_scheduling_element_in_bits {
5417         u8         opcode[0x10];
5418         u8         reserved_at_10[0x10];
5419
5420         u8         reserved_at_20[0x10];
5421         u8         op_mod[0x10];
5422
5423         u8         scheduling_hierarchy[0x8];
5424         u8         reserved_at_48[0x18];
5425
5426         u8         scheduling_element_id[0x20];
5427
5428         u8         reserved_at_80[0x20];
5429
5430         u8         modify_bitmask[0x20];
5431
5432         u8         reserved_at_c0[0x40];
5433
5434         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5435
5436         u8         reserved_at_300[0x100];
5437 };
5438
5439 struct mlx5_ifc_modify_rqt_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_at_8[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_at_40[0x40];
5446 };
5447
5448 struct mlx5_ifc_rqt_bitmask_bits {
5449         u8         reserved_at_0[0x20];
5450
5451         u8         reserved_at_20[0x1f];
5452         u8         rqn_list[0x1];
5453 };
5454
5455 struct mlx5_ifc_modify_rqt_in_bits {
5456         u8         opcode[0x10];
5457         u8         reserved_at_10[0x10];
5458
5459         u8         reserved_at_20[0x10];
5460         u8         op_mod[0x10];
5461
5462         u8         reserved_at_40[0x8];
5463         u8         rqtn[0x18];
5464
5465         u8         reserved_at_60[0x20];
5466
5467         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5468
5469         u8         reserved_at_c0[0x40];
5470
5471         struct mlx5_ifc_rqtc_bits ctx;
5472 };
5473
5474 struct mlx5_ifc_modify_rq_out_bits {
5475         u8         status[0x8];
5476         u8         reserved_at_8[0x18];
5477
5478         u8         syndrome[0x20];
5479
5480         u8         reserved_at_40[0x40];
5481 };
5482
5483 enum {
5484         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5485         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5486         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5487 };
5488
5489 struct mlx5_ifc_modify_rq_in_bits {
5490         u8         opcode[0x10];
5491         u8         reserved_at_10[0x10];
5492
5493         u8         reserved_at_20[0x10];
5494         u8         op_mod[0x10];
5495
5496         u8         rq_state[0x4];
5497         u8         reserved_at_44[0x4];
5498         u8         rqn[0x18];
5499
5500         u8         reserved_at_60[0x20];
5501
5502         u8         modify_bitmask[0x40];
5503
5504         u8         reserved_at_c0[0x40];
5505
5506         struct mlx5_ifc_rqc_bits ctx;
5507 };
5508
5509 struct mlx5_ifc_modify_rmp_out_bits {
5510         u8         status[0x8];
5511         u8         reserved_at_8[0x18];
5512
5513         u8         syndrome[0x20];
5514
5515         u8         reserved_at_40[0x40];
5516 };
5517
5518 struct mlx5_ifc_rmp_bitmask_bits {
5519         u8         reserved_at_0[0x20];
5520
5521         u8         reserved_at_20[0x1f];
5522         u8         lwm[0x1];
5523 };
5524
5525 struct mlx5_ifc_modify_rmp_in_bits {
5526         u8         opcode[0x10];
5527         u8         reserved_at_10[0x10];
5528
5529         u8         reserved_at_20[0x10];
5530         u8         op_mod[0x10];
5531
5532         u8         rmp_state[0x4];
5533         u8         reserved_at_44[0x4];
5534         u8         rmpn[0x18];
5535
5536         u8         reserved_at_60[0x20];
5537
5538         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5539
5540         u8         reserved_at_c0[0x40];
5541
5542         struct mlx5_ifc_rmpc_bits ctx;
5543 };
5544
5545 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5546         u8         status[0x8];
5547         u8         reserved_at_8[0x18];
5548
5549         u8         syndrome[0x20];
5550
5551         u8         reserved_at_40[0x40];
5552 };
5553
5554 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5555         u8         reserved_at_0[0x12];
5556         u8         affiliation[0x1];
5557         u8         reserved_at_e[0x1];
5558         u8         disable_uc_local_lb[0x1];
5559         u8         disable_mc_local_lb[0x1];
5560         u8         node_guid[0x1];
5561         u8         port_guid[0x1];
5562         u8         min_inline[0x1];
5563         u8         mtu[0x1];
5564         u8         change_event[0x1];
5565         u8         promisc[0x1];
5566         u8         permanent_address[0x1];
5567         u8         addresses_list[0x1];
5568         u8         roce_en[0x1];
5569         u8         reserved_at_1f[0x1];
5570 };
5571
5572 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5573         u8         opcode[0x10];
5574         u8         reserved_at_10[0x10];
5575
5576         u8         reserved_at_20[0x10];
5577         u8         op_mod[0x10];
5578
5579         u8         other_vport[0x1];
5580         u8         reserved_at_41[0xf];
5581         u8         vport_number[0x10];
5582
5583         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5584
5585         u8         reserved_at_80[0x780];
5586
5587         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5588 };
5589
5590 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5591         u8         status[0x8];
5592         u8         reserved_at_8[0x18];
5593
5594         u8         syndrome[0x20];
5595
5596         u8         reserved_at_40[0x40];
5597 };
5598
5599 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5600         u8         opcode[0x10];
5601         u8         reserved_at_10[0x10];
5602
5603         u8         reserved_at_20[0x10];
5604         u8         op_mod[0x10];
5605
5606         u8         other_vport[0x1];
5607         u8         reserved_at_41[0xb];
5608         u8         port_num[0x4];
5609         u8         vport_number[0x10];
5610
5611         u8         reserved_at_60[0x20];
5612
5613         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5614 };
5615
5616 struct mlx5_ifc_modify_cq_out_bits {
5617         u8         status[0x8];
5618         u8         reserved_at_8[0x18];
5619
5620         u8         syndrome[0x20];
5621
5622         u8         reserved_at_40[0x40];
5623 };
5624
5625 enum {
5626         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5627         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5628 };
5629
5630 struct mlx5_ifc_modify_cq_in_bits {
5631         u8         opcode[0x10];
5632         u8         uid[0x10];
5633
5634         u8         reserved_at_20[0x10];
5635         u8         op_mod[0x10];
5636
5637         u8         reserved_at_40[0x8];
5638         u8         cqn[0x18];
5639
5640         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5641
5642         struct mlx5_ifc_cqc_bits cq_context;
5643
5644         u8         reserved_at_280[0x600];
5645
5646         u8         pas[0][0x40];
5647 };
5648
5649 struct mlx5_ifc_modify_cong_status_out_bits {
5650         u8         status[0x8];
5651         u8         reserved_at_8[0x18];
5652
5653         u8         syndrome[0x20];
5654
5655         u8         reserved_at_40[0x40];
5656 };
5657
5658 struct mlx5_ifc_modify_cong_status_in_bits {
5659         u8         opcode[0x10];
5660         u8         reserved_at_10[0x10];
5661
5662         u8         reserved_at_20[0x10];
5663         u8         op_mod[0x10];
5664
5665         u8         reserved_at_40[0x18];
5666         u8         priority[0x4];
5667         u8         cong_protocol[0x4];
5668
5669         u8         enable[0x1];
5670         u8         tag_enable[0x1];
5671         u8         reserved_at_62[0x1e];
5672 };
5673
5674 struct mlx5_ifc_modify_cong_params_out_bits {
5675         u8         status[0x8];
5676         u8         reserved_at_8[0x18];
5677
5678         u8         syndrome[0x20];
5679
5680         u8         reserved_at_40[0x40];
5681 };
5682
5683 struct mlx5_ifc_modify_cong_params_in_bits {
5684         u8         opcode[0x10];
5685         u8         reserved_at_10[0x10];
5686
5687         u8         reserved_at_20[0x10];
5688         u8         op_mod[0x10];
5689
5690         u8         reserved_at_40[0x1c];
5691         u8         cong_protocol[0x4];
5692
5693         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5694
5695         u8         reserved_at_80[0x80];
5696
5697         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5698 };
5699
5700 struct mlx5_ifc_manage_pages_out_bits {
5701         u8         status[0x8];
5702         u8         reserved_at_8[0x18];
5703
5704         u8         syndrome[0x20];
5705
5706         u8         output_num_entries[0x20];
5707
5708         u8         reserved_at_60[0x20];
5709
5710         u8         pas[0][0x40];
5711 };
5712
5713 enum {
5714         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5715         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5716         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5717 };
5718
5719 struct mlx5_ifc_manage_pages_in_bits {
5720         u8         opcode[0x10];
5721         u8         reserved_at_10[0x10];
5722
5723         u8         reserved_at_20[0x10];
5724         u8         op_mod[0x10];
5725
5726         u8         reserved_at_40[0x10];
5727         u8         function_id[0x10];
5728
5729         u8         input_num_entries[0x20];
5730
5731         u8         pas[0][0x40];
5732 };
5733
5734 struct mlx5_ifc_mad_ifc_out_bits {
5735         u8         status[0x8];
5736         u8         reserved_at_8[0x18];
5737
5738         u8         syndrome[0x20];
5739
5740         u8         reserved_at_40[0x40];
5741
5742         u8         response_mad_packet[256][0x8];
5743 };
5744
5745 struct mlx5_ifc_mad_ifc_in_bits {
5746         u8         opcode[0x10];
5747         u8         reserved_at_10[0x10];
5748
5749         u8         reserved_at_20[0x10];
5750         u8         op_mod[0x10];
5751
5752         u8         remote_lid[0x10];
5753         u8         reserved_at_50[0x8];
5754         u8         port[0x8];
5755
5756         u8         reserved_at_60[0x20];
5757
5758         u8         mad[256][0x8];
5759 };
5760
5761 struct mlx5_ifc_init_hca_out_bits {
5762         u8         status[0x8];
5763         u8         reserved_at_8[0x18];
5764
5765         u8         syndrome[0x20];
5766
5767         u8         reserved_at_40[0x40];
5768 };
5769
5770 struct mlx5_ifc_init_hca_in_bits {
5771         u8         opcode[0x10];
5772         u8         reserved_at_10[0x10];
5773
5774         u8         reserved_at_20[0x10];
5775         u8         op_mod[0x10];
5776
5777         u8         reserved_at_40[0x40];
5778         u8         sw_owner_id[4][0x20];
5779 };
5780
5781 struct mlx5_ifc_init2rtr_qp_out_bits {
5782         u8         status[0x8];
5783         u8         reserved_at_8[0x18];
5784
5785         u8         syndrome[0x20];
5786
5787         u8         reserved_at_40[0x40];
5788 };
5789
5790 struct mlx5_ifc_init2rtr_qp_in_bits {
5791         u8         opcode[0x10];
5792         u8         uid[0x10];
5793
5794         u8         reserved_at_20[0x10];
5795         u8         op_mod[0x10];
5796
5797         u8         reserved_at_40[0x8];
5798         u8         qpn[0x18];
5799
5800         u8         reserved_at_60[0x20];
5801
5802         u8         opt_param_mask[0x20];
5803
5804         u8         reserved_at_a0[0x20];
5805
5806         struct mlx5_ifc_qpc_bits qpc;
5807
5808         u8         reserved_at_800[0x80];
5809 };
5810
5811 struct mlx5_ifc_init2init_qp_out_bits {
5812         u8         status[0x8];
5813         u8         reserved_at_8[0x18];
5814
5815         u8         syndrome[0x20];
5816
5817         u8         reserved_at_40[0x40];
5818 };
5819
5820 struct mlx5_ifc_init2init_qp_in_bits {
5821         u8         opcode[0x10];
5822         u8         uid[0x10];
5823
5824         u8         reserved_at_20[0x10];
5825         u8         op_mod[0x10];
5826
5827         u8         reserved_at_40[0x8];
5828         u8         qpn[0x18];
5829
5830         u8         reserved_at_60[0x20];
5831
5832         u8         opt_param_mask[0x20];
5833
5834         u8         reserved_at_a0[0x20];
5835
5836         struct mlx5_ifc_qpc_bits qpc;
5837
5838         u8         reserved_at_800[0x80];
5839 };
5840
5841 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5842         u8         status[0x8];
5843         u8         reserved_at_8[0x18];
5844
5845         u8         syndrome[0x20];
5846
5847         u8         reserved_at_40[0x40];
5848
5849         u8         packet_headers_log[128][0x8];
5850
5851         u8         packet_syndrome[64][0x8];
5852 };
5853
5854 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5855         u8         opcode[0x10];
5856         u8         reserved_at_10[0x10];
5857
5858         u8         reserved_at_20[0x10];
5859         u8         op_mod[0x10];
5860
5861         u8         reserved_at_40[0x40];
5862 };
5863
5864 struct mlx5_ifc_gen_eqe_in_bits {
5865         u8         opcode[0x10];
5866         u8         reserved_at_10[0x10];
5867
5868         u8         reserved_at_20[0x10];
5869         u8         op_mod[0x10];
5870
5871         u8         reserved_at_40[0x18];
5872         u8         eq_number[0x8];
5873
5874         u8         reserved_at_60[0x20];
5875
5876         u8         eqe[64][0x8];
5877 };
5878
5879 struct mlx5_ifc_gen_eq_out_bits {
5880         u8         status[0x8];
5881         u8         reserved_at_8[0x18];
5882
5883         u8         syndrome[0x20];
5884
5885         u8         reserved_at_40[0x40];
5886 };
5887
5888 struct mlx5_ifc_enable_hca_out_bits {
5889         u8         status[0x8];
5890         u8         reserved_at_8[0x18];
5891
5892         u8         syndrome[0x20];
5893
5894         u8         reserved_at_40[0x20];
5895 };
5896
5897 struct mlx5_ifc_enable_hca_in_bits {
5898         u8         opcode[0x10];
5899         u8         reserved_at_10[0x10];
5900
5901         u8         reserved_at_20[0x10];
5902         u8         op_mod[0x10];
5903
5904         u8         reserved_at_40[0x10];
5905         u8         function_id[0x10];
5906
5907         u8         reserved_at_60[0x20];
5908 };
5909
5910 struct mlx5_ifc_drain_dct_out_bits {
5911         u8         status[0x8];
5912         u8         reserved_at_8[0x18];
5913
5914         u8         syndrome[0x20];
5915
5916         u8         reserved_at_40[0x40];
5917 };
5918
5919 struct mlx5_ifc_drain_dct_in_bits {
5920         u8         opcode[0x10];
5921         u8         reserved_at_10[0x10];
5922
5923         u8         reserved_at_20[0x10];
5924         u8         op_mod[0x10];
5925
5926         u8         reserved_at_40[0x8];
5927         u8         dctn[0x18];
5928
5929         u8         reserved_at_60[0x20];
5930 };
5931
5932 struct mlx5_ifc_disable_hca_out_bits {
5933         u8         status[0x8];
5934         u8         reserved_at_8[0x18];
5935
5936         u8         syndrome[0x20];
5937
5938         u8         reserved_at_40[0x20];
5939 };
5940
5941 struct mlx5_ifc_disable_hca_in_bits {
5942         u8         opcode[0x10];
5943         u8         reserved_at_10[0x10];
5944
5945         u8         reserved_at_20[0x10];
5946         u8         op_mod[0x10];
5947
5948         u8         reserved_at_40[0x10];
5949         u8         function_id[0x10];
5950
5951         u8         reserved_at_60[0x20];
5952 };
5953
5954 struct mlx5_ifc_detach_from_mcg_out_bits {
5955         u8         status[0x8];
5956         u8         reserved_at_8[0x18];
5957
5958         u8         syndrome[0x20];
5959
5960         u8         reserved_at_40[0x40];
5961 };
5962
5963 struct mlx5_ifc_detach_from_mcg_in_bits {
5964         u8         opcode[0x10];
5965         u8         reserved_at_10[0x10];
5966
5967         u8         reserved_at_20[0x10];
5968         u8         op_mod[0x10];
5969
5970         u8         reserved_at_40[0x8];
5971         u8         qpn[0x18];
5972
5973         u8         reserved_at_60[0x20];
5974
5975         u8         multicast_gid[16][0x8];
5976 };
5977
5978 struct mlx5_ifc_destroy_xrq_out_bits {
5979         u8         status[0x8];
5980         u8         reserved_at_8[0x18];
5981
5982         u8         syndrome[0x20];
5983
5984         u8         reserved_at_40[0x40];
5985 };
5986
5987 struct mlx5_ifc_destroy_xrq_in_bits {
5988         u8         opcode[0x10];
5989         u8         reserved_at_10[0x10];
5990
5991         u8         reserved_at_20[0x10];
5992         u8         op_mod[0x10];
5993
5994         u8         reserved_at_40[0x8];
5995         u8         xrqn[0x18];
5996
5997         u8         reserved_at_60[0x20];
5998 };
5999
6000 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6001         u8         status[0x8];
6002         u8         reserved_at_8[0x18];
6003
6004         u8         syndrome[0x20];
6005
6006         u8         reserved_at_40[0x40];
6007 };
6008
6009 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6010         u8         opcode[0x10];
6011         u8         reserved_at_10[0x10];
6012
6013         u8         reserved_at_20[0x10];
6014         u8         op_mod[0x10];
6015
6016         u8         reserved_at_40[0x8];
6017         u8         xrc_srqn[0x18];
6018
6019         u8         reserved_at_60[0x20];
6020 };
6021
6022 struct mlx5_ifc_destroy_tis_out_bits {
6023         u8         status[0x8];
6024         u8         reserved_at_8[0x18];
6025
6026         u8         syndrome[0x20];
6027
6028         u8         reserved_at_40[0x40];
6029 };
6030
6031 struct mlx5_ifc_destroy_tis_in_bits {
6032         u8         opcode[0x10];
6033         u8         reserved_at_10[0x10];
6034
6035         u8         reserved_at_20[0x10];
6036         u8         op_mod[0x10];
6037
6038         u8         reserved_at_40[0x8];
6039         u8         tisn[0x18];
6040
6041         u8         reserved_at_60[0x20];
6042 };
6043
6044 struct mlx5_ifc_destroy_tir_out_bits {
6045         u8         status[0x8];
6046         u8         reserved_at_8[0x18];
6047
6048         u8         syndrome[0x20];
6049
6050         u8         reserved_at_40[0x40];
6051 };
6052
6053 struct mlx5_ifc_destroy_tir_in_bits {
6054         u8         opcode[0x10];
6055         u8         reserved_at_10[0x10];
6056
6057         u8         reserved_at_20[0x10];
6058         u8         op_mod[0x10];
6059
6060         u8         reserved_at_40[0x8];
6061         u8         tirn[0x18];
6062
6063         u8         reserved_at_60[0x20];
6064 };
6065
6066 struct mlx5_ifc_destroy_srq_out_bits {
6067         u8         status[0x8];
6068         u8         reserved_at_8[0x18];
6069
6070         u8         syndrome[0x20];
6071
6072         u8         reserved_at_40[0x40];
6073 };
6074
6075 struct mlx5_ifc_destroy_srq_in_bits {
6076         u8         opcode[0x10];
6077         u8         reserved_at_10[0x10];
6078
6079         u8         reserved_at_20[0x10];
6080         u8         op_mod[0x10];
6081
6082         u8         reserved_at_40[0x8];
6083         u8         srqn[0x18];
6084
6085         u8         reserved_at_60[0x20];
6086 };
6087
6088 struct mlx5_ifc_destroy_sq_out_bits {
6089         u8         status[0x8];
6090         u8         reserved_at_8[0x18];
6091
6092         u8         syndrome[0x20];
6093
6094         u8         reserved_at_40[0x40];
6095 };
6096
6097 struct mlx5_ifc_destroy_sq_in_bits {
6098         u8         opcode[0x10];
6099         u8         reserved_at_10[0x10];
6100
6101         u8         reserved_at_20[0x10];
6102         u8         op_mod[0x10];
6103
6104         u8         reserved_at_40[0x8];
6105         u8         sqn[0x18];
6106
6107         u8         reserved_at_60[0x20];
6108 };
6109
6110 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6111         u8         status[0x8];
6112         u8         reserved_at_8[0x18];
6113
6114         u8         syndrome[0x20];
6115
6116         u8         reserved_at_40[0x1c0];
6117 };
6118
6119 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6120         u8         opcode[0x10];
6121         u8         reserved_at_10[0x10];
6122
6123         u8         reserved_at_20[0x10];
6124         u8         op_mod[0x10];
6125
6126         u8         scheduling_hierarchy[0x8];
6127         u8         reserved_at_48[0x18];
6128
6129         u8         scheduling_element_id[0x20];
6130
6131         u8         reserved_at_80[0x180];
6132 };
6133
6134 struct mlx5_ifc_destroy_rqt_out_bits {
6135         u8         status[0x8];
6136         u8         reserved_at_8[0x18];
6137
6138         u8         syndrome[0x20];
6139
6140         u8         reserved_at_40[0x40];
6141 };
6142
6143 struct mlx5_ifc_destroy_rqt_in_bits {
6144         u8         opcode[0x10];
6145         u8         reserved_at_10[0x10];
6146
6147         u8         reserved_at_20[0x10];
6148         u8         op_mod[0x10];
6149
6150         u8         reserved_at_40[0x8];
6151         u8         rqtn[0x18];
6152
6153         u8         reserved_at_60[0x20];
6154 };
6155
6156 struct mlx5_ifc_destroy_rq_out_bits {
6157         u8         status[0x8];
6158         u8         reserved_at_8[0x18];
6159
6160         u8         syndrome[0x20];
6161
6162         u8         reserved_at_40[0x40];
6163 };
6164
6165 struct mlx5_ifc_destroy_rq_in_bits {
6166         u8         opcode[0x10];
6167         u8         reserved_at_10[0x10];
6168
6169         u8         reserved_at_20[0x10];
6170         u8         op_mod[0x10];
6171
6172         u8         reserved_at_40[0x8];
6173         u8         rqn[0x18];
6174
6175         u8         reserved_at_60[0x20];
6176 };
6177
6178 struct mlx5_ifc_set_delay_drop_params_in_bits {
6179         u8         opcode[0x10];
6180         u8         reserved_at_10[0x10];
6181
6182         u8         reserved_at_20[0x10];
6183         u8         op_mod[0x10];
6184
6185         u8         reserved_at_40[0x20];
6186
6187         u8         reserved_at_60[0x10];
6188         u8         delay_drop_timeout[0x10];
6189 };
6190
6191 struct mlx5_ifc_set_delay_drop_params_out_bits {
6192         u8         status[0x8];
6193         u8         reserved_at_8[0x18];
6194
6195         u8         syndrome[0x20];
6196
6197         u8         reserved_at_40[0x40];
6198 };
6199
6200 struct mlx5_ifc_destroy_rmp_out_bits {
6201         u8         status[0x8];
6202         u8         reserved_at_8[0x18];
6203
6204         u8         syndrome[0x20];
6205
6206         u8         reserved_at_40[0x40];
6207 };
6208
6209 struct mlx5_ifc_destroy_rmp_in_bits {
6210         u8         opcode[0x10];
6211         u8         reserved_at_10[0x10];
6212
6213         u8         reserved_at_20[0x10];
6214         u8         op_mod[0x10];
6215
6216         u8         reserved_at_40[0x8];
6217         u8         rmpn[0x18];
6218
6219         u8         reserved_at_60[0x20];
6220 };
6221
6222 struct mlx5_ifc_destroy_qp_out_bits {
6223         u8         status[0x8];
6224         u8         reserved_at_8[0x18];
6225
6226         u8         syndrome[0x20];
6227
6228         u8         reserved_at_40[0x40];
6229 };
6230
6231 struct mlx5_ifc_destroy_qp_in_bits {
6232         u8         opcode[0x10];
6233         u8         uid[0x10];
6234
6235         u8         reserved_at_20[0x10];
6236         u8         op_mod[0x10];
6237
6238         u8         reserved_at_40[0x8];
6239         u8         qpn[0x18];
6240
6241         u8         reserved_at_60[0x20];
6242 };
6243
6244 struct mlx5_ifc_destroy_psv_out_bits {
6245         u8         status[0x8];
6246         u8         reserved_at_8[0x18];
6247
6248         u8         syndrome[0x20];
6249
6250         u8         reserved_at_40[0x40];
6251 };
6252
6253 struct mlx5_ifc_destroy_psv_in_bits {
6254         u8         opcode[0x10];
6255         u8         reserved_at_10[0x10];
6256
6257         u8         reserved_at_20[0x10];
6258         u8         op_mod[0x10];
6259
6260         u8         reserved_at_40[0x8];
6261         u8         psvn[0x18];
6262
6263         u8         reserved_at_60[0x20];
6264 };
6265
6266 struct mlx5_ifc_destroy_mkey_out_bits {
6267         u8         status[0x8];
6268         u8         reserved_at_8[0x18];
6269
6270         u8         syndrome[0x20];
6271
6272         u8         reserved_at_40[0x40];
6273 };
6274
6275 struct mlx5_ifc_destroy_mkey_in_bits {
6276         u8         opcode[0x10];
6277         u8         reserved_at_10[0x10];
6278
6279         u8         reserved_at_20[0x10];
6280         u8         op_mod[0x10];
6281
6282         u8         reserved_at_40[0x8];
6283         u8         mkey_index[0x18];
6284
6285         u8         reserved_at_60[0x20];
6286 };
6287
6288 struct mlx5_ifc_destroy_flow_table_out_bits {
6289         u8         status[0x8];
6290         u8         reserved_at_8[0x18];
6291
6292         u8         syndrome[0x20];
6293
6294         u8         reserved_at_40[0x40];
6295 };
6296
6297 struct mlx5_ifc_destroy_flow_table_in_bits {
6298         u8         opcode[0x10];
6299         u8         reserved_at_10[0x10];
6300
6301         u8         reserved_at_20[0x10];
6302         u8         op_mod[0x10];
6303
6304         u8         other_vport[0x1];
6305         u8         reserved_at_41[0xf];
6306         u8         vport_number[0x10];
6307
6308         u8         reserved_at_60[0x20];
6309
6310         u8         table_type[0x8];
6311         u8         reserved_at_88[0x18];
6312
6313         u8         reserved_at_a0[0x8];
6314         u8         table_id[0x18];
6315
6316         u8         reserved_at_c0[0x140];
6317 };
6318
6319 struct mlx5_ifc_destroy_flow_group_out_bits {
6320         u8         status[0x8];
6321         u8         reserved_at_8[0x18];
6322
6323         u8         syndrome[0x20];
6324
6325         u8         reserved_at_40[0x40];
6326 };
6327
6328 struct mlx5_ifc_destroy_flow_group_in_bits {
6329         u8         opcode[0x10];
6330         u8         reserved_at_10[0x10];
6331
6332         u8         reserved_at_20[0x10];
6333         u8         op_mod[0x10];
6334
6335         u8         other_vport[0x1];
6336         u8         reserved_at_41[0xf];
6337         u8         vport_number[0x10];
6338
6339         u8         reserved_at_60[0x20];
6340
6341         u8         table_type[0x8];
6342         u8         reserved_at_88[0x18];
6343
6344         u8         reserved_at_a0[0x8];
6345         u8         table_id[0x18];
6346
6347         u8         group_id[0x20];
6348
6349         u8         reserved_at_e0[0x120];
6350 };
6351
6352 struct mlx5_ifc_destroy_eq_out_bits {
6353         u8         status[0x8];
6354         u8         reserved_at_8[0x18];
6355
6356         u8         syndrome[0x20];
6357
6358         u8         reserved_at_40[0x40];
6359 };
6360
6361 struct mlx5_ifc_destroy_eq_in_bits {
6362         u8         opcode[0x10];
6363         u8         reserved_at_10[0x10];
6364
6365         u8         reserved_at_20[0x10];
6366         u8         op_mod[0x10];
6367
6368         u8         reserved_at_40[0x18];
6369         u8         eq_number[0x8];
6370
6371         u8         reserved_at_60[0x20];
6372 };
6373
6374 struct mlx5_ifc_destroy_dct_out_bits {
6375         u8         status[0x8];
6376         u8         reserved_at_8[0x18];
6377
6378         u8         syndrome[0x20];
6379
6380         u8         reserved_at_40[0x40];
6381 };
6382
6383 struct mlx5_ifc_destroy_dct_in_bits {
6384         u8         opcode[0x10];
6385         u8         reserved_at_10[0x10];
6386
6387         u8         reserved_at_20[0x10];
6388         u8         op_mod[0x10];
6389
6390         u8         reserved_at_40[0x8];
6391         u8         dctn[0x18];
6392
6393         u8         reserved_at_60[0x20];
6394 };
6395
6396 struct mlx5_ifc_destroy_cq_out_bits {
6397         u8         status[0x8];
6398         u8         reserved_at_8[0x18];
6399
6400         u8         syndrome[0x20];
6401
6402         u8         reserved_at_40[0x40];
6403 };
6404
6405 struct mlx5_ifc_destroy_cq_in_bits {
6406         u8         opcode[0x10];
6407         u8         uid[0x10];
6408
6409         u8         reserved_at_20[0x10];
6410         u8         op_mod[0x10];
6411
6412         u8         reserved_at_40[0x8];
6413         u8         cqn[0x18];
6414
6415         u8         reserved_at_60[0x20];
6416 };
6417
6418 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6419         u8         status[0x8];
6420         u8         reserved_at_8[0x18];
6421
6422         u8         syndrome[0x20];
6423
6424         u8         reserved_at_40[0x40];
6425 };
6426
6427 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6428         u8         opcode[0x10];
6429         u8         reserved_at_10[0x10];
6430
6431         u8         reserved_at_20[0x10];
6432         u8         op_mod[0x10];
6433
6434         u8         reserved_at_40[0x20];
6435
6436         u8         reserved_at_60[0x10];
6437         u8         vxlan_udp_port[0x10];
6438 };
6439
6440 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6441         u8         status[0x8];
6442         u8         reserved_at_8[0x18];
6443
6444         u8         syndrome[0x20];
6445
6446         u8         reserved_at_40[0x40];
6447 };
6448
6449 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6450         u8         opcode[0x10];
6451         u8         reserved_at_10[0x10];
6452
6453         u8         reserved_at_20[0x10];
6454         u8         op_mod[0x10];
6455
6456         u8         reserved_at_40[0x60];
6457
6458         u8         reserved_at_a0[0x8];
6459         u8         table_index[0x18];
6460
6461         u8         reserved_at_c0[0x140];
6462 };
6463
6464 struct mlx5_ifc_delete_fte_out_bits {
6465         u8         status[0x8];
6466         u8         reserved_at_8[0x18];
6467
6468         u8         syndrome[0x20];
6469
6470         u8         reserved_at_40[0x40];
6471 };
6472
6473 struct mlx5_ifc_delete_fte_in_bits {
6474         u8         opcode[0x10];
6475         u8         reserved_at_10[0x10];
6476
6477         u8         reserved_at_20[0x10];
6478         u8         op_mod[0x10];
6479
6480         u8         other_vport[0x1];
6481         u8         reserved_at_41[0xf];
6482         u8         vport_number[0x10];
6483
6484         u8         reserved_at_60[0x20];
6485
6486         u8         table_type[0x8];
6487         u8         reserved_at_88[0x18];
6488
6489         u8         reserved_at_a0[0x8];
6490         u8         table_id[0x18];
6491
6492         u8         reserved_at_c0[0x40];
6493
6494         u8         flow_index[0x20];
6495
6496         u8         reserved_at_120[0xe0];
6497 };
6498
6499 struct mlx5_ifc_dealloc_xrcd_out_bits {
6500         u8         status[0x8];
6501         u8         reserved_at_8[0x18];
6502
6503         u8         syndrome[0x20];
6504
6505         u8         reserved_at_40[0x40];
6506 };
6507
6508 struct mlx5_ifc_dealloc_xrcd_in_bits {
6509         u8         opcode[0x10];
6510         u8         reserved_at_10[0x10];
6511
6512         u8         reserved_at_20[0x10];
6513         u8         op_mod[0x10];
6514
6515         u8         reserved_at_40[0x8];
6516         u8         xrcd[0x18];
6517
6518         u8         reserved_at_60[0x20];
6519 };
6520
6521 struct mlx5_ifc_dealloc_uar_out_bits {
6522         u8         status[0x8];
6523         u8         reserved_at_8[0x18];
6524
6525         u8         syndrome[0x20];
6526
6527         u8         reserved_at_40[0x40];
6528 };
6529
6530 struct mlx5_ifc_dealloc_uar_in_bits {
6531         u8         opcode[0x10];
6532         u8         reserved_at_10[0x10];
6533
6534         u8         reserved_at_20[0x10];
6535         u8         op_mod[0x10];
6536
6537         u8         reserved_at_40[0x8];
6538         u8         uar[0x18];
6539
6540         u8         reserved_at_60[0x20];
6541 };
6542
6543 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6544         u8         status[0x8];
6545         u8         reserved_at_8[0x18];
6546
6547         u8         syndrome[0x20];
6548
6549         u8         reserved_at_40[0x40];
6550 };
6551
6552 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6553         u8         opcode[0x10];
6554         u8         reserved_at_10[0x10];
6555
6556         u8         reserved_at_20[0x10];
6557         u8         op_mod[0x10];
6558
6559         u8         reserved_at_40[0x8];
6560         u8         transport_domain[0x18];
6561
6562         u8         reserved_at_60[0x20];
6563 };
6564
6565 struct mlx5_ifc_dealloc_q_counter_out_bits {
6566         u8         status[0x8];
6567         u8         reserved_at_8[0x18];
6568
6569         u8         syndrome[0x20];
6570
6571         u8         reserved_at_40[0x40];
6572 };
6573
6574 struct mlx5_ifc_dealloc_q_counter_in_bits {
6575         u8         opcode[0x10];
6576         u8         reserved_at_10[0x10];
6577
6578         u8         reserved_at_20[0x10];
6579         u8         op_mod[0x10];
6580
6581         u8         reserved_at_40[0x18];
6582         u8         counter_set_id[0x8];
6583
6584         u8         reserved_at_60[0x20];
6585 };
6586
6587 struct mlx5_ifc_dealloc_pd_out_bits {
6588         u8         status[0x8];
6589         u8         reserved_at_8[0x18];
6590
6591         u8         syndrome[0x20];
6592
6593         u8         reserved_at_40[0x40];
6594 };
6595
6596 struct mlx5_ifc_dealloc_pd_in_bits {
6597         u8         opcode[0x10];
6598         u8         reserved_at_10[0x10];
6599
6600         u8         reserved_at_20[0x10];
6601         u8         op_mod[0x10];
6602
6603         u8         reserved_at_40[0x8];
6604         u8         pd[0x18];
6605
6606         u8         reserved_at_60[0x20];
6607 };
6608
6609 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6610         u8         status[0x8];
6611         u8         reserved_at_8[0x18];
6612
6613         u8         syndrome[0x20];
6614
6615         u8         reserved_at_40[0x40];
6616 };
6617
6618 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6619         u8         opcode[0x10];
6620         u8         reserved_at_10[0x10];
6621
6622         u8         reserved_at_20[0x10];
6623         u8         op_mod[0x10];
6624
6625         u8         flow_counter_id[0x20];
6626
6627         u8         reserved_at_60[0x20];
6628 };
6629
6630 struct mlx5_ifc_create_xrq_out_bits {
6631         u8         status[0x8];
6632         u8         reserved_at_8[0x18];
6633
6634         u8         syndrome[0x20];
6635
6636         u8         reserved_at_40[0x8];
6637         u8         xrqn[0x18];
6638
6639         u8         reserved_at_60[0x20];
6640 };
6641
6642 struct mlx5_ifc_create_xrq_in_bits {
6643         u8         opcode[0x10];
6644         u8         reserved_at_10[0x10];
6645
6646         u8         reserved_at_20[0x10];
6647         u8         op_mod[0x10];
6648
6649         u8         reserved_at_40[0x40];
6650
6651         struct mlx5_ifc_xrqc_bits xrq_context;
6652 };
6653
6654 struct mlx5_ifc_create_xrc_srq_out_bits {
6655         u8         status[0x8];
6656         u8         reserved_at_8[0x18];
6657
6658         u8         syndrome[0x20];
6659
6660         u8         reserved_at_40[0x8];
6661         u8         xrc_srqn[0x18];
6662
6663         u8         reserved_at_60[0x20];
6664 };
6665
6666 struct mlx5_ifc_create_xrc_srq_in_bits {
6667         u8         opcode[0x10];
6668         u8         reserved_at_10[0x10];
6669
6670         u8         reserved_at_20[0x10];
6671         u8         op_mod[0x10];
6672
6673         u8         reserved_at_40[0x40];
6674
6675         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6676
6677         u8         reserved_at_280[0x600];
6678
6679         u8         pas[0][0x40];
6680 };
6681
6682 struct mlx5_ifc_create_tis_out_bits {
6683         u8         status[0x8];
6684         u8         reserved_at_8[0x18];
6685
6686         u8         syndrome[0x20];
6687
6688         u8         reserved_at_40[0x8];
6689         u8         tisn[0x18];
6690
6691         u8         reserved_at_60[0x20];
6692 };
6693
6694 struct mlx5_ifc_create_tis_in_bits {
6695         u8         opcode[0x10];
6696         u8         reserved_at_10[0x10];
6697
6698         u8         reserved_at_20[0x10];
6699         u8         op_mod[0x10];
6700
6701         u8         reserved_at_40[0xc0];
6702
6703         struct mlx5_ifc_tisc_bits ctx;
6704 };
6705
6706 struct mlx5_ifc_create_tir_out_bits {
6707         u8         status[0x8];
6708         u8         reserved_at_8[0x18];
6709
6710         u8         syndrome[0x20];
6711
6712         u8         reserved_at_40[0x8];
6713         u8         tirn[0x18];
6714
6715         u8         reserved_at_60[0x20];
6716 };
6717
6718 struct mlx5_ifc_create_tir_in_bits {
6719         u8         opcode[0x10];
6720         u8         reserved_at_10[0x10];
6721
6722         u8         reserved_at_20[0x10];
6723         u8         op_mod[0x10];
6724
6725         u8         reserved_at_40[0xc0];
6726
6727         struct mlx5_ifc_tirc_bits ctx;
6728 };
6729
6730 struct mlx5_ifc_create_srq_out_bits {
6731         u8         status[0x8];
6732         u8         reserved_at_8[0x18];
6733
6734         u8         syndrome[0x20];
6735
6736         u8         reserved_at_40[0x8];
6737         u8         srqn[0x18];
6738
6739         u8         reserved_at_60[0x20];
6740 };
6741
6742 struct mlx5_ifc_create_srq_in_bits {
6743         u8         opcode[0x10];
6744         u8         reserved_at_10[0x10];
6745
6746         u8         reserved_at_20[0x10];
6747         u8         op_mod[0x10];
6748
6749         u8         reserved_at_40[0x40];
6750
6751         struct mlx5_ifc_srqc_bits srq_context_entry;
6752
6753         u8         reserved_at_280[0x600];
6754
6755         u8         pas[0][0x40];
6756 };
6757
6758 struct mlx5_ifc_create_sq_out_bits {
6759         u8         status[0x8];
6760         u8         reserved_at_8[0x18];
6761
6762         u8         syndrome[0x20];
6763
6764         u8         reserved_at_40[0x8];
6765         u8         sqn[0x18];
6766
6767         u8         reserved_at_60[0x20];
6768 };
6769
6770 struct mlx5_ifc_create_sq_in_bits {
6771         u8         opcode[0x10];
6772         u8         reserved_at_10[0x10];
6773
6774         u8         reserved_at_20[0x10];
6775         u8         op_mod[0x10];
6776
6777         u8         reserved_at_40[0xc0];
6778
6779         struct mlx5_ifc_sqc_bits ctx;
6780 };
6781
6782 struct mlx5_ifc_create_scheduling_element_out_bits {
6783         u8         status[0x8];
6784         u8         reserved_at_8[0x18];
6785
6786         u8         syndrome[0x20];
6787
6788         u8         reserved_at_40[0x40];
6789
6790         u8         scheduling_element_id[0x20];
6791
6792         u8         reserved_at_a0[0x160];
6793 };
6794
6795 struct mlx5_ifc_create_scheduling_element_in_bits {
6796         u8         opcode[0x10];
6797         u8         reserved_at_10[0x10];
6798
6799         u8         reserved_at_20[0x10];
6800         u8         op_mod[0x10];
6801
6802         u8         scheduling_hierarchy[0x8];
6803         u8         reserved_at_48[0x18];
6804
6805         u8         reserved_at_60[0xa0];
6806
6807         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6808
6809         u8         reserved_at_300[0x100];
6810 };
6811
6812 struct mlx5_ifc_create_rqt_out_bits {
6813         u8         status[0x8];
6814         u8         reserved_at_8[0x18];
6815
6816         u8         syndrome[0x20];
6817
6818         u8         reserved_at_40[0x8];
6819         u8         rqtn[0x18];
6820
6821         u8         reserved_at_60[0x20];
6822 };
6823
6824 struct mlx5_ifc_create_rqt_in_bits {
6825         u8         opcode[0x10];
6826         u8         reserved_at_10[0x10];
6827
6828         u8         reserved_at_20[0x10];
6829         u8         op_mod[0x10];
6830
6831         u8         reserved_at_40[0xc0];
6832
6833         struct mlx5_ifc_rqtc_bits rqt_context;
6834 };
6835
6836 struct mlx5_ifc_create_rq_out_bits {
6837         u8         status[0x8];
6838         u8         reserved_at_8[0x18];
6839
6840         u8         syndrome[0x20];
6841
6842         u8         reserved_at_40[0x8];
6843         u8         rqn[0x18];
6844
6845         u8         reserved_at_60[0x20];
6846 };
6847
6848 struct mlx5_ifc_create_rq_in_bits {
6849         u8         opcode[0x10];
6850         u8         reserved_at_10[0x10];
6851
6852         u8         reserved_at_20[0x10];
6853         u8         op_mod[0x10];
6854
6855         u8         reserved_at_40[0xc0];
6856
6857         struct mlx5_ifc_rqc_bits ctx;
6858 };
6859
6860 struct mlx5_ifc_create_rmp_out_bits {
6861         u8         status[0x8];
6862         u8         reserved_at_8[0x18];
6863
6864         u8         syndrome[0x20];
6865
6866         u8         reserved_at_40[0x8];
6867         u8         rmpn[0x18];
6868
6869         u8         reserved_at_60[0x20];
6870 };
6871
6872 struct mlx5_ifc_create_rmp_in_bits {
6873         u8         opcode[0x10];
6874         u8         reserved_at_10[0x10];
6875
6876         u8         reserved_at_20[0x10];
6877         u8         op_mod[0x10];
6878
6879         u8         reserved_at_40[0xc0];
6880
6881         struct mlx5_ifc_rmpc_bits ctx;
6882 };
6883
6884 struct mlx5_ifc_create_qp_out_bits {
6885         u8         status[0x8];
6886         u8         reserved_at_8[0x18];
6887
6888         u8         syndrome[0x20];
6889
6890         u8         reserved_at_40[0x8];
6891         u8         qpn[0x18];
6892
6893         u8         reserved_at_60[0x20];
6894 };
6895
6896 struct mlx5_ifc_create_qp_in_bits {
6897         u8         opcode[0x10];
6898         u8         uid[0x10];
6899
6900         u8         reserved_at_20[0x10];
6901         u8         op_mod[0x10];
6902
6903         u8         reserved_at_40[0x40];
6904
6905         u8         opt_param_mask[0x20];
6906
6907         u8         reserved_at_a0[0x20];
6908
6909         struct mlx5_ifc_qpc_bits qpc;
6910
6911         u8         reserved_at_800[0x80];
6912
6913         u8         pas[0][0x40];
6914 };
6915
6916 struct mlx5_ifc_create_psv_out_bits {
6917         u8         status[0x8];
6918         u8         reserved_at_8[0x18];
6919
6920         u8         syndrome[0x20];
6921
6922         u8         reserved_at_40[0x40];
6923
6924         u8         reserved_at_80[0x8];
6925         u8         psv0_index[0x18];
6926
6927         u8         reserved_at_a0[0x8];
6928         u8         psv1_index[0x18];
6929
6930         u8         reserved_at_c0[0x8];
6931         u8         psv2_index[0x18];
6932
6933         u8         reserved_at_e0[0x8];
6934         u8         psv3_index[0x18];
6935 };
6936
6937 struct mlx5_ifc_create_psv_in_bits {
6938         u8         opcode[0x10];
6939         u8         reserved_at_10[0x10];
6940
6941         u8         reserved_at_20[0x10];
6942         u8         op_mod[0x10];
6943
6944         u8         num_psv[0x4];
6945         u8         reserved_at_44[0x4];
6946         u8         pd[0x18];
6947
6948         u8         reserved_at_60[0x20];
6949 };
6950
6951 struct mlx5_ifc_create_mkey_out_bits {
6952         u8         status[0x8];
6953         u8         reserved_at_8[0x18];
6954
6955         u8         syndrome[0x20];
6956
6957         u8         reserved_at_40[0x8];
6958         u8         mkey_index[0x18];
6959
6960         u8         reserved_at_60[0x20];
6961 };
6962
6963 struct mlx5_ifc_create_mkey_in_bits {
6964         u8         opcode[0x10];
6965         u8         reserved_at_10[0x10];
6966
6967         u8         reserved_at_20[0x10];
6968         u8         op_mod[0x10];
6969
6970         u8         reserved_at_40[0x20];
6971
6972         u8         pg_access[0x1];
6973         u8         reserved_at_61[0x1f];
6974
6975         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6976
6977         u8         reserved_at_280[0x80];
6978
6979         u8         translations_octword_actual_size[0x20];
6980
6981         u8         reserved_at_320[0x560];
6982
6983         u8         klm_pas_mtt[0][0x20];
6984 };
6985
6986 struct mlx5_ifc_create_flow_table_out_bits {
6987         u8         status[0x8];
6988         u8         reserved_at_8[0x18];
6989
6990         u8         syndrome[0x20];
6991
6992         u8         reserved_at_40[0x8];
6993         u8         table_id[0x18];
6994
6995         u8         reserved_at_60[0x20];
6996 };
6997
6998 struct mlx5_ifc_flow_table_context_bits {
6999         u8         reformat_en[0x1];
7000         u8         decap_en[0x1];
7001         u8         reserved_at_2[0x2];
7002         u8         table_miss_action[0x4];
7003         u8         level[0x8];
7004         u8         reserved_at_10[0x8];
7005         u8         log_size[0x8];
7006
7007         u8         reserved_at_20[0x8];
7008         u8         table_miss_id[0x18];
7009
7010         u8         reserved_at_40[0x8];
7011         u8         lag_master_next_table_id[0x18];
7012
7013         u8         reserved_at_60[0xe0];
7014 };
7015
7016 struct mlx5_ifc_create_flow_table_in_bits {
7017         u8         opcode[0x10];
7018         u8         reserved_at_10[0x10];
7019
7020         u8         reserved_at_20[0x10];
7021         u8         op_mod[0x10];
7022
7023         u8         other_vport[0x1];
7024         u8         reserved_at_41[0xf];
7025         u8         vport_number[0x10];
7026
7027         u8         reserved_at_60[0x20];
7028
7029         u8         table_type[0x8];
7030         u8         reserved_at_88[0x18];
7031
7032         u8         reserved_at_a0[0x20];
7033
7034         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7035 };
7036
7037 struct mlx5_ifc_create_flow_group_out_bits {
7038         u8         status[0x8];
7039         u8         reserved_at_8[0x18];
7040
7041         u8         syndrome[0x20];
7042
7043         u8         reserved_at_40[0x8];
7044         u8         group_id[0x18];
7045
7046         u8         reserved_at_60[0x20];
7047 };
7048
7049 enum {
7050         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7051         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7052         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7053         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7054 };
7055
7056 struct mlx5_ifc_create_flow_group_in_bits {
7057         u8         opcode[0x10];
7058         u8         reserved_at_10[0x10];
7059
7060         u8         reserved_at_20[0x10];
7061         u8         op_mod[0x10];
7062
7063         u8         other_vport[0x1];
7064         u8         reserved_at_41[0xf];
7065         u8         vport_number[0x10];
7066
7067         u8         reserved_at_60[0x20];
7068
7069         u8         table_type[0x8];
7070         u8         reserved_at_88[0x18];
7071
7072         u8         reserved_at_a0[0x8];
7073         u8         table_id[0x18];
7074
7075         u8         source_eswitch_owner_vhca_id_valid[0x1];
7076
7077         u8         reserved_at_c1[0x1f];
7078
7079         u8         start_flow_index[0x20];
7080
7081         u8         reserved_at_100[0x20];
7082
7083         u8         end_flow_index[0x20];
7084
7085         u8         reserved_at_140[0xa0];
7086
7087         u8         reserved_at_1e0[0x18];
7088         u8         match_criteria_enable[0x8];
7089
7090         struct mlx5_ifc_fte_match_param_bits match_criteria;
7091
7092         u8         reserved_at_1200[0xe00];
7093 };
7094
7095 struct mlx5_ifc_create_eq_out_bits {
7096         u8         status[0x8];
7097         u8         reserved_at_8[0x18];
7098
7099         u8         syndrome[0x20];
7100
7101         u8         reserved_at_40[0x18];
7102         u8         eq_number[0x8];
7103
7104         u8         reserved_at_60[0x20];
7105 };
7106
7107 struct mlx5_ifc_create_eq_in_bits {
7108         u8         opcode[0x10];
7109         u8         reserved_at_10[0x10];
7110
7111         u8         reserved_at_20[0x10];
7112         u8         op_mod[0x10];
7113
7114         u8         reserved_at_40[0x40];
7115
7116         struct mlx5_ifc_eqc_bits eq_context_entry;
7117
7118         u8         reserved_at_280[0x40];
7119
7120         u8         event_bitmask[0x40];
7121
7122         u8         reserved_at_300[0x580];
7123
7124         u8         pas[0][0x40];
7125 };
7126
7127 struct mlx5_ifc_create_dct_out_bits {
7128         u8         status[0x8];
7129         u8         reserved_at_8[0x18];
7130
7131         u8         syndrome[0x20];
7132
7133         u8         reserved_at_40[0x8];
7134         u8         dctn[0x18];
7135
7136         u8         reserved_at_60[0x20];
7137 };
7138
7139 struct mlx5_ifc_create_dct_in_bits {
7140         u8         opcode[0x10];
7141         u8         reserved_at_10[0x10];
7142
7143         u8         reserved_at_20[0x10];
7144         u8         op_mod[0x10];
7145
7146         u8         reserved_at_40[0x40];
7147
7148         struct mlx5_ifc_dctc_bits dct_context_entry;
7149
7150         u8         reserved_at_280[0x180];
7151 };
7152
7153 struct mlx5_ifc_create_cq_out_bits {
7154         u8         status[0x8];
7155         u8         reserved_at_8[0x18];
7156
7157         u8         syndrome[0x20];
7158
7159         u8         reserved_at_40[0x8];
7160         u8         cqn[0x18];
7161
7162         u8         reserved_at_60[0x20];
7163 };
7164
7165 struct mlx5_ifc_create_cq_in_bits {
7166         u8         opcode[0x10];
7167         u8         uid[0x10];
7168
7169         u8         reserved_at_20[0x10];
7170         u8         op_mod[0x10];
7171
7172         u8         reserved_at_40[0x40];
7173
7174         struct mlx5_ifc_cqc_bits cq_context;
7175
7176         u8         reserved_at_280[0x600];
7177
7178         u8         pas[0][0x40];
7179 };
7180
7181 struct mlx5_ifc_config_int_moderation_out_bits {
7182         u8         status[0x8];
7183         u8         reserved_at_8[0x18];
7184
7185         u8         syndrome[0x20];
7186
7187         u8         reserved_at_40[0x4];
7188         u8         min_delay[0xc];
7189         u8         int_vector[0x10];
7190
7191         u8         reserved_at_60[0x20];
7192 };
7193
7194 enum {
7195         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7196         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7197 };
7198
7199 struct mlx5_ifc_config_int_moderation_in_bits {
7200         u8         opcode[0x10];
7201         u8         reserved_at_10[0x10];
7202
7203         u8         reserved_at_20[0x10];
7204         u8         op_mod[0x10];
7205
7206         u8         reserved_at_40[0x4];
7207         u8         min_delay[0xc];
7208         u8         int_vector[0x10];
7209
7210         u8         reserved_at_60[0x20];
7211 };
7212
7213 struct mlx5_ifc_attach_to_mcg_out_bits {
7214         u8         status[0x8];
7215         u8         reserved_at_8[0x18];
7216
7217         u8         syndrome[0x20];
7218
7219         u8         reserved_at_40[0x40];
7220 };
7221
7222 struct mlx5_ifc_attach_to_mcg_in_bits {
7223         u8         opcode[0x10];
7224         u8         reserved_at_10[0x10];
7225
7226         u8         reserved_at_20[0x10];
7227         u8         op_mod[0x10];
7228
7229         u8         reserved_at_40[0x8];
7230         u8         qpn[0x18];
7231
7232         u8         reserved_at_60[0x20];
7233
7234         u8         multicast_gid[16][0x8];
7235 };
7236
7237 struct mlx5_ifc_arm_xrq_out_bits {
7238         u8         status[0x8];
7239         u8         reserved_at_8[0x18];
7240
7241         u8         syndrome[0x20];
7242
7243         u8         reserved_at_40[0x40];
7244 };
7245
7246 struct mlx5_ifc_arm_xrq_in_bits {
7247         u8         opcode[0x10];
7248         u8         reserved_at_10[0x10];
7249
7250         u8         reserved_at_20[0x10];
7251         u8         op_mod[0x10];
7252
7253         u8         reserved_at_40[0x8];
7254         u8         xrqn[0x18];
7255
7256         u8         reserved_at_60[0x10];
7257         u8         lwm[0x10];
7258 };
7259
7260 struct mlx5_ifc_arm_xrc_srq_out_bits {
7261         u8         status[0x8];
7262         u8         reserved_at_8[0x18];
7263
7264         u8         syndrome[0x20];
7265
7266         u8         reserved_at_40[0x40];
7267 };
7268
7269 enum {
7270         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7271 };
7272
7273 struct mlx5_ifc_arm_xrc_srq_in_bits {
7274         u8         opcode[0x10];
7275         u8         reserved_at_10[0x10];
7276
7277         u8         reserved_at_20[0x10];
7278         u8         op_mod[0x10];
7279
7280         u8         reserved_at_40[0x8];
7281         u8         xrc_srqn[0x18];
7282
7283         u8         reserved_at_60[0x10];
7284         u8         lwm[0x10];
7285 };
7286
7287 struct mlx5_ifc_arm_rq_out_bits {
7288         u8         status[0x8];
7289         u8         reserved_at_8[0x18];
7290
7291         u8         syndrome[0x20];
7292
7293         u8         reserved_at_40[0x40];
7294 };
7295
7296 enum {
7297         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7298         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7299 };
7300
7301 struct mlx5_ifc_arm_rq_in_bits {
7302         u8         opcode[0x10];
7303         u8         reserved_at_10[0x10];
7304
7305         u8         reserved_at_20[0x10];
7306         u8         op_mod[0x10];
7307
7308         u8         reserved_at_40[0x8];
7309         u8         srq_number[0x18];
7310
7311         u8         reserved_at_60[0x10];
7312         u8         lwm[0x10];
7313 };
7314
7315 struct mlx5_ifc_arm_dct_out_bits {
7316         u8         status[0x8];
7317         u8         reserved_at_8[0x18];
7318
7319         u8         syndrome[0x20];
7320
7321         u8         reserved_at_40[0x40];
7322 };
7323
7324 struct mlx5_ifc_arm_dct_in_bits {
7325         u8         opcode[0x10];
7326         u8         reserved_at_10[0x10];
7327
7328         u8         reserved_at_20[0x10];
7329         u8         op_mod[0x10];
7330
7331         u8         reserved_at_40[0x8];
7332         u8         dct_number[0x18];
7333
7334         u8         reserved_at_60[0x20];
7335 };
7336
7337 struct mlx5_ifc_alloc_xrcd_out_bits {
7338         u8         status[0x8];
7339         u8         reserved_at_8[0x18];
7340
7341         u8         syndrome[0x20];
7342
7343         u8         reserved_at_40[0x8];
7344         u8         xrcd[0x18];
7345
7346         u8         reserved_at_60[0x20];
7347 };
7348
7349 struct mlx5_ifc_alloc_xrcd_in_bits {
7350         u8         opcode[0x10];
7351         u8         reserved_at_10[0x10];
7352
7353         u8         reserved_at_20[0x10];
7354         u8         op_mod[0x10];
7355
7356         u8         reserved_at_40[0x40];
7357 };
7358
7359 struct mlx5_ifc_alloc_uar_out_bits {
7360         u8         status[0x8];
7361         u8         reserved_at_8[0x18];
7362
7363         u8         syndrome[0x20];
7364
7365         u8         reserved_at_40[0x8];
7366         u8         uar[0x18];
7367
7368         u8         reserved_at_60[0x20];
7369 };
7370
7371 struct mlx5_ifc_alloc_uar_in_bits {
7372         u8         opcode[0x10];
7373         u8         reserved_at_10[0x10];
7374
7375         u8         reserved_at_20[0x10];
7376         u8         op_mod[0x10];
7377
7378         u8         reserved_at_40[0x40];
7379 };
7380
7381 struct mlx5_ifc_alloc_transport_domain_out_bits {
7382         u8         status[0x8];
7383         u8         reserved_at_8[0x18];
7384
7385         u8         syndrome[0x20];
7386
7387         u8         reserved_at_40[0x8];
7388         u8         transport_domain[0x18];
7389
7390         u8         reserved_at_60[0x20];
7391 };
7392
7393 struct mlx5_ifc_alloc_transport_domain_in_bits {
7394         u8         opcode[0x10];
7395         u8         reserved_at_10[0x10];
7396
7397         u8         reserved_at_20[0x10];
7398         u8         op_mod[0x10];
7399
7400         u8         reserved_at_40[0x40];
7401 };
7402
7403 struct mlx5_ifc_alloc_q_counter_out_bits {
7404         u8         status[0x8];
7405         u8         reserved_at_8[0x18];
7406
7407         u8         syndrome[0x20];
7408
7409         u8         reserved_at_40[0x18];
7410         u8         counter_set_id[0x8];
7411
7412         u8         reserved_at_60[0x20];
7413 };
7414
7415 struct mlx5_ifc_alloc_q_counter_in_bits {
7416         u8         opcode[0x10];
7417         u8         reserved_at_10[0x10];
7418
7419         u8         reserved_at_20[0x10];
7420         u8         op_mod[0x10];
7421
7422         u8         reserved_at_40[0x40];
7423 };
7424
7425 struct mlx5_ifc_alloc_pd_out_bits {
7426         u8         status[0x8];
7427         u8         reserved_at_8[0x18];
7428
7429         u8         syndrome[0x20];
7430
7431         u8         reserved_at_40[0x8];
7432         u8         pd[0x18];
7433
7434         u8         reserved_at_60[0x20];
7435 };
7436
7437 struct mlx5_ifc_alloc_pd_in_bits {
7438         u8         opcode[0x10];
7439         u8         reserved_at_10[0x10];
7440
7441         u8         reserved_at_20[0x10];
7442         u8         op_mod[0x10];
7443
7444         u8         reserved_at_40[0x40];
7445 };
7446
7447 struct mlx5_ifc_alloc_flow_counter_out_bits {
7448         u8         status[0x8];
7449         u8         reserved_at_8[0x18];
7450
7451         u8         syndrome[0x20];
7452
7453         u8         flow_counter_id[0x20];
7454
7455         u8         reserved_at_60[0x20];
7456 };
7457
7458 struct mlx5_ifc_alloc_flow_counter_in_bits {
7459         u8         opcode[0x10];
7460         u8         reserved_at_10[0x10];
7461
7462         u8         reserved_at_20[0x10];
7463         u8         op_mod[0x10];
7464
7465         u8         reserved_at_40[0x40];
7466 };
7467
7468 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7469         u8         status[0x8];
7470         u8         reserved_at_8[0x18];
7471
7472         u8         syndrome[0x20];
7473
7474         u8         reserved_at_40[0x40];
7475 };
7476
7477 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7478         u8         opcode[0x10];
7479         u8         reserved_at_10[0x10];
7480
7481         u8         reserved_at_20[0x10];
7482         u8         op_mod[0x10];
7483
7484         u8         reserved_at_40[0x20];
7485
7486         u8         reserved_at_60[0x10];
7487         u8         vxlan_udp_port[0x10];
7488 };
7489
7490 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7491         u8         status[0x8];
7492         u8         reserved_at_8[0x18];
7493
7494         u8         syndrome[0x20];
7495
7496         u8         reserved_at_40[0x40];
7497 };
7498
7499 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7500         u8         opcode[0x10];
7501         u8         reserved_at_10[0x10];
7502
7503         u8         reserved_at_20[0x10];
7504         u8         op_mod[0x10];
7505
7506         u8         reserved_at_40[0x10];
7507         u8         rate_limit_index[0x10];
7508
7509         u8         reserved_at_60[0x20];
7510
7511         u8         rate_limit[0x20];
7512
7513         u8         burst_upper_bound[0x20];
7514
7515         u8         reserved_at_c0[0x10];
7516         u8         typical_packet_size[0x10];
7517
7518         u8         reserved_at_e0[0x120];
7519 };
7520
7521 struct mlx5_ifc_access_register_out_bits {
7522         u8         status[0x8];
7523         u8         reserved_at_8[0x18];
7524
7525         u8         syndrome[0x20];
7526
7527         u8         reserved_at_40[0x40];
7528
7529         u8         register_data[0][0x20];
7530 };
7531
7532 enum {
7533         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7534         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7535 };
7536
7537 struct mlx5_ifc_access_register_in_bits {
7538         u8         opcode[0x10];
7539         u8         reserved_at_10[0x10];
7540
7541         u8         reserved_at_20[0x10];
7542         u8         op_mod[0x10];
7543
7544         u8         reserved_at_40[0x10];
7545         u8         register_id[0x10];
7546
7547         u8         argument[0x20];
7548
7549         u8         register_data[0][0x20];
7550 };
7551
7552 struct mlx5_ifc_sltp_reg_bits {
7553         u8         status[0x4];
7554         u8         version[0x4];
7555         u8         local_port[0x8];
7556         u8         pnat[0x2];
7557         u8         reserved_at_12[0x2];
7558         u8         lane[0x4];
7559         u8         reserved_at_18[0x8];
7560
7561         u8         reserved_at_20[0x20];
7562
7563         u8         reserved_at_40[0x7];
7564         u8         polarity[0x1];
7565         u8         ob_tap0[0x8];
7566         u8         ob_tap1[0x8];
7567         u8         ob_tap2[0x8];
7568
7569         u8         reserved_at_60[0xc];
7570         u8         ob_preemp_mode[0x4];
7571         u8         ob_reg[0x8];
7572         u8         ob_bias[0x8];
7573
7574         u8         reserved_at_80[0x20];
7575 };
7576
7577 struct mlx5_ifc_slrg_reg_bits {
7578         u8         status[0x4];
7579         u8         version[0x4];
7580         u8         local_port[0x8];
7581         u8         pnat[0x2];
7582         u8         reserved_at_12[0x2];
7583         u8         lane[0x4];
7584         u8         reserved_at_18[0x8];
7585
7586         u8         time_to_link_up[0x10];
7587         u8         reserved_at_30[0xc];
7588         u8         grade_lane_speed[0x4];
7589
7590         u8         grade_version[0x8];
7591         u8         grade[0x18];
7592
7593         u8         reserved_at_60[0x4];
7594         u8         height_grade_type[0x4];
7595         u8         height_grade[0x18];
7596
7597         u8         height_dz[0x10];
7598         u8         height_dv[0x10];
7599
7600         u8         reserved_at_a0[0x10];
7601         u8         height_sigma[0x10];
7602
7603         u8         reserved_at_c0[0x20];
7604
7605         u8         reserved_at_e0[0x4];
7606         u8         phase_grade_type[0x4];
7607         u8         phase_grade[0x18];
7608
7609         u8         reserved_at_100[0x8];
7610         u8         phase_eo_pos[0x8];
7611         u8         reserved_at_110[0x8];
7612         u8         phase_eo_neg[0x8];
7613
7614         u8         ffe_set_tested[0x10];
7615         u8         test_errors_per_lane[0x10];
7616 };
7617
7618 struct mlx5_ifc_pvlc_reg_bits {
7619         u8         reserved_at_0[0x8];
7620         u8         local_port[0x8];
7621         u8         reserved_at_10[0x10];
7622
7623         u8         reserved_at_20[0x1c];
7624         u8         vl_hw_cap[0x4];
7625
7626         u8         reserved_at_40[0x1c];
7627         u8         vl_admin[0x4];
7628
7629         u8         reserved_at_60[0x1c];
7630         u8         vl_operational[0x4];
7631 };
7632
7633 struct mlx5_ifc_pude_reg_bits {
7634         u8         swid[0x8];
7635         u8         local_port[0x8];
7636         u8         reserved_at_10[0x4];
7637         u8         admin_status[0x4];
7638         u8         reserved_at_18[0x4];
7639         u8         oper_status[0x4];
7640
7641         u8         reserved_at_20[0x60];
7642 };
7643
7644 struct mlx5_ifc_ptys_reg_bits {
7645         u8         reserved_at_0[0x1];
7646         u8         an_disable_admin[0x1];
7647         u8         an_disable_cap[0x1];
7648         u8         reserved_at_3[0x5];
7649         u8         local_port[0x8];
7650         u8         reserved_at_10[0xd];
7651         u8         proto_mask[0x3];
7652
7653         u8         an_status[0x4];
7654         u8         reserved_at_24[0x3c];
7655
7656         u8         eth_proto_capability[0x20];
7657
7658         u8         ib_link_width_capability[0x10];
7659         u8         ib_proto_capability[0x10];
7660
7661         u8         reserved_at_a0[0x20];
7662
7663         u8         eth_proto_admin[0x20];
7664
7665         u8         ib_link_width_admin[0x10];
7666         u8         ib_proto_admin[0x10];
7667
7668         u8         reserved_at_100[0x20];
7669
7670         u8         eth_proto_oper[0x20];
7671
7672         u8         ib_link_width_oper[0x10];
7673         u8         ib_proto_oper[0x10];
7674
7675         u8         reserved_at_160[0x1c];
7676         u8         connector_type[0x4];
7677
7678         u8         eth_proto_lp_advertise[0x20];
7679
7680         u8         reserved_at_1a0[0x60];
7681 };
7682
7683 struct mlx5_ifc_mlcr_reg_bits {
7684         u8         reserved_at_0[0x8];
7685         u8         local_port[0x8];
7686         u8         reserved_at_10[0x20];
7687
7688         u8         beacon_duration[0x10];
7689         u8         reserved_at_40[0x10];
7690
7691         u8         beacon_remain[0x10];
7692 };
7693
7694 struct mlx5_ifc_ptas_reg_bits {
7695         u8         reserved_at_0[0x20];
7696
7697         u8         algorithm_options[0x10];
7698         u8         reserved_at_30[0x4];
7699         u8         repetitions_mode[0x4];
7700         u8         num_of_repetitions[0x8];
7701
7702         u8         grade_version[0x8];
7703         u8         height_grade_type[0x4];
7704         u8         phase_grade_type[0x4];
7705         u8         height_grade_weight[0x8];
7706         u8         phase_grade_weight[0x8];
7707
7708         u8         gisim_measure_bits[0x10];
7709         u8         adaptive_tap_measure_bits[0x10];
7710
7711         u8         ber_bath_high_error_threshold[0x10];
7712         u8         ber_bath_mid_error_threshold[0x10];
7713
7714         u8         ber_bath_low_error_threshold[0x10];
7715         u8         one_ratio_high_threshold[0x10];
7716
7717         u8         one_ratio_high_mid_threshold[0x10];
7718         u8         one_ratio_low_mid_threshold[0x10];
7719
7720         u8         one_ratio_low_threshold[0x10];
7721         u8         ndeo_error_threshold[0x10];
7722
7723         u8         mixer_offset_step_size[0x10];
7724         u8         reserved_at_110[0x8];
7725         u8         mix90_phase_for_voltage_bath[0x8];
7726
7727         u8         mixer_offset_start[0x10];
7728         u8         mixer_offset_end[0x10];
7729
7730         u8         reserved_at_140[0x15];
7731         u8         ber_test_time[0xb];
7732 };
7733
7734 struct mlx5_ifc_pspa_reg_bits {
7735         u8         swid[0x8];
7736         u8         local_port[0x8];
7737         u8         sub_port[0x8];
7738         u8         reserved_at_18[0x8];
7739
7740         u8         reserved_at_20[0x20];
7741 };
7742
7743 struct mlx5_ifc_pqdr_reg_bits {
7744         u8         reserved_at_0[0x8];
7745         u8         local_port[0x8];
7746         u8         reserved_at_10[0x5];
7747         u8         prio[0x3];
7748         u8         reserved_at_18[0x6];
7749         u8         mode[0x2];
7750
7751         u8         reserved_at_20[0x20];
7752
7753         u8         reserved_at_40[0x10];
7754         u8         min_threshold[0x10];
7755
7756         u8         reserved_at_60[0x10];
7757         u8         max_threshold[0x10];
7758
7759         u8         reserved_at_80[0x10];
7760         u8         mark_probability_denominator[0x10];
7761
7762         u8         reserved_at_a0[0x60];
7763 };
7764
7765 struct mlx5_ifc_ppsc_reg_bits {
7766         u8         reserved_at_0[0x8];
7767         u8         local_port[0x8];
7768         u8         reserved_at_10[0x10];
7769
7770         u8         reserved_at_20[0x60];
7771
7772         u8         reserved_at_80[0x1c];
7773         u8         wrps_admin[0x4];
7774
7775         u8         reserved_at_a0[0x1c];
7776         u8         wrps_status[0x4];
7777
7778         u8         reserved_at_c0[0x8];
7779         u8         up_threshold[0x8];
7780         u8         reserved_at_d0[0x8];
7781         u8         down_threshold[0x8];
7782
7783         u8         reserved_at_e0[0x20];
7784
7785         u8         reserved_at_100[0x1c];
7786         u8         srps_admin[0x4];
7787
7788         u8         reserved_at_120[0x1c];
7789         u8         srps_status[0x4];
7790
7791         u8         reserved_at_140[0x40];
7792 };
7793
7794 struct mlx5_ifc_pplr_reg_bits {
7795         u8         reserved_at_0[0x8];
7796         u8         local_port[0x8];
7797         u8         reserved_at_10[0x10];
7798
7799         u8         reserved_at_20[0x8];
7800         u8         lb_cap[0x8];
7801         u8         reserved_at_30[0x8];
7802         u8         lb_en[0x8];
7803 };
7804
7805 struct mlx5_ifc_pplm_reg_bits {
7806         u8         reserved_at_0[0x8];
7807         u8         local_port[0x8];
7808         u8         reserved_at_10[0x10];
7809
7810         u8         reserved_at_20[0x20];
7811
7812         u8         port_profile_mode[0x8];
7813         u8         static_port_profile[0x8];
7814         u8         active_port_profile[0x8];
7815         u8         reserved_at_58[0x8];
7816
7817         u8         retransmission_active[0x8];
7818         u8         fec_mode_active[0x18];
7819
7820         u8         reserved_at_80[0x20];
7821 };
7822
7823 struct mlx5_ifc_ppcnt_reg_bits {
7824         u8         swid[0x8];
7825         u8         local_port[0x8];
7826         u8         pnat[0x2];
7827         u8         reserved_at_12[0x8];
7828         u8         grp[0x6];
7829
7830         u8         clr[0x1];
7831         u8         reserved_at_21[0x1c];
7832         u8         prio_tc[0x3];
7833
7834         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7835 };
7836
7837 struct mlx5_ifc_mpcnt_reg_bits {
7838         u8         reserved_at_0[0x8];
7839         u8         pcie_index[0x8];
7840         u8         reserved_at_10[0xa];
7841         u8         grp[0x6];
7842
7843         u8         clr[0x1];
7844         u8         reserved_at_21[0x1f];
7845
7846         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7847 };
7848
7849 struct mlx5_ifc_ppad_reg_bits {
7850         u8         reserved_at_0[0x3];
7851         u8         single_mac[0x1];
7852         u8         reserved_at_4[0x4];
7853         u8         local_port[0x8];
7854         u8         mac_47_32[0x10];
7855
7856         u8         mac_31_0[0x20];
7857
7858         u8         reserved_at_40[0x40];
7859 };
7860
7861 struct mlx5_ifc_pmtu_reg_bits {
7862         u8         reserved_at_0[0x8];
7863         u8         local_port[0x8];
7864         u8         reserved_at_10[0x10];
7865
7866         u8         max_mtu[0x10];
7867         u8         reserved_at_30[0x10];
7868
7869         u8         admin_mtu[0x10];
7870         u8         reserved_at_50[0x10];
7871
7872         u8         oper_mtu[0x10];
7873         u8         reserved_at_70[0x10];
7874 };
7875
7876 struct mlx5_ifc_pmpr_reg_bits {
7877         u8         reserved_at_0[0x8];
7878         u8         module[0x8];
7879         u8         reserved_at_10[0x10];
7880
7881         u8         reserved_at_20[0x18];
7882         u8         attenuation_5g[0x8];
7883
7884         u8         reserved_at_40[0x18];
7885         u8         attenuation_7g[0x8];
7886
7887         u8         reserved_at_60[0x18];
7888         u8         attenuation_12g[0x8];
7889 };
7890
7891 struct mlx5_ifc_pmpe_reg_bits {
7892         u8         reserved_at_0[0x8];
7893         u8         module[0x8];
7894         u8         reserved_at_10[0xc];
7895         u8         module_status[0x4];
7896
7897         u8         reserved_at_20[0x60];
7898 };
7899
7900 struct mlx5_ifc_pmpc_reg_bits {
7901         u8         module_state_updated[32][0x8];
7902 };
7903
7904 struct mlx5_ifc_pmlpn_reg_bits {
7905         u8         reserved_at_0[0x4];
7906         u8         mlpn_status[0x4];
7907         u8         local_port[0x8];
7908         u8         reserved_at_10[0x10];
7909
7910         u8         e[0x1];
7911         u8         reserved_at_21[0x1f];
7912 };
7913
7914 struct mlx5_ifc_pmlp_reg_bits {
7915         u8         rxtx[0x1];
7916         u8         reserved_at_1[0x7];
7917         u8         local_port[0x8];
7918         u8         reserved_at_10[0x8];
7919         u8         width[0x8];
7920
7921         u8         lane0_module_mapping[0x20];
7922
7923         u8         lane1_module_mapping[0x20];
7924
7925         u8         lane2_module_mapping[0x20];
7926
7927         u8         lane3_module_mapping[0x20];
7928
7929         u8         reserved_at_a0[0x160];
7930 };
7931
7932 struct mlx5_ifc_pmaos_reg_bits {
7933         u8         reserved_at_0[0x8];
7934         u8         module[0x8];
7935         u8         reserved_at_10[0x4];
7936         u8         admin_status[0x4];
7937         u8         reserved_at_18[0x4];
7938         u8         oper_status[0x4];
7939
7940         u8         ase[0x1];
7941         u8         ee[0x1];
7942         u8         reserved_at_22[0x1c];
7943         u8         e[0x2];
7944
7945         u8         reserved_at_40[0x40];
7946 };
7947
7948 struct mlx5_ifc_plpc_reg_bits {
7949         u8         reserved_at_0[0x4];
7950         u8         profile_id[0xc];
7951         u8         reserved_at_10[0x4];
7952         u8         proto_mask[0x4];
7953         u8         reserved_at_18[0x8];
7954
7955         u8         reserved_at_20[0x10];
7956         u8         lane_speed[0x10];
7957
7958         u8         reserved_at_40[0x17];
7959         u8         lpbf[0x1];
7960         u8         fec_mode_policy[0x8];
7961
7962         u8         retransmission_capability[0x8];
7963         u8         fec_mode_capability[0x18];
7964
7965         u8         retransmission_support_admin[0x8];
7966         u8         fec_mode_support_admin[0x18];
7967
7968         u8         retransmission_request_admin[0x8];
7969         u8         fec_mode_request_admin[0x18];
7970
7971         u8         reserved_at_c0[0x80];
7972 };
7973
7974 struct mlx5_ifc_plib_reg_bits {
7975         u8         reserved_at_0[0x8];
7976         u8         local_port[0x8];
7977         u8         reserved_at_10[0x8];
7978         u8         ib_port[0x8];
7979
7980         u8         reserved_at_20[0x60];
7981 };
7982
7983 struct mlx5_ifc_plbf_reg_bits {
7984         u8         reserved_at_0[0x8];
7985         u8         local_port[0x8];
7986         u8         reserved_at_10[0xd];
7987         u8         lbf_mode[0x3];
7988
7989         u8         reserved_at_20[0x20];
7990 };
7991
7992 struct mlx5_ifc_pipg_reg_bits {
7993         u8         reserved_at_0[0x8];
7994         u8         local_port[0x8];
7995         u8         reserved_at_10[0x10];
7996
7997         u8         dic[0x1];
7998         u8         reserved_at_21[0x19];
7999         u8         ipg[0x4];
8000         u8         reserved_at_3e[0x2];
8001 };
8002
8003 struct mlx5_ifc_pifr_reg_bits {
8004         u8         reserved_at_0[0x8];
8005         u8         local_port[0x8];
8006         u8         reserved_at_10[0x10];
8007
8008         u8         reserved_at_20[0xe0];
8009
8010         u8         port_filter[8][0x20];
8011
8012         u8         port_filter_update_en[8][0x20];
8013 };
8014
8015 struct mlx5_ifc_pfcc_reg_bits {
8016         u8         reserved_at_0[0x8];
8017         u8         local_port[0x8];
8018         u8         reserved_at_10[0xb];
8019         u8         ppan_mask_n[0x1];
8020         u8         minor_stall_mask[0x1];
8021         u8         critical_stall_mask[0x1];
8022         u8         reserved_at_1e[0x2];
8023
8024         u8         ppan[0x4];
8025         u8         reserved_at_24[0x4];
8026         u8         prio_mask_tx[0x8];
8027         u8         reserved_at_30[0x8];
8028         u8         prio_mask_rx[0x8];
8029
8030         u8         pptx[0x1];
8031         u8         aptx[0x1];
8032         u8         pptx_mask_n[0x1];
8033         u8         reserved_at_43[0x5];
8034         u8         pfctx[0x8];
8035         u8         reserved_at_50[0x10];
8036
8037         u8         pprx[0x1];
8038         u8         aprx[0x1];
8039         u8         pprx_mask_n[0x1];
8040         u8         reserved_at_63[0x5];
8041         u8         pfcrx[0x8];
8042         u8         reserved_at_70[0x10];
8043
8044         u8         device_stall_minor_watermark[0x10];
8045         u8         device_stall_critical_watermark[0x10];
8046
8047         u8         reserved_at_a0[0x60];
8048 };
8049
8050 struct mlx5_ifc_pelc_reg_bits {
8051         u8         op[0x4];
8052         u8         reserved_at_4[0x4];
8053         u8         local_port[0x8];
8054         u8         reserved_at_10[0x10];
8055
8056         u8         op_admin[0x8];
8057         u8         op_capability[0x8];
8058         u8         op_request[0x8];
8059         u8         op_active[0x8];
8060
8061         u8         admin[0x40];
8062
8063         u8         capability[0x40];
8064
8065         u8         request[0x40];
8066
8067         u8         active[0x40];
8068
8069         u8         reserved_at_140[0x80];
8070 };
8071
8072 struct mlx5_ifc_peir_reg_bits {
8073         u8         reserved_at_0[0x8];
8074         u8         local_port[0x8];
8075         u8         reserved_at_10[0x10];
8076
8077         u8         reserved_at_20[0xc];
8078         u8         error_count[0x4];
8079         u8         reserved_at_30[0x10];
8080
8081         u8         reserved_at_40[0xc];
8082         u8         lane[0x4];
8083         u8         reserved_at_50[0x8];
8084         u8         error_type[0x8];
8085 };
8086
8087 struct mlx5_ifc_mpegc_reg_bits {
8088         u8         reserved_at_0[0x30];
8089         u8         field_select[0x10];
8090
8091         u8         tx_overflow_sense[0x1];
8092         u8         mark_cqe[0x1];
8093         u8         mark_cnp[0x1];
8094         u8         reserved_at_43[0x1b];
8095         u8         tx_lossy_overflow_oper[0x2];
8096
8097         u8         reserved_at_60[0x100];
8098 };
8099
8100 struct mlx5_ifc_pcam_enhanced_features_bits {
8101         u8         reserved_at_0[0x6d];
8102         u8         rx_icrc_encapsulated_counter[0x1];
8103         u8         reserved_at_6e[0x8];
8104         u8         pfcc_mask[0x1];
8105         u8         reserved_at_77[0x4];
8106         u8         rx_buffer_fullness_counters[0x1];
8107         u8         ptys_connector_type[0x1];
8108         u8         reserved_at_7d[0x1];
8109         u8         ppcnt_discard_group[0x1];
8110         u8         ppcnt_statistical_group[0x1];
8111 };
8112
8113 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8114         u8         port_access_reg_cap_mask_127_to_96[0x20];
8115         u8         port_access_reg_cap_mask_95_to_64[0x20];
8116         u8         port_access_reg_cap_mask_63_to_32[0x20];
8117
8118         u8         port_access_reg_cap_mask_31_to_13[0x13];
8119         u8         pbmc[0x1];
8120         u8         pptb[0x1];
8121         u8         port_access_reg_cap_mask_10_to_0[0xb];
8122 };
8123
8124 struct mlx5_ifc_pcam_reg_bits {
8125         u8         reserved_at_0[0x8];
8126         u8         feature_group[0x8];
8127         u8         reserved_at_10[0x8];
8128         u8         access_reg_group[0x8];
8129
8130         u8         reserved_at_20[0x20];
8131
8132         union {
8133                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8134                 u8         reserved_at_0[0x80];
8135         } port_access_reg_cap_mask;
8136
8137         u8         reserved_at_c0[0x80];
8138
8139         union {
8140                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8141                 u8         reserved_at_0[0x80];
8142         } feature_cap_mask;
8143
8144         u8         reserved_at_1c0[0xc0];
8145 };
8146
8147 struct mlx5_ifc_mcam_enhanced_features_bits {
8148         u8         reserved_at_0[0x74];
8149         u8         mark_tx_action_cnp[0x1];
8150         u8         mark_tx_action_cqe[0x1];
8151         u8         dynamic_tx_overflow[0x1];
8152         u8         reserved_at_77[0x4];
8153         u8         pcie_outbound_stalled[0x1];
8154         u8         tx_overflow_buffer_pkt[0x1];
8155         u8         mtpps_enh_out_per_adj[0x1];
8156         u8         mtpps_fs[0x1];
8157         u8         pcie_performance_group[0x1];
8158 };
8159
8160 struct mlx5_ifc_mcam_access_reg_bits {
8161         u8         reserved_at_0[0x1c];
8162         u8         mcda[0x1];
8163         u8         mcc[0x1];
8164         u8         mcqi[0x1];
8165         u8         reserved_at_1f[0x1];
8166
8167         u8         regs_95_to_87[0x9];
8168         u8         mpegc[0x1];
8169         u8         regs_85_to_68[0x12];
8170         u8         tracer_registers[0x4];
8171
8172         u8         regs_63_to_32[0x20];
8173         u8         regs_31_to_0[0x20];
8174 };
8175
8176 struct mlx5_ifc_mcam_reg_bits {
8177         u8         reserved_at_0[0x8];
8178         u8         feature_group[0x8];
8179         u8         reserved_at_10[0x8];
8180         u8         access_reg_group[0x8];
8181
8182         u8         reserved_at_20[0x20];
8183
8184         union {
8185                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8186                 u8         reserved_at_0[0x80];
8187         } mng_access_reg_cap_mask;
8188
8189         u8         reserved_at_c0[0x80];
8190
8191         union {
8192                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8193                 u8         reserved_at_0[0x80];
8194         } mng_feature_cap_mask;
8195
8196         u8         reserved_at_1c0[0x80];
8197 };
8198
8199 struct mlx5_ifc_qcam_access_reg_cap_mask {
8200         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8201         u8         qpdpm[0x1];
8202         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8203         u8         qdpm[0x1];
8204         u8         qpts[0x1];
8205         u8         qcap[0x1];
8206         u8         qcam_access_reg_cap_mask_0[0x1];
8207 };
8208
8209 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8210         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8211         u8         qpts_trust_both[0x1];
8212 };
8213
8214 struct mlx5_ifc_qcam_reg_bits {
8215         u8         reserved_at_0[0x8];
8216         u8         feature_group[0x8];
8217         u8         reserved_at_10[0x8];
8218         u8         access_reg_group[0x8];
8219         u8         reserved_at_20[0x20];
8220
8221         union {
8222                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8223                 u8  reserved_at_0[0x80];
8224         } qos_access_reg_cap_mask;
8225
8226         u8         reserved_at_c0[0x80];
8227
8228         union {
8229                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8230                 u8  reserved_at_0[0x80];
8231         } qos_feature_cap_mask;
8232
8233         u8         reserved_at_1c0[0x80];
8234 };
8235
8236 struct mlx5_ifc_pcap_reg_bits {
8237         u8         reserved_at_0[0x8];
8238         u8         local_port[0x8];
8239         u8         reserved_at_10[0x10];
8240
8241         u8         port_capability_mask[4][0x20];
8242 };
8243
8244 struct mlx5_ifc_paos_reg_bits {
8245         u8         swid[0x8];
8246         u8         local_port[0x8];
8247         u8         reserved_at_10[0x4];
8248         u8         admin_status[0x4];
8249         u8         reserved_at_18[0x4];
8250         u8         oper_status[0x4];
8251
8252         u8         ase[0x1];
8253         u8         ee[0x1];
8254         u8         reserved_at_22[0x1c];
8255         u8         e[0x2];
8256
8257         u8         reserved_at_40[0x40];
8258 };
8259
8260 struct mlx5_ifc_pamp_reg_bits {
8261         u8         reserved_at_0[0x8];
8262         u8         opamp_group[0x8];
8263         u8         reserved_at_10[0xc];
8264         u8         opamp_group_type[0x4];
8265
8266         u8         start_index[0x10];
8267         u8         reserved_at_30[0x4];
8268         u8         num_of_indices[0xc];
8269
8270         u8         index_data[18][0x10];
8271 };
8272
8273 struct mlx5_ifc_pcmr_reg_bits {
8274         u8         reserved_at_0[0x8];
8275         u8         local_port[0x8];
8276         u8         reserved_at_10[0x2e];
8277         u8         fcs_cap[0x1];
8278         u8         reserved_at_3f[0x1f];
8279         u8         fcs_chk[0x1];
8280         u8         reserved_at_5f[0x1];
8281 };
8282
8283 struct mlx5_ifc_lane_2_module_mapping_bits {
8284         u8         reserved_at_0[0x6];
8285         u8         rx_lane[0x2];
8286         u8         reserved_at_8[0x6];
8287         u8         tx_lane[0x2];
8288         u8         reserved_at_10[0x8];
8289         u8         module[0x8];
8290 };
8291
8292 struct mlx5_ifc_bufferx_reg_bits {
8293         u8         reserved_at_0[0x6];
8294         u8         lossy[0x1];
8295         u8         epsb[0x1];
8296         u8         reserved_at_8[0xc];
8297         u8         size[0xc];
8298
8299         u8         xoff_threshold[0x10];
8300         u8         xon_threshold[0x10];
8301 };
8302
8303 struct mlx5_ifc_set_node_in_bits {
8304         u8         node_description[64][0x8];
8305 };
8306
8307 struct mlx5_ifc_register_power_settings_bits {
8308         u8         reserved_at_0[0x18];
8309         u8         power_settings_level[0x8];
8310
8311         u8         reserved_at_20[0x60];
8312 };
8313
8314 struct mlx5_ifc_register_host_endianness_bits {
8315         u8         he[0x1];
8316         u8         reserved_at_1[0x1f];
8317
8318         u8         reserved_at_20[0x60];
8319 };
8320
8321 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8322         u8         reserved_at_0[0x20];
8323
8324         u8         mkey[0x20];
8325
8326         u8         addressh_63_32[0x20];
8327
8328         u8         addressl_31_0[0x20];
8329 };
8330
8331 struct mlx5_ifc_ud_adrs_vector_bits {
8332         u8         dc_key[0x40];
8333
8334         u8         ext[0x1];
8335         u8         reserved_at_41[0x7];
8336         u8         destination_qp_dct[0x18];
8337
8338         u8         static_rate[0x4];
8339         u8         sl_eth_prio[0x4];
8340         u8         fl[0x1];
8341         u8         mlid[0x7];
8342         u8         rlid_udp_sport[0x10];
8343
8344         u8         reserved_at_80[0x20];
8345
8346         u8         rmac_47_16[0x20];
8347
8348         u8         rmac_15_0[0x10];
8349         u8         tclass[0x8];
8350         u8         hop_limit[0x8];
8351
8352         u8         reserved_at_e0[0x1];
8353         u8         grh[0x1];
8354         u8         reserved_at_e2[0x2];
8355         u8         src_addr_index[0x8];
8356         u8         flow_label[0x14];
8357
8358         u8         rgid_rip[16][0x8];
8359 };
8360
8361 struct mlx5_ifc_pages_req_event_bits {
8362         u8         reserved_at_0[0x10];
8363         u8         function_id[0x10];
8364
8365         u8         num_pages[0x20];
8366
8367         u8         reserved_at_40[0xa0];
8368 };
8369
8370 struct mlx5_ifc_eqe_bits {
8371         u8         reserved_at_0[0x8];
8372         u8         event_type[0x8];
8373         u8         reserved_at_10[0x8];
8374         u8         event_sub_type[0x8];
8375
8376         u8         reserved_at_20[0xe0];
8377
8378         union mlx5_ifc_event_auto_bits event_data;
8379
8380         u8         reserved_at_1e0[0x10];
8381         u8         signature[0x8];
8382         u8         reserved_at_1f8[0x7];
8383         u8         owner[0x1];
8384 };
8385
8386 enum {
8387         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8388 };
8389
8390 struct mlx5_ifc_cmd_queue_entry_bits {
8391         u8         type[0x8];
8392         u8         reserved_at_8[0x18];
8393
8394         u8         input_length[0x20];
8395
8396         u8         input_mailbox_pointer_63_32[0x20];
8397
8398         u8         input_mailbox_pointer_31_9[0x17];
8399         u8         reserved_at_77[0x9];
8400
8401         u8         command_input_inline_data[16][0x8];
8402
8403         u8         command_output_inline_data[16][0x8];
8404
8405         u8         output_mailbox_pointer_63_32[0x20];
8406
8407         u8         output_mailbox_pointer_31_9[0x17];
8408         u8         reserved_at_1b7[0x9];
8409
8410         u8         output_length[0x20];
8411
8412         u8         token[0x8];
8413         u8         signature[0x8];
8414         u8         reserved_at_1f0[0x8];
8415         u8         status[0x7];
8416         u8         ownership[0x1];
8417 };
8418
8419 struct mlx5_ifc_cmd_out_bits {
8420         u8         status[0x8];
8421         u8         reserved_at_8[0x18];
8422
8423         u8         syndrome[0x20];
8424
8425         u8         command_output[0x20];
8426 };
8427
8428 struct mlx5_ifc_cmd_in_bits {
8429         u8         opcode[0x10];
8430         u8         reserved_at_10[0x10];
8431
8432         u8         reserved_at_20[0x10];
8433         u8         op_mod[0x10];
8434
8435         u8         command[0][0x20];
8436 };
8437
8438 struct mlx5_ifc_cmd_if_box_bits {
8439         u8         mailbox_data[512][0x8];
8440
8441         u8         reserved_at_1000[0x180];
8442
8443         u8         next_pointer_63_32[0x20];
8444
8445         u8         next_pointer_31_10[0x16];
8446         u8         reserved_at_11b6[0xa];
8447
8448         u8         block_number[0x20];
8449
8450         u8         reserved_at_11e0[0x8];
8451         u8         token[0x8];
8452         u8         ctrl_signature[0x8];
8453         u8         signature[0x8];
8454 };
8455
8456 struct mlx5_ifc_mtt_bits {
8457         u8         ptag_63_32[0x20];
8458
8459         u8         ptag_31_8[0x18];
8460         u8         reserved_at_38[0x6];
8461         u8         wr_en[0x1];
8462         u8         rd_en[0x1];
8463 };
8464
8465 struct mlx5_ifc_query_wol_rol_out_bits {
8466         u8         status[0x8];
8467         u8         reserved_at_8[0x18];
8468
8469         u8         syndrome[0x20];
8470
8471         u8         reserved_at_40[0x10];
8472         u8         rol_mode[0x8];
8473         u8         wol_mode[0x8];
8474
8475         u8         reserved_at_60[0x20];
8476 };
8477
8478 struct mlx5_ifc_query_wol_rol_in_bits {
8479         u8         opcode[0x10];
8480         u8         reserved_at_10[0x10];
8481
8482         u8         reserved_at_20[0x10];
8483         u8         op_mod[0x10];
8484
8485         u8         reserved_at_40[0x40];
8486 };
8487
8488 struct mlx5_ifc_set_wol_rol_out_bits {
8489         u8         status[0x8];
8490         u8         reserved_at_8[0x18];
8491
8492         u8         syndrome[0x20];
8493
8494         u8         reserved_at_40[0x40];
8495 };
8496
8497 struct mlx5_ifc_set_wol_rol_in_bits {
8498         u8         opcode[0x10];
8499         u8         reserved_at_10[0x10];
8500
8501         u8         reserved_at_20[0x10];
8502         u8         op_mod[0x10];
8503
8504         u8         rol_mode_valid[0x1];
8505         u8         wol_mode_valid[0x1];
8506         u8         reserved_at_42[0xe];
8507         u8         rol_mode[0x8];
8508         u8         wol_mode[0x8];
8509
8510         u8         reserved_at_60[0x20];
8511 };
8512
8513 enum {
8514         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8515         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8516         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8517 };
8518
8519 enum {
8520         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8521         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8522         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8523 };
8524
8525 enum {
8526         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8527         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8528         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8529         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8530         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8531         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8532         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8533         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8534         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8535         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8536         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8537 };
8538
8539 struct mlx5_ifc_initial_seg_bits {
8540         u8         fw_rev_minor[0x10];
8541         u8         fw_rev_major[0x10];
8542
8543         u8         cmd_interface_rev[0x10];
8544         u8         fw_rev_subminor[0x10];
8545
8546         u8         reserved_at_40[0x40];
8547
8548         u8         cmdq_phy_addr_63_32[0x20];
8549
8550         u8         cmdq_phy_addr_31_12[0x14];
8551         u8         reserved_at_b4[0x2];
8552         u8         nic_interface[0x2];
8553         u8         log_cmdq_size[0x4];
8554         u8         log_cmdq_stride[0x4];
8555
8556         u8         command_doorbell_vector[0x20];
8557
8558         u8         reserved_at_e0[0xf00];
8559
8560         u8         initializing[0x1];
8561         u8         reserved_at_fe1[0x4];
8562         u8         nic_interface_supported[0x3];
8563         u8         reserved_at_fe8[0x18];
8564
8565         struct mlx5_ifc_health_buffer_bits health_buffer;
8566
8567         u8         no_dram_nic_offset[0x20];
8568
8569         u8         reserved_at_1220[0x6e40];
8570
8571         u8         reserved_at_8060[0x1f];
8572         u8         clear_int[0x1];
8573
8574         u8         health_syndrome[0x8];
8575         u8         health_counter[0x18];
8576
8577         u8         reserved_at_80a0[0x17fc0];
8578 };
8579
8580 struct mlx5_ifc_mtpps_reg_bits {
8581         u8         reserved_at_0[0xc];
8582         u8         cap_number_of_pps_pins[0x4];
8583         u8         reserved_at_10[0x4];
8584         u8         cap_max_num_of_pps_in_pins[0x4];
8585         u8         reserved_at_18[0x4];
8586         u8         cap_max_num_of_pps_out_pins[0x4];
8587
8588         u8         reserved_at_20[0x24];
8589         u8         cap_pin_3_mode[0x4];
8590         u8         reserved_at_48[0x4];
8591         u8         cap_pin_2_mode[0x4];
8592         u8         reserved_at_50[0x4];
8593         u8         cap_pin_1_mode[0x4];
8594         u8         reserved_at_58[0x4];
8595         u8         cap_pin_0_mode[0x4];
8596
8597         u8         reserved_at_60[0x4];
8598         u8         cap_pin_7_mode[0x4];
8599         u8         reserved_at_68[0x4];
8600         u8         cap_pin_6_mode[0x4];
8601         u8         reserved_at_70[0x4];
8602         u8         cap_pin_5_mode[0x4];
8603         u8         reserved_at_78[0x4];
8604         u8         cap_pin_4_mode[0x4];
8605
8606         u8         field_select[0x20];
8607         u8         reserved_at_a0[0x60];
8608
8609         u8         enable[0x1];
8610         u8         reserved_at_101[0xb];
8611         u8         pattern[0x4];
8612         u8         reserved_at_110[0x4];
8613         u8         pin_mode[0x4];
8614         u8         pin[0x8];
8615
8616         u8         reserved_at_120[0x20];
8617
8618         u8         time_stamp[0x40];
8619
8620         u8         out_pulse_duration[0x10];
8621         u8         out_periodic_adjustment[0x10];
8622         u8         enhanced_out_periodic_adjustment[0x20];
8623
8624         u8         reserved_at_1c0[0x20];
8625 };
8626
8627 struct mlx5_ifc_mtppse_reg_bits {
8628         u8         reserved_at_0[0x18];
8629         u8         pin[0x8];
8630         u8         event_arm[0x1];
8631         u8         reserved_at_21[0x1b];
8632         u8         event_generation_mode[0x4];
8633         u8         reserved_at_40[0x40];
8634 };
8635
8636 struct mlx5_ifc_mcqi_cap_bits {
8637         u8         supported_info_bitmask[0x20];
8638
8639         u8         component_size[0x20];
8640
8641         u8         max_component_size[0x20];
8642
8643         u8         log_mcda_word_size[0x4];
8644         u8         reserved_at_64[0xc];
8645         u8         mcda_max_write_size[0x10];
8646
8647         u8         rd_en[0x1];
8648         u8         reserved_at_81[0x1];
8649         u8         match_chip_id[0x1];
8650         u8         match_psid[0x1];
8651         u8         check_user_timestamp[0x1];
8652         u8         match_base_guid_mac[0x1];
8653         u8         reserved_at_86[0x1a];
8654 };
8655
8656 struct mlx5_ifc_mcqi_reg_bits {
8657         u8         read_pending_component[0x1];
8658         u8         reserved_at_1[0xf];
8659         u8         component_index[0x10];
8660
8661         u8         reserved_at_20[0x20];
8662
8663         u8         reserved_at_40[0x1b];
8664         u8         info_type[0x5];
8665
8666         u8         info_size[0x20];
8667
8668         u8         offset[0x20];
8669
8670         u8         reserved_at_a0[0x10];
8671         u8         data_size[0x10];
8672
8673         u8         data[0][0x20];
8674 };
8675
8676 struct mlx5_ifc_mcc_reg_bits {
8677         u8         reserved_at_0[0x4];
8678         u8         time_elapsed_since_last_cmd[0xc];
8679         u8         reserved_at_10[0x8];
8680         u8         instruction[0x8];
8681
8682         u8         reserved_at_20[0x10];
8683         u8         component_index[0x10];
8684
8685         u8         reserved_at_40[0x8];
8686         u8         update_handle[0x18];
8687
8688         u8         handle_owner_type[0x4];
8689         u8         handle_owner_host_id[0x4];
8690         u8         reserved_at_68[0x1];
8691         u8         control_progress[0x7];
8692         u8         error_code[0x8];
8693         u8         reserved_at_78[0x4];
8694         u8         control_state[0x4];
8695
8696         u8         component_size[0x20];
8697
8698         u8         reserved_at_a0[0x60];
8699 };
8700
8701 struct mlx5_ifc_mcda_reg_bits {
8702         u8         reserved_at_0[0x8];
8703         u8         update_handle[0x18];
8704
8705         u8         offset[0x20];
8706
8707         u8         reserved_at_40[0x10];
8708         u8         size[0x10];
8709
8710         u8         reserved_at_60[0x20];
8711
8712         u8         data[0][0x20];
8713 };
8714
8715 union mlx5_ifc_ports_control_registers_document_bits {
8716         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8717         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8718         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8719         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8720         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8721         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8722         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8723         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8724         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8725         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8726         struct mlx5_ifc_paos_reg_bits paos_reg;
8727         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8728         struct mlx5_ifc_peir_reg_bits peir_reg;
8729         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8730         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8731         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8732         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8733         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8734         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8735         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8736         struct mlx5_ifc_plib_reg_bits plib_reg;
8737         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8738         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8739         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8740         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8741         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8742         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8743         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8744         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8745         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8746         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8747         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8748         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8749         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8750         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8751         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8752         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8753         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8754         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8755         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8756         struct mlx5_ifc_pude_reg_bits pude_reg;
8757         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8758         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8759         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8760         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8761         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8762         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8763         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8764         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8765         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8766         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8767         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8768         u8         reserved_at_0[0x60e0];
8769 };
8770
8771 union mlx5_ifc_debug_enhancements_document_bits {
8772         struct mlx5_ifc_health_buffer_bits health_buffer;
8773         u8         reserved_at_0[0x200];
8774 };
8775
8776 union mlx5_ifc_uplink_pci_interface_document_bits {
8777         struct mlx5_ifc_initial_seg_bits initial_seg;
8778         u8         reserved_at_0[0x20060];
8779 };
8780
8781 struct mlx5_ifc_set_flow_table_root_out_bits {
8782         u8         status[0x8];
8783         u8         reserved_at_8[0x18];
8784
8785         u8         syndrome[0x20];
8786
8787         u8         reserved_at_40[0x40];
8788 };
8789
8790 struct mlx5_ifc_set_flow_table_root_in_bits {
8791         u8         opcode[0x10];
8792         u8         reserved_at_10[0x10];
8793
8794         u8         reserved_at_20[0x10];
8795         u8         op_mod[0x10];
8796
8797         u8         other_vport[0x1];
8798         u8         reserved_at_41[0xf];
8799         u8         vport_number[0x10];
8800
8801         u8         reserved_at_60[0x20];
8802
8803         u8         table_type[0x8];
8804         u8         reserved_at_88[0x18];
8805
8806         u8         reserved_at_a0[0x8];
8807         u8         table_id[0x18];
8808
8809         u8         reserved_at_c0[0x8];
8810         u8         underlay_qpn[0x18];
8811         u8         reserved_at_e0[0x120];
8812 };
8813
8814 enum {
8815         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8816         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8817 };
8818
8819 struct mlx5_ifc_modify_flow_table_out_bits {
8820         u8         status[0x8];
8821         u8         reserved_at_8[0x18];
8822
8823         u8         syndrome[0x20];
8824
8825         u8         reserved_at_40[0x40];
8826 };
8827
8828 struct mlx5_ifc_modify_flow_table_in_bits {
8829         u8         opcode[0x10];
8830         u8         reserved_at_10[0x10];
8831
8832         u8         reserved_at_20[0x10];
8833         u8         op_mod[0x10];
8834
8835         u8         other_vport[0x1];
8836         u8         reserved_at_41[0xf];
8837         u8         vport_number[0x10];
8838
8839         u8         reserved_at_60[0x10];
8840         u8         modify_field_select[0x10];
8841
8842         u8         table_type[0x8];
8843         u8         reserved_at_88[0x18];
8844
8845         u8         reserved_at_a0[0x8];
8846         u8         table_id[0x18];
8847
8848         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8849 };
8850
8851 struct mlx5_ifc_ets_tcn_config_reg_bits {
8852         u8         g[0x1];
8853         u8         b[0x1];
8854         u8         r[0x1];
8855         u8         reserved_at_3[0x9];
8856         u8         group[0x4];
8857         u8         reserved_at_10[0x9];
8858         u8         bw_allocation[0x7];
8859
8860         u8         reserved_at_20[0xc];
8861         u8         max_bw_units[0x4];
8862         u8         reserved_at_30[0x8];
8863         u8         max_bw_value[0x8];
8864 };
8865
8866 struct mlx5_ifc_ets_global_config_reg_bits {
8867         u8         reserved_at_0[0x2];
8868         u8         r[0x1];
8869         u8         reserved_at_3[0x1d];
8870
8871         u8         reserved_at_20[0xc];
8872         u8         max_bw_units[0x4];
8873         u8         reserved_at_30[0x8];
8874         u8         max_bw_value[0x8];
8875 };
8876
8877 struct mlx5_ifc_qetc_reg_bits {
8878         u8                                         reserved_at_0[0x8];
8879         u8                                         port_number[0x8];
8880         u8                                         reserved_at_10[0x30];
8881
8882         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8883         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8884 };
8885
8886 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8887         u8         e[0x1];
8888         u8         reserved_at_01[0x0b];
8889         u8         prio[0x04];
8890 };
8891
8892 struct mlx5_ifc_qpdpm_reg_bits {
8893         u8                                     reserved_at_0[0x8];
8894         u8                                     local_port[0x8];
8895         u8                                     reserved_at_10[0x10];
8896         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8897 };
8898
8899 struct mlx5_ifc_qpts_reg_bits {
8900         u8         reserved_at_0[0x8];
8901         u8         local_port[0x8];
8902         u8         reserved_at_10[0x2d];
8903         u8         trust_state[0x3];
8904 };
8905
8906 struct mlx5_ifc_pptb_reg_bits {
8907         u8         reserved_at_0[0x2];
8908         u8         mm[0x2];
8909         u8         reserved_at_4[0x4];
8910         u8         local_port[0x8];
8911         u8         reserved_at_10[0x6];
8912         u8         cm[0x1];
8913         u8         um[0x1];
8914         u8         pm[0x8];
8915
8916         u8         prio_x_buff[0x20];
8917
8918         u8         pm_msb[0x8];
8919         u8         reserved_at_48[0x10];
8920         u8         ctrl_buff[0x4];
8921         u8         untagged_buff[0x4];
8922 };
8923
8924 struct mlx5_ifc_pbmc_reg_bits {
8925         u8         reserved_at_0[0x8];
8926         u8         local_port[0x8];
8927         u8         reserved_at_10[0x10];
8928
8929         u8         xoff_timer_value[0x10];
8930         u8         xoff_refresh[0x10];
8931
8932         u8         reserved_at_40[0x9];
8933         u8         fullness_threshold[0x7];
8934         u8         port_buffer_size[0x10];
8935
8936         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8937
8938         u8         reserved_at_2e0[0x40];
8939 };
8940
8941 struct mlx5_ifc_qtct_reg_bits {
8942         u8         reserved_at_0[0x8];
8943         u8         port_number[0x8];
8944         u8         reserved_at_10[0xd];
8945         u8         prio[0x3];
8946
8947         u8         reserved_at_20[0x1d];
8948         u8         tclass[0x3];
8949 };
8950
8951 struct mlx5_ifc_mcia_reg_bits {
8952         u8         l[0x1];
8953         u8         reserved_at_1[0x7];
8954         u8         module[0x8];
8955         u8         reserved_at_10[0x8];
8956         u8         status[0x8];
8957
8958         u8         i2c_device_address[0x8];
8959         u8         page_number[0x8];
8960         u8         device_address[0x10];
8961
8962         u8         reserved_at_40[0x10];
8963         u8         size[0x10];
8964
8965         u8         reserved_at_60[0x20];
8966
8967         u8         dword_0[0x20];
8968         u8         dword_1[0x20];
8969         u8         dword_2[0x20];
8970         u8         dword_3[0x20];
8971         u8         dword_4[0x20];
8972         u8         dword_5[0x20];
8973         u8         dword_6[0x20];
8974         u8         dword_7[0x20];
8975         u8         dword_8[0x20];
8976         u8         dword_9[0x20];
8977         u8         dword_10[0x20];
8978         u8         dword_11[0x20];
8979 };
8980
8981 struct mlx5_ifc_dcbx_param_bits {
8982         u8         dcbx_cee_cap[0x1];
8983         u8         dcbx_ieee_cap[0x1];
8984         u8         dcbx_standby_cap[0x1];
8985         u8         reserved_at_0[0x5];
8986         u8         port_number[0x8];
8987         u8         reserved_at_10[0xa];
8988         u8         max_application_table_size[6];
8989         u8         reserved_at_20[0x15];
8990         u8         version_oper[0x3];
8991         u8         reserved_at_38[5];
8992         u8         version_admin[0x3];
8993         u8         willing_admin[0x1];
8994         u8         reserved_at_41[0x3];
8995         u8         pfc_cap_oper[0x4];
8996         u8         reserved_at_48[0x4];
8997         u8         pfc_cap_admin[0x4];
8998         u8         reserved_at_50[0x4];
8999         u8         num_of_tc_oper[0x4];
9000         u8         reserved_at_58[0x4];
9001         u8         num_of_tc_admin[0x4];
9002         u8         remote_willing[0x1];
9003         u8         reserved_at_61[3];
9004         u8         remote_pfc_cap[4];
9005         u8         reserved_at_68[0x14];
9006         u8         remote_num_of_tc[0x4];
9007         u8         reserved_at_80[0x18];
9008         u8         error[0x8];
9009         u8         reserved_at_a0[0x160];
9010 };
9011
9012 struct mlx5_ifc_lagc_bits {
9013         u8         reserved_at_0[0x1d];
9014         u8         lag_state[0x3];
9015
9016         u8         reserved_at_20[0x14];
9017         u8         tx_remap_affinity_2[0x4];
9018         u8         reserved_at_38[0x4];
9019         u8         tx_remap_affinity_1[0x4];
9020 };
9021
9022 struct mlx5_ifc_create_lag_out_bits {
9023         u8         status[0x8];
9024         u8         reserved_at_8[0x18];
9025
9026         u8         syndrome[0x20];
9027
9028         u8         reserved_at_40[0x40];
9029 };
9030
9031 struct mlx5_ifc_create_lag_in_bits {
9032         u8         opcode[0x10];
9033         u8         reserved_at_10[0x10];
9034
9035         u8         reserved_at_20[0x10];
9036         u8         op_mod[0x10];
9037
9038         struct mlx5_ifc_lagc_bits ctx;
9039 };
9040
9041 struct mlx5_ifc_modify_lag_out_bits {
9042         u8         status[0x8];
9043         u8         reserved_at_8[0x18];
9044
9045         u8         syndrome[0x20];
9046
9047         u8         reserved_at_40[0x40];
9048 };
9049
9050 struct mlx5_ifc_modify_lag_in_bits {
9051         u8         opcode[0x10];
9052         u8         reserved_at_10[0x10];
9053
9054         u8         reserved_at_20[0x10];
9055         u8         op_mod[0x10];
9056
9057         u8         reserved_at_40[0x20];
9058         u8         field_select[0x20];
9059
9060         struct mlx5_ifc_lagc_bits ctx;
9061 };
9062
9063 struct mlx5_ifc_query_lag_out_bits {
9064         u8         status[0x8];
9065         u8         reserved_at_8[0x18];
9066
9067         u8         syndrome[0x20];
9068
9069         u8         reserved_at_40[0x40];
9070
9071         struct mlx5_ifc_lagc_bits ctx;
9072 };
9073
9074 struct mlx5_ifc_query_lag_in_bits {
9075         u8         opcode[0x10];
9076         u8         reserved_at_10[0x10];
9077
9078         u8         reserved_at_20[0x10];
9079         u8         op_mod[0x10];
9080
9081         u8         reserved_at_40[0x40];
9082 };
9083
9084 struct mlx5_ifc_destroy_lag_out_bits {
9085         u8         status[0x8];
9086         u8         reserved_at_8[0x18];
9087
9088         u8         syndrome[0x20];
9089
9090         u8         reserved_at_40[0x40];
9091 };
9092
9093 struct mlx5_ifc_destroy_lag_in_bits {
9094         u8         opcode[0x10];
9095         u8         reserved_at_10[0x10];
9096
9097         u8         reserved_at_20[0x10];
9098         u8         op_mod[0x10];
9099
9100         u8         reserved_at_40[0x40];
9101 };
9102
9103 struct mlx5_ifc_create_vport_lag_out_bits {
9104         u8         status[0x8];
9105         u8         reserved_at_8[0x18];
9106
9107         u8         syndrome[0x20];
9108
9109         u8         reserved_at_40[0x40];
9110 };
9111
9112 struct mlx5_ifc_create_vport_lag_in_bits {
9113         u8         opcode[0x10];
9114         u8         reserved_at_10[0x10];
9115
9116         u8         reserved_at_20[0x10];
9117         u8         op_mod[0x10];
9118
9119         u8         reserved_at_40[0x40];
9120 };
9121
9122 struct mlx5_ifc_destroy_vport_lag_out_bits {
9123         u8         status[0x8];
9124         u8         reserved_at_8[0x18];
9125
9126         u8         syndrome[0x20];
9127
9128         u8         reserved_at_40[0x40];
9129 };
9130
9131 struct mlx5_ifc_destroy_vport_lag_in_bits {
9132         u8         opcode[0x10];
9133         u8         reserved_at_10[0x10];
9134
9135         u8         reserved_at_20[0x10];
9136         u8         op_mod[0x10];
9137
9138         u8         reserved_at_40[0x40];
9139 };
9140
9141 struct mlx5_ifc_alloc_memic_in_bits {
9142         u8         opcode[0x10];
9143         u8         reserved_at_10[0x10];
9144
9145         u8         reserved_at_20[0x10];
9146         u8         op_mod[0x10];
9147
9148         u8         reserved_at_30[0x20];
9149
9150         u8         reserved_at_40[0x18];
9151         u8         log_memic_addr_alignment[0x8];
9152
9153         u8         range_start_addr[0x40];
9154
9155         u8         range_size[0x20];
9156
9157         u8         memic_size[0x20];
9158 };
9159
9160 struct mlx5_ifc_alloc_memic_out_bits {
9161         u8         status[0x8];
9162         u8         reserved_at_8[0x18];
9163
9164         u8         syndrome[0x20];
9165
9166         u8         memic_start_addr[0x40];
9167 };
9168
9169 struct mlx5_ifc_dealloc_memic_in_bits {
9170         u8         opcode[0x10];
9171         u8         reserved_at_10[0x10];
9172
9173         u8         reserved_at_20[0x10];
9174         u8         op_mod[0x10];
9175
9176         u8         reserved_at_40[0x40];
9177
9178         u8         memic_start_addr[0x40];
9179
9180         u8         memic_size[0x20];
9181
9182         u8         reserved_at_e0[0x20];
9183 };
9184
9185 struct mlx5_ifc_dealloc_memic_out_bits {
9186         u8         status[0x8];
9187         u8         reserved_at_8[0x18];
9188
9189         u8         syndrome[0x20];
9190
9191         u8         reserved_at_40[0x40];
9192 };
9193
9194 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9195         u8         opcode[0x10];
9196         u8         uid[0x10];
9197
9198         u8         reserved_at_20[0x10];
9199         u8         obj_type[0x10];
9200
9201         u8         obj_id[0x20];
9202
9203         u8         reserved_at_60[0x20];
9204 };
9205
9206 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9207         u8         status[0x8];
9208         u8         reserved_at_8[0x18];
9209
9210         u8         syndrome[0x20];
9211
9212         u8         obj_id[0x20];
9213
9214         u8         reserved_at_60[0x20];
9215 };
9216
9217 struct mlx5_ifc_umem_bits {
9218         u8         modify_field_select[0x40];
9219
9220         u8         reserved_at_40[0x5b];
9221         u8         log_page_size[0x5];
9222
9223         u8         page_offset[0x20];
9224
9225         u8         num_of_mtt[0x40];
9226
9227         struct mlx5_ifc_mtt_bits  mtt[0];
9228 };
9229
9230 struct mlx5_ifc_uctx_bits {
9231         u8         modify_field_select[0x40];
9232
9233         u8         reserved_at_40[0x1c0];
9234 };
9235
9236 struct mlx5_ifc_create_umem_in_bits {
9237         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9238         struct mlx5_ifc_umem_bits                     umem;
9239 };
9240
9241 struct mlx5_ifc_create_uctx_in_bits {
9242         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9243         struct mlx5_ifc_uctx_bits                     uctx;
9244 };
9245
9246 struct mlx5_ifc_mtrc_string_db_param_bits {
9247         u8         string_db_base_address[0x20];
9248
9249         u8         reserved_at_20[0x8];
9250         u8         string_db_size[0x18];
9251 };
9252
9253 struct mlx5_ifc_mtrc_cap_bits {
9254         u8         trace_owner[0x1];
9255         u8         trace_to_memory[0x1];
9256         u8         reserved_at_2[0x4];
9257         u8         trc_ver[0x2];
9258         u8         reserved_at_8[0x14];
9259         u8         num_string_db[0x4];
9260
9261         u8         first_string_trace[0x8];
9262         u8         num_string_trace[0x8];
9263         u8         reserved_at_30[0x28];
9264
9265         u8         log_max_trace_buffer_size[0x8];
9266
9267         u8         reserved_at_60[0x20];
9268
9269         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9270
9271         u8         reserved_at_280[0x180];
9272 };
9273
9274 struct mlx5_ifc_mtrc_conf_bits {
9275         u8         reserved_at_0[0x1c];
9276         u8         trace_mode[0x4];
9277         u8         reserved_at_20[0x18];
9278         u8         log_trace_buffer_size[0x8];
9279         u8         trace_mkey[0x20];
9280         u8         reserved_at_60[0x3a0];
9281 };
9282
9283 struct mlx5_ifc_mtrc_stdb_bits {
9284         u8         string_db_index[0x4];
9285         u8         reserved_at_4[0x4];
9286         u8         read_size[0x18];
9287         u8         start_offset[0x20];
9288         u8         string_db_data[0];
9289 };
9290
9291 struct mlx5_ifc_mtrc_ctrl_bits {
9292         u8         trace_status[0x2];
9293         u8         reserved_at_2[0x2];
9294         u8         arm_event[0x1];
9295         u8         reserved_at_5[0xb];
9296         u8         modify_field_select[0x10];
9297         u8         reserved_at_20[0x2b];
9298         u8         current_timestamp52_32[0x15];
9299         u8         current_timestamp31_0[0x20];
9300         u8         reserved_at_80[0x180];
9301 };
9302
9303 #endif /* MLX5_IFC_H */