include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  76 };
  77
  78 enum {
  79         MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
  80         MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_UCTX = 0x0004,
  85         MLX5_OBJ_TYPE_UMEM = 0x0005,
  86 };
  87
  88 enum {
  89         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  90         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  91         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  92         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  93         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  94         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  95         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  96         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  97         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  98         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  99         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 100         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 101         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 102         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 103         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 104         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 105         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 106         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 107         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 108         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 109         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 110         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 111         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 112         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 113         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 114         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 115         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 116         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 117         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 118         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 119         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 120         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 121         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 122         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 123         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 124         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 125         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 126         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 127         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 128         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 129         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 130         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 131         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 132         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 133         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 134         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 135         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 136         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 137         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 138         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 139         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 140         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 141         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 142         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 143         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 144         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 145         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 146         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 147         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 148         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 149         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 150         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 151         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 152         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 153         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 154         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 155         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 156         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 157         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 158         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 159         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 160         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 161         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 162         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 163         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 164         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 165         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 166         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 167         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 168         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 169         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 170         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 171         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 172         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 173         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 174         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 175         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 176         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 177         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 178         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 179         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 180         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 181         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 182         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 183         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 184         MLX5_CMD_OP_NOP                           = 0x80d,
 185         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 186         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 187         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 188         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 189         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 190         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 191         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 192         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 193         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 194         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 195         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 196         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 197         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 198         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 199         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 200         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 201         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 202         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 203         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 204         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 205         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 206         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 207         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 208         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 209         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 210         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 211         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 212         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 213         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 214         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 215         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 216         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 217         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 218         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 219         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 220         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 221         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 222         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 223         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 224         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 225         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 226         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 227         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 228         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 229         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 230         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 231         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 232         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 233         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 234         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 235         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 236         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 237         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 238         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 239         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 240         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 241         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 242         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 243         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 244         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 245         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 246         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 247         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 248         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 249         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 250         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 251         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 252         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 253         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 254         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 255         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 256         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 257         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 258         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 259         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 260         MLX5_CMD_OP_MAX
 261 };
 262
 263 struct mlx5_ifc_flow_table_fields_supported_bits {
 264         u8         outer_dmac[0x1];
 265         u8         outer_smac[0x1];
 266         u8         outer_ether_type[0x1];
 267         u8         outer_ip_version[0x1];
 268         u8         outer_first_prio[0x1];
 269         u8         outer_first_cfi[0x1];
 270         u8         outer_first_vid[0x1];
 271         u8         outer_ipv4_ttl[0x1];
 272         u8         outer_second_prio[0x1];
 273         u8         outer_second_cfi[0x1];
 274         u8         outer_second_vid[0x1];
 275         u8         reserved_at_b[0x1];
 276         u8         outer_sip[0x1];
 277         u8         outer_dip[0x1];
 278         u8         outer_frag[0x1];
 279         u8         outer_ip_protocol[0x1];
 280         u8         outer_ip_ecn[0x1];
 281         u8         outer_ip_dscp[0x1];
 282         u8         outer_udp_sport[0x1];
 283         u8         outer_udp_dport[0x1];
 284         u8         outer_tcp_sport[0x1];
 285         u8         outer_tcp_dport[0x1];
 286         u8         outer_tcp_flags[0x1];
 287         u8         outer_gre_protocol[0x1];
 288         u8         outer_gre_key[0x1];
 289         u8         outer_vxlan_vni[0x1];
 290         u8         reserved_at_1a[0x5];
 291         u8         source_eswitch_port[0x1];
 292
 293         u8         inner_dmac[0x1];
 294         u8         inner_smac[0x1];
 295         u8         inner_ether_type[0x1];
 296         u8         inner_ip_version[0x1];
 297         u8         inner_first_prio[0x1];
 298         u8         inner_first_cfi[0x1];
 299         u8         inner_first_vid[0x1];
 300         u8         reserved_at_27[0x1];
 301         u8         inner_second_prio[0x1];
 302         u8         inner_second_cfi[0x1];
 303         u8         inner_second_vid[0x1];
 304         u8         reserved_at_2b[0x1];
 305         u8         inner_sip[0x1];
 306         u8         inner_dip[0x1];
 307         u8         inner_frag[0x1];
 308         u8         inner_ip_protocol[0x1];
 309         u8         inner_ip_ecn[0x1];
 310         u8         inner_ip_dscp[0x1];
 311         u8         inner_udp_sport[0x1];
 312         u8         inner_udp_dport[0x1];
 313         u8         inner_tcp_sport[0x1];
 314         u8         inner_tcp_dport[0x1];
 315         u8         inner_tcp_flags[0x1];
 316         u8         reserved_at_37[0x9];
 317
 318         u8         reserved_at_40[0x5];
 319         u8         outer_first_mpls_over_udp[0x4];
 320         u8         outer_first_mpls_over_gre[0x4];
 321         u8         inner_first_mpls[0x4];
 322         u8         outer_first_mpls[0x4];
 323         u8         reserved_at_55[0x2];
 324         u8         outer_esp_spi[0x1];
 325         u8         reserved_at_58[0x2];
 326         u8         bth_dst_qp[0x1];
 327
 328         u8         reserved_at_5b[0x25];
 329 };
 330
 331 struct mlx5_ifc_flow_table_prop_layout_bits {
 332         u8         ft_support[0x1];
 333         u8         reserved_at_1[0x1];
 334         u8         flow_counter[0x1];
 335         u8         flow_modify_en[0x1];
 336         u8         modify_root[0x1];
 337         u8         identified_miss_table_mode[0x1];
 338         u8         flow_table_modify[0x1];
 339         u8         reformat[0x1];
 340         u8         decap[0x1];
 341         u8         reserved_at_9[0x1];
 342         u8         pop_vlan[0x1];
 343         u8         push_vlan[0x1];
 344         u8         reserved_at_c[0x1];
 345         u8         pop_vlan_2[0x1];
 346         u8         push_vlan_2[0x1];
 347         u8         reformat_and_vlan_action[0x1];
 348         u8         reserved_at_10[0x2];
 349         u8         reformat_l3_tunnel_to_l2[0x1];
 350         u8         reformat_l2_to_l3_tunnel[0x1];
 351         u8         reformat_and_modify_action[0x1];
 352         u8         reserved_at_15[0xb];
 353         u8         reserved_at_20[0x2];
 354         u8         log_max_ft_size[0x6];
 355         u8         log_max_modify_header_context[0x8];
 356         u8         max_modify_header_actions[0x8];
 357         u8         max_ft_level[0x8];
 358
 359         u8         reserved_at_40[0x20];
 360
 361         u8         reserved_at_60[0x18];
 362         u8         log_max_ft_num[0x8];
 363
 364         u8         reserved_at_80[0x18];
 365         u8         log_max_destination[0x8];
 366
 367         u8         log_max_flow_counter[0x8];
 368         u8         reserved_at_a8[0x10];
 369         u8         log_max_flow[0x8];
 370
 371         u8         reserved_at_c0[0x40];
 372
 373         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 374
 375         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 376 };
 377
 378 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 379         u8         send[0x1];
 380         u8         receive[0x1];
 381         u8         write[0x1];
 382         u8         read[0x1];
 383         u8         atomic[0x1];
 384         u8         srq_receive[0x1];
 385         u8         reserved_at_6[0x1a];
 386 };
 387
 388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 389         u8         smac_47_16[0x20];
 390
 391         u8         smac_15_0[0x10];
 392         u8         ethertype[0x10];
 393
 394         u8         dmac_47_16[0x20];
 395
 396         u8         dmac_15_0[0x10];
 397         u8         first_prio[0x3];
 398         u8         first_cfi[0x1];
 399         u8         first_vid[0xc];
 400
 401         u8         ip_protocol[0x8];
 402         u8         ip_dscp[0x6];
 403         u8         ip_ecn[0x2];
 404         u8         cvlan_tag[0x1];
 405         u8         svlan_tag[0x1];
 406         u8         frag[0x1];
 407         u8         ip_version[0x4];
 408         u8         tcp_flags[0x9];
 409
 410         u8         tcp_sport[0x10];
 411         u8         tcp_dport[0x10];
 412
 413         u8         reserved_at_c0[0x18];
 414         u8         ttl_hoplimit[0x8];
 415
 416         u8         udp_sport[0x10];
 417         u8         udp_dport[0x10];
 418
 419         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 420
 421         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 422 };
 423
 424 struct mlx5_ifc_fte_match_set_misc_bits {
 425         u8         reserved_at_0[0x8];
 426         u8         source_sqn[0x18];
 427
 428         u8         source_eswitch_owner_vhca_id[0x10];
 429         u8         source_port[0x10];
 430
 431         u8         outer_second_prio[0x3];
 432         u8         outer_second_cfi[0x1];
 433         u8         outer_second_vid[0xc];
 434         u8         inner_second_prio[0x3];
 435         u8         inner_second_cfi[0x1];
 436         u8         inner_second_vid[0xc];
 437
 438         u8         outer_second_cvlan_tag[0x1];
 439         u8         inner_second_cvlan_tag[0x1];
 440         u8         outer_second_svlan_tag[0x1];
 441         u8         inner_second_svlan_tag[0x1];
 442         u8         reserved_at_64[0xc];
 443         u8         gre_protocol[0x10];
 444
 445         u8         gre_key_h[0x18];
 446         u8         gre_key_l[0x8];
 447
 448         u8         vxlan_vni[0x18];
 449         u8         reserved_at_b8[0x8];
 450
 451         u8         reserved_at_c0[0x20];
 452
 453         u8         reserved_at_e0[0xc];
 454         u8         outer_ipv6_flow_label[0x14];
 455
 456         u8         reserved_at_100[0xc];
 457         u8         inner_ipv6_flow_label[0x14];
 458
 459         u8         reserved_at_120[0x28];
 460         u8         bth_dst_qp[0x18];
 461         u8         reserved_at_160[0x20];
 462         u8         outer_esp_spi[0x20];
 463         u8         reserved_at_1a0[0x60];
 464 };
 465
 466 struct mlx5_ifc_fte_match_mpls_bits {
 467         u8         mpls_label[0x14];
 468         u8         mpls_exp[0x3];
 469         u8         mpls_s_bos[0x1];
 470         u8         mpls_ttl[0x8];
 471 };
 472
 473 struct mlx5_ifc_fte_match_set_misc2_bits {
 474         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 475
 476         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 477
 478         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 479
 480         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 481
 482         u8         reserved_at_80[0x100];
 483
 484         u8         metadata_reg_a[0x20];
 485
 486         u8         reserved_at_1a0[0x60];
 487 };
 488
 489 struct mlx5_ifc_cmd_pas_bits {
 490         u8         pa_h[0x20];
 491
 492         u8         pa_l[0x14];
 493         u8         reserved_at_34[0xc];
 494 };
 495
 496 struct mlx5_ifc_uint64_bits {
 497         u8         hi[0x20];
 498
 499         u8         lo[0x20];
 500 };
 501
 502 enum {
 503         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 504         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 505         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 506         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 507         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 508         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 509         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 510         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 511         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 512         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 513 };
 514
 515 struct mlx5_ifc_ads_bits {
 516         u8         fl[0x1];
 517         u8         free_ar[0x1];
 518         u8         reserved_at_2[0xe];
 519         u8         pkey_index[0x10];
 520
 521         u8         reserved_at_20[0x8];
 522         u8         grh[0x1];
 523         u8         mlid[0x7];
 524         u8         rlid[0x10];
 525
 526         u8         ack_timeout[0x5];
 527         u8         reserved_at_45[0x3];
 528         u8         src_addr_index[0x8];
 529         u8         reserved_at_50[0x4];
 530         u8         stat_rate[0x4];
 531         u8         hop_limit[0x8];
 532
 533         u8         reserved_at_60[0x4];
 534         u8         tclass[0x8];
 535         u8         flow_label[0x14];
 536
 537         u8         rgid_rip[16][0x8];
 538
 539         u8         reserved_at_100[0x4];
 540         u8         f_dscp[0x1];
 541         u8         f_ecn[0x1];
 542         u8         reserved_at_106[0x1];
 543         u8         f_eth_prio[0x1];
 544         u8         ecn[0x2];
 545         u8         dscp[0x6];
 546         u8         udp_sport[0x10];
 547
 548         u8         dei_cfi[0x1];
 549         u8         eth_prio[0x3];
 550         u8         sl[0x4];
 551         u8         vhca_port_num[0x8];
 552         u8         rmac_47_32[0x10];
 553
 554         u8         rmac_31_0[0x20];
 555 };
 556
 557 struct mlx5_ifc_flow_table_nic_cap_bits {
 558         u8         nic_rx_multi_path_tirs[0x1];
 559         u8         nic_rx_multi_path_tirs_fts[0x1];
 560         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 561         u8         reserved_at_3[0x1d];
 562         u8         encap_general_header[0x1];
 563         u8         reserved_at_21[0xa];
 564         u8         log_max_packet_reformat_context[0x5];
 565         u8         reserved_at_30[0x6];
 566         u8         max_encap_header_size[0xa];
 567         u8         reserved_at_40[0x1c0];
 568
 569         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 570
 571         u8         reserved_at_400[0x200];
 572
 573         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 574
 575         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 576
 577         u8         reserved_at_a00[0x200];
 578
 579         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 580
 581         u8         reserved_at_e00[0x7200];
 582 };
 583
 584 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 585         u8      reserved_at_0[0x1c];
 586         u8      fdb_multi_path_to_table[0x1];
 587         u8      reserved_at_1d[0x1];
 588         u8      multi_fdb_encap[0x1];
 589         u8      reserved_at_1f[0x1e1];
 590
 591         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 592
 593         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 594
 595         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 596
 597         u8      reserved_at_800[0x7800];
 598 };
 599
 600 struct mlx5_ifc_e_switch_cap_bits {
 601         u8         vport_svlan_strip[0x1];
 602         u8         vport_cvlan_strip[0x1];
 603         u8         vport_svlan_insert[0x1];
 604         u8         vport_cvlan_insert_if_not_exist[0x1];
 605         u8         vport_cvlan_insert_overwrite[0x1];
 606         u8         reserved_at_5[0x18];
 607         u8         merged_eswitch[0x1];
 608         u8         nic_vport_node_guid_modify[0x1];
 609         u8         nic_vport_port_guid_modify[0x1];
 610
 611         u8         vxlan_encap_decap[0x1];
 612         u8         nvgre_encap_decap[0x1];
 613         u8         reserved_at_22[0x9];
 614         u8         log_max_packet_reformat_context[0x5];
 615         u8         reserved_2b[0x6];
 616         u8         max_encap_header_size[0xa];
 617
 618         u8         reserved_40[0x7c0];
 619
 620 };
 621
 622 struct mlx5_ifc_qos_cap_bits {
 623         u8         packet_pacing[0x1];
 624         u8         esw_scheduling[0x1];
 625         u8         esw_bw_share[0x1];
 626         u8         esw_rate_limit[0x1];
 627         u8         reserved_at_4[0x1];
 628         u8         packet_pacing_burst_bound[0x1];
 629         u8         packet_pacing_typical_size[0x1];
 630         u8         reserved_at_7[0x19];
 631
 632         u8         reserved_at_20[0x20];
 633
 634         u8         packet_pacing_max_rate[0x20];
 635
 636         u8         packet_pacing_min_rate[0x20];
 637
 638         u8         reserved_at_80[0x10];
 639         u8         packet_pacing_rate_table_size[0x10];
 640
 641         u8         esw_element_type[0x10];
 642         u8         esw_tsar_type[0x10];
 643
 644         u8         reserved_at_c0[0x10];
 645         u8         max_qos_para_vport[0x10];
 646
 647         u8         max_tsar_bw_share[0x20];
 648
 649         u8         reserved_at_100[0x700];
 650 };
 651
 652 struct mlx5_ifc_debug_cap_bits {
 653         u8         reserved_at_0[0x20];
 654
 655         u8         reserved_at_20[0x2];
 656         u8         stall_detect[0x1];
 657         u8         reserved_at_23[0x1d];
 658
 659         u8         reserved_at_40[0x7c0];
 660 };
 661
 662 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 663         u8         csum_cap[0x1];
 664         u8         vlan_cap[0x1];
 665         u8         lro_cap[0x1];
 666         u8         lro_psh_flag[0x1];
 667         u8         lro_time_stamp[0x1];
 668         u8         reserved_at_5[0x2];
 669         u8         wqe_vlan_insert[0x1];
 670         u8         self_lb_en_modifiable[0x1];
 671         u8         reserved_at_9[0x2];
 672         u8         max_lso_cap[0x5];
 673         u8         multi_pkt_send_wqe[0x2];
 674         u8         wqe_inline_mode[0x2];
 675         u8         rss_ind_tbl_cap[0x4];
 676         u8         reg_umr_sq[0x1];
 677         u8         scatter_fcs[0x1];
 678         u8         enhanced_multi_pkt_send_wqe[0x1];
 679         u8         tunnel_lso_const_out_ip_id[0x1];
 680         u8         reserved_at_1c[0x2];
 681         u8         tunnel_stateless_gre[0x1];
 682         u8         tunnel_stateless_vxlan[0x1];
 683
 684         u8         swp[0x1];
 685         u8         swp_csum[0x1];
 686         u8         swp_lso[0x1];
 687         u8         reserved_at_23[0xd];
 688         u8         max_vxlan_udp_ports[0x8];
 689         u8         reserved_at_38[0x6];
 690         u8         max_geneve_opt_len[0x1];
 691         u8         tunnel_stateless_geneve_rx[0x1];
 692
 693         u8         reserved_at_40[0x10];
 694         u8         lro_min_mss_size[0x10];
 695
 696         u8         reserved_at_60[0x120];
 697
 698         u8         lro_timer_supported_periods[4][0x20];
 699
 700         u8         reserved_at_200[0x600];
 701 };
 702
 703 struct mlx5_ifc_roce_cap_bits {
 704         u8         roce_apm[0x1];
 705         u8         reserved_at_1[0x1f];
 706
 707         u8         reserved_at_20[0x60];
 708
 709         u8         reserved_at_80[0xc];
 710         u8         l3_type[0x4];
 711         u8         reserved_at_90[0x8];
 712         u8         roce_version[0x8];
 713
 714         u8         reserved_at_a0[0x10];
 715         u8         r_roce_dest_udp_port[0x10];
 716
 717         u8         r_roce_max_src_udp_port[0x10];
 718         u8         r_roce_min_src_udp_port[0x10];
 719
 720         u8         reserved_at_e0[0x10];
 721         u8         roce_address_table_size[0x10];
 722
 723         u8         reserved_at_100[0x700];
 724 };
 725
 726 struct mlx5_ifc_device_mem_cap_bits {
 727         u8         memic[0x1];
 728         u8         reserved_at_1[0x1f];
 729
 730         u8         reserved_at_20[0xb];
 731         u8         log_min_memic_alloc_size[0x5];
 732         u8         reserved_at_30[0x8];
 733         u8         log_max_memic_addr_alignment[0x8];
 734
 735         u8         memic_bar_start_addr[0x40];
 736
 737         u8         memic_bar_size[0x20];
 738
 739         u8         max_memic_size[0x20];
 740
 741         u8         reserved_at_c0[0x740];
 742 };
 743
 744 enum {
 745         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 746         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 747         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 748         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 749         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 750         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 751         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 752         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 753         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 754 };
 755
 756 enum {
 757         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 758         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 759         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 760         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 761         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 762         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 763         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 764         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 765         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 766 };
 767
 768 struct mlx5_ifc_atomic_caps_bits {
 769         u8         reserved_at_0[0x40];
 770
 771         u8         atomic_req_8B_endianness_mode[0x2];
 772         u8         reserved_at_42[0x4];
 773         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 774
 775         u8         reserved_at_47[0x19];
 776
 777         u8         reserved_at_60[0x20];
 778
 779         u8         reserved_at_80[0x10];
 780         u8         atomic_operations[0x10];
 781
 782         u8         reserved_at_a0[0x10];
 783         u8         atomic_size_qp[0x10];
 784
 785         u8         reserved_at_c0[0x10];
 786         u8         atomic_size_dc[0x10];
 787
 788         u8         reserved_at_e0[0x720];
 789 };
 790
 791 struct mlx5_ifc_odp_cap_bits {
 792         u8         reserved_at_0[0x40];
 793
 794         u8         sig[0x1];
 795         u8         reserved_at_41[0x1f];
 796
 797         u8         reserved_at_60[0x20];
 798
 799         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 800
 801         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 802
 803         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 804
 805         u8         reserved_at_e0[0x720];
 806 };
 807
 808 struct mlx5_ifc_calc_op {
 809         u8        reserved_at_0[0x10];
 810         u8        reserved_at_10[0x9];
 811         u8        op_swap_endianness[0x1];
 812         u8        op_min[0x1];
 813         u8        op_xor[0x1];
 814         u8        op_or[0x1];
 815         u8        op_and[0x1];
 816         u8        op_max[0x1];
 817         u8        op_add[0x1];
 818 };
 819
 820 struct mlx5_ifc_vector_calc_cap_bits {
 821         u8         calc_matrix[0x1];
 822         u8         reserved_at_1[0x1f];
 823         u8         reserved_at_20[0x8];
 824         u8         max_vec_count[0x8];
 825         u8         reserved_at_30[0xd];
 826         u8         max_chunk_size[0x3];
 827         struct mlx5_ifc_calc_op calc0;
 828         struct mlx5_ifc_calc_op calc1;
 829         struct mlx5_ifc_calc_op calc2;
 830         struct mlx5_ifc_calc_op calc3;
 831
 832         u8         reserved_at_c0[0x720];
 833 };
 834
 835 enum {
 836         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 837         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 838         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 839         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 840 };
 841
 842 enum {
 843         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 844         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 845 };
 846
 847 enum {
 848         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 849         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 850         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 851         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 852         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 853 };
 854
 855 enum {
 856         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 857         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 858         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 859         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 860         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 861         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 862 };
 863
 864 enum {
 865         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 866         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 867 };
 868
 869 enum {
 870         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 871         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 872         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 873 };
 874
 875 enum {
 876         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 877         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 878 };
 879
 880 enum {
 881         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 882         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 883         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 884 };
 885
 886 enum {
 887         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
 888 };
 889
 890 struct mlx5_ifc_cmd_hca_cap_bits {
 891         u8         reserved_at_0[0x30];
 892         u8         vhca_id[0x10];
 893
 894         u8         reserved_at_40[0x40];
 895
 896         u8         log_max_srq_sz[0x8];
 897         u8         log_max_qp_sz[0x8];
 898         u8         reserved_at_90[0xb];
 899         u8         log_max_qp[0x5];
 900
 901         u8         reserved_at_a0[0xb];
 902         u8         log_max_srq[0x5];
 903         u8         reserved_at_b0[0x10];
 904
 905         u8         reserved_at_c0[0x8];
 906         u8         log_max_cq_sz[0x8];
 907         u8         reserved_at_d0[0xb];
 908         u8         log_max_cq[0x5];
 909
 910         u8         log_max_eq_sz[0x8];
 911         u8         reserved_at_e8[0x2];
 912         u8         log_max_mkey[0x6];
 913         u8         reserved_at_f0[0x8];
 914         u8         dump_fill_mkey[0x1];
 915         u8         reserved_at_f9[0x2];
 916         u8         fast_teardown[0x1];
 917         u8         log_max_eq[0x4];
 918
 919         u8         max_indirection[0x8];
 920         u8         fixed_buffer_size[0x1];
 921         u8         log_max_mrw_sz[0x7];
 922         u8         force_teardown[0x1];
 923         u8         reserved_at_111[0x1];
 924         u8         log_max_bsf_list_size[0x6];
 925         u8         umr_extended_translation_offset[0x1];
 926         u8         null_mkey[0x1];
 927         u8         log_max_klm_list_size[0x6];
 928
 929         u8         reserved_at_120[0xa];
 930         u8         log_max_ra_req_dc[0x6];
 931         u8         reserved_at_130[0xa];
 932         u8         log_max_ra_res_dc[0x6];
 933
 934         u8         reserved_at_140[0xa];
 935         u8         log_max_ra_req_qp[0x6];
 936         u8         reserved_at_150[0xa];
 937         u8         log_max_ra_res_qp[0x6];
 938
 939         u8         end_pad[0x1];
 940         u8         cc_query_allowed[0x1];
 941         u8         cc_modify_allowed[0x1];
 942         u8         start_pad[0x1];
 943         u8         cache_line_128byte[0x1];
 944         u8         reserved_at_165[0xa];
 945         u8         qcam_reg[0x1];
 946         u8         gid_table_size[0x10];
 947
 948         u8         out_of_seq_cnt[0x1];
 949         u8         vport_counters[0x1];
 950         u8         retransmission_q_counters[0x1];
 951         u8         debug[0x1];
 952         u8         modify_rq_counter_set_id[0x1];
 953         u8         rq_delay_drop[0x1];
 954         u8         max_qp_cnt[0xa];
 955         u8         pkey_table_size[0x10];
 956
 957         u8         vport_group_manager[0x1];
 958         u8         vhca_group_manager[0x1];
 959         u8         ib_virt[0x1];
 960         u8         eth_virt[0x1];
 961         u8         vnic_env_queue_counters[0x1];
 962         u8         ets[0x1];
 963         u8         nic_flow_table[0x1];
 964         u8         eswitch_manager[0x1];
 965         u8         device_memory[0x1];
 966         u8         mcam_reg[0x1];
 967         u8         pcam_reg[0x1];
 968         u8         local_ca_ack_delay[0x5];
 969         u8         port_module_event[0x1];
 970         u8         enhanced_error_q_counters[0x1];
 971         u8         ports_check[0x1];
 972         u8         reserved_at_1b3[0x1];
 973         u8         disable_link_up[0x1];
 974         u8         beacon_led[0x1];
 975         u8         port_type[0x2];
 976         u8         num_ports[0x8];
 977
 978         u8         reserved_at_1c0[0x1];
 979         u8         pps[0x1];
 980         u8         pps_modify[0x1];
 981         u8         log_max_msg[0x5];
 982         u8         reserved_at_1c8[0x4];
 983         u8         max_tc[0x4];
 984         u8         temp_warn_event[0x1];
 985         u8         dcbx[0x1];
 986         u8         general_notification_event[0x1];
 987         u8         reserved_at_1d3[0x2];
 988         u8         fpga[0x1];
 989         u8         rol_s[0x1];
 990         u8         rol_g[0x1];
 991         u8         reserved_at_1d8[0x1];
 992         u8         wol_s[0x1];
 993         u8         wol_g[0x1];
 994         u8         wol_a[0x1];
 995         u8         wol_b[0x1];
 996         u8         wol_m[0x1];
 997         u8         wol_u[0x1];
 998         u8         wol_p[0x1];
 999
1000         u8         stat_rate_support[0x10];
1001         u8         reserved_at_1f0[0xc];
1002         u8         cqe_version[0x4];
1003
1004         u8         compact_address_vector[0x1];
1005         u8         striding_rq[0x1];
1006         u8         reserved_at_202[0x1];
1007         u8         ipoib_enhanced_offloads[0x1];
1008         u8         ipoib_basic_offloads[0x1];
1009         u8         reserved_at_205[0x1];
1010         u8         repeated_block_disabled[0x1];
1011         u8         umr_modify_entity_size_disabled[0x1];
1012         u8         umr_modify_atomic_disabled[0x1];
1013         u8         umr_indirect_mkey_disabled[0x1];
1014         u8         umr_fence[0x2];
1015         u8         dc_req_scat_data_cqe[0x1];
1016         u8         reserved_at_20d[0x2];
1017         u8         drain_sigerr[0x1];
1018         u8         cmdif_checksum[0x2];
1019         u8         sigerr_cqe[0x1];
1020         u8         reserved_at_213[0x1];
1021         u8         wq_signature[0x1];
1022         u8         sctr_data_cqe[0x1];
1023         u8         reserved_at_216[0x1];
1024         u8         sho[0x1];
1025         u8         tph[0x1];
1026         u8         rf[0x1];
1027         u8         dct[0x1];
1028         u8         qos[0x1];
1029         u8         eth_net_offloads[0x1];
1030         u8         roce[0x1];
1031         u8         atomic[0x1];
1032         u8         reserved_at_21f[0x1];
1033
1034         u8         cq_oi[0x1];
1035         u8         cq_resize[0x1];
1036         u8         cq_moderation[0x1];
1037         u8         reserved_at_223[0x3];
1038         u8         cq_eq_remap[0x1];
1039         u8         pg[0x1];
1040         u8         block_lb_mc[0x1];
1041         u8         reserved_at_229[0x1];
1042         u8         scqe_break_moderation[0x1];
1043         u8         cq_period_start_from_cqe[0x1];
1044         u8         cd[0x1];
1045         u8         reserved_at_22d[0x1];
1046         u8         apm[0x1];
1047         u8         vector_calc[0x1];
1048         u8         umr_ptr_rlky[0x1];
1049         u8         imaicl[0x1];
1050         u8         reserved_at_232[0x4];
1051         u8         qkv[0x1];
1052         u8         pkv[0x1];
1053         u8         set_deth_sqpn[0x1];
1054         u8         reserved_at_239[0x3];
1055         u8         xrc[0x1];
1056         u8         ud[0x1];
1057         u8         uc[0x1];
1058         u8         rc[0x1];
1059
1060         u8         uar_4k[0x1];
1061         u8         reserved_at_241[0x9];
1062         u8         uar_sz[0x6];
1063         u8         reserved_at_250[0x8];
1064         u8         log_pg_sz[0x8];
1065
1066         u8         bf[0x1];
1067         u8         driver_version[0x1];
1068         u8         pad_tx_eth_packet[0x1];
1069         u8         reserved_at_263[0x8];
1070         u8         log_bf_reg_size[0x5];
1071
1072         u8         reserved_at_270[0xb];
1073         u8         lag_master[0x1];
1074         u8         num_lag_ports[0x4];
1075
1076         u8         reserved_at_280[0x10];
1077         u8         max_wqe_sz_sq[0x10];
1078
1079         u8         reserved_at_2a0[0x10];
1080         u8         max_wqe_sz_rq[0x10];
1081
1082         u8         max_flow_counter_31_16[0x10];
1083         u8         max_wqe_sz_sq_dc[0x10];
1084
1085         u8         reserved_at_2e0[0x7];
1086         u8         max_qp_mcg[0x19];
1087
1088         u8         reserved_at_300[0x18];
1089         u8         log_max_mcg[0x8];
1090
1091         u8         reserved_at_320[0x3];
1092         u8         log_max_transport_domain[0x5];
1093         u8         reserved_at_328[0x3];
1094         u8         log_max_pd[0x5];
1095         u8         reserved_at_330[0xb];
1096         u8         log_max_xrcd[0x5];
1097
1098         u8         nic_receive_steering_discard[0x1];
1099         u8         receive_discard_vport_down[0x1];
1100         u8         transmit_discard_vport_down[0x1];
1101         u8         reserved_at_343[0x5];
1102         u8         log_max_flow_counter_bulk[0x8];
1103         u8         max_flow_counter_15_0[0x10];
1104
1105
1106         u8         reserved_at_360[0x3];
1107         u8         log_max_rq[0x5];
1108         u8         reserved_at_368[0x3];
1109         u8         log_max_sq[0x5];
1110         u8         reserved_at_370[0x3];
1111         u8         log_max_tir[0x5];
1112         u8         reserved_at_378[0x3];
1113         u8         log_max_tis[0x5];
1114
1115         u8         basic_cyclic_rcv_wqe[0x1];
1116         u8         reserved_at_381[0x2];
1117         u8         log_max_rmp[0x5];
1118         u8         reserved_at_388[0x3];
1119         u8         log_max_rqt[0x5];
1120         u8         reserved_at_390[0x3];
1121         u8         log_max_rqt_size[0x5];
1122         u8         reserved_at_398[0x3];
1123         u8         log_max_tis_per_sq[0x5];
1124
1125         u8         ext_stride_num_range[0x1];
1126         u8         reserved_at_3a1[0x2];
1127         u8         log_max_stride_sz_rq[0x5];
1128         u8         reserved_at_3a8[0x3];
1129         u8         log_min_stride_sz_rq[0x5];
1130         u8         reserved_at_3b0[0x3];
1131         u8         log_max_stride_sz_sq[0x5];
1132         u8         reserved_at_3b8[0x3];
1133         u8         log_min_stride_sz_sq[0x5];
1134
1135         u8         hairpin[0x1];
1136         u8         reserved_at_3c1[0x2];
1137         u8         log_max_hairpin_queues[0x5];
1138         u8         reserved_at_3c8[0x3];
1139         u8         log_max_hairpin_wq_data_sz[0x5];
1140         u8         reserved_at_3d0[0x3];
1141         u8         log_max_hairpin_num_packets[0x5];
1142         u8         reserved_at_3d8[0x3];
1143         u8         log_max_wq_sz[0x5];
1144
1145         u8         nic_vport_change_event[0x1];
1146         u8         disable_local_lb_uc[0x1];
1147         u8         disable_local_lb_mc[0x1];
1148         u8         log_min_hairpin_wq_data_sz[0x5];
1149         u8         reserved_at_3e8[0x3];
1150         u8         log_max_vlan_list[0x5];
1151         u8         reserved_at_3f0[0x3];
1152         u8         log_max_current_mc_list[0x5];
1153         u8         reserved_at_3f8[0x3];
1154         u8         log_max_current_uc_list[0x5];
1155
1156         u8         general_obj_types[0x40];
1157
1158         u8         reserved_at_440[0x20];
1159
1160         u8         reserved_at_460[0x10];
1161         u8         max_num_eqs[0x10];
1162
1163         u8         reserved_at_480[0x3];
1164         u8         log_max_l2_table[0x5];
1165         u8         reserved_at_488[0x8];
1166         u8         log_uar_page_sz[0x10];
1167
1168         u8         reserved_at_4a0[0x20];
1169         u8         device_frequency_mhz[0x20];
1170         u8         device_frequency_khz[0x20];
1171
1172         u8         reserved_at_500[0x20];
1173         u8         num_of_uars_per_page[0x20];
1174
1175         u8         flex_parser_protocols[0x20];
1176         u8         reserved_at_560[0x20];
1177
1178         u8         reserved_at_580[0x3c];
1179         u8         mini_cqe_resp_stride_index[0x1];
1180         u8         cqe_128_always[0x1];
1181         u8         cqe_compression_128[0x1];
1182         u8         cqe_compression[0x1];
1183
1184         u8         cqe_compression_timeout[0x10];
1185         u8         cqe_compression_max_num[0x10];
1186
1187         u8         reserved_at_5e0[0x10];
1188         u8         tag_matching[0x1];
1189         u8         rndv_offload_rc[0x1];
1190         u8         rndv_offload_dc[0x1];
1191         u8         log_tag_matching_list_sz[0x5];
1192         u8         reserved_at_5f8[0x3];
1193         u8         log_max_xrq[0x5];
1194
1195         u8         affiliate_nic_vport_criteria[0x8];
1196         u8         native_port_num[0x8];
1197         u8         num_vhca_ports[0x8];
1198         u8         reserved_at_618[0x6];
1199         u8         sw_owner_id[0x1];
1200         u8         reserved_at_61f[0x1];
1201
1202         u8         reserved_at_620[0x80];
1203
1204         u8         uctx_cap[0x20];
1205
1206         u8         reserved_at_6c0[0x140];
1207 };
1208
1209 enum mlx5_flow_destination_type {
1210         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1211         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1212         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1213
1214         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1215         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1216         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1217 };
1218
1219 struct mlx5_ifc_dest_format_struct_bits {
1220         u8         destination_type[0x8];
1221         u8         destination_id[0x18];
1222         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1223         u8         reserved_at_21[0xf];
1224         u8         destination_eswitch_owner_vhca_id[0x10];
1225 };
1226
1227 struct mlx5_ifc_flow_counter_list_bits {
1228         u8         flow_counter_id[0x20];
1229
1230         u8         reserved_at_20[0x20];
1231 };
1232
1233 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1234         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1235         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1236         u8         reserved_at_0[0x40];
1237 };
1238
1239 struct mlx5_ifc_fte_match_param_bits {
1240         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1241
1242         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1243
1244         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1245
1246         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1247
1248         u8         reserved_at_800[0x800];
1249 };
1250
1251 enum {
1252         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1253         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1254         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1255         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1256         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1257 };
1258
1259 struct mlx5_ifc_rx_hash_field_select_bits {
1260         u8         l3_prot_type[0x1];
1261         u8         l4_prot_type[0x1];
1262         u8         selected_fields[0x1e];
1263 };
1264
1265 enum {
1266         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1267         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1268 };
1269
1270 enum {
1271         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1272         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1273 };
1274
1275 struct mlx5_ifc_wq_bits {
1276         u8         wq_type[0x4];
1277         u8         wq_signature[0x1];
1278         u8         end_padding_mode[0x2];
1279         u8         cd_slave[0x1];
1280         u8         reserved_at_8[0x18];
1281
1282         u8         hds_skip_first_sge[0x1];
1283         u8         log2_hds_buf_size[0x3];
1284         u8         reserved_at_24[0x7];
1285         u8         page_offset[0x5];
1286         u8         lwm[0x10];
1287
1288         u8         reserved_at_40[0x8];
1289         u8         pd[0x18];
1290
1291         u8         reserved_at_60[0x8];
1292         u8         uar_page[0x18];
1293
1294         u8         dbr_addr[0x40];
1295
1296         u8         hw_counter[0x20];
1297
1298         u8         sw_counter[0x20];
1299
1300         u8         reserved_at_100[0xc];
1301         u8         log_wq_stride[0x4];
1302         u8         reserved_at_110[0x3];
1303         u8         log_wq_pg_sz[0x5];
1304         u8         reserved_at_118[0x3];
1305         u8         log_wq_sz[0x5];
1306
1307         u8         dbr_umem_valid[0x1];
1308         u8         wq_umem_valid[0x1];
1309         u8         reserved_at_122[0x1];
1310         u8         log_hairpin_num_packets[0x5];
1311         u8         reserved_at_128[0x3];
1312         u8         log_hairpin_data_sz[0x5];
1313
1314         u8         reserved_at_130[0x4];
1315         u8         log_wqe_num_of_strides[0x4];
1316         u8         two_byte_shift_en[0x1];
1317         u8         reserved_at_139[0x4];
1318         u8         log_wqe_stride_size[0x3];
1319
1320         u8         reserved_at_140[0x4c0];
1321
1322         struct mlx5_ifc_cmd_pas_bits pas[0];
1323 };
1324
1325 struct mlx5_ifc_rq_num_bits {
1326         u8         reserved_at_0[0x8];
1327         u8         rq_num[0x18];
1328 };
1329
1330 struct mlx5_ifc_mac_address_layout_bits {
1331         u8         reserved_at_0[0x10];
1332         u8         mac_addr_47_32[0x10];
1333
1334         u8         mac_addr_31_0[0x20];
1335 };
1336
1337 struct mlx5_ifc_vlan_layout_bits {
1338         u8         reserved_at_0[0x14];
1339         u8         vlan[0x0c];
1340
1341         u8         reserved_at_20[0x20];
1342 };
1343
1344 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1345         u8         reserved_at_0[0xa0];
1346
1347         u8         min_time_between_cnps[0x20];
1348
1349         u8         reserved_at_c0[0x12];
1350         u8         cnp_dscp[0x6];
1351         u8         reserved_at_d8[0x4];
1352         u8         cnp_prio_mode[0x1];
1353         u8         cnp_802p_prio[0x3];
1354
1355         u8         reserved_at_e0[0x720];
1356 };
1357
1358 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1359         u8         reserved_at_0[0x60];
1360
1361         u8         reserved_at_60[0x4];
1362         u8         clamp_tgt_rate[0x1];
1363         u8         reserved_at_65[0x3];
1364         u8         clamp_tgt_rate_after_time_inc[0x1];
1365         u8         reserved_at_69[0x17];
1366
1367         u8         reserved_at_80[0x20];
1368
1369         u8         rpg_time_reset[0x20];
1370
1371         u8         rpg_byte_reset[0x20];
1372
1373         u8         rpg_threshold[0x20];
1374
1375         u8         rpg_max_rate[0x20];
1376
1377         u8         rpg_ai_rate[0x20];
1378
1379         u8         rpg_hai_rate[0x20];
1380
1381         u8         rpg_gd[0x20];
1382
1383         u8         rpg_min_dec_fac[0x20];
1384
1385         u8         rpg_min_rate[0x20];
1386
1387         u8         reserved_at_1c0[0xe0];
1388
1389         u8         rate_to_set_on_first_cnp[0x20];
1390
1391         u8         dce_tcp_g[0x20];
1392
1393         u8         dce_tcp_rtt[0x20];
1394
1395         u8         rate_reduce_monitor_period[0x20];
1396
1397         u8         reserved_at_320[0x20];
1398
1399         u8         initial_alpha_value[0x20];
1400
1401         u8         reserved_at_360[0x4a0];
1402 };
1403
1404 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1405         u8         reserved_at_0[0x80];
1406
1407         u8         rppp_max_rps[0x20];
1408
1409         u8         rpg_time_reset[0x20];
1410
1411         u8         rpg_byte_reset[0x20];
1412
1413         u8         rpg_threshold[0x20];
1414
1415         u8         rpg_max_rate[0x20];
1416
1417         u8         rpg_ai_rate[0x20];
1418
1419         u8         rpg_hai_rate[0x20];
1420
1421         u8         rpg_gd[0x20];
1422
1423         u8         rpg_min_dec_fac[0x20];
1424
1425         u8         rpg_min_rate[0x20];
1426
1427         u8         reserved_at_1c0[0x640];
1428 };
1429
1430 enum {
1431         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1432         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1433         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1434 };
1435
1436 struct mlx5_ifc_resize_field_select_bits {
1437         u8         resize_field_select[0x20];
1438 };
1439
1440 enum {
1441         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1442         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1443         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1444         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1445 };
1446
1447 struct mlx5_ifc_modify_field_select_bits {
1448         u8         modify_field_select[0x20];
1449 };
1450
1451 struct mlx5_ifc_field_select_r_roce_np_bits {
1452         u8         field_select_r_roce_np[0x20];
1453 };
1454
1455 struct mlx5_ifc_field_select_r_roce_rp_bits {
1456         u8         field_select_r_roce_rp[0x20];
1457 };
1458
1459 enum {
1460         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1461         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1462         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1463         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1464         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1465         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1466         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1467         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1468         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1469         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1470 };
1471
1472 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1473         u8         field_select_8021qaurp[0x20];
1474 };
1475
1476 struct mlx5_ifc_phys_layer_cntrs_bits {
1477         u8         time_since_last_clear_high[0x20];
1478
1479         u8         time_since_last_clear_low[0x20];
1480
1481         u8         symbol_errors_high[0x20];
1482
1483         u8         symbol_errors_low[0x20];
1484
1485         u8         sync_headers_errors_high[0x20];
1486
1487         u8         sync_headers_errors_low[0x20];
1488
1489         u8         edpl_bip_errors_lane0_high[0x20];
1490
1491         u8         edpl_bip_errors_lane0_low[0x20];
1492
1493         u8         edpl_bip_errors_lane1_high[0x20];
1494
1495         u8         edpl_bip_errors_lane1_low[0x20];
1496
1497         u8         edpl_bip_errors_lane2_high[0x20];
1498
1499         u8         edpl_bip_errors_lane2_low[0x20];
1500
1501         u8         edpl_bip_errors_lane3_high[0x20];
1502
1503         u8         edpl_bip_errors_lane3_low[0x20];
1504
1505         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1506
1507         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1508
1509         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1510
1511         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1512
1513         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1514
1515         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1516
1517         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1518
1519         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1520
1521         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1522
1523         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1524
1525         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1526
1527         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1528
1529         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1530
1531         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1532
1533         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1534
1535         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1536
1537         u8         rs_fec_corrected_blocks_high[0x20];
1538
1539         u8         rs_fec_corrected_blocks_low[0x20];
1540
1541         u8         rs_fec_uncorrectable_blocks_high[0x20];
1542
1543         u8         rs_fec_uncorrectable_blocks_low[0x20];
1544
1545         u8         rs_fec_no_errors_blocks_high[0x20];
1546
1547         u8         rs_fec_no_errors_blocks_low[0x20];
1548
1549         u8         rs_fec_single_error_blocks_high[0x20];
1550
1551         u8         rs_fec_single_error_blocks_low[0x20];
1552
1553         u8         rs_fec_corrected_symbols_total_high[0x20];
1554
1555         u8         rs_fec_corrected_symbols_total_low[0x20];
1556
1557         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1558
1559         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1560
1561         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1562
1563         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1564
1565         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1566
1567         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1568
1569         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1570
1571         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1572
1573         u8         link_down_events[0x20];
1574
1575         u8         successful_recovery_events[0x20];
1576
1577         u8         reserved_at_640[0x180];
1578 };
1579
1580 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1581         u8         time_since_last_clear_high[0x20];
1582
1583         u8         time_since_last_clear_low[0x20];
1584
1585         u8         phy_received_bits_high[0x20];
1586
1587         u8         phy_received_bits_low[0x20];
1588
1589         u8         phy_symbol_errors_high[0x20];
1590
1591         u8         phy_symbol_errors_low[0x20];
1592
1593         u8         phy_corrected_bits_high[0x20];
1594
1595         u8         phy_corrected_bits_low[0x20];
1596
1597         u8         phy_corrected_bits_lane0_high[0x20];
1598
1599         u8         phy_corrected_bits_lane0_low[0x20];
1600
1601         u8         phy_corrected_bits_lane1_high[0x20];
1602
1603         u8         phy_corrected_bits_lane1_low[0x20];
1604
1605         u8         phy_corrected_bits_lane2_high[0x20];
1606
1607         u8         phy_corrected_bits_lane2_low[0x20];
1608
1609         u8         phy_corrected_bits_lane3_high[0x20];
1610
1611         u8         phy_corrected_bits_lane3_low[0x20];
1612
1613         u8         reserved_at_200[0x5c0];
1614 };
1615
1616 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1617         u8         symbol_error_counter[0x10];
1618
1619         u8         link_error_recovery_counter[0x8];
1620
1621         u8         link_downed_counter[0x8];
1622
1623         u8         port_rcv_errors[0x10];
1624
1625         u8         port_rcv_remote_physical_errors[0x10];
1626
1627         u8         port_rcv_switch_relay_errors[0x10];
1628
1629         u8         port_xmit_discards[0x10];
1630
1631         u8         port_xmit_constraint_errors[0x8];
1632
1633         u8         port_rcv_constraint_errors[0x8];
1634
1635         u8         reserved_at_70[0x8];
1636
1637         u8         link_overrun_errors[0x8];
1638
1639         u8         reserved_at_80[0x10];
1640
1641         u8         vl_15_dropped[0x10];
1642
1643         u8         reserved_at_a0[0x80];
1644
1645         u8         port_xmit_wait[0x20];
1646 };
1647
1648 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1649         u8         transmit_queue_high[0x20];
1650
1651         u8         transmit_queue_low[0x20];
1652
1653         u8         reserved_at_40[0x780];
1654 };
1655
1656 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1657         u8         rx_octets_high[0x20];
1658
1659         u8         rx_octets_low[0x20];
1660
1661         u8         reserved_at_40[0xc0];
1662
1663         u8         rx_frames_high[0x20];
1664
1665         u8         rx_frames_low[0x20];
1666
1667         u8         tx_octets_high[0x20];
1668
1669         u8         tx_octets_low[0x20];
1670
1671         u8         reserved_at_180[0xc0];
1672
1673         u8         tx_frames_high[0x20];
1674
1675         u8         tx_frames_low[0x20];
1676
1677         u8         rx_pause_high[0x20];
1678
1679         u8         rx_pause_low[0x20];
1680
1681         u8         rx_pause_duration_high[0x20];
1682
1683         u8         rx_pause_duration_low[0x20];
1684
1685         u8         tx_pause_high[0x20];
1686
1687         u8         tx_pause_low[0x20];
1688
1689         u8         tx_pause_duration_high[0x20];
1690
1691         u8         tx_pause_duration_low[0x20];
1692
1693         u8         rx_pause_transition_high[0x20];
1694
1695         u8         rx_pause_transition_low[0x20];
1696
1697         u8         reserved_at_3c0[0x40];
1698
1699         u8         device_stall_minor_watermark_cnt_high[0x20];
1700
1701         u8         device_stall_minor_watermark_cnt_low[0x20];
1702
1703         u8         device_stall_critical_watermark_cnt_high[0x20];
1704
1705         u8         device_stall_critical_watermark_cnt_low[0x20];
1706
1707         u8         reserved_at_480[0x340];
1708 };
1709
1710 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1711         u8         port_transmit_wait_high[0x20];
1712
1713         u8         port_transmit_wait_low[0x20];
1714
1715         u8         reserved_at_40[0x100];
1716
1717         u8         rx_buffer_almost_full_high[0x20];
1718
1719         u8         rx_buffer_almost_full_low[0x20];
1720
1721         u8         rx_buffer_full_high[0x20];
1722
1723         u8         rx_buffer_full_low[0x20];
1724
1725         u8         rx_icrc_encapsulated_high[0x20];
1726
1727         u8         rx_icrc_encapsulated_low[0x20];
1728
1729         u8         reserved_at_200[0x5c0];
1730 };
1731
1732 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1733         u8         dot3stats_alignment_errors_high[0x20];
1734
1735         u8         dot3stats_alignment_errors_low[0x20];
1736
1737         u8         dot3stats_fcs_errors_high[0x20];
1738
1739         u8         dot3stats_fcs_errors_low[0x20];
1740
1741         u8         dot3stats_single_collision_frames_high[0x20];
1742
1743         u8         dot3stats_single_collision_frames_low[0x20];
1744
1745         u8         dot3stats_multiple_collision_frames_high[0x20];
1746
1747         u8         dot3stats_multiple_collision_frames_low[0x20];
1748
1749         u8         dot3stats_sqe_test_errors_high[0x20];
1750
1751         u8         dot3stats_sqe_test_errors_low[0x20];
1752
1753         u8         dot3stats_deferred_transmissions_high[0x20];
1754
1755         u8         dot3stats_deferred_transmissions_low[0x20];
1756
1757         u8         dot3stats_late_collisions_high[0x20];
1758
1759         u8         dot3stats_late_collisions_low[0x20];
1760
1761         u8         dot3stats_excessive_collisions_high[0x20];
1762
1763         u8         dot3stats_excessive_collisions_low[0x20];
1764
1765         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1766
1767         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1768
1769         u8         dot3stats_carrier_sense_errors_high[0x20];
1770
1771         u8         dot3stats_carrier_sense_errors_low[0x20];
1772
1773         u8         dot3stats_frame_too_longs_high[0x20];
1774
1775         u8         dot3stats_frame_too_longs_low[0x20];
1776
1777         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1778
1779         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1780
1781         u8         dot3stats_symbol_errors_high[0x20];
1782
1783         u8         dot3stats_symbol_errors_low[0x20];
1784
1785         u8         dot3control_in_unknown_opcodes_high[0x20];
1786
1787         u8         dot3control_in_unknown_opcodes_low[0x20];
1788
1789         u8         dot3in_pause_frames_high[0x20];
1790
1791         u8         dot3in_pause_frames_low[0x20];
1792
1793         u8         dot3out_pause_frames_high[0x20];
1794
1795         u8         dot3out_pause_frames_low[0x20];
1796
1797         u8         reserved_at_400[0x3c0];
1798 };
1799
1800 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1801         u8         ether_stats_drop_events_high[0x20];
1802
1803         u8         ether_stats_drop_events_low[0x20];
1804
1805         u8         ether_stats_octets_high[0x20];
1806
1807         u8         ether_stats_octets_low[0x20];
1808
1809         u8         ether_stats_pkts_high[0x20];
1810
1811         u8         ether_stats_pkts_low[0x20];
1812
1813         u8         ether_stats_broadcast_pkts_high[0x20];
1814
1815         u8         ether_stats_broadcast_pkts_low[0x20];
1816
1817         u8         ether_stats_multicast_pkts_high[0x20];
1818
1819         u8         ether_stats_multicast_pkts_low[0x20];
1820
1821         u8         ether_stats_crc_align_errors_high[0x20];
1822
1823         u8         ether_stats_crc_align_errors_low[0x20];
1824
1825         u8         ether_stats_undersize_pkts_high[0x20];
1826
1827         u8         ether_stats_undersize_pkts_low[0x20];
1828
1829         u8         ether_stats_oversize_pkts_high[0x20];
1830
1831         u8         ether_stats_oversize_pkts_low[0x20];
1832
1833         u8         ether_stats_fragments_high[0x20];
1834
1835         u8         ether_stats_fragments_low[0x20];
1836
1837         u8         ether_stats_jabbers_high[0x20];
1838
1839         u8         ether_stats_jabbers_low[0x20];
1840
1841         u8         ether_stats_collisions_high[0x20];
1842
1843         u8         ether_stats_collisions_low[0x20];
1844
1845         u8         ether_stats_pkts64octets_high[0x20];
1846
1847         u8         ether_stats_pkts64octets_low[0x20];
1848
1849         u8         ether_stats_pkts65to127octets_high[0x20];
1850
1851         u8         ether_stats_pkts65to127octets_low[0x20];
1852
1853         u8         ether_stats_pkts128to255octets_high[0x20];
1854
1855         u8         ether_stats_pkts128to255octets_low[0x20];
1856
1857         u8         ether_stats_pkts256to511octets_high[0x20];
1858
1859         u8         ether_stats_pkts256to511octets_low[0x20];
1860
1861         u8         ether_stats_pkts512to1023octets_high[0x20];
1862
1863         u8         ether_stats_pkts512to1023octets_low[0x20];
1864
1865         u8         ether_stats_pkts1024to1518octets_high[0x20];
1866
1867         u8         ether_stats_pkts1024to1518octets_low[0x20];
1868
1869         u8         ether_stats_pkts1519to2047octets_high[0x20];
1870
1871         u8         ether_stats_pkts1519to2047octets_low[0x20];
1872
1873         u8         ether_stats_pkts2048to4095octets_high[0x20];
1874
1875         u8         ether_stats_pkts2048to4095octets_low[0x20];
1876
1877         u8         ether_stats_pkts4096to8191octets_high[0x20];
1878
1879         u8         ether_stats_pkts4096to8191octets_low[0x20];
1880
1881         u8         ether_stats_pkts8192to10239octets_high[0x20];
1882
1883         u8         ether_stats_pkts8192to10239octets_low[0x20];
1884
1885         u8         reserved_at_540[0x280];
1886 };
1887
1888 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1889         u8         if_in_octets_high[0x20];
1890
1891         u8         if_in_octets_low[0x20];
1892
1893         u8         if_in_ucast_pkts_high[0x20];
1894
1895         u8         if_in_ucast_pkts_low[0x20];
1896
1897         u8         if_in_discards_high[0x20];
1898
1899         u8         if_in_discards_low[0x20];
1900
1901         u8         if_in_errors_high[0x20];
1902
1903         u8         if_in_errors_low[0x20];
1904
1905         u8         if_in_unknown_protos_high[0x20];
1906
1907         u8         if_in_unknown_protos_low[0x20];
1908
1909         u8         if_out_octets_high[0x20];
1910
1911         u8         if_out_octets_low[0x20];
1912
1913         u8         if_out_ucast_pkts_high[0x20];
1914
1915         u8         if_out_ucast_pkts_low[0x20];
1916
1917         u8         if_out_discards_high[0x20];
1918
1919         u8         if_out_discards_low[0x20];
1920
1921         u8         if_out_errors_high[0x20];
1922
1923         u8         if_out_errors_low[0x20];
1924
1925         u8         if_in_multicast_pkts_high[0x20];
1926
1927         u8         if_in_multicast_pkts_low[0x20];
1928
1929         u8         if_in_broadcast_pkts_high[0x20];
1930
1931         u8         if_in_broadcast_pkts_low[0x20];
1932
1933         u8         if_out_multicast_pkts_high[0x20];
1934
1935         u8         if_out_multicast_pkts_low[0x20];
1936
1937         u8         if_out_broadcast_pkts_high[0x20];
1938
1939         u8         if_out_broadcast_pkts_low[0x20];
1940
1941         u8         reserved_at_340[0x480];
1942 };
1943
1944 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1945         u8         a_frames_transmitted_ok_high[0x20];
1946
1947         u8         a_frames_transmitted_ok_low[0x20];
1948
1949         u8         a_frames_received_ok_high[0x20];
1950
1951         u8         a_frames_received_ok_low[0x20];
1952
1953         u8         a_frame_check_sequence_errors_high[0x20];
1954
1955         u8         a_frame_check_sequence_errors_low[0x20];
1956
1957         u8         a_alignment_errors_high[0x20];
1958
1959         u8         a_alignment_errors_low[0x20];
1960
1961         u8         a_octets_transmitted_ok_high[0x20];
1962
1963         u8         a_octets_transmitted_ok_low[0x20];
1964
1965         u8         a_octets_received_ok_high[0x20];
1966
1967         u8         a_octets_received_ok_low[0x20];
1968
1969         u8         a_multicast_frames_xmitted_ok_high[0x20];
1970
1971         u8         a_multicast_frames_xmitted_ok_low[0x20];
1972
1973         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1974
1975         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1976
1977         u8         a_multicast_frames_received_ok_high[0x20];
1978
1979         u8         a_multicast_frames_received_ok_low[0x20];
1980
1981         u8         a_broadcast_frames_received_ok_high[0x20];
1982
1983         u8         a_broadcast_frames_received_ok_low[0x20];
1984
1985         u8         a_in_range_length_errors_high[0x20];
1986
1987         u8         a_in_range_length_errors_low[0x20];
1988
1989         u8         a_out_of_range_length_field_high[0x20];
1990
1991         u8         a_out_of_range_length_field_low[0x20];
1992
1993         u8         a_frame_too_long_errors_high[0x20];
1994
1995         u8         a_frame_too_long_errors_low[0x20];
1996
1997         u8         a_symbol_error_during_carrier_high[0x20];
1998
1999         u8         a_symbol_error_during_carrier_low[0x20];
2000
2001         u8         a_mac_control_frames_transmitted_high[0x20];
2002
2003         u8         a_mac_control_frames_transmitted_low[0x20];
2004
2005         u8         a_mac_control_frames_received_high[0x20];
2006
2007         u8         a_mac_control_frames_received_low[0x20];
2008
2009         u8         a_unsupported_opcodes_received_high[0x20];
2010
2011         u8         a_unsupported_opcodes_received_low[0x20];
2012
2013         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2014
2015         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2016
2017         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2018
2019         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2020
2021         u8         reserved_at_4c0[0x300];
2022 };
2023
2024 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2025         u8         life_time_counter_high[0x20];
2026
2027         u8         life_time_counter_low[0x20];
2028
2029         u8         rx_errors[0x20];
2030
2031         u8         tx_errors[0x20];
2032
2033         u8         l0_to_recovery_eieos[0x20];
2034
2035         u8         l0_to_recovery_ts[0x20];
2036
2037         u8         l0_to_recovery_framing[0x20];
2038
2039         u8         l0_to_recovery_retrain[0x20];
2040
2041         u8         crc_error_dllp[0x20];
2042
2043         u8         crc_error_tlp[0x20];
2044
2045         u8         tx_overflow_buffer_pkt_high[0x20];
2046
2047         u8         tx_overflow_buffer_pkt_low[0x20];
2048
2049         u8         outbound_stalled_reads[0x20];
2050
2051         u8         outbound_stalled_writes[0x20];
2052
2053         u8         outbound_stalled_reads_events[0x20];
2054
2055         u8         outbound_stalled_writes_events[0x20];
2056
2057         u8         reserved_at_200[0x5c0];
2058 };
2059
2060 struct mlx5_ifc_cmd_inter_comp_event_bits {
2061         u8         command_completion_vector[0x20];
2062
2063         u8         reserved_at_20[0xc0];
2064 };
2065
2066 struct mlx5_ifc_stall_vl_event_bits {
2067         u8         reserved_at_0[0x18];
2068         u8         port_num[0x1];
2069         u8         reserved_at_19[0x3];
2070         u8         vl[0x4];
2071
2072         u8         reserved_at_20[0xa0];
2073 };
2074
2075 struct mlx5_ifc_db_bf_congestion_event_bits {
2076         u8         event_subtype[0x8];
2077         u8         reserved_at_8[0x8];
2078         u8         congestion_level[0x8];
2079         u8         reserved_at_18[0x8];
2080
2081         u8         reserved_at_20[0xa0];
2082 };
2083
2084 struct mlx5_ifc_gpio_event_bits {
2085         u8         reserved_at_0[0x60];
2086
2087         u8         gpio_event_hi[0x20];
2088
2089         u8         gpio_event_lo[0x20];
2090
2091         u8         reserved_at_a0[0x40];
2092 };
2093
2094 struct mlx5_ifc_port_state_change_event_bits {
2095         u8         reserved_at_0[0x40];
2096
2097         u8         port_num[0x4];
2098         u8         reserved_at_44[0x1c];
2099
2100         u8         reserved_at_60[0x80];
2101 };
2102
2103 struct mlx5_ifc_dropped_packet_logged_bits {
2104         u8         reserved_at_0[0xe0];
2105 };
2106
2107 enum {
2108         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2109         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2110 };
2111
2112 struct mlx5_ifc_cq_error_bits {
2113         u8         reserved_at_0[0x8];
2114         u8         cqn[0x18];
2115
2116         u8         reserved_at_20[0x20];
2117
2118         u8         reserved_at_40[0x18];
2119         u8         syndrome[0x8];
2120
2121         u8         reserved_at_60[0x80];
2122 };
2123
2124 struct mlx5_ifc_rdma_page_fault_event_bits {
2125         u8         bytes_committed[0x20];
2126
2127         u8         r_key[0x20];
2128
2129         u8         reserved_at_40[0x10];
2130         u8         packet_len[0x10];
2131
2132         u8         rdma_op_len[0x20];
2133
2134         u8         rdma_va[0x40];
2135
2136         u8         reserved_at_c0[0x5];
2137         u8         rdma[0x1];
2138         u8         write[0x1];
2139         u8         requestor[0x1];
2140         u8         qp_number[0x18];
2141 };
2142
2143 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2144         u8         bytes_committed[0x20];
2145
2146         u8         reserved_at_20[0x10];
2147         u8         wqe_index[0x10];
2148
2149         u8         reserved_at_40[0x10];
2150         u8         len[0x10];
2151
2152         u8         reserved_at_60[0x60];
2153
2154         u8         reserved_at_c0[0x5];
2155         u8         rdma[0x1];
2156         u8         write_read[0x1];
2157         u8         requestor[0x1];
2158         u8         qpn[0x18];
2159 };
2160
2161 struct mlx5_ifc_qp_events_bits {
2162         u8         reserved_at_0[0xa0];
2163
2164         u8         type[0x8];
2165         u8         reserved_at_a8[0x18];
2166
2167         u8         reserved_at_c0[0x8];
2168         u8         qpn_rqn_sqn[0x18];
2169 };
2170
2171 struct mlx5_ifc_dct_events_bits {
2172         u8         reserved_at_0[0xc0];
2173
2174         u8         reserved_at_c0[0x8];
2175         u8         dct_number[0x18];
2176 };
2177
2178 struct mlx5_ifc_comp_event_bits {
2179         u8         reserved_at_0[0xc0];
2180
2181         u8         reserved_at_c0[0x8];
2182         u8         cq_number[0x18];
2183 };
2184
2185 enum {
2186         MLX5_QPC_STATE_RST        = 0x0,
2187         MLX5_QPC_STATE_INIT       = 0x1,
2188         MLX5_QPC_STATE_RTR        = 0x2,
2189         MLX5_QPC_STATE_RTS        = 0x3,
2190         MLX5_QPC_STATE_SQER       = 0x4,
2191         MLX5_QPC_STATE_ERR        = 0x6,
2192         MLX5_QPC_STATE_SQD        = 0x7,
2193         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2194 };
2195
2196 enum {
2197         MLX5_QPC_ST_RC            = 0x0,
2198         MLX5_QPC_ST_UC            = 0x1,
2199         MLX5_QPC_ST_UD            = 0x2,
2200         MLX5_QPC_ST_XRC           = 0x3,
2201         MLX5_QPC_ST_DCI           = 0x5,
2202         MLX5_QPC_ST_QP0           = 0x7,
2203         MLX5_QPC_ST_QP1           = 0x8,
2204         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2205         MLX5_QPC_ST_REG_UMR       = 0xc,
2206 };
2207
2208 enum {
2209         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2210         MLX5_QPC_PM_STATE_REARM     = 0x1,
2211         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2212         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2213 };
2214
2215 enum {
2216         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2217 };
2218
2219 enum {
2220         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2221         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2222 };
2223
2224 enum {
2225         MLX5_QPC_MTU_256_BYTES        = 0x1,
2226         MLX5_QPC_MTU_512_BYTES        = 0x2,
2227         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2228         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2229         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2230         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2231 };
2232
2233 enum {
2234         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2235         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2236         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2237         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2238         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2239         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2240         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2241         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2242 };
2243
2244 enum {
2245         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2246         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2247         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2248 };
2249
2250 enum {
2251         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2252         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2253         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2254 };
2255
2256 struct mlx5_ifc_qpc_bits {
2257         u8         state[0x4];
2258         u8         lag_tx_port_affinity[0x4];
2259         u8         st[0x8];
2260         u8         reserved_at_10[0x3];
2261         u8         pm_state[0x2];
2262         u8         reserved_at_15[0x3];
2263         u8         offload_type[0x4];
2264         u8         end_padding_mode[0x2];
2265         u8         reserved_at_1e[0x2];
2266
2267         u8         wq_signature[0x1];
2268         u8         block_lb_mc[0x1];
2269         u8         atomic_like_write_en[0x1];
2270         u8         latency_sensitive[0x1];
2271         u8         reserved_at_24[0x1];
2272         u8         drain_sigerr[0x1];
2273         u8         reserved_at_26[0x2];
2274         u8         pd[0x18];
2275
2276         u8         mtu[0x3];
2277         u8         log_msg_max[0x5];
2278         u8         reserved_at_48[0x1];
2279         u8         log_rq_size[0x4];
2280         u8         log_rq_stride[0x3];
2281         u8         no_sq[0x1];
2282         u8         log_sq_size[0x4];
2283         u8         reserved_at_55[0x6];
2284         u8         rlky[0x1];
2285         u8         ulp_stateless_offload_mode[0x4];
2286
2287         u8         counter_set_id[0x8];
2288         u8         uar_page[0x18];
2289
2290         u8         reserved_at_80[0x8];
2291         u8         user_index[0x18];
2292
2293         u8         reserved_at_a0[0x3];
2294         u8         log_page_size[0x5];
2295         u8         remote_qpn[0x18];
2296
2297         struct mlx5_ifc_ads_bits primary_address_path;
2298
2299         struct mlx5_ifc_ads_bits secondary_address_path;
2300
2301         u8         log_ack_req_freq[0x4];
2302         u8         reserved_at_384[0x4];
2303         u8         log_sra_max[0x3];
2304         u8         reserved_at_38b[0x2];
2305         u8         retry_count[0x3];
2306         u8         rnr_retry[0x3];
2307         u8         reserved_at_393[0x1];
2308         u8         fre[0x1];
2309         u8         cur_rnr_retry[0x3];
2310         u8         cur_retry_count[0x3];
2311         u8         reserved_at_39b[0x5];
2312
2313         u8         reserved_at_3a0[0x20];
2314
2315         u8         reserved_at_3c0[0x8];
2316         u8         next_send_psn[0x18];
2317
2318         u8         reserved_at_3e0[0x8];
2319         u8         cqn_snd[0x18];
2320
2321         u8         reserved_at_400[0x8];
2322         u8         deth_sqpn[0x18];
2323
2324         u8         reserved_at_420[0x20];
2325
2326         u8         reserved_at_440[0x8];
2327         u8         last_acked_psn[0x18];
2328
2329         u8         reserved_at_460[0x8];
2330         u8         ssn[0x18];
2331
2332         u8         reserved_at_480[0x8];
2333         u8         log_rra_max[0x3];
2334         u8         reserved_at_48b[0x1];
2335         u8         atomic_mode[0x4];
2336         u8         rre[0x1];
2337         u8         rwe[0x1];
2338         u8         rae[0x1];
2339         u8         reserved_at_493[0x1];
2340         u8         page_offset[0x6];
2341         u8         reserved_at_49a[0x3];
2342         u8         cd_slave_receive[0x1];
2343         u8         cd_slave_send[0x1];
2344         u8         cd_master[0x1];
2345
2346         u8         reserved_at_4a0[0x3];
2347         u8         min_rnr_nak[0x5];
2348         u8         next_rcv_psn[0x18];
2349
2350         u8         reserved_at_4c0[0x8];
2351         u8         xrcd[0x18];
2352
2353         u8         reserved_at_4e0[0x8];
2354         u8         cqn_rcv[0x18];
2355
2356         u8         dbr_addr[0x40];
2357
2358         u8         q_key[0x20];
2359
2360         u8         reserved_at_560[0x5];
2361         u8         rq_type[0x3];
2362         u8         srqn_rmpn_xrqn[0x18];
2363
2364         u8         reserved_at_580[0x8];
2365         u8         rmsn[0x18];
2366
2367         u8         hw_sq_wqebb_counter[0x10];
2368         u8         sw_sq_wqebb_counter[0x10];
2369
2370         u8         hw_rq_counter[0x20];
2371
2372         u8         sw_rq_counter[0x20];
2373
2374         u8         reserved_at_600[0x20];
2375
2376         u8         reserved_at_620[0xf];
2377         u8         cgs[0x1];
2378         u8         cs_req[0x8];
2379         u8         cs_res[0x8];
2380
2381         u8         dc_access_key[0x40];
2382
2383         u8         reserved_at_680[0x3];
2384         u8         dbr_umem_valid[0x1];
2385
2386         u8         reserved_at_684[0xbc];
2387 };
2388
2389 struct mlx5_ifc_roce_addr_layout_bits {
2390         u8         source_l3_address[16][0x8];
2391
2392         u8         reserved_at_80[0x3];
2393         u8         vlan_valid[0x1];
2394         u8         vlan_id[0xc];
2395         u8         source_mac_47_32[0x10];
2396
2397         u8         source_mac_31_0[0x20];
2398
2399         u8         reserved_at_c0[0x14];
2400         u8         roce_l3_type[0x4];
2401         u8         roce_version[0x8];
2402
2403         u8         reserved_at_e0[0x20];
2404 };
2405
2406 union mlx5_ifc_hca_cap_union_bits {
2407         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2408         struct mlx5_ifc_odp_cap_bits odp_cap;
2409         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2410         struct mlx5_ifc_roce_cap_bits roce_cap;
2411         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2412         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2413         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2414         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2415         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2416         struct mlx5_ifc_qos_cap_bits qos_cap;
2417         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2418         u8         reserved_at_0[0x8000];
2419 };
2420
2421 enum {
2422         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2423         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2424         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2425         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2426         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2427         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2428         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2429         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2430         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2431         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2432         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2433 };
2434
2435 struct mlx5_ifc_vlan_bits {
2436         u8         ethtype[0x10];
2437         u8         prio[0x3];
2438         u8         cfi[0x1];
2439         u8         vid[0xc];
2440 };
2441
2442 struct mlx5_ifc_flow_context_bits {
2443         struct mlx5_ifc_vlan_bits push_vlan;
2444
2445         u8         group_id[0x20];
2446
2447         u8         reserved_at_40[0x8];
2448         u8         flow_tag[0x18];
2449
2450         u8         reserved_at_60[0x10];
2451         u8         action[0x10];
2452
2453         u8         reserved_at_80[0x8];
2454         u8         destination_list_size[0x18];
2455
2456         u8         reserved_at_a0[0x8];
2457         u8         flow_counter_list_size[0x18];
2458
2459         u8         packet_reformat_id[0x20];
2460
2461         u8         modify_header_id[0x20];
2462
2463         struct mlx5_ifc_vlan_bits push_vlan_2;
2464
2465         u8         reserved_at_120[0xe0];
2466
2467         struct mlx5_ifc_fte_match_param_bits match_value;
2468
2469         u8         reserved_at_1200[0x600];
2470
2471         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2472 };
2473
2474 enum {
2475         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2476         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2477 };
2478
2479 struct mlx5_ifc_xrc_srqc_bits {
2480         u8         state[0x4];
2481         u8         log_xrc_srq_size[0x4];
2482         u8         reserved_at_8[0x18];
2483
2484         u8         wq_signature[0x1];
2485         u8         cont_srq[0x1];
2486         u8         reserved_at_22[0x1];
2487         u8         rlky[0x1];
2488         u8         basic_cyclic_rcv_wqe[0x1];
2489         u8         log_rq_stride[0x3];
2490         u8         xrcd[0x18];
2491
2492         u8         page_offset[0x6];
2493         u8         reserved_at_46[0x1];
2494         u8         dbr_umem_valid[0x1];
2495         u8         cqn[0x18];
2496
2497         u8         reserved_at_60[0x20];
2498
2499         u8         user_index_equal_xrc_srqn[0x1];
2500         u8         reserved_at_81[0x1];
2501         u8         log_page_size[0x6];
2502         u8         user_index[0x18];
2503
2504         u8         reserved_at_a0[0x20];
2505
2506         u8         reserved_at_c0[0x8];
2507         u8         pd[0x18];
2508
2509         u8         lwm[0x10];
2510         u8         wqe_cnt[0x10];
2511
2512         u8         reserved_at_100[0x40];
2513
2514         u8         db_record_addr_h[0x20];
2515
2516         u8         db_record_addr_l[0x1e];
2517         u8         reserved_at_17e[0x2];
2518
2519         u8         reserved_at_180[0x80];
2520 };
2521
2522 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2523         u8         counter_error_queues[0x20];
2524
2525         u8         total_error_queues[0x20];
2526
2527         u8         send_queue_priority_update_flow[0x20];
2528
2529         u8         reserved_at_60[0x20];
2530
2531         u8         nic_receive_steering_discard[0x40];
2532
2533         u8         receive_discard_vport_down[0x40];
2534
2535         u8         transmit_discard_vport_down[0x40];
2536
2537         u8         reserved_at_140[0xec0];
2538 };
2539
2540 struct mlx5_ifc_traffic_counter_bits {
2541         u8         packets[0x40];
2542
2543         u8         octets[0x40];
2544 };
2545
2546 struct mlx5_ifc_tisc_bits {
2547         u8         strict_lag_tx_port_affinity[0x1];
2548         u8         reserved_at_1[0x3];
2549         u8         lag_tx_port_affinity[0x04];
2550
2551         u8         reserved_at_8[0x4];
2552         u8         prio[0x4];
2553         u8         reserved_at_10[0x10];
2554
2555         u8         reserved_at_20[0x100];
2556
2557         u8         reserved_at_120[0x8];
2558         u8         transport_domain[0x18];
2559
2560         u8         reserved_at_140[0x8];
2561         u8         underlay_qpn[0x18];
2562         u8         reserved_at_160[0x3a0];
2563 };
2564
2565 enum {
2566         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2567         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2568 };
2569
2570 enum {
2571         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2572         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2573 };
2574
2575 enum {
2576         MLX5_RX_HASH_FN_NONE           = 0x0,
2577         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2578         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2579 };
2580
2581 enum {
2582         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2583         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2584 };
2585
2586 struct mlx5_ifc_tirc_bits {
2587         u8         reserved_at_0[0x20];
2588
2589         u8         disp_type[0x4];
2590         u8         reserved_at_24[0x1c];
2591
2592         u8         reserved_at_40[0x40];
2593
2594         u8         reserved_at_80[0x4];
2595         u8         lro_timeout_period_usecs[0x10];
2596         u8         lro_enable_mask[0x4];
2597         u8         lro_max_ip_payload_size[0x8];
2598
2599         u8         reserved_at_a0[0x40];
2600
2601         u8         reserved_at_e0[0x8];
2602         u8         inline_rqn[0x18];
2603
2604         u8         rx_hash_symmetric[0x1];
2605         u8         reserved_at_101[0x1];
2606         u8         tunneled_offload_en[0x1];
2607         u8         reserved_at_103[0x5];
2608         u8         indirect_table[0x18];
2609
2610         u8         rx_hash_fn[0x4];
2611         u8         reserved_at_124[0x2];
2612         u8         self_lb_block[0x2];
2613         u8         transport_domain[0x18];
2614
2615         u8         rx_hash_toeplitz_key[10][0x20];
2616
2617         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2618
2619         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2620
2621         u8         reserved_at_2c0[0x4c0];
2622 };
2623
2624 enum {
2625         MLX5_SRQC_STATE_GOOD   = 0x0,
2626         MLX5_SRQC_STATE_ERROR  = 0x1,
2627 };
2628
2629 struct mlx5_ifc_srqc_bits {
2630         u8         state[0x4];
2631         u8         log_srq_size[0x4];
2632         u8         reserved_at_8[0x18];
2633
2634         u8         wq_signature[0x1];
2635         u8         cont_srq[0x1];
2636         u8         reserved_at_22[0x1];
2637         u8         rlky[0x1];
2638         u8         reserved_at_24[0x1];
2639         u8         log_rq_stride[0x3];
2640         u8         xrcd[0x18];
2641
2642         u8         page_offset[0x6];
2643         u8         reserved_at_46[0x2];
2644         u8         cqn[0x18];
2645
2646         u8         reserved_at_60[0x20];
2647
2648         u8         reserved_at_80[0x2];
2649         u8         log_page_size[0x6];
2650         u8         reserved_at_88[0x18];
2651
2652         u8         reserved_at_a0[0x20];
2653
2654         u8         reserved_at_c0[0x8];
2655         u8         pd[0x18];
2656
2657         u8         lwm[0x10];
2658         u8         wqe_cnt[0x10];
2659
2660         u8         reserved_at_100[0x40];
2661
2662         u8         dbr_addr[0x40];
2663
2664         u8         reserved_at_180[0x80];
2665 };
2666
2667 enum {
2668         MLX5_SQC_STATE_RST  = 0x0,
2669         MLX5_SQC_STATE_RDY  = 0x1,
2670         MLX5_SQC_STATE_ERR  = 0x3,
2671 };
2672
2673 struct mlx5_ifc_sqc_bits {
2674         u8         rlky[0x1];
2675         u8         cd_master[0x1];
2676         u8         fre[0x1];
2677         u8         flush_in_error_en[0x1];
2678         u8         allow_multi_pkt_send_wqe[0x1];
2679         u8         min_wqe_inline_mode[0x3];
2680         u8         state[0x4];
2681         u8         reg_umr[0x1];
2682         u8         allow_swp[0x1];
2683         u8         hairpin[0x1];
2684         u8         reserved_at_f[0x11];
2685
2686         u8         reserved_at_20[0x8];
2687         u8         user_index[0x18];
2688
2689         u8         reserved_at_40[0x8];
2690         u8         cqn[0x18];
2691
2692         u8         reserved_at_60[0x8];
2693         u8         hairpin_peer_rq[0x18];
2694
2695         u8         reserved_at_80[0x10];
2696         u8         hairpin_peer_vhca[0x10];
2697
2698         u8         reserved_at_a0[0x50];
2699
2700         u8         packet_pacing_rate_limit_index[0x10];
2701         u8         tis_lst_sz[0x10];
2702         u8         reserved_at_110[0x10];
2703
2704         u8         reserved_at_120[0x40];
2705
2706         u8         reserved_at_160[0x8];
2707         u8         tis_num_0[0x18];
2708
2709         struct mlx5_ifc_wq_bits wq;
2710 };
2711
2712 enum {
2713         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2714         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2715         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2716         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2717 };
2718
2719 struct mlx5_ifc_scheduling_context_bits {
2720         u8         element_type[0x8];
2721         u8         reserved_at_8[0x18];
2722
2723         u8         element_attributes[0x20];
2724
2725         u8         parent_element_id[0x20];
2726
2727         u8         reserved_at_60[0x40];
2728
2729         u8         bw_share[0x20];
2730
2731         u8         max_average_bw[0x20];
2732
2733         u8         reserved_at_e0[0x120];
2734 };
2735
2736 struct mlx5_ifc_rqtc_bits {
2737         u8         reserved_at_0[0xa0];
2738
2739         u8         reserved_at_a0[0x10];
2740         u8         rqt_max_size[0x10];
2741
2742         u8         reserved_at_c0[0x10];
2743         u8         rqt_actual_size[0x10];
2744
2745         u8         reserved_at_e0[0x6a0];
2746
2747         struct mlx5_ifc_rq_num_bits rq_num[0];
2748 };
2749
2750 enum {
2751         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2752         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2753 };
2754
2755 enum {
2756         MLX5_RQC_STATE_RST  = 0x0,
2757         MLX5_RQC_STATE_RDY  = 0x1,
2758         MLX5_RQC_STATE_ERR  = 0x3,
2759 };
2760
2761 struct mlx5_ifc_rqc_bits {
2762         u8         rlky[0x1];
2763         u8         delay_drop_en[0x1];
2764         u8         scatter_fcs[0x1];
2765         u8         vsd[0x1];
2766         u8         mem_rq_type[0x4];
2767         u8         state[0x4];
2768         u8         reserved_at_c[0x1];
2769         u8         flush_in_error_en[0x1];
2770         u8         hairpin[0x1];
2771         u8         reserved_at_f[0x11];
2772
2773         u8         reserved_at_20[0x8];
2774         u8         user_index[0x18];
2775
2776         u8         reserved_at_40[0x8];
2777         u8         cqn[0x18];
2778
2779         u8         counter_set_id[0x8];
2780         u8         reserved_at_68[0x18];
2781
2782         u8         reserved_at_80[0x8];
2783         u8         rmpn[0x18];
2784
2785         u8         reserved_at_a0[0x8];
2786         u8         hairpin_peer_sq[0x18];
2787
2788         u8         reserved_at_c0[0x10];
2789         u8         hairpin_peer_vhca[0x10];
2790
2791         u8         reserved_at_e0[0xa0];
2792
2793         struct mlx5_ifc_wq_bits wq;
2794 };
2795
2796 enum {
2797         MLX5_RMPC_STATE_RDY  = 0x1,
2798         MLX5_RMPC_STATE_ERR  = 0x3,
2799 };
2800
2801 struct mlx5_ifc_rmpc_bits {
2802         u8         reserved_at_0[0x8];
2803         u8         state[0x4];
2804         u8         reserved_at_c[0x14];
2805
2806         u8         basic_cyclic_rcv_wqe[0x1];
2807         u8         reserved_at_21[0x1f];
2808
2809         u8         reserved_at_40[0x140];
2810
2811         struct mlx5_ifc_wq_bits wq;
2812 };
2813
2814 struct mlx5_ifc_nic_vport_context_bits {
2815         u8         reserved_at_0[0x5];
2816         u8         min_wqe_inline_mode[0x3];
2817         u8         reserved_at_8[0x15];
2818         u8         disable_mc_local_lb[0x1];
2819         u8         disable_uc_local_lb[0x1];
2820         u8         roce_en[0x1];
2821
2822         u8         arm_change_event[0x1];
2823         u8         reserved_at_21[0x1a];
2824         u8         event_on_mtu[0x1];
2825         u8         event_on_promisc_change[0x1];
2826         u8         event_on_vlan_change[0x1];
2827         u8         event_on_mc_address_change[0x1];
2828         u8         event_on_uc_address_change[0x1];
2829
2830         u8         reserved_at_40[0xc];
2831
2832         u8         affiliation_criteria[0x4];
2833         u8         affiliated_vhca_id[0x10];
2834
2835         u8         reserved_at_60[0xd0];
2836
2837         u8         mtu[0x10];
2838
2839         u8         system_image_guid[0x40];
2840         u8         port_guid[0x40];
2841         u8         node_guid[0x40];
2842
2843         u8         reserved_at_200[0x140];
2844         u8         qkey_violation_counter[0x10];
2845         u8         reserved_at_350[0x430];
2846
2847         u8         promisc_uc[0x1];
2848         u8         promisc_mc[0x1];
2849         u8         promisc_all[0x1];
2850         u8         reserved_at_783[0x2];
2851         u8         allowed_list_type[0x3];
2852         u8         reserved_at_788[0xc];
2853         u8         allowed_list_size[0xc];
2854
2855         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2856
2857         u8         reserved_at_7e0[0x20];
2858
2859         u8         current_uc_mac_address[0][0x40];
2860 };
2861
2862 enum {
2863         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2864         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2865         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2866         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2867         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2868 };
2869
2870 struct mlx5_ifc_mkc_bits {
2871         u8         reserved_at_0[0x1];
2872         u8         free[0x1];
2873         u8         reserved_at_2[0x1];
2874         u8         access_mode_4_2[0x3];
2875         u8         reserved_at_6[0x7];
2876         u8         relaxed_ordering_write[0x1];
2877         u8         reserved_at_e[0x1];
2878         u8         small_fence_on_rdma_read_response[0x1];
2879         u8         umr_en[0x1];
2880         u8         a[0x1];
2881         u8         rw[0x1];
2882         u8         rr[0x1];
2883         u8         lw[0x1];
2884         u8         lr[0x1];
2885         u8         access_mode_1_0[0x2];
2886         u8         reserved_at_18[0x8];
2887
2888         u8         qpn[0x18];
2889         u8         mkey_7_0[0x8];
2890
2891         u8         reserved_at_40[0x20];
2892
2893         u8         length64[0x1];
2894         u8         bsf_en[0x1];
2895         u8         sync_umr[0x1];
2896         u8         reserved_at_63[0x2];
2897         u8         expected_sigerr_count[0x1];
2898         u8         reserved_at_66[0x1];
2899         u8         en_rinval[0x1];
2900         u8         pd[0x18];
2901
2902         u8         start_addr[0x40];
2903
2904         u8         len[0x40];
2905
2906         u8         bsf_octword_size[0x20];
2907
2908         u8         reserved_at_120[0x80];
2909
2910         u8         translations_octword_size[0x20];
2911
2912         u8         reserved_at_1c0[0x1b];
2913         u8         log_page_size[0x5];
2914
2915         u8         reserved_at_1e0[0x20];
2916 };
2917
2918 struct mlx5_ifc_pkey_bits {
2919         u8         reserved_at_0[0x10];
2920         u8         pkey[0x10];
2921 };
2922
2923 struct mlx5_ifc_array128_auto_bits {
2924         u8         array128_auto[16][0x8];
2925 };
2926
2927 struct mlx5_ifc_hca_vport_context_bits {
2928         u8         field_select[0x20];
2929
2930         u8         reserved_at_20[0xe0];
2931
2932         u8         sm_virt_aware[0x1];
2933         u8         has_smi[0x1];
2934         u8         has_raw[0x1];
2935         u8         grh_required[0x1];
2936         u8         reserved_at_104[0xc];
2937         u8         port_physical_state[0x4];
2938         u8         vport_state_policy[0x4];
2939         u8         port_state[0x4];
2940         u8         vport_state[0x4];
2941
2942         u8         reserved_at_120[0x20];
2943
2944         u8         system_image_guid[0x40];
2945
2946         u8         port_guid[0x40];
2947
2948         u8         node_guid[0x40];
2949
2950         u8         cap_mask1[0x20];
2951
2952         u8         cap_mask1_field_select[0x20];
2953
2954         u8         cap_mask2[0x20];
2955
2956         u8         cap_mask2_field_select[0x20];
2957
2958         u8         reserved_at_280[0x80];
2959
2960         u8         lid[0x10];
2961         u8         reserved_at_310[0x4];
2962         u8         init_type_reply[0x4];
2963         u8         lmc[0x3];
2964         u8         subnet_timeout[0x5];
2965
2966         u8         sm_lid[0x10];
2967         u8         sm_sl[0x4];
2968         u8         reserved_at_334[0xc];
2969
2970         u8         qkey_violation_counter[0x10];
2971         u8         pkey_violation_counter[0x10];
2972
2973         u8         reserved_at_360[0xca0];
2974 };
2975
2976 struct mlx5_ifc_esw_vport_context_bits {
2977         u8         reserved_at_0[0x3];
2978         u8         vport_svlan_strip[0x1];
2979         u8         vport_cvlan_strip[0x1];
2980         u8         vport_svlan_insert[0x1];
2981         u8         vport_cvlan_insert[0x2];
2982         u8         reserved_at_8[0x18];
2983
2984         u8         reserved_at_20[0x20];
2985
2986         u8         svlan_cfi[0x1];
2987         u8         svlan_pcp[0x3];
2988         u8         svlan_id[0xc];
2989         u8         cvlan_cfi[0x1];
2990         u8         cvlan_pcp[0x3];
2991         u8         cvlan_id[0xc];
2992
2993         u8         reserved_at_60[0x7a0];
2994 };
2995
2996 enum {
2997         MLX5_EQC_STATUS_OK                = 0x0,
2998         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2999 };
3000
3001 enum {
3002         MLX5_EQC_ST_ARMED  = 0x9,
3003         MLX5_EQC_ST_FIRED  = 0xa,
3004 };
3005
3006 struct mlx5_ifc_eqc_bits {
3007         u8         status[0x4];
3008         u8         reserved_at_4[0x9];
3009         u8         ec[0x1];
3010         u8         oi[0x1];
3011         u8         reserved_at_f[0x5];
3012         u8         st[0x4];
3013         u8         reserved_at_18[0x8];
3014
3015         u8         reserved_at_20[0x20];
3016
3017         u8         reserved_at_40[0x14];
3018         u8         page_offset[0x6];
3019         u8         reserved_at_5a[0x6];
3020
3021         u8         reserved_at_60[0x3];
3022         u8         log_eq_size[0x5];
3023         u8         uar_page[0x18];
3024
3025         u8         reserved_at_80[0x20];
3026
3027         u8         reserved_at_a0[0x18];
3028         u8         intr[0x8];
3029
3030         u8         reserved_at_c0[0x3];
3031         u8         log_page_size[0x5];
3032         u8         reserved_at_c8[0x18];
3033
3034         u8         reserved_at_e0[0x60];
3035
3036         u8         reserved_at_140[0x8];
3037         u8         consumer_counter[0x18];
3038
3039         u8         reserved_at_160[0x8];
3040         u8         producer_counter[0x18];
3041
3042         u8         reserved_at_180[0x80];
3043 };
3044
3045 enum {
3046         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3047         MLX5_DCTC_STATE_DRAINING  = 0x1,
3048         MLX5_DCTC_STATE_DRAINED   = 0x2,
3049 };
3050
3051 enum {
3052         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3053         MLX5_DCTC_CS_RES_NA         = 0x1,
3054         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3055 };
3056
3057 enum {
3058         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3059         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3060         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3061         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3062         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3063 };
3064
3065 struct mlx5_ifc_dctc_bits {
3066         u8         reserved_at_0[0x4];
3067         u8         state[0x4];
3068         u8         reserved_at_8[0x18];
3069
3070         u8         reserved_at_20[0x8];
3071         u8         user_index[0x18];
3072
3073         u8         reserved_at_40[0x8];
3074         u8         cqn[0x18];
3075
3076         u8         counter_set_id[0x8];
3077         u8         atomic_mode[0x4];
3078         u8         rre[0x1];
3079         u8         rwe[0x1];
3080         u8         rae[0x1];
3081         u8         atomic_like_write_en[0x1];
3082         u8         latency_sensitive[0x1];
3083         u8         rlky[0x1];
3084         u8         free_ar[0x1];
3085         u8         reserved_at_73[0xd];
3086
3087         u8         reserved_at_80[0x8];
3088         u8         cs_res[0x8];
3089         u8         reserved_at_90[0x3];
3090         u8         min_rnr_nak[0x5];
3091         u8         reserved_at_98[0x8];
3092
3093         u8         reserved_at_a0[0x8];
3094         u8         srqn_xrqn[0x18];
3095
3096         u8         reserved_at_c0[0x8];
3097         u8         pd[0x18];
3098
3099         u8         tclass[0x8];
3100         u8         reserved_at_e8[0x4];
3101         u8         flow_label[0x14];
3102
3103         u8         dc_access_key[0x40];
3104
3105         u8         reserved_at_140[0x5];
3106         u8         mtu[0x3];
3107         u8         port[0x8];
3108         u8         pkey_index[0x10];
3109
3110         u8         reserved_at_160[0x8];
3111         u8         my_addr_index[0x8];
3112         u8         reserved_at_170[0x8];
3113         u8         hop_limit[0x8];
3114
3115         u8         dc_access_key_violation_count[0x20];
3116
3117         u8         reserved_at_1a0[0x14];
3118         u8         dei_cfi[0x1];
3119         u8         eth_prio[0x3];
3120         u8         ecn[0x2];
3121         u8         dscp[0x6];
3122
3123         u8         reserved_at_1c0[0x40];
3124 };
3125
3126 enum {
3127         MLX5_CQC_STATUS_OK             = 0x0,
3128         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3129         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3130 };
3131
3132 enum {
3133         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3134         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3135 };
3136
3137 enum {
3138         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3139         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3140         MLX5_CQC_ST_FIRED                                 = 0xa,
3141 };
3142
3143 enum {
3144         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3145         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3146         MLX5_CQ_PERIOD_NUM_MODES
3147 };
3148
3149 struct mlx5_ifc_cqc_bits {
3150         u8         status[0x4];
3151         u8         reserved_at_4[0x2];
3152         u8         dbr_umem_valid[0x1];
3153         u8         reserved_at_7[0x1];
3154         u8         cqe_sz[0x3];
3155         u8         cc[0x1];
3156         u8         reserved_at_c[0x1];
3157         u8         scqe_break_moderation_en[0x1];
3158         u8         oi[0x1];
3159         u8         cq_period_mode[0x2];
3160         u8         cqe_comp_en[0x1];
3161         u8         mini_cqe_res_format[0x2];
3162         u8         st[0x4];
3163         u8         reserved_at_18[0x8];
3164
3165         u8         reserved_at_20[0x20];
3166
3167         u8         reserved_at_40[0x14];
3168         u8         page_offset[0x6];
3169         u8         reserved_at_5a[0x6];
3170
3171         u8         reserved_at_60[0x3];
3172         u8         log_cq_size[0x5];
3173         u8         uar_page[0x18];
3174
3175         u8         reserved_at_80[0x4];
3176         u8         cq_period[0xc];
3177         u8         cq_max_count[0x10];
3178
3179         u8         reserved_at_a0[0x18];
3180         u8         c_eqn[0x8];
3181
3182         u8         reserved_at_c0[0x3];
3183         u8         log_page_size[0x5];
3184         u8         reserved_at_c8[0x18];
3185
3186         u8         reserved_at_e0[0x20];
3187
3188         u8         reserved_at_100[0x8];
3189         u8         last_notified_index[0x18];
3190
3191         u8         reserved_at_120[0x8];
3192         u8         last_solicit_index[0x18];
3193
3194         u8         reserved_at_140[0x8];
3195         u8         consumer_counter[0x18];
3196
3197         u8         reserved_at_160[0x8];
3198         u8         producer_counter[0x18];
3199
3200         u8         reserved_at_180[0x40];
3201
3202         u8         dbr_addr[0x40];
3203 };
3204
3205 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3206         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3207         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3208         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3209         u8         reserved_at_0[0x800];
3210 };
3211
3212 struct mlx5_ifc_query_adapter_param_block_bits {
3213         u8         reserved_at_0[0xc0];
3214
3215         u8         reserved_at_c0[0x8];
3216         u8         ieee_vendor_id[0x18];
3217
3218         u8         reserved_at_e0[0x10];
3219         u8         vsd_vendor_id[0x10];
3220
3221         u8         vsd[208][0x8];
3222
3223         u8         vsd_contd_psid[16][0x8];
3224 };
3225
3226 enum {
3227         MLX5_XRQC_STATE_GOOD   = 0x0,
3228         MLX5_XRQC_STATE_ERROR  = 0x1,
3229 };
3230
3231 enum {
3232         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3233         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3234 };
3235
3236 enum {
3237         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3238 };
3239
3240 struct mlx5_ifc_tag_matching_topology_context_bits {
3241         u8         log_matching_list_sz[0x4];
3242         u8         reserved_at_4[0xc];
3243         u8         append_next_index[0x10];
3244
3245         u8         sw_phase_cnt[0x10];
3246         u8         hw_phase_cnt[0x10];
3247
3248         u8         reserved_at_40[0x40];
3249 };
3250
3251 struct mlx5_ifc_xrqc_bits {
3252         u8         state[0x4];
3253         u8         rlkey[0x1];
3254         u8         reserved_at_5[0xf];
3255         u8         topology[0x4];
3256         u8         reserved_at_18[0x4];
3257         u8         offload[0x4];
3258
3259         u8         reserved_at_20[0x8];
3260         u8         user_index[0x18];
3261
3262         u8         reserved_at_40[0x8];
3263         u8         cqn[0x18];
3264
3265         u8         reserved_at_60[0xa0];
3266
3267         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3268
3269         u8         reserved_at_180[0x280];
3270
3271         struct mlx5_ifc_wq_bits wq;
3272 };
3273
3274 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3275         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3276         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3277         u8         reserved_at_0[0x20];
3278 };
3279
3280 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3281         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3282         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3283         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3284         u8         reserved_at_0[0x20];
3285 };
3286
3287 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3288         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3289         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3290         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3291         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3292         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3293         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3294         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3295         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3296         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3297         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3298         u8         reserved_at_0[0x7c0];
3299 };
3300
3301 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3302         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3303         u8         reserved_at_0[0x7c0];
3304 };
3305
3306 union mlx5_ifc_event_auto_bits {
3307         struct mlx5_ifc_comp_event_bits comp_event;
3308         struct mlx5_ifc_dct_events_bits dct_events;
3309         struct mlx5_ifc_qp_events_bits qp_events;
3310         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3311         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3312         struct mlx5_ifc_cq_error_bits cq_error;
3313         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3314         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3315         struct mlx5_ifc_gpio_event_bits gpio_event;
3316         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3317         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3318         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3319         u8         reserved_at_0[0xe0];
3320 };
3321
3322 struct mlx5_ifc_health_buffer_bits {
3323         u8         reserved_at_0[0x100];
3324
3325         u8         assert_existptr[0x20];
3326
3327         u8         assert_callra[0x20];
3328
3329         u8         reserved_at_140[0x40];
3330
3331         u8         fw_version[0x20];
3332
3333         u8         hw_id[0x20];
3334
3335         u8         reserved_at_1c0[0x20];
3336
3337         u8         irisc_index[0x8];
3338         u8         synd[0x8];
3339         u8         ext_synd[0x10];
3340 };
3341
3342 struct mlx5_ifc_register_loopback_control_bits {
3343         u8         no_lb[0x1];
3344         u8         reserved_at_1[0x7];
3345         u8         port[0x8];
3346         u8         reserved_at_10[0x10];
3347
3348         u8         reserved_at_20[0x60];
3349 };
3350
3351 struct mlx5_ifc_vport_tc_element_bits {
3352         u8         traffic_class[0x4];
3353         u8         reserved_at_4[0xc];
3354         u8         vport_number[0x10];
3355 };
3356
3357 struct mlx5_ifc_vport_element_bits {
3358         u8         reserved_at_0[0x10];
3359         u8         vport_number[0x10];
3360 };
3361
3362 enum {
3363         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3364         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3365         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3366 };
3367
3368 struct mlx5_ifc_tsar_element_bits {
3369         u8         reserved_at_0[0x8];
3370         u8         tsar_type[0x8];
3371         u8         reserved_at_10[0x10];
3372 };
3373
3374 enum {
3375         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3376         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3377 };
3378
3379 struct mlx5_ifc_teardown_hca_out_bits {
3380         u8         status[0x8];
3381         u8         reserved_at_8[0x18];
3382
3383         u8         syndrome[0x20];
3384
3385         u8         reserved_at_40[0x3f];
3386
3387         u8         state[0x1];
3388 };
3389
3390 enum {
3391         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3392         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3393         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3394 };
3395
3396 struct mlx5_ifc_teardown_hca_in_bits {
3397         u8         opcode[0x10];
3398         u8         reserved_at_10[0x10];
3399
3400         u8         reserved_at_20[0x10];
3401         u8         op_mod[0x10];
3402
3403         u8         reserved_at_40[0x10];
3404         u8         profile[0x10];
3405
3406         u8         reserved_at_60[0x20];
3407 };
3408
3409 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3410         u8         status[0x8];
3411         u8         reserved_at_8[0x18];
3412
3413         u8         syndrome[0x20];
3414
3415         u8         reserved_at_40[0x40];
3416 };
3417
3418 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3419         u8         opcode[0x10];
3420         u8         uid[0x10];
3421
3422         u8         reserved_at_20[0x10];
3423         u8         op_mod[0x10];
3424
3425         u8         reserved_at_40[0x8];
3426         u8         qpn[0x18];
3427
3428         u8         reserved_at_60[0x20];
3429
3430         u8         opt_param_mask[0x20];
3431
3432         u8         reserved_at_a0[0x20];
3433
3434         struct mlx5_ifc_qpc_bits qpc;
3435
3436         u8         reserved_at_800[0x80];
3437 };
3438
3439 struct mlx5_ifc_sqd2rts_qp_out_bits {
3440         u8         status[0x8];
3441         u8         reserved_at_8[0x18];
3442
3443         u8         syndrome[0x20];
3444
3445         u8         reserved_at_40[0x40];
3446 };
3447
3448 struct mlx5_ifc_sqd2rts_qp_in_bits {
3449         u8         opcode[0x10];
3450         u8         uid[0x10];
3451
3452         u8         reserved_at_20[0x10];
3453         u8         op_mod[0x10];
3454
3455         u8         reserved_at_40[0x8];
3456         u8         qpn[0x18];
3457
3458         u8         reserved_at_60[0x20];
3459
3460         u8         opt_param_mask[0x20];
3461
3462         u8         reserved_at_a0[0x20];
3463
3464         struct mlx5_ifc_qpc_bits qpc;
3465
3466         u8         reserved_at_800[0x80];
3467 };
3468
3469 struct mlx5_ifc_set_roce_address_out_bits {
3470         u8         status[0x8];
3471         u8         reserved_at_8[0x18];
3472
3473         u8         syndrome[0x20];
3474
3475         u8         reserved_at_40[0x40];
3476 };
3477
3478 struct mlx5_ifc_set_roce_address_in_bits {
3479         u8         opcode[0x10];
3480         u8         reserved_at_10[0x10];
3481
3482         u8         reserved_at_20[0x10];
3483         u8         op_mod[0x10];
3484
3485         u8         roce_address_index[0x10];
3486         u8         reserved_at_50[0xc];
3487         u8         vhca_port_num[0x4];
3488
3489         u8         reserved_at_60[0x20];
3490
3491         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3492 };
3493
3494 struct mlx5_ifc_set_mad_demux_out_bits {
3495         u8         status[0x8];
3496         u8         reserved_at_8[0x18];
3497
3498         u8         syndrome[0x20];
3499
3500         u8         reserved_at_40[0x40];
3501 };
3502
3503 enum {
3504         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3505         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3506 };
3507
3508 struct mlx5_ifc_set_mad_demux_in_bits {
3509         u8         opcode[0x10];
3510         u8         reserved_at_10[0x10];
3511
3512         u8         reserved_at_20[0x10];
3513         u8         op_mod[0x10];
3514
3515         u8         reserved_at_40[0x20];
3516
3517         u8         reserved_at_60[0x6];
3518         u8         demux_mode[0x2];
3519         u8         reserved_at_68[0x18];
3520 };
3521
3522 struct mlx5_ifc_set_l2_table_entry_out_bits {
3523         u8         status[0x8];
3524         u8         reserved_at_8[0x18];
3525
3526         u8         syndrome[0x20];
3527
3528         u8         reserved_at_40[0x40];
3529 };
3530
3531 struct mlx5_ifc_set_l2_table_entry_in_bits {
3532         u8         opcode[0x10];
3533         u8         reserved_at_10[0x10];
3534
3535         u8         reserved_at_20[0x10];
3536         u8         op_mod[0x10];
3537
3538         u8         reserved_at_40[0x60];
3539
3540         u8         reserved_at_a0[0x8];
3541         u8         table_index[0x18];
3542
3543         u8         reserved_at_c0[0x20];
3544
3545         u8         reserved_at_e0[0x13];
3546         u8         vlan_valid[0x1];
3547         u8         vlan[0xc];
3548
3549         struct mlx5_ifc_mac_address_layout_bits mac_address;
3550
3551         u8         reserved_at_140[0xc0];
3552 };
3553
3554 struct mlx5_ifc_set_issi_out_bits {
3555         u8         status[0x8];
3556         u8         reserved_at_8[0x18];
3557
3558         u8         syndrome[0x20];
3559
3560         u8         reserved_at_40[0x40];
3561 };
3562
3563 struct mlx5_ifc_set_issi_in_bits {
3564         u8         opcode[0x10];
3565         u8         reserved_at_10[0x10];
3566
3567         u8         reserved_at_20[0x10];
3568         u8         op_mod[0x10];
3569
3570         u8         reserved_at_40[0x10];
3571         u8         current_issi[0x10];
3572
3573         u8         reserved_at_60[0x20];
3574 };
3575
3576 struct mlx5_ifc_set_hca_cap_out_bits {
3577         u8         status[0x8];
3578         u8         reserved_at_8[0x18];
3579
3580         u8         syndrome[0x20];
3581
3582         u8         reserved_at_40[0x40];
3583 };
3584
3585 struct mlx5_ifc_set_hca_cap_in_bits {
3586         u8         opcode[0x10];
3587         u8         reserved_at_10[0x10];
3588
3589         u8         reserved_at_20[0x10];
3590         u8         op_mod[0x10];
3591
3592         u8         reserved_at_40[0x40];
3593
3594         union mlx5_ifc_hca_cap_union_bits capability;
3595 };
3596
3597 enum {
3598         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3599         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3600         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3601         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3602 };
3603
3604 struct mlx5_ifc_set_fte_out_bits {
3605         u8         status[0x8];
3606         u8         reserved_at_8[0x18];
3607
3608         u8         syndrome[0x20];
3609
3610         u8         reserved_at_40[0x40];
3611 };
3612
3613 struct mlx5_ifc_set_fte_in_bits {
3614         u8         opcode[0x10];
3615         u8         reserved_at_10[0x10];
3616
3617         u8         reserved_at_20[0x10];
3618         u8         op_mod[0x10];
3619
3620         u8         other_vport[0x1];
3621         u8         reserved_at_41[0xf];
3622         u8         vport_number[0x10];
3623
3624         u8         reserved_at_60[0x20];
3625
3626         u8         table_type[0x8];
3627         u8         reserved_at_88[0x18];
3628
3629         u8         reserved_at_a0[0x8];
3630         u8         table_id[0x18];
3631
3632         u8         reserved_at_c0[0x18];
3633         u8         modify_enable_mask[0x8];
3634
3635         u8         reserved_at_e0[0x20];
3636
3637         u8         flow_index[0x20];
3638
3639         u8         reserved_at_120[0xe0];
3640
3641         struct mlx5_ifc_flow_context_bits flow_context;
3642 };
3643
3644 struct mlx5_ifc_rts2rts_qp_out_bits {
3645         u8         status[0x8];
3646         u8         reserved_at_8[0x18];
3647
3648         u8         syndrome[0x20];
3649
3650         u8         reserved_at_40[0x40];
3651 };
3652
3653 struct mlx5_ifc_rts2rts_qp_in_bits {
3654         u8         opcode[0x10];
3655         u8         uid[0x10];
3656
3657         u8         reserved_at_20[0x10];
3658         u8         op_mod[0x10];
3659
3660         u8         reserved_at_40[0x8];
3661         u8         qpn[0x18];
3662
3663         u8         reserved_at_60[0x20];
3664
3665         u8         opt_param_mask[0x20];
3666
3667         u8         reserved_at_a0[0x20];
3668
3669         struct mlx5_ifc_qpc_bits qpc;
3670
3671         u8         reserved_at_800[0x80];
3672 };
3673
3674 struct mlx5_ifc_rtr2rts_qp_out_bits {
3675         u8         status[0x8];
3676         u8         reserved_at_8[0x18];
3677
3678         u8         syndrome[0x20];
3679
3680         u8         reserved_at_40[0x40];
3681 };
3682
3683 struct mlx5_ifc_rtr2rts_qp_in_bits {
3684         u8         opcode[0x10];
3685         u8         uid[0x10];
3686
3687         u8         reserved_at_20[0x10];
3688         u8         op_mod[0x10];
3689
3690         u8         reserved_at_40[0x8];
3691         u8         qpn[0x18];
3692
3693         u8         reserved_at_60[0x20];
3694
3695         u8         opt_param_mask[0x20];
3696
3697         u8         reserved_at_a0[0x20];
3698
3699         struct mlx5_ifc_qpc_bits qpc;
3700
3701         u8         reserved_at_800[0x80];
3702 };
3703
3704 struct mlx5_ifc_rst2init_qp_out_bits {
3705         u8         status[0x8];
3706         u8         reserved_at_8[0x18];
3707
3708         u8         syndrome[0x20];
3709
3710         u8         reserved_at_40[0x40];
3711 };
3712
3713 struct mlx5_ifc_rst2init_qp_in_bits {
3714         u8         opcode[0x10];
3715         u8         uid[0x10];
3716
3717         u8         reserved_at_20[0x10];
3718         u8         op_mod[0x10];
3719
3720         u8         reserved_at_40[0x8];
3721         u8         qpn[0x18];
3722
3723         u8         reserved_at_60[0x20];
3724
3725         u8         opt_param_mask[0x20];
3726
3727         u8         reserved_at_a0[0x20];
3728
3729         struct mlx5_ifc_qpc_bits qpc;
3730
3731         u8         reserved_at_800[0x80];
3732 };
3733
3734 struct mlx5_ifc_query_xrq_out_bits {
3735         u8         status[0x8];
3736         u8         reserved_at_8[0x18];
3737
3738         u8         syndrome[0x20];
3739
3740         u8         reserved_at_40[0x40];
3741
3742         struct mlx5_ifc_xrqc_bits xrq_context;
3743 };
3744
3745 struct mlx5_ifc_query_xrq_in_bits {
3746         u8         opcode[0x10];
3747         u8         reserved_at_10[0x10];
3748
3749         u8         reserved_at_20[0x10];
3750         u8         op_mod[0x10];
3751
3752         u8         reserved_at_40[0x8];
3753         u8         xrqn[0x18];
3754
3755         u8         reserved_at_60[0x20];
3756 };
3757
3758 struct mlx5_ifc_query_xrc_srq_out_bits {
3759         u8         status[0x8];
3760         u8         reserved_at_8[0x18];
3761
3762         u8         syndrome[0x20];
3763
3764         u8         reserved_at_40[0x40];
3765
3766         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3767
3768         u8         reserved_at_280[0x600];
3769
3770         u8         pas[0][0x40];
3771 };
3772
3773 struct mlx5_ifc_query_xrc_srq_in_bits {
3774         u8         opcode[0x10];
3775         u8         reserved_at_10[0x10];
3776
3777         u8         reserved_at_20[0x10];
3778         u8         op_mod[0x10];
3779
3780         u8         reserved_at_40[0x8];
3781         u8         xrc_srqn[0x18];
3782
3783         u8         reserved_at_60[0x20];
3784 };
3785
3786 enum {
3787         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3788         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3789 };
3790
3791 struct mlx5_ifc_query_vport_state_out_bits {
3792         u8         status[0x8];
3793         u8         reserved_at_8[0x18];
3794
3795         u8         syndrome[0x20];
3796
3797         u8         reserved_at_40[0x20];
3798
3799         u8         reserved_at_60[0x18];
3800         u8         admin_state[0x4];
3801         u8         state[0x4];
3802 };
3803
3804 enum {
3805         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
3806         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
3807 };
3808
3809 struct mlx5_ifc_query_vport_state_in_bits {
3810         u8         opcode[0x10];
3811         u8         reserved_at_10[0x10];
3812
3813         u8         reserved_at_20[0x10];
3814         u8         op_mod[0x10];
3815
3816         u8         other_vport[0x1];
3817         u8         reserved_at_41[0xf];
3818         u8         vport_number[0x10];
3819
3820         u8         reserved_at_60[0x20];
3821 };
3822
3823 struct mlx5_ifc_query_vnic_env_out_bits {
3824         u8         status[0x8];
3825         u8         reserved_at_8[0x18];
3826
3827         u8         syndrome[0x20];
3828
3829         u8         reserved_at_40[0x40];
3830
3831         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3832 };
3833
3834 enum {
3835         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
3836 };
3837
3838 struct mlx5_ifc_query_vnic_env_in_bits {
3839         u8         opcode[0x10];
3840         u8         reserved_at_10[0x10];
3841
3842         u8         reserved_at_20[0x10];
3843         u8         op_mod[0x10];
3844
3845         u8         other_vport[0x1];
3846         u8         reserved_at_41[0xf];
3847         u8         vport_number[0x10];
3848
3849         u8         reserved_at_60[0x20];
3850 };
3851
3852 struct mlx5_ifc_query_vport_counter_out_bits {
3853         u8         status[0x8];
3854         u8         reserved_at_8[0x18];
3855
3856         u8         syndrome[0x20];
3857
3858         u8         reserved_at_40[0x40];
3859
3860         struct mlx5_ifc_traffic_counter_bits received_errors;
3861
3862         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3863
3864         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3865
3866         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3867
3868         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3869
3870         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3871
3872         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3873
3874         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3875
3876         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3877
3878         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3879
3880         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3881
3882         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3883
3884         u8         reserved_at_680[0xa00];
3885 };
3886
3887 enum {
3888         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3889 };
3890
3891 struct mlx5_ifc_query_vport_counter_in_bits {
3892         u8         opcode[0x10];
3893         u8         reserved_at_10[0x10];
3894
3895         u8         reserved_at_20[0x10];
3896         u8         op_mod[0x10];
3897
3898         u8         other_vport[0x1];
3899         u8         reserved_at_41[0xb];
3900         u8         port_num[0x4];
3901         u8         vport_number[0x10];
3902
3903         u8         reserved_at_60[0x60];
3904
3905         u8         clear[0x1];
3906         u8         reserved_at_c1[0x1f];
3907
3908         u8         reserved_at_e0[0x20];
3909 };
3910
3911 struct mlx5_ifc_query_tis_out_bits {
3912         u8         status[0x8];
3913         u8         reserved_at_8[0x18];
3914
3915         u8         syndrome[0x20];
3916
3917         u8         reserved_at_40[0x40];
3918
3919         struct mlx5_ifc_tisc_bits tis_context;
3920 };
3921
3922 struct mlx5_ifc_query_tis_in_bits {
3923         u8         opcode[0x10];
3924         u8         reserved_at_10[0x10];
3925
3926         u8         reserved_at_20[0x10];
3927         u8         op_mod[0x10];
3928
3929         u8         reserved_at_40[0x8];
3930         u8         tisn[0x18];
3931
3932         u8         reserved_at_60[0x20];
3933 };
3934
3935 struct mlx5_ifc_query_tir_out_bits {
3936         u8         status[0x8];
3937         u8         reserved_at_8[0x18];
3938
3939         u8         syndrome[0x20];
3940
3941         u8         reserved_at_40[0xc0];
3942
3943         struct mlx5_ifc_tirc_bits tir_context;
3944 };
3945
3946 struct mlx5_ifc_query_tir_in_bits {
3947         u8         opcode[0x10];
3948         u8         reserved_at_10[0x10];
3949
3950         u8         reserved_at_20[0x10];
3951         u8         op_mod[0x10];
3952
3953         u8         reserved_at_40[0x8];
3954         u8         tirn[0x18];
3955
3956         u8         reserved_at_60[0x20];
3957 };
3958
3959 struct mlx5_ifc_query_srq_out_bits {
3960         u8         status[0x8];
3961         u8         reserved_at_8[0x18];
3962
3963         u8         syndrome[0x20];
3964
3965         u8         reserved_at_40[0x40];
3966
3967         struct mlx5_ifc_srqc_bits srq_context_entry;
3968
3969         u8         reserved_at_280[0x600];
3970
3971         u8         pas[0][0x40];
3972 };
3973
3974 struct mlx5_ifc_query_srq_in_bits {
3975         u8         opcode[0x10];
3976         u8         reserved_at_10[0x10];
3977
3978         u8         reserved_at_20[0x10];
3979         u8         op_mod[0x10];
3980
3981         u8         reserved_at_40[0x8];
3982         u8         srqn[0x18];
3983
3984         u8         reserved_at_60[0x20];
3985 };
3986
3987 struct mlx5_ifc_query_sq_out_bits {
3988         u8         status[0x8];
3989         u8         reserved_at_8[0x18];
3990
3991         u8         syndrome[0x20];
3992
3993         u8         reserved_at_40[0xc0];
3994
3995         struct mlx5_ifc_sqc_bits sq_context;
3996 };
3997
3998 struct mlx5_ifc_query_sq_in_bits {
3999         u8         opcode[0x10];
4000         u8         reserved_at_10[0x10];
4001
4002         u8         reserved_at_20[0x10];
4003         u8         op_mod[0x10];
4004
4005         u8         reserved_at_40[0x8];
4006         u8         sqn[0x18];
4007
4008         u8         reserved_at_60[0x20];
4009 };
4010
4011 struct mlx5_ifc_query_special_contexts_out_bits {
4012         u8         status[0x8];
4013         u8         reserved_at_8[0x18];
4014
4015         u8         syndrome[0x20];
4016
4017         u8         dump_fill_mkey[0x20];
4018
4019         u8         resd_lkey[0x20];
4020
4021         u8         null_mkey[0x20];
4022
4023         u8         reserved_at_a0[0x60];
4024 };
4025
4026 struct mlx5_ifc_query_special_contexts_in_bits {
4027         u8         opcode[0x10];
4028         u8         reserved_at_10[0x10];
4029
4030         u8         reserved_at_20[0x10];
4031         u8         op_mod[0x10];
4032
4033         u8         reserved_at_40[0x40];
4034 };
4035
4036 struct mlx5_ifc_query_scheduling_element_out_bits {
4037         u8         opcode[0x10];
4038         u8         reserved_at_10[0x10];
4039
4040         u8         reserved_at_20[0x10];
4041         u8         op_mod[0x10];
4042
4043         u8         reserved_at_40[0xc0];
4044
4045         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4046
4047         u8         reserved_at_300[0x100];
4048 };
4049
4050 enum {
4051         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4052 };
4053
4054 struct mlx5_ifc_query_scheduling_element_in_bits {
4055         u8         opcode[0x10];
4056         u8         reserved_at_10[0x10];
4057
4058         u8         reserved_at_20[0x10];
4059         u8         op_mod[0x10];
4060
4061         u8         scheduling_hierarchy[0x8];
4062         u8         reserved_at_48[0x18];
4063
4064         u8         scheduling_element_id[0x20];
4065
4066         u8         reserved_at_80[0x180];
4067 };
4068
4069 struct mlx5_ifc_query_rqt_out_bits {
4070         u8         status[0x8];
4071         u8         reserved_at_8[0x18];
4072
4073         u8         syndrome[0x20];
4074
4075         u8         reserved_at_40[0xc0];
4076
4077         struct mlx5_ifc_rqtc_bits rqt_context;
4078 };
4079
4080 struct mlx5_ifc_query_rqt_in_bits {
4081         u8         opcode[0x10];
4082         u8         reserved_at_10[0x10];
4083
4084         u8         reserved_at_20[0x10];
4085         u8         op_mod[0x10];
4086
4087         u8         reserved_at_40[0x8];
4088         u8         rqtn[0x18];
4089
4090         u8         reserved_at_60[0x20];
4091 };
4092
4093 struct mlx5_ifc_query_rq_out_bits {
4094         u8         status[0x8];
4095         u8         reserved_at_8[0x18];
4096
4097         u8         syndrome[0x20];
4098
4099         u8         reserved_at_40[0xc0];
4100
4101         struct mlx5_ifc_rqc_bits rq_context;
4102 };
4103
4104 struct mlx5_ifc_query_rq_in_bits {
4105         u8         opcode[0x10];
4106         u8         reserved_at_10[0x10];
4107
4108         u8         reserved_at_20[0x10];
4109         u8         op_mod[0x10];
4110
4111         u8         reserved_at_40[0x8];
4112         u8         rqn[0x18];
4113
4114         u8         reserved_at_60[0x20];
4115 };
4116
4117 struct mlx5_ifc_query_roce_address_out_bits {
4118         u8         status[0x8];
4119         u8         reserved_at_8[0x18];
4120
4121         u8         syndrome[0x20];
4122
4123         u8         reserved_at_40[0x40];
4124
4125         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4126 };
4127
4128 struct mlx5_ifc_query_roce_address_in_bits {
4129         u8         opcode[0x10];
4130         u8         reserved_at_10[0x10];
4131
4132         u8         reserved_at_20[0x10];
4133         u8         op_mod[0x10];
4134
4135         u8         roce_address_index[0x10];
4136         u8         reserved_at_50[0xc];
4137         u8         vhca_port_num[0x4];
4138
4139         u8         reserved_at_60[0x20];
4140 };
4141
4142 struct mlx5_ifc_query_rmp_out_bits {
4143         u8         status[0x8];
4144         u8         reserved_at_8[0x18];
4145
4146         u8         syndrome[0x20];
4147
4148         u8         reserved_at_40[0xc0];
4149
4150         struct mlx5_ifc_rmpc_bits rmp_context;
4151 };
4152
4153 struct mlx5_ifc_query_rmp_in_bits {
4154         u8         opcode[0x10];
4155         u8         reserved_at_10[0x10];
4156
4157         u8         reserved_at_20[0x10];
4158         u8         op_mod[0x10];
4159
4160         u8         reserved_at_40[0x8];
4161         u8         rmpn[0x18];
4162
4163         u8         reserved_at_60[0x20];
4164 };
4165
4166 struct mlx5_ifc_query_qp_out_bits {
4167         u8         status[0x8];
4168         u8         reserved_at_8[0x18];
4169
4170         u8         syndrome[0x20];
4171
4172         u8         reserved_at_40[0x40];
4173
4174         u8         opt_param_mask[0x20];
4175
4176         u8         reserved_at_a0[0x20];
4177
4178         struct mlx5_ifc_qpc_bits qpc;
4179
4180         u8         reserved_at_800[0x80];
4181
4182         u8         pas[0][0x40];
4183 };
4184
4185 struct mlx5_ifc_query_qp_in_bits {
4186         u8         opcode[0x10];
4187         u8         reserved_at_10[0x10];
4188
4189         u8         reserved_at_20[0x10];
4190         u8         op_mod[0x10];
4191
4192         u8         reserved_at_40[0x8];
4193         u8         qpn[0x18];
4194
4195         u8         reserved_at_60[0x20];
4196 };
4197
4198 struct mlx5_ifc_query_q_counter_out_bits {
4199         u8         status[0x8];
4200         u8         reserved_at_8[0x18];
4201
4202         u8         syndrome[0x20];
4203
4204         u8         reserved_at_40[0x40];
4205
4206         u8         rx_write_requests[0x20];
4207
4208         u8         reserved_at_a0[0x20];
4209
4210         u8         rx_read_requests[0x20];
4211
4212         u8         reserved_at_e0[0x20];
4213
4214         u8         rx_atomic_requests[0x20];
4215
4216         u8         reserved_at_120[0x20];
4217
4218         u8         rx_dct_connect[0x20];
4219
4220         u8         reserved_at_160[0x20];
4221
4222         u8         out_of_buffer[0x20];
4223
4224         u8         reserved_at_1a0[0x20];
4225
4226         u8         out_of_sequence[0x20];
4227
4228         u8         reserved_at_1e0[0x20];
4229
4230         u8         duplicate_request[0x20];
4231
4232         u8         reserved_at_220[0x20];
4233
4234         u8         rnr_nak_retry_err[0x20];
4235
4236         u8         reserved_at_260[0x20];
4237
4238         u8         packet_seq_err[0x20];
4239
4240         u8         reserved_at_2a0[0x20];
4241
4242         u8         implied_nak_seq_err[0x20];
4243
4244         u8         reserved_at_2e0[0x20];
4245
4246         u8         local_ack_timeout_err[0x20];
4247
4248         u8         reserved_at_320[0xa0];
4249
4250         u8         resp_local_length_error[0x20];
4251
4252         u8         req_local_length_error[0x20];
4253
4254         u8         resp_local_qp_error[0x20];
4255
4256         u8         local_operation_error[0x20];
4257
4258         u8         resp_local_protection[0x20];
4259
4260         u8         req_local_protection[0x20];
4261
4262         u8         resp_cqe_error[0x20];
4263
4264         u8         req_cqe_error[0x20];
4265
4266         u8         req_mw_binding[0x20];
4267
4268         u8         req_bad_response[0x20];
4269
4270         u8         req_remote_invalid_request[0x20];
4271
4272         u8         resp_remote_invalid_request[0x20];
4273
4274         u8         req_remote_access_errors[0x20];
4275
4276         u8         resp_remote_access_errors[0x20];
4277
4278         u8         req_remote_operation_errors[0x20];
4279
4280         u8         req_transport_retries_exceeded[0x20];
4281
4282         u8         cq_overflow[0x20];
4283
4284         u8         resp_cqe_flush_error[0x20];
4285
4286         u8         req_cqe_flush_error[0x20];
4287
4288         u8         reserved_at_620[0x1e0];
4289 };
4290
4291 struct mlx5_ifc_query_q_counter_in_bits {
4292         u8         opcode[0x10];
4293         u8         reserved_at_10[0x10];
4294
4295         u8         reserved_at_20[0x10];
4296         u8         op_mod[0x10];
4297
4298         u8         reserved_at_40[0x80];
4299
4300         u8         clear[0x1];
4301         u8         reserved_at_c1[0x1f];
4302
4303         u8         reserved_at_e0[0x18];
4304         u8         counter_set_id[0x8];
4305 };
4306
4307 struct mlx5_ifc_query_pages_out_bits {
4308         u8         status[0x8];
4309         u8         reserved_at_8[0x18];
4310
4311         u8         syndrome[0x20];
4312
4313         u8         reserved_at_40[0x10];
4314         u8         function_id[0x10];
4315
4316         u8         num_pages[0x20];
4317 };
4318
4319 enum {
4320         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4321         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4322         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4323 };
4324
4325 struct mlx5_ifc_query_pages_in_bits {
4326         u8         opcode[0x10];
4327         u8         reserved_at_10[0x10];
4328
4329         u8         reserved_at_20[0x10];
4330         u8         op_mod[0x10];
4331
4332         u8         reserved_at_40[0x10];
4333         u8         function_id[0x10];
4334
4335         u8         reserved_at_60[0x20];
4336 };
4337
4338 struct mlx5_ifc_query_nic_vport_context_out_bits {
4339         u8         status[0x8];
4340         u8         reserved_at_8[0x18];
4341
4342         u8         syndrome[0x20];
4343
4344         u8         reserved_at_40[0x40];
4345
4346         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4347 };
4348
4349 struct mlx5_ifc_query_nic_vport_context_in_bits {
4350         u8         opcode[0x10];
4351         u8         reserved_at_10[0x10];
4352
4353         u8         reserved_at_20[0x10];
4354         u8         op_mod[0x10];
4355
4356         u8         other_vport[0x1];
4357         u8         reserved_at_41[0xf];
4358         u8         vport_number[0x10];
4359
4360         u8         reserved_at_60[0x5];
4361         u8         allowed_list_type[0x3];
4362         u8         reserved_at_68[0x18];
4363 };
4364
4365 struct mlx5_ifc_query_mkey_out_bits {
4366         u8         status[0x8];
4367         u8         reserved_at_8[0x18];
4368
4369         u8         syndrome[0x20];
4370
4371         u8         reserved_at_40[0x40];
4372
4373         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4374
4375         u8         reserved_at_280[0x600];
4376
4377         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4378
4379         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4380 };
4381
4382 struct mlx5_ifc_query_mkey_in_bits {
4383         u8         opcode[0x10];
4384         u8         reserved_at_10[0x10];
4385
4386         u8         reserved_at_20[0x10];
4387         u8         op_mod[0x10];
4388
4389         u8         reserved_at_40[0x8];
4390         u8         mkey_index[0x18];
4391
4392         u8         pg_access[0x1];
4393         u8         reserved_at_61[0x1f];
4394 };
4395
4396 struct mlx5_ifc_query_mad_demux_out_bits {
4397         u8         status[0x8];
4398         u8         reserved_at_8[0x18];
4399
4400         u8         syndrome[0x20];
4401
4402         u8         reserved_at_40[0x40];
4403
4404         u8         mad_dumux_parameters_block[0x20];
4405 };
4406
4407 struct mlx5_ifc_query_mad_demux_in_bits {
4408         u8         opcode[0x10];
4409         u8         reserved_at_10[0x10];
4410
4411         u8         reserved_at_20[0x10];
4412         u8         op_mod[0x10];
4413
4414         u8         reserved_at_40[0x40];
4415 };
4416
4417 struct mlx5_ifc_query_l2_table_entry_out_bits {
4418         u8         status[0x8];
4419         u8         reserved_at_8[0x18];
4420
4421         u8         syndrome[0x20];
4422
4423         u8         reserved_at_40[0xa0];
4424
4425         u8         reserved_at_e0[0x13];
4426         u8         vlan_valid[0x1];
4427         u8         vlan[0xc];
4428
4429         struct mlx5_ifc_mac_address_layout_bits mac_address;
4430
4431         u8         reserved_at_140[0xc0];
4432 };
4433
4434 struct mlx5_ifc_query_l2_table_entry_in_bits {
4435         u8         opcode[0x10];
4436         u8         reserved_at_10[0x10];
4437
4438         u8         reserved_at_20[0x10];
4439         u8         op_mod[0x10];
4440
4441         u8         reserved_at_40[0x60];
4442
4443         u8         reserved_at_a0[0x8];
4444         u8         table_index[0x18];
4445
4446         u8         reserved_at_c0[0x140];
4447 };
4448
4449 struct mlx5_ifc_query_issi_out_bits {
4450         u8         status[0x8];
4451         u8         reserved_at_8[0x18];
4452
4453         u8         syndrome[0x20];
4454
4455         u8         reserved_at_40[0x10];
4456         u8         current_issi[0x10];
4457
4458         u8         reserved_at_60[0xa0];
4459
4460         u8         reserved_at_100[76][0x8];
4461         u8         supported_issi_dw0[0x20];
4462 };
4463
4464 struct mlx5_ifc_query_issi_in_bits {
4465         u8         opcode[0x10];
4466         u8         reserved_at_10[0x10];
4467
4468         u8         reserved_at_20[0x10];
4469         u8         op_mod[0x10];
4470
4471         u8         reserved_at_40[0x40];
4472 };
4473
4474 struct mlx5_ifc_set_driver_version_out_bits {
4475         u8         status[0x8];
4476         u8         reserved_0[0x18];
4477
4478         u8         syndrome[0x20];
4479         u8         reserved_1[0x40];
4480 };
4481
4482 struct mlx5_ifc_set_driver_version_in_bits {
4483         u8         opcode[0x10];
4484         u8         reserved_0[0x10];
4485
4486         u8         reserved_1[0x10];
4487         u8         op_mod[0x10];
4488
4489         u8         reserved_2[0x40];
4490         u8         driver_version[64][0x8];
4491 };
4492
4493 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4494         u8         status[0x8];
4495         u8         reserved_at_8[0x18];
4496
4497         u8         syndrome[0x20];
4498
4499         u8         reserved_at_40[0x40];
4500
4501         struct mlx5_ifc_pkey_bits pkey[0];
4502 };
4503
4504 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4505         u8         opcode[0x10];
4506         u8         reserved_at_10[0x10];
4507
4508         u8         reserved_at_20[0x10];
4509         u8         op_mod[0x10];
4510
4511         u8         other_vport[0x1];
4512         u8         reserved_at_41[0xb];
4513         u8         port_num[0x4];
4514         u8         vport_number[0x10];
4515
4516         u8         reserved_at_60[0x10];
4517         u8         pkey_index[0x10];
4518 };
4519
4520 enum {
4521         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4522         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4523         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4524 };
4525
4526 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4527         u8         status[0x8];
4528         u8         reserved_at_8[0x18];
4529
4530         u8         syndrome[0x20];
4531
4532         u8         reserved_at_40[0x20];
4533
4534         u8         gids_num[0x10];
4535         u8         reserved_at_70[0x10];
4536
4537         struct mlx5_ifc_array128_auto_bits gid[0];
4538 };
4539
4540 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4541         u8         opcode[0x10];
4542         u8         reserved_at_10[0x10];
4543
4544         u8         reserved_at_20[0x10];
4545         u8         op_mod[0x10];
4546
4547         u8         other_vport[0x1];
4548         u8         reserved_at_41[0xb];
4549         u8         port_num[0x4];
4550         u8         vport_number[0x10];
4551
4552         u8         reserved_at_60[0x10];
4553         u8         gid_index[0x10];
4554 };
4555
4556 struct mlx5_ifc_query_hca_vport_context_out_bits {
4557         u8         status[0x8];
4558         u8         reserved_at_8[0x18];
4559
4560         u8         syndrome[0x20];
4561
4562         u8         reserved_at_40[0x40];
4563
4564         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4565 };
4566
4567 struct mlx5_ifc_query_hca_vport_context_in_bits {
4568         u8         opcode[0x10];
4569         u8         reserved_at_10[0x10];
4570
4571         u8         reserved_at_20[0x10];
4572         u8         op_mod[0x10];
4573
4574         u8         other_vport[0x1];
4575         u8         reserved_at_41[0xb];
4576         u8         port_num[0x4];
4577         u8         vport_number[0x10];
4578
4579         u8         reserved_at_60[0x20];
4580 };
4581
4582 struct mlx5_ifc_query_hca_cap_out_bits {
4583         u8         status[0x8];
4584         u8         reserved_at_8[0x18];
4585
4586         u8         syndrome[0x20];
4587
4588         u8         reserved_at_40[0x40];
4589
4590         union mlx5_ifc_hca_cap_union_bits capability;
4591 };
4592
4593 struct mlx5_ifc_query_hca_cap_in_bits {
4594         u8         opcode[0x10];
4595         u8         reserved_at_10[0x10];
4596
4597         u8         reserved_at_20[0x10];
4598         u8         op_mod[0x10];
4599
4600         u8         reserved_at_40[0x40];
4601 };
4602
4603 struct mlx5_ifc_query_flow_table_out_bits {
4604         u8         status[0x8];
4605         u8         reserved_at_8[0x18];
4606
4607         u8         syndrome[0x20];
4608
4609         u8         reserved_at_40[0x80];
4610
4611         u8         reserved_at_c0[0x8];
4612         u8         level[0x8];
4613         u8         reserved_at_d0[0x8];
4614         u8         log_size[0x8];
4615
4616         u8         reserved_at_e0[0x120];
4617 };
4618
4619 struct mlx5_ifc_query_flow_table_in_bits {
4620         u8         opcode[0x10];
4621         u8         reserved_at_10[0x10];
4622
4623         u8         reserved_at_20[0x10];
4624         u8         op_mod[0x10];
4625
4626         u8         reserved_at_40[0x40];
4627
4628         u8         table_type[0x8];
4629         u8         reserved_at_88[0x18];
4630
4631         u8         reserved_at_a0[0x8];
4632         u8         table_id[0x18];
4633
4634         u8         reserved_at_c0[0x140];
4635 };
4636
4637 struct mlx5_ifc_query_fte_out_bits {
4638         u8         status[0x8];
4639         u8         reserved_at_8[0x18];
4640
4641         u8         syndrome[0x20];
4642
4643         u8         reserved_at_40[0x1c0];
4644
4645         struct mlx5_ifc_flow_context_bits flow_context;
4646 };
4647
4648 struct mlx5_ifc_query_fte_in_bits {
4649         u8         opcode[0x10];
4650         u8         reserved_at_10[0x10];
4651
4652         u8         reserved_at_20[0x10];
4653         u8         op_mod[0x10];
4654
4655         u8         reserved_at_40[0x40];
4656
4657         u8         table_type[0x8];
4658         u8         reserved_at_88[0x18];
4659
4660         u8         reserved_at_a0[0x8];
4661         u8         table_id[0x18];
4662
4663         u8         reserved_at_c0[0x40];
4664
4665         u8         flow_index[0x20];
4666
4667         u8         reserved_at_120[0xe0];
4668 };
4669
4670 enum {
4671         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4672         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4673         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4674         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4675 };
4676
4677 struct mlx5_ifc_query_flow_group_out_bits {
4678         u8         status[0x8];
4679         u8         reserved_at_8[0x18];
4680
4681         u8         syndrome[0x20];
4682
4683         u8         reserved_at_40[0xa0];
4684
4685         u8         start_flow_index[0x20];
4686
4687         u8         reserved_at_100[0x20];
4688
4689         u8         end_flow_index[0x20];
4690
4691         u8         reserved_at_140[0xa0];
4692
4693         u8         reserved_at_1e0[0x18];
4694         u8         match_criteria_enable[0x8];
4695
4696         struct mlx5_ifc_fte_match_param_bits match_criteria;
4697
4698         u8         reserved_at_1200[0xe00];
4699 };
4700
4701 struct mlx5_ifc_query_flow_group_in_bits {
4702         u8         opcode[0x10];
4703         u8         reserved_at_10[0x10];
4704
4705         u8         reserved_at_20[0x10];
4706         u8         op_mod[0x10];
4707
4708         u8         reserved_at_40[0x40];
4709
4710         u8         table_type[0x8];
4711         u8         reserved_at_88[0x18];
4712
4713         u8         reserved_at_a0[0x8];
4714         u8         table_id[0x18];
4715
4716         u8         group_id[0x20];
4717
4718         u8         reserved_at_e0[0x120];
4719 };
4720
4721 struct mlx5_ifc_query_flow_counter_out_bits {
4722         u8         status[0x8];
4723         u8         reserved_at_8[0x18];
4724
4725         u8         syndrome[0x20];
4726
4727         u8         reserved_at_40[0x40];
4728
4729         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4730 };
4731
4732 struct mlx5_ifc_query_flow_counter_in_bits {
4733         u8         opcode[0x10];
4734         u8         reserved_at_10[0x10];
4735
4736         u8         reserved_at_20[0x10];
4737         u8         op_mod[0x10];
4738
4739         u8         reserved_at_40[0x80];
4740
4741         u8         clear[0x1];
4742         u8         reserved_at_c1[0xf];
4743         u8         num_of_counters[0x10];
4744
4745         u8         flow_counter_id[0x20];
4746 };
4747
4748 struct mlx5_ifc_query_esw_vport_context_out_bits {
4749         u8         status[0x8];
4750         u8         reserved_at_8[0x18];
4751
4752         u8         syndrome[0x20];
4753
4754         u8         reserved_at_40[0x40];
4755
4756         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4757 };
4758
4759 struct mlx5_ifc_query_esw_vport_context_in_bits {
4760         u8         opcode[0x10];
4761         u8         reserved_at_10[0x10];
4762
4763         u8         reserved_at_20[0x10];
4764         u8         op_mod[0x10];
4765
4766         u8         other_vport[0x1];
4767         u8         reserved_at_41[0xf];
4768         u8         vport_number[0x10];
4769
4770         u8         reserved_at_60[0x20];
4771 };
4772
4773 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4774         u8         status[0x8];
4775         u8         reserved_at_8[0x18];
4776
4777         u8         syndrome[0x20];
4778
4779         u8         reserved_at_40[0x40];
4780 };
4781
4782 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4783         u8         reserved_at_0[0x1c];
4784         u8         vport_cvlan_insert[0x1];
4785         u8         vport_svlan_insert[0x1];
4786         u8         vport_cvlan_strip[0x1];
4787         u8         vport_svlan_strip[0x1];
4788 };
4789
4790 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4791         u8         opcode[0x10];
4792         u8         reserved_at_10[0x10];
4793
4794         u8         reserved_at_20[0x10];
4795         u8         op_mod[0x10];
4796
4797         u8         other_vport[0x1];
4798         u8         reserved_at_41[0xf];
4799         u8         vport_number[0x10];
4800
4801         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4802
4803         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4804 };
4805
4806 struct mlx5_ifc_query_eq_out_bits {
4807         u8         status[0x8];
4808         u8         reserved_at_8[0x18];
4809
4810         u8         syndrome[0x20];
4811
4812         u8         reserved_at_40[0x40];
4813
4814         struct mlx5_ifc_eqc_bits eq_context_entry;
4815
4816         u8         reserved_at_280[0x40];
4817
4818         u8         event_bitmask[0x40];
4819
4820         u8         reserved_at_300[0x580];
4821
4822         u8         pas[0][0x40];
4823 };
4824
4825 struct mlx5_ifc_query_eq_in_bits {
4826         u8         opcode[0x10];
4827         u8         reserved_at_10[0x10];
4828
4829         u8         reserved_at_20[0x10];
4830         u8         op_mod[0x10];
4831
4832         u8         reserved_at_40[0x18];
4833         u8         eq_number[0x8];
4834
4835         u8         reserved_at_60[0x20];
4836 };
4837
4838 struct mlx5_ifc_packet_reformat_context_in_bits {
4839         u8         reserved_at_0[0x5];
4840         u8         reformat_type[0x3];
4841         u8         reserved_at_8[0xe];
4842         u8         reformat_data_size[0xa];
4843
4844         u8         reserved_at_20[0x10];
4845         u8         reformat_data[2][0x8];
4846
4847         u8         more_reformat_data[0][0x8];
4848 };
4849
4850 struct mlx5_ifc_query_packet_reformat_context_out_bits {
4851         u8         status[0x8];
4852         u8         reserved_at_8[0x18];
4853
4854         u8         syndrome[0x20];
4855
4856         u8         reserved_at_40[0xa0];
4857
4858         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
4859 };
4860
4861 struct mlx5_ifc_query_packet_reformat_context_in_bits {
4862         u8         opcode[0x10];
4863         u8         reserved_at_10[0x10];
4864
4865         u8         reserved_at_20[0x10];
4866         u8         op_mod[0x10];
4867
4868         u8         packet_reformat_id[0x20];
4869
4870         u8         reserved_at_60[0xa0];
4871 };
4872
4873 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
4874         u8         status[0x8];
4875         u8         reserved_at_8[0x18];
4876
4877         u8         syndrome[0x20];
4878
4879         u8         packet_reformat_id[0x20];
4880
4881         u8         reserved_at_60[0x20];
4882 };
4883
4884 enum {
4885         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
4886         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
4887         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
4888         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
4889         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
4890 };
4891
4892 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
4893         u8         opcode[0x10];
4894         u8         reserved_at_10[0x10];
4895
4896         u8         reserved_at_20[0x10];
4897         u8         op_mod[0x10];
4898
4899         u8         reserved_at_40[0xa0];
4900
4901         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
4902 };
4903
4904 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
4905         u8         status[0x8];
4906         u8         reserved_at_8[0x18];
4907
4908         u8         syndrome[0x20];
4909
4910         u8         reserved_at_40[0x40];
4911 };
4912
4913 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
4914         u8         opcode[0x10];
4915         u8         reserved_at_10[0x10];
4916
4917         u8         reserved_20[0x10];
4918         u8         op_mod[0x10];
4919
4920         u8         packet_reformat_id[0x20];
4921
4922         u8         reserved_60[0x20];
4923 };
4924
4925 struct mlx5_ifc_set_action_in_bits {
4926         u8         action_type[0x4];
4927         u8         field[0xc];
4928         u8         reserved_at_10[0x3];
4929         u8         offset[0x5];
4930         u8         reserved_at_18[0x3];
4931         u8         length[0x5];
4932
4933         u8         data[0x20];
4934 };
4935
4936 struct mlx5_ifc_add_action_in_bits {
4937         u8         action_type[0x4];
4938         u8         field[0xc];
4939         u8         reserved_at_10[0x10];
4940
4941         u8         data[0x20];
4942 };
4943
4944 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4945         struct mlx5_ifc_set_action_in_bits set_action_in;
4946         struct mlx5_ifc_add_action_in_bits add_action_in;
4947         u8         reserved_at_0[0x40];
4948 };
4949
4950 enum {
4951         MLX5_ACTION_TYPE_SET   = 0x1,
4952         MLX5_ACTION_TYPE_ADD   = 0x2,
4953 };
4954
4955 enum {
4956         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4957         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4958         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4959         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4960         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4961         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4962         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4963         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4964         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4965         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4966         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4967         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4968         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4969         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4970         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4971         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4972         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4973         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4974         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4975         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4976         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4977         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4978         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4979 };
4980
4981 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4982         u8         status[0x8];
4983         u8         reserved_at_8[0x18];
4984
4985         u8         syndrome[0x20];
4986
4987         u8         modify_header_id[0x20];
4988
4989         u8         reserved_at_60[0x20];
4990 };
4991
4992 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4993         u8         opcode[0x10];
4994         u8         reserved_at_10[0x10];
4995
4996         u8         reserved_at_20[0x10];
4997         u8         op_mod[0x10];
4998
4999         u8         reserved_at_40[0x20];
5000
5001         u8         table_type[0x8];
5002         u8         reserved_at_68[0x10];
5003         u8         num_of_actions[0x8];
5004
5005         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5006 };
5007
5008 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5009         u8         status[0x8];
5010         u8         reserved_at_8[0x18];
5011
5012         u8         syndrome[0x20];
5013
5014         u8         reserved_at_40[0x40];
5015 };
5016
5017 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5018         u8         opcode[0x10];
5019         u8         reserved_at_10[0x10];
5020
5021         u8         reserved_at_20[0x10];
5022         u8         op_mod[0x10];
5023
5024         u8         modify_header_id[0x20];
5025
5026         u8         reserved_at_60[0x20];
5027 };
5028
5029 struct mlx5_ifc_query_dct_out_bits {
5030         u8         status[0x8];
5031         u8         reserved_at_8[0x18];
5032
5033         u8         syndrome[0x20];
5034
5035         u8         reserved_at_40[0x40];
5036
5037         struct mlx5_ifc_dctc_bits dct_context_entry;
5038
5039         u8         reserved_at_280[0x180];
5040 };
5041
5042 struct mlx5_ifc_query_dct_in_bits {
5043         u8         opcode[0x10];
5044         u8         reserved_at_10[0x10];
5045
5046         u8         reserved_at_20[0x10];
5047         u8         op_mod[0x10];
5048
5049         u8         reserved_at_40[0x8];
5050         u8         dctn[0x18];
5051
5052         u8         reserved_at_60[0x20];
5053 };
5054
5055 struct mlx5_ifc_query_cq_out_bits {
5056         u8         status[0x8];
5057         u8         reserved_at_8[0x18];
5058
5059         u8         syndrome[0x20];
5060
5061         u8         reserved_at_40[0x40];
5062
5063         struct mlx5_ifc_cqc_bits cq_context;
5064
5065         u8         reserved_at_280[0x600];
5066
5067         u8         pas[0][0x40];
5068 };
5069
5070 struct mlx5_ifc_query_cq_in_bits {
5071         u8         opcode[0x10];
5072         u8         reserved_at_10[0x10];
5073
5074         u8         reserved_at_20[0x10];
5075         u8         op_mod[0x10];
5076
5077         u8         reserved_at_40[0x8];
5078         u8         cqn[0x18];
5079
5080         u8         reserved_at_60[0x20];
5081 };
5082
5083 struct mlx5_ifc_query_cong_status_out_bits {
5084         u8         status[0x8];
5085         u8         reserved_at_8[0x18];
5086
5087         u8         syndrome[0x20];
5088
5089         u8         reserved_at_40[0x20];
5090
5091         u8         enable[0x1];
5092         u8         tag_enable[0x1];
5093         u8         reserved_at_62[0x1e];
5094 };
5095
5096 struct mlx5_ifc_query_cong_status_in_bits {
5097         u8         opcode[0x10];
5098         u8         reserved_at_10[0x10];
5099
5100         u8         reserved_at_20[0x10];
5101         u8         op_mod[0x10];
5102
5103         u8         reserved_at_40[0x18];
5104         u8         priority[0x4];
5105         u8         cong_protocol[0x4];
5106
5107         u8         reserved_at_60[0x20];
5108 };
5109
5110 struct mlx5_ifc_query_cong_statistics_out_bits {
5111         u8         status[0x8];
5112         u8         reserved_at_8[0x18];
5113
5114         u8         syndrome[0x20];
5115
5116         u8         reserved_at_40[0x40];
5117
5118         u8         rp_cur_flows[0x20];
5119
5120         u8         sum_flows[0x20];
5121
5122         u8         rp_cnp_ignored_high[0x20];
5123
5124         u8         rp_cnp_ignored_low[0x20];
5125
5126         u8         rp_cnp_handled_high[0x20];
5127
5128         u8         rp_cnp_handled_low[0x20];
5129
5130         u8         reserved_at_140[0x100];
5131
5132         u8         time_stamp_high[0x20];
5133
5134         u8         time_stamp_low[0x20];
5135
5136         u8         accumulators_period[0x20];
5137
5138         u8         np_ecn_marked_roce_packets_high[0x20];
5139
5140         u8         np_ecn_marked_roce_packets_low[0x20];
5141
5142         u8         np_cnp_sent_high[0x20];
5143
5144         u8         np_cnp_sent_low[0x20];
5145
5146         u8         reserved_at_320[0x560];
5147 };
5148
5149 struct mlx5_ifc_query_cong_statistics_in_bits {
5150         u8         opcode[0x10];
5151         u8         reserved_at_10[0x10];
5152
5153         u8         reserved_at_20[0x10];
5154         u8         op_mod[0x10];
5155
5156         u8         clear[0x1];
5157         u8         reserved_at_41[0x1f];
5158
5159         u8         reserved_at_60[0x20];
5160 };
5161
5162 struct mlx5_ifc_query_cong_params_out_bits {
5163         u8         status[0x8];
5164         u8         reserved_at_8[0x18];
5165
5166         u8         syndrome[0x20];
5167
5168         u8         reserved_at_40[0x40];
5169
5170         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5171 };
5172
5173 struct mlx5_ifc_query_cong_params_in_bits {
5174         u8         opcode[0x10];
5175         u8         reserved_at_10[0x10];
5176
5177         u8         reserved_at_20[0x10];
5178         u8         op_mod[0x10];
5179
5180         u8         reserved_at_40[0x1c];
5181         u8         cong_protocol[0x4];
5182
5183         u8         reserved_at_60[0x20];
5184 };
5185
5186 struct mlx5_ifc_query_adapter_out_bits {
5187         u8         status[0x8];
5188         u8         reserved_at_8[0x18];
5189
5190         u8         syndrome[0x20];
5191
5192         u8         reserved_at_40[0x40];
5193
5194         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5195 };
5196
5197 struct mlx5_ifc_query_adapter_in_bits {
5198         u8         opcode[0x10];
5199         u8         reserved_at_10[0x10];
5200
5201         u8         reserved_at_20[0x10];
5202         u8         op_mod[0x10];
5203
5204         u8         reserved_at_40[0x40];
5205 };
5206
5207 struct mlx5_ifc_qp_2rst_out_bits {
5208         u8         status[0x8];
5209         u8         reserved_at_8[0x18];
5210
5211         u8         syndrome[0x20];
5212
5213         u8         reserved_at_40[0x40];
5214 };
5215
5216 struct mlx5_ifc_qp_2rst_in_bits {
5217         u8         opcode[0x10];
5218         u8         uid[0x10];
5219
5220         u8         reserved_at_20[0x10];
5221         u8         op_mod[0x10];
5222
5223         u8         reserved_at_40[0x8];
5224         u8         qpn[0x18];
5225
5226         u8         reserved_at_60[0x20];
5227 };
5228
5229 struct mlx5_ifc_qp_2err_out_bits {
5230         u8         status[0x8];
5231         u8         reserved_at_8[0x18];
5232
5233         u8         syndrome[0x20];
5234
5235         u8         reserved_at_40[0x40];
5236 };
5237
5238 struct mlx5_ifc_qp_2err_in_bits {
5239         u8         opcode[0x10];
5240         u8         uid[0x10];
5241
5242         u8         reserved_at_20[0x10];
5243         u8         op_mod[0x10];
5244
5245         u8         reserved_at_40[0x8];
5246         u8         qpn[0x18];
5247
5248         u8         reserved_at_60[0x20];
5249 };
5250
5251 struct mlx5_ifc_page_fault_resume_out_bits {
5252         u8         status[0x8];
5253         u8         reserved_at_8[0x18];
5254
5255         u8         syndrome[0x20];
5256
5257         u8         reserved_at_40[0x40];
5258 };
5259
5260 struct mlx5_ifc_page_fault_resume_in_bits {
5261         u8         opcode[0x10];
5262         u8         reserved_at_10[0x10];
5263
5264         u8         reserved_at_20[0x10];
5265         u8         op_mod[0x10];
5266
5267         u8         error[0x1];
5268         u8         reserved_at_41[0x4];
5269         u8         page_fault_type[0x3];
5270         u8         wq_number[0x18];
5271
5272         u8         reserved_at_60[0x8];
5273         u8         token[0x18];
5274 };
5275
5276 struct mlx5_ifc_nop_out_bits {
5277         u8         status[0x8];
5278         u8         reserved_at_8[0x18];
5279
5280         u8         syndrome[0x20];
5281
5282         u8         reserved_at_40[0x40];
5283 };
5284
5285 struct mlx5_ifc_nop_in_bits {
5286         u8         opcode[0x10];
5287         u8         reserved_at_10[0x10];
5288
5289         u8         reserved_at_20[0x10];
5290         u8         op_mod[0x10];
5291
5292         u8         reserved_at_40[0x40];
5293 };
5294
5295 struct mlx5_ifc_modify_vport_state_out_bits {
5296         u8         status[0x8];
5297         u8         reserved_at_8[0x18];
5298
5299         u8         syndrome[0x20];
5300
5301         u8         reserved_at_40[0x40];
5302 };
5303
5304 struct mlx5_ifc_modify_vport_state_in_bits {
5305         u8         opcode[0x10];
5306         u8         reserved_at_10[0x10];
5307
5308         u8         reserved_at_20[0x10];
5309         u8         op_mod[0x10];
5310
5311         u8         other_vport[0x1];
5312         u8         reserved_at_41[0xf];
5313         u8         vport_number[0x10];
5314
5315         u8         reserved_at_60[0x18];
5316         u8         admin_state[0x4];
5317         u8         reserved_at_7c[0x4];
5318 };
5319
5320 struct mlx5_ifc_modify_tis_out_bits {
5321         u8         status[0x8];
5322         u8         reserved_at_8[0x18];
5323
5324         u8         syndrome[0x20];
5325
5326         u8         reserved_at_40[0x40];
5327 };
5328
5329 struct mlx5_ifc_modify_tis_bitmask_bits {
5330         u8         reserved_at_0[0x20];
5331
5332         u8         reserved_at_20[0x1d];
5333         u8         lag_tx_port_affinity[0x1];
5334         u8         strict_lag_tx_port_affinity[0x1];
5335         u8         prio[0x1];
5336 };
5337
5338 struct mlx5_ifc_modify_tis_in_bits {
5339         u8         opcode[0x10];
5340         u8         uid[0x10];
5341
5342         u8         reserved_at_20[0x10];
5343         u8         op_mod[0x10];
5344
5345         u8         reserved_at_40[0x8];
5346         u8         tisn[0x18];
5347
5348         u8         reserved_at_60[0x20];
5349
5350         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5351
5352         u8         reserved_at_c0[0x40];
5353
5354         struct mlx5_ifc_tisc_bits ctx;
5355 };
5356
5357 struct mlx5_ifc_modify_tir_bitmask_bits {
5358         u8         reserved_at_0[0x20];
5359
5360         u8         reserved_at_20[0x1b];
5361         u8         self_lb_en[0x1];
5362         u8         reserved_at_3c[0x1];
5363         u8         hash[0x1];
5364         u8         reserved_at_3e[0x1];
5365         u8         lro[0x1];
5366 };
5367
5368 struct mlx5_ifc_modify_tir_out_bits {
5369         u8         status[0x8];
5370         u8         reserved_at_8[0x18];
5371
5372         u8         syndrome[0x20];
5373
5374         u8         reserved_at_40[0x40];
5375 };
5376
5377 struct mlx5_ifc_modify_tir_in_bits {
5378         u8         opcode[0x10];
5379         u8         uid[0x10];
5380
5381         u8         reserved_at_20[0x10];
5382         u8         op_mod[0x10];
5383
5384         u8         reserved_at_40[0x8];
5385         u8         tirn[0x18];
5386
5387         u8         reserved_at_60[0x20];
5388
5389         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5390
5391         u8         reserved_at_c0[0x40];
5392
5393         struct mlx5_ifc_tirc_bits ctx;
5394 };
5395
5396 struct mlx5_ifc_modify_sq_out_bits {
5397         u8         status[0x8];
5398         u8         reserved_at_8[0x18];
5399
5400         u8         syndrome[0x20];
5401
5402         u8         reserved_at_40[0x40];
5403 };
5404
5405 struct mlx5_ifc_modify_sq_in_bits {
5406         u8         opcode[0x10];
5407         u8         uid[0x10];
5408
5409         u8         reserved_at_20[0x10];
5410         u8         op_mod[0x10];
5411
5412         u8         sq_state[0x4];
5413         u8         reserved_at_44[0x4];
5414         u8         sqn[0x18];
5415
5416         u8         reserved_at_60[0x20];
5417
5418         u8         modify_bitmask[0x40];
5419
5420         u8         reserved_at_c0[0x40];
5421
5422         struct mlx5_ifc_sqc_bits ctx;
5423 };
5424
5425 struct mlx5_ifc_modify_scheduling_element_out_bits {
5426         u8         status[0x8];
5427         u8         reserved_at_8[0x18];
5428
5429         u8         syndrome[0x20];
5430
5431         u8         reserved_at_40[0x1c0];
5432 };
5433
5434 enum {
5435         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5436         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5437 };
5438
5439 struct mlx5_ifc_modify_scheduling_element_in_bits {
5440         u8         opcode[0x10];
5441         u8         reserved_at_10[0x10];
5442
5443         u8         reserved_at_20[0x10];
5444         u8         op_mod[0x10];
5445
5446         u8         scheduling_hierarchy[0x8];
5447         u8         reserved_at_48[0x18];
5448
5449         u8         scheduling_element_id[0x20];
5450
5451         u8         reserved_at_80[0x20];
5452
5453         u8         modify_bitmask[0x20];
5454
5455         u8         reserved_at_c0[0x40];
5456
5457         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5458
5459         u8         reserved_at_300[0x100];
5460 };
5461
5462 struct mlx5_ifc_modify_rqt_out_bits {
5463         u8         status[0x8];
5464         u8         reserved_at_8[0x18];
5465
5466         u8         syndrome[0x20];
5467
5468         u8         reserved_at_40[0x40];
5469 };
5470
5471 struct mlx5_ifc_rqt_bitmask_bits {
5472         u8         reserved_at_0[0x20];
5473
5474         u8         reserved_at_20[0x1f];
5475         u8         rqn_list[0x1];
5476 };
5477
5478 struct mlx5_ifc_modify_rqt_in_bits {
5479         u8         opcode[0x10];
5480         u8         uid[0x10];
5481
5482         u8         reserved_at_20[0x10];
5483         u8         op_mod[0x10];
5484
5485         u8         reserved_at_40[0x8];
5486         u8         rqtn[0x18];
5487
5488         u8         reserved_at_60[0x20];
5489
5490         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5491
5492         u8         reserved_at_c0[0x40];
5493
5494         struct mlx5_ifc_rqtc_bits ctx;
5495 };
5496
5497 struct mlx5_ifc_modify_rq_out_bits {
5498         u8         status[0x8];
5499         u8         reserved_at_8[0x18];
5500
5501         u8         syndrome[0x20];
5502
5503         u8         reserved_at_40[0x40];
5504 };
5505
5506 enum {
5507         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5508         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5509         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5510 };
5511
5512 struct mlx5_ifc_modify_rq_in_bits {
5513         u8         opcode[0x10];
5514         u8         uid[0x10];
5515
5516         u8         reserved_at_20[0x10];
5517         u8         op_mod[0x10];
5518
5519         u8         rq_state[0x4];
5520         u8         reserved_at_44[0x4];
5521         u8         rqn[0x18];
5522
5523         u8         reserved_at_60[0x20];
5524
5525         u8         modify_bitmask[0x40];
5526
5527         u8         reserved_at_c0[0x40];
5528
5529         struct mlx5_ifc_rqc_bits ctx;
5530 };
5531
5532 struct mlx5_ifc_modify_rmp_out_bits {
5533         u8         status[0x8];
5534         u8         reserved_at_8[0x18];
5535
5536         u8         syndrome[0x20];
5537
5538         u8         reserved_at_40[0x40];
5539 };
5540
5541 struct mlx5_ifc_rmp_bitmask_bits {
5542         u8         reserved_at_0[0x20];
5543
5544         u8         reserved_at_20[0x1f];
5545         u8         lwm[0x1];
5546 };
5547
5548 struct mlx5_ifc_modify_rmp_in_bits {
5549         u8         opcode[0x10];
5550         u8         uid[0x10];
5551
5552         u8         reserved_at_20[0x10];
5553         u8         op_mod[0x10];
5554
5555         u8         rmp_state[0x4];
5556         u8         reserved_at_44[0x4];
5557         u8         rmpn[0x18];
5558
5559         u8         reserved_at_60[0x20];
5560
5561         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5562
5563         u8         reserved_at_c0[0x40];
5564
5565         struct mlx5_ifc_rmpc_bits ctx;
5566 };
5567
5568 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5569         u8         status[0x8];
5570         u8         reserved_at_8[0x18];
5571
5572         u8         syndrome[0x20];
5573
5574         u8         reserved_at_40[0x40];
5575 };
5576
5577 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5578         u8         reserved_at_0[0x12];
5579         u8         affiliation[0x1];
5580         u8         reserved_at_13[0x1];
5581         u8         disable_uc_local_lb[0x1];
5582         u8         disable_mc_local_lb[0x1];
5583         u8         node_guid[0x1];
5584         u8         port_guid[0x1];
5585         u8         min_inline[0x1];
5586         u8         mtu[0x1];
5587         u8         change_event[0x1];
5588         u8         promisc[0x1];
5589         u8         permanent_address[0x1];
5590         u8         addresses_list[0x1];
5591         u8         roce_en[0x1];
5592         u8         reserved_at_1f[0x1];
5593 };
5594
5595 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5596         u8         opcode[0x10];
5597         u8         reserved_at_10[0x10];
5598
5599         u8         reserved_at_20[0x10];
5600         u8         op_mod[0x10];
5601
5602         u8         other_vport[0x1];
5603         u8         reserved_at_41[0xf];
5604         u8         vport_number[0x10];
5605
5606         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5607
5608         u8         reserved_at_80[0x780];
5609
5610         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5611 };
5612
5613 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5614         u8         status[0x8];
5615         u8         reserved_at_8[0x18];
5616
5617         u8         syndrome[0x20];
5618
5619         u8         reserved_at_40[0x40];
5620 };
5621
5622 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5623         u8         opcode[0x10];
5624         u8         reserved_at_10[0x10];
5625
5626         u8         reserved_at_20[0x10];
5627         u8         op_mod[0x10];
5628
5629         u8         other_vport[0x1];
5630         u8         reserved_at_41[0xb];
5631         u8         port_num[0x4];
5632         u8         vport_number[0x10];
5633
5634         u8         reserved_at_60[0x20];
5635
5636         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5637 };
5638
5639 struct mlx5_ifc_modify_cq_out_bits {
5640         u8         status[0x8];
5641         u8         reserved_at_8[0x18];
5642
5643         u8         syndrome[0x20];
5644
5645         u8         reserved_at_40[0x40];
5646 };
5647
5648 enum {
5649         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5650         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5651 };
5652
5653 struct mlx5_ifc_modify_cq_in_bits {
5654         u8         opcode[0x10];
5655         u8         uid[0x10];
5656
5657         u8         reserved_at_20[0x10];
5658         u8         op_mod[0x10];
5659
5660         u8         reserved_at_40[0x8];
5661         u8         cqn[0x18];
5662
5663         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5664
5665         struct mlx5_ifc_cqc_bits cq_context;
5666
5667         u8         reserved_at_280[0x40];
5668
5669         u8         cq_umem_valid[0x1];
5670         u8         reserved_at_2c1[0x5bf];
5671
5672         u8         pas[0][0x40];
5673 };
5674
5675 struct mlx5_ifc_modify_cong_status_out_bits {
5676         u8         status[0x8];
5677         u8         reserved_at_8[0x18];
5678
5679         u8         syndrome[0x20];
5680
5681         u8         reserved_at_40[0x40];
5682 };
5683
5684 struct mlx5_ifc_modify_cong_status_in_bits {
5685         u8         opcode[0x10];
5686         u8         reserved_at_10[0x10];
5687
5688         u8         reserved_at_20[0x10];
5689         u8         op_mod[0x10];
5690
5691         u8         reserved_at_40[0x18];
5692         u8         priority[0x4];
5693         u8         cong_protocol[0x4];
5694
5695         u8         enable[0x1];
5696         u8         tag_enable[0x1];
5697         u8         reserved_at_62[0x1e];
5698 };
5699
5700 struct mlx5_ifc_modify_cong_params_out_bits {
5701         u8         status[0x8];
5702         u8         reserved_at_8[0x18];
5703
5704         u8         syndrome[0x20];
5705
5706         u8         reserved_at_40[0x40];
5707 };
5708
5709 struct mlx5_ifc_modify_cong_params_in_bits {
5710         u8         opcode[0x10];
5711         u8         reserved_at_10[0x10];
5712
5713         u8         reserved_at_20[0x10];
5714         u8         op_mod[0x10];
5715
5716         u8         reserved_at_40[0x1c];
5717         u8         cong_protocol[0x4];
5718
5719         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5720
5721         u8         reserved_at_80[0x80];
5722
5723         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5724 };
5725
5726 struct mlx5_ifc_manage_pages_out_bits {
5727         u8         status[0x8];
5728         u8         reserved_at_8[0x18];
5729
5730         u8         syndrome[0x20];
5731
5732         u8         output_num_entries[0x20];
5733
5734         u8         reserved_at_60[0x20];
5735
5736         u8         pas[0][0x40];
5737 };
5738
5739 enum {
5740         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5741         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5742         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5743 };
5744
5745 struct mlx5_ifc_manage_pages_in_bits {
5746         u8         opcode[0x10];
5747         u8         reserved_at_10[0x10];
5748
5749         u8         reserved_at_20[0x10];
5750         u8         op_mod[0x10];
5751
5752         u8         reserved_at_40[0x10];
5753         u8         function_id[0x10];
5754
5755         u8         input_num_entries[0x20];
5756
5757         u8         pas[0][0x40];
5758 };
5759
5760 struct mlx5_ifc_mad_ifc_out_bits {
5761         u8         status[0x8];
5762         u8         reserved_at_8[0x18];
5763
5764         u8         syndrome[0x20];
5765
5766         u8         reserved_at_40[0x40];
5767
5768         u8         response_mad_packet[256][0x8];
5769 };
5770
5771 struct mlx5_ifc_mad_ifc_in_bits {
5772         u8         opcode[0x10];
5773         u8         reserved_at_10[0x10];
5774
5775         u8         reserved_at_20[0x10];
5776         u8         op_mod[0x10];
5777
5778         u8         remote_lid[0x10];
5779         u8         reserved_at_50[0x8];
5780         u8         port[0x8];
5781
5782         u8         reserved_at_60[0x20];
5783
5784         u8         mad[256][0x8];
5785 };
5786
5787 struct mlx5_ifc_init_hca_out_bits {
5788         u8         status[0x8];
5789         u8         reserved_at_8[0x18];
5790
5791         u8         syndrome[0x20];
5792
5793         u8         reserved_at_40[0x40];
5794 };
5795
5796 struct mlx5_ifc_init_hca_in_bits {
5797         u8         opcode[0x10];
5798         u8         reserved_at_10[0x10];
5799
5800         u8         reserved_at_20[0x10];
5801         u8         op_mod[0x10];
5802
5803         u8         reserved_at_40[0x40];
5804         u8         sw_owner_id[4][0x20];
5805 };
5806
5807 struct mlx5_ifc_init2rtr_qp_out_bits {
5808         u8         status[0x8];
5809         u8         reserved_at_8[0x18];
5810
5811         u8         syndrome[0x20];
5812
5813         u8         reserved_at_40[0x40];
5814 };
5815
5816 struct mlx5_ifc_init2rtr_qp_in_bits {
5817         u8         opcode[0x10];
5818         u8         uid[0x10];
5819
5820         u8         reserved_at_20[0x10];
5821         u8         op_mod[0x10];
5822
5823         u8         reserved_at_40[0x8];
5824         u8         qpn[0x18];
5825
5826         u8         reserved_at_60[0x20];
5827
5828         u8         opt_param_mask[0x20];
5829
5830         u8         reserved_at_a0[0x20];
5831
5832         struct mlx5_ifc_qpc_bits qpc;
5833
5834         u8         reserved_at_800[0x80];
5835 };
5836
5837 struct mlx5_ifc_init2init_qp_out_bits {
5838         u8         status[0x8];
5839         u8         reserved_at_8[0x18];
5840
5841         u8         syndrome[0x20];
5842
5843         u8         reserved_at_40[0x40];
5844 };
5845
5846 struct mlx5_ifc_init2init_qp_in_bits {
5847         u8         opcode[0x10];
5848         u8         uid[0x10];
5849
5850         u8         reserved_at_20[0x10];
5851         u8         op_mod[0x10];
5852
5853         u8         reserved_at_40[0x8];
5854         u8         qpn[0x18];
5855
5856         u8         reserved_at_60[0x20];
5857
5858         u8         opt_param_mask[0x20];
5859
5860         u8         reserved_at_a0[0x20];
5861
5862         struct mlx5_ifc_qpc_bits qpc;
5863
5864         u8         reserved_at_800[0x80];
5865 };
5866
5867 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5868         u8         status[0x8];
5869         u8         reserved_at_8[0x18];
5870
5871         u8         syndrome[0x20];
5872
5873         u8         reserved_at_40[0x40];
5874
5875         u8         packet_headers_log[128][0x8];
5876
5877         u8         packet_syndrome[64][0x8];
5878 };
5879
5880 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5881         u8         opcode[0x10];
5882         u8         reserved_at_10[0x10];
5883
5884         u8         reserved_at_20[0x10];
5885         u8         op_mod[0x10];
5886
5887         u8         reserved_at_40[0x40];
5888 };
5889
5890 struct mlx5_ifc_gen_eqe_in_bits {
5891         u8         opcode[0x10];
5892         u8         reserved_at_10[0x10];
5893
5894         u8         reserved_at_20[0x10];
5895         u8         op_mod[0x10];
5896
5897         u8         reserved_at_40[0x18];
5898         u8         eq_number[0x8];
5899
5900         u8         reserved_at_60[0x20];
5901
5902         u8         eqe[64][0x8];
5903 };
5904
5905 struct mlx5_ifc_gen_eq_out_bits {
5906         u8         status[0x8];
5907         u8         reserved_at_8[0x18];
5908
5909         u8         syndrome[0x20];
5910
5911         u8         reserved_at_40[0x40];
5912 };
5913
5914 struct mlx5_ifc_enable_hca_out_bits {
5915         u8         status[0x8];
5916         u8         reserved_at_8[0x18];
5917
5918         u8         syndrome[0x20];
5919
5920         u8         reserved_at_40[0x20];
5921 };
5922
5923 struct mlx5_ifc_enable_hca_in_bits {
5924         u8         opcode[0x10];
5925         u8         reserved_at_10[0x10];
5926
5927         u8         reserved_at_20[0x10];
5928         u8         op_mod[0x10];
5929
5930         u8         reserved_at_40[0x10];
5931         u8         function_id[0x10];
5932
5933         u8         reserved_at_60[0x20];
5934 };
5935
5936 struct mlx5_ifc_drain_dct_out_bits {
5937         u8         status[0x8];
5938         u8         reserved_at_8[0x18];
5939
5940         u8         syndrome[0x20];
5941
5942         u8         reserved_at_40[0x40];
5943 };
5944
5945 struct mlx5_ifc_drain_dct_in_bits {
5946         u8         opcode[0x10];
5947         u8         uid[0x10];
5948
5949         u8         reserved_at_20[0x10];
5950         u8         op_mod[0x10];
5951
5952         u8         reserved_at_40[0x8];
5953         u8         dctn[0x18];
5954
5955         u8         reserved_at_60[0x20];
5956 };
5957
5958 struct mlx5_ifc_disable_hca_out_bits {
5959         u8         status[0x8];
5960         u8         reserved_at_8[0x18];
5961
5962         u8         syndrome[0x20];
5963
5964         u8         reserved_at_40[0x20];
5965 };
5966
5967 struct mlx5_ifc_disable_hca_in_bits {
5968         u8         opcode[0x10];
5969         u8         reserved_at_10[0x10];
5970
5971         u8         reserved_at_20[0x10];
5972         u8         op_mod[0x10];
5973
5974         u8         reserved_at_40[0x10];
5975         u8         function_id[0x10];
5976
5977         u8         reserved_at_60[0x20];
5978 };
5979
5980 struct mlx5_ifc_detach_from_mcg_out_bits {
5981         u8         status[0x8];
5982         u8         reserved_at_8[0x18];
5983
5984         u8         syndrome[0x20];
5985
5986         u8         reserved_at_40[0x40];
5987 };
5988
5989 struct mlx5_ifc_detach_from_mcg_in_bits {
5990         u8         opcode[0x10];
5991         u8         uid[0x10];
5992
5993         u8         reserved_at_20[0x10];
5994         u8         op_mod[0x10];
5995
5996         u8         reserved_at_40[0x8];
5997         u8         qpn[0x18];
5998
5999         u8         reserved_at_60[0x20];
6000
6001         u8         multicast_gid[16][0x8];
6002 };
6003
6004 struct mlx5_ifc_destroy_xrq_out_bits {
6005         u8         status[0x8];
6006         u8         reserved_at_8[0x18];
6007
6008         u8         syndrome[0x20];
6009
6010         u8         reserved_at_40[0x40];
6011 };
6012
6013 struct mlx5_ifc_destroy_xrq_in_bits {
6014         u8         opcode[0x10];
6015         u8         uid[0x10];
6016
6017         u8         reserved_at_20[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_at_40[0x8];
6021         u8         xrqn[0x18];
6022
6023         u8         reserved_at_60[0x20];
6024 };
6025
6026 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6027         u8         status[0x8];
6028         u8         reserved_at_8[0x18];
6029
6030         u8         syndrome[0x20];
6031
6032         u8         reserved_at_40[0x40];
6033 };
6034
6035 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6036         u8         opcode[0x10];
6037         u8         uid[0x10];
6038
6039         u8         reserved_at_20[0x10];
6040         u8         op_mod[0x10];
6041
6042         u8         reserved_at_40[0x8];
6043         u8         xrc_srqn[0x18];
6044
6045         u8         reserved_at_60[0x20];
6046 };
6047
6048 struct mlx5_ifc_destroy_tis_out_bits {
6049         u8         status[0x8];
6050         u8         reserved_at_8[0x18];
6051
6052         u8         syndrome[0x20];
6053
6054         u8         reserved_at_40[0x40];
6055 };
6056
6057 struct mlx5_ifc_destroy_tis_in_bits {
6058         u8         opcode[0x10];
6059         u8         uid[0x10];
6060
6061         u8         reserved_at_20[0x10];
6062         u8         op_mod[0x10];
6063
6064         u8         reserved_at_40[0x8];
6065         u8         tisn[0x18];
6066
6067         u8         reserved_at_60[0x20];
6068 };
6069
6070 struct mlx5_ifc_destroy_tir_out_bits {
6071         u8         status[0x8];
6072         u8         reserved_at_8[0x18];
6073
6074         u8         syndrome[0x20];
6075
6076         u8         reserved_at_40[0x40];
6077 };
6078
6079 struct mlx5_ifc_destroy_tir_in_bits {
6080         u8         opcode[0x10];
6081         u8         uid[0x10];
6082
6083         u8         reserved_at_20[0x10];
6084         u8         op_mod[0x10];
6085
6086         u8         reserved_at_40[0x8];
6087         u8         tirn[0x18];
6088
6089         u8         reserved_at_60[0x20];
6090 };
6091
6092 struct mlx5_ifc_destroy_srq_out_bits {
6093         u8         status[0x8];
6094         u8         reserved_at_8[0x18];
6095
6096         u8         syndrome[0x20];
6097
6098         u8         reserved_at_40[0x40];
6099 };
6100
6101 struct mlx5_ifc_destroy_srq_in_bits {
6102         u8         opcode[0x10];
6103         u8         uid[0x10];
6104
6105         u8         reserved_at_20[0x10];
6106         u8         op_mod[0x10];
6107
6108         u8         reserved_at_40[0x8];
6109         u8         srqn[0x18];
6110
6111         u8         reserved_at_60[0x20];
6112 };
6113
6114 struct mlx5_ifc_destroy_sq_out_bits {
6115         u8         status[0x8];
6116         u8         reserved_at_8[0x18];
6117
6118         u8         syndrome[0x20];
6119
6120         u8         reserved_at_40[0x40];
6121 };
6122
6123 struct mlx5_ifc_destroy_sq_in_bits {
6124         u8         opcode[0x10];
6125         u8         uid[0x10];
6126
6127         u8         reserved_at_20[0x10];
6128         u8         op_mod[0x10];
6129
6130         u8         reserved_at_40[0x8];
6131         u8         sqn[0x18];
6132
6133         u8         reserved_at_60[0x20];
6134 };
6135
6136 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6137         u8         status[0x8];
6138         u8         reserved_at_8[0x18];
6139
6140         u8         syndrome[0x20];
6141
6142         u8         reserved_at_40[0x1c0];
6143 };
6144
6145 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6146         u8         opcode[0x10];
6147         u8         reserved_at_10[0x10];
6148
6149         u8         reserved_at_20[0x10];
6150         u8         op_mod[0x10];
6151
6152         u8         scheduling_hierarchy[0x8];
6153         u8         reserved_at_48[0x18];
6154
6155         u8         scheduling_element_id[0x20];
6156
6157         u8         reserved_at_80[0x180];
6158 };
6159
6160 struct mlx5_ifc_destroy_rqt_out_bits {
6161         u8         status[0x8];
6162         u8         reserved_at_8[0x18];
6163
6164         u8         syndrome[0x20];
6165
6166         u8         reserved_at_40[0x40];
6167 };
6168
6169 struct mlx5_ifc_destroy_rqt_in_bits {
6170         u8         opcode[0x10];
6171         u8         uid[0x10];
6172
6173         u8         reserved_at_20[0x10];
6174         u8         op_mod[0x10];
6175
6176         u8         reserved_at_40[0x8];
6177         u8         rqtn[0x18];
6178
6179         u8         reserved_at_60[0x20];
6180 };
6181
6182 struct mlx5_ifc_destroy_rq_out_bits {
6183         u8         status[0x8];
6184         u8         reserved_at_8[0x18];
6185
6186         u8         syndrome[0x20];
6187
6188         u8         reserved_at_40[0x40];
6189 };
6190
6191 struct mlx5_ifc_destroy_rq_in_bits {
6192         u8         opcode[0x10];
6193         u8         uid[0x10];
6194
6195         u8         reserved_at_20[0x10];
6196         u8         op_mod[0x10];
6197
6198         u8         reserved_at_40[0x8];
6199         u8         rqn[0x18];
6200
6201         u8         reserved_at_60[0x20];
6202 };
6203
6204 struct mlx5_ifc_set_delay_drop_params_in_bits {
6205         u8         opcode[0x10];
6206         u8         reserved_at_10[0x10];
6207
6208         u8         reserved_at_20[0x10];
6209         u8         op_mod[0x10];
6210
6211         u8         reserved_at_40[0x20];
6212
6213         u8         reserved_at_60[0x10];
6214         u8         delay_drop_timeout[0x10];
6215 };
6216
6217 struct mlx5_ifc_set_delay_drop_params_out_bits {
6218         u8         status[0x8];
6219         u8         reserved_at_8[0x18];
6220
6221         u8         syndrome[0x20];
6222
6223         u8         reserved_at_40[0x40];
6224 };
6225
6226 struct mlx5_ifc_destroy_rmp_out_bits {
6227         u8         status[0x8];
6228         u8         reserved_at_8[0x18];
6229
6230         u8         syndrome[0x20];
6231
6232         u8         reserved_at_40[0x40];
6233 };
6234
6235 struct mlx5_ifc_destroy_rmp_in_bits {
6236         u8         opcode[0x10];
6237         u8         uid[0x10];
6238
6239         u8         reserved_at_20[0x10];
6240         u8         op_mod[0x10];
6241
6242         u8         reserved_at_40[0x8];
6243         u8         rmpn[0x18];
6244
6245         u8         reserved_at_60[0x20];
6246 };
6247
6248 struct mlx5_ifc_destroy_qp_out_bits {
6249         u8         status[0x8];
6250         u8         reserved_at_8[0x18];
6251
6252         u8         syndrome[0x20];
6253
6254         u8         reserved_at_40[0x40];
6255 };
6256
6257 struct mlx5_ifc_destroy_qp_in_bits {
6258         u8         opcode[0x10];
6259         u8         uid[0x10];
6260
6261         u8         reserved_at_20[0x10];
6262         u8         op_mod[0x10];
6263
6264         u8         reserved_at_40[0x8];
6265         u8         qpn[0x18];
6266
6267         u8         reserved_at_60[0x20];
6268 };
6269
6270 struct mlx5_ifc_destroy_psv_out_bits {
6271         u8         status[0x8];
6272         u8         reserved_at_8[0x18];
6273
6274         u8         syndrome[0x20];
6275
6276         u8         reserved_at_40[0x40];
6277 };
6278
6279 struct mlx5_ifc_destroy_psv_in_bits {
6280         u8         opcode[0x10];
6281         u8         reserved_at_10[0x10];
6282
6283         u8         reserved_at_20[0x10];
6284         u8         op_mod[0x10];
6285
6286         u8         reserved_at_40[0x8];
6287         u8         psvn[0x18];
6288
6289         u8         reserved_at_60[0x20];
6290 };
6291
6292 struct mlx5_ifc_destroy_mkey_out_bits {
6293         u8         status[0x8];
6294         u8         reserved_at_8[0x18];
6295
6296         u8         syndrome[0x20];
6297
6298         u8         reserved_at_40[0x40];
6299 };
6300
6301 struct mlx5_ifc_destroy_mkey_in_bits {
6302         u8         opcode[0x10];
6303         u8         reserved_at_10[0x10];
6304
6305         u8         reserved_at_20[0x10];
6306         u8         op_mod[0x10];
6307
6308         u8         reserved_at_40[0x8];
6309         u8         mkey_index[0x18];
6310
6311         u8         reserved_at_60[0x20];
6312 };
6313
6314 struct mlx5_ifc_destroy_flow_table_out_bits {
6315         u8         status[0x8];
6316         u8         reserved_at_8[0x18];
6317
6318         u8         syndrome[0x20];
6319
6320         u8         reserved_at_40[0x40];
6321 };
6322
6323 struct mlx5_ifc_destroy_flow_table_in_bits {
6324         u8         opcode[0x10];
6325         u8         reserved_at_10[0x10];
6326
6327         u8         reserved_at_20[0x10];
6328         u8         op_mod[0x10];
6329
6330         u8         other_vport[0x1];
6331         u8         reserved_at_41[0xf];
6332         u8         vport_number[0x10];
6333
6334         u8         reserved_at_60[0x20];
6335
6336         u8         table_type[0x8];
6337         u8         reserved_at_88[0x18];
6338
6339         u8         reserved_at_a0[0x8];
6340         u8         table_id[0x18];
6341
6342         u8         reserved_at_c0[0x140];
6343 };
6344
6345 struct mlx5_ifc_destroy_flow_group_out_bits {
6346         u8         status[0x8];
6347         u8         reserved_at_8[0x18];
6348
6349         u8         syndrome[0x20];
6350
6351         u8         reserved_at_40[0x40];
6352 };
6353
6354 struct mlx5_ifc_destroy_flow_group_in_bits {
6355         u8         opcode[0x10];
6356         u8         reserved_at_10[0x10];
6357
6358         u8         reserved_at_20[0x10];
6359         u8         op_mod[0x10];
6360
6361         u8         other_vport[0x1];
6362         u8         reserved_at_41[0xf];
6363         u8         vport_number[0x10];
6364
6365         u8         reserved_at_60[0x20];
6366
6367         u8         table_type[0x8];
6368         u8         reserved_at_88[0x18];
6369
6370         u8         reserved_at_a0[0x8];
6371         u8         table_id[0x18];
6372
6373         u8         group_id[0x20];
6374
6375         u8         reserved_at_e0[0x120];
6376 };
6377
6378 struct mlx5_ifc_destroy_eq_out_bits {
6379         u8         status[0x8];
6380         u8         reserved_at_8[0x18];
6381
6382         u8         syndrome[0x20];
6383
6384         u8         reserved_at_40[0x40];
6385 };
6386
6387 struct mlx5_ifc_destroy_eq_in_bits {
6388         u8         opcode[0x10];
6389         u8         reserved_at_10[0x10];
6390
6391         u8         reserved_at_20[0x10];
6392         u8         op_mod[0x10];
6393
6394         u8         reserved_at_40[0x18];
6395         u8         eq_number[0x8];
6396
6397         u8         reserved_at_60[0x20];
6398 };
6399
6400 struct mlx5_ifc_destroy_dct_out_bits {
6401         u8         status[0x8];
6402         u8         reserved_at_8[0x18];
6403
6404         u8         syndrome[0x20];
6405
6406         u8         reserved_at_40[0x40];
6407 };
6408
6409 struct mlx5_ifc_destroy_dct_in_bits {
6410         u8         opcode[0x10];
6411         u8         uid[0x10];
6412
6413         u8         reserved_at_20[0x10];
6414         u8         op_mod[0x10];
6415
6416         u8         reserved_at_40[0x8];
6417         u8         dctn[0x18];
6418
6419         u8         reserved_at_60[0x20];
6420 };
6421
6422 struct mlx5_ifc_destroy_cq_out_bits {
6423         u8         status[0x8];
6424         u8         reserved_at_8[0x18];
6425
6426         u8         syndrome[0x20];
6427
6428         u8         reserved_at_40[0x40];
6429 };
6430
6431 struct mlx5_ifc_destroy_cq_in_bits {
6432         u8         opcode[0x10];
6433         u8         uid[0x10];
6434
6435         u8         reserved_at_20[0x10];
6436         u8         op_mod[0x10];
6437
6438         u8         reserved_at_40[0x8];
6439         u8         cqn[0x18];
6440
6441         u8         reserved_at_60[0x20];
6442 };
6443
6444 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6445         u8         status[0x8];
6446         u8         reserved_at_8[0x18];
6447
6448         u8         syndrome[0x20];
6449
6450         u8         reserved_at_40[0x40];
6451 };
6452
6453 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6454         u8         opcode[0x10];
6455         u8         reserved_at_10[0x10];
6456
6457         u8         reserved_at_20[0x10];
6458         u8         op_mod[0x10];
6459
6460         u8         reserved_at_40[0x20];
6461
6462         u8         reserved_at_60[0x10];
6463         u8         vxlan_udp_port[0x10];
6464 };
6465
6466 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6467         u8         status[0x8];
6468         u8         reserved_at_8[0x18];
6469
6470         u8         syndrome[0x20];
6471
6472         u8         reserved_at_40[0x40];
6473 };
6474
6475 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6476         u8         opcode[0x10];
6477         u8         reserved_at_10[0x10];
6478
6479         u8         reserved_at_20[0x10];
6480         u8         op_mod[0x10];
6481
6482         u8         reserved_at_40[0x60];
6483
6484         u8         reserved_at_a0[0x8];
6485         u8         table_index[0x18];
6486
6487         u8         reserved_at_c0[0x140];
6488 };
6489
6490 struct mlx5_ifc_delete_fte_out_bits {
6491         u8         status[0x8];
6492         u8         reserved_at_8[0x18];
6493
6494         u8         syndrome[0x20];
6495
6496         u8         reserved_at_40[0x40];
6497 };
6498
6499 struct mlx5_ifc_delete_fte_in_bits {
6500         u8         opcode[0x10];
6501         u8         reserved_at_10[0x10];
6502
6503         u8         reserved_at_20[0x10];
6504         u8         op_mod[0x10];
6505
6506         u8         other_vport[0x1];
6507         u8         reserved_at_41[0xf];
6508         u8         vport_number[0x10];
6509
6510         u8         reserved_at_60[0x20];
6511
6512         u8         table_type[0x8];
6513         u8         reserved_at_88[0x18];
6514
6515         u8         reserved_at_a0[0x8];
6516         u8         table_id[0x18];
6517
6518         u8         reserved_at_c0[0x40];
6519
6520         u8         flow_index[0x20];
6521
6522         u8         reserved_at_120[0xe0];
6523 };
6524
6525 struct mlx5_ifc_dealloc_xrcd_out_bits {
6526         u8         status[0x8];
6527         u8         reserved_at_8[0x18];
6528
6529         u8         syndrome[0x20];
6530
6531         u8         reserved_at_40[0x40];
6532 };
6533
6534 struct mlx5_ifc_dealloc_xrcd_in_bits {
6535         u8         opcode[0x10];
6536         u8         uid[0x10];
6537
6538         u8         reserved_at_20[0x10];
6539         u8         op_mod[0x10];
6540
6541         u8         reserved_at_40[0x8];
6542         u8         xrcd[0x18];
6543
6544         u8         reserved_at_60[0x20];
6545 };
6546
6547 struct mlx5_ifc_dealloc_uar_out_bits {
6548         u8         status[0x8];
6549         u8         reserved_at_8[0x18];
6550
6551         u8         syndrome[0x20];
6552
6553         u8         reserved_at_40[0x40];
6554 };
6555
6556 struct mlx5_ifc_dealloc_uar_in_bits {
6557         u8         opcode[0x10];
6558         u8         reserved_at_10[0x10];
6559
6560         u8         reserved_at_20[0x10];
6561         u8         op_mod[0x10];
6562
6563         u8         reserved_at_40[0x8];
6564         u8         uar[0x18];
6565
6566         u8         reserved_at_60[0x20];
6567 };
6568
6569 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6570         u8         status[0x8];
6571         u8         reserved_at_8[0x18];
6572
6573         u8         syndrome[0x20];
6574
6575         u8         reserved_at_40[0x40];
6576 };
6577
6578 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6579         u8         opcode[0x10];
6580         u8         reserved_at_10[0x10];
6581
6582         u8         reserved_at_20[0x10];
6583         u8         op_mod[0x10];
6584
6585         u8         reserved_at_40[0x8];
6586         u8         transport_domain[0x18];
6587
6588         u8         reserved_at_60[0x20];
6589 };
6590
6591 struct mlx5_ifc_dealloc_q_counter_out_bits {
6592         u8         status[0x8];
6593         u8         reserved_at_8[0x18];
6594
6595         u8         syndrome[0x20];
6596
6597         u8         reserved_at_40[0x40];
6598 };
6599
6600 struct mlx5_ifc_dealloc_q_counter_in_bits {
6601         u8         opcode[0x10];
6602         u8         reserved_at_10[0x10];
6603
6604         u8         reserved_at_20[0x10];
6605         u8         op_mod[0x10];
6606
6607         u8         reserved_at_40[0x18];
6608         u8         counter_set_id[0x8];
6609
6610         u8         reserved_at_60[0x20];
6611 };
6612
6613 struct mlx5_ifc_dealloc_pd_out_bits {
6614         u8         status[0x8];
6615         u8         reserved_at_8[0x18];
6616
6617         u8         syndrome[0x20];
6618
6619         u8         reserved_at_40[0x40];
6620 };
6621
6622 struct mlx5_ifc_dealloc_pd_in_bits {
6623         u8         opcode[0x10];
6624         u8         uid[0x10];
6625
6626         u8         reserved_at_20[0x10];
6627         u8         op_mod[0x10];
6628
6629         u8         reserved_at_40[0x8];
6630         u8         pd[0x18];
6631
6632         u8         reserved_at_60[0x20];
6633 };
6634
6635 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6636         u8         status[0x8];
6637         u8         reserved_at_8[0x18];
6638
6639         u8         syndrome[0x20];
6640
6641         u8         reserved_at_40[0x40];
6642 };
6643
6644 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6645         u8         opcode[0x10];
6646         u8         reserved_at_10[0x10];
6647
6648         u8         reserved_at_20[0x10];
6649         u8         op_mod[0x10];
6650
6651         u8         flow_counter_id[0x20];
6652
6653         u8         reserved_at_60[0x20];
6654 };
6655
6656 struct mlx5_ifc_create_xrq_out_bits {
6657         u8         status[0x8];
6658         u8         reserved_at_8[0x18];
6659
6660         u8         syndrome[0x20];
6661
6662         u8         reserved_at_40[0x8];
6663         u8         xrqn[0x18];
6664
6665         u8         reserved_at_60[0x20];
6666 };
6667
6668 struct mlx5_ifc_create_xrq_in_bits {
6669         u8         opcode[0x10];
6670         u8         uid[0x10];
6671
6672         u8         reserved_at_20[0x10];
6673         u8         op_mod[0x10];
6674
6675         u8         reserved_at_40[0x40];
6676
6677         struct mlx5_ifc_xrqc_bits xrq_context;
6678 };
6679
6680 struct mlx5_ifc_create_xrc_srq_out_bits {
6681         u8         status[0x8];
6682         u8         reserved_at_8[0x18];
6683
6684         u8         syndrome[0x20];
6685
6686         u8         reserved_at_40[0x8];
6687         u8         xrc_srqn[0x18];
6688
6689         u8         reserved_at_60[0x20];
6690 };
6691
6692 struct mlx5_ifc_create_xrc_srq_in_bits {
6693         u8         opcode[0x10];
6694         u8         uid[0x10];
6695
6696         u8         reserved_at_20[0x10];
6697         u8         op_mod[0x10];
6698
6699         u8         reserved_at_40[0x40];
6700
6701         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6702
6703         u8         reserved_at_280[0x60];
6704
6705         u8         xrc_srq_umem_valid[0x1];
6706         u8         reserved_at_2e1[0x1f];
6707
6708         u8         reserved_at_300[0x580];
6709
6710         u8         pas[0][0x40];
6711 };
6712
6713 struct mlx5_ifc_create_tis_out_bits {
6714         u8         status[0x8];
6715         u8         reserved_at_8[0x18];
6716
6717         u8         syndrome[0x20];
6718
6719         u8         reserved_at_40[0x8];
6720         u8         tisn[0x18];
6721
6722         u8         reserved_at_60[0x20];
6723 };
6724
6725 struct mlx5_ifc_create_tis_in_bits {
6726         u8         opcode[0x10];
6727         u8         uid[0x10];
6728
6729         u8         reserved_at_20[0x10];
6730         u8         op_mod[0x10];
6731
6732         u8         reserved_at_40[0xc0];
6733
6734         struct mlx5_ifc_tisc_bits ctx;
6735 };
6736
6737 struct mlx5_ifc_create_tir_out_bits {
6738         u8         status[0x8];
6739         u8         reserved_at_8[0x18];
6740
6741         u8         syndrome[0x20];
6742
6743         u8         reserved_at_40[0x8];
6744         u8         tirn[0x18];
6745
6746         u8         reserved_at_60[0x20];
6747 };
6748
6749 struct mlx5_ifc_create_tir_in_bits {
6750         u8         opcode[0x10];
6751         u8         uid[0x10];
6752
6753         u8         reserved_at_20[0x10];
6754         u8         op_mod[0x10];
6755
6756         u8         reserved_at_40[0xc0];
6757
6758         struct mlx5_ifc_tirc_bits ctx;
6759 };
6760
6761 struct mlx5_ifc_create_srq_out_bits {
6762         u8         status[0x8];
6763         u8         reserved_at_8[0x18];
6764
6765         u8         syndrome[0x20];
6766
6767         u8         reserved_at_40[0x8];
6768         u8         srqn[0x18];
6769
6770         u8         reserved_at_60[0x20];
6771 };
6772
6773 struct mlx5_ifc_create_srq_in_bits {
6774         u8         opcode[0x10];
6775         u8         uid[0x10];
6776
6777         u8         reserved_at_20[0x10];
6778         u8         op_mod[0x10];
6779
6780         u8         reserved_at_40[0x40];
6781
6782         struct mlx5_ifc_srqc_bits srq_context_entry;
6783
6784         u8         reserved_at_280[0x600];
6785
6786         u8         pas[0][0x40];
6787 };
6788
6789 struct mlx5_ifc_create_sq_out_bits {
6790         u8         status[0x8];
6791         u8         reserved_at_8[0x18];
6792
6793         u8         syndrome[0x20];
6794
6795         u8         reserved_at_40[0x8];
6796         u8         sqn[0x18];
6797
6798         u8         reserved_at_60[0x20];
6799 };
6800
6801 struct mlx5_ifc_create_sq_in_bits {
6802         u8         opcode[0x10];
6803         u8         uid[0x10];
6804
6805         u8         reserved_at_20[0x10];
6806         u8         op_mod[0x10];
6807
6808         u8         reserved_at_40[0xc0];
6809
6810         struct mlx5_ifc_sqc_bits ctx;
6811 };
6812
6813 struct mlx5_ifc_create_scheduling_element_out_bits {
6814         u8         status[0x8];
6815         u8         reserved_at_8[0x18];
6816
6817         u8         syndrome[0x20];
6818
6819         u8         reserved_at_40[0x40];
6820
6821         u8         scheduling_element_id[0x20];
6822
6823         u8         reserved_at_a0[0x160];
6824 };
6825
6826 struct mlx5_ifc_create_scheduling_element_in_bits {
6827         u8         opcode[0x10];
6828         u8         reserved_at_10[0x10];
6829
6830         u8         reserved_at_20[0x10];
6831         u8         op_mod[0x10];
6832
6833         u8         scheduling_hierarchy[0x8];
6834         u8         reserved_at_48[0x18];
6835
6836         u8         reserved_at_60[0xa0];
6837
6838         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6839
6840         u8         reserved_at_300[0x100];
6841 };
6842
6843 struct mlx5_ifc_create_rqt_out_bits {
6844         u8         status[0x8];
6845         u8         reserved_at_8[0x18];
6846
6847         u8         syndrome[0x20];
6848
6849         u8         reserved_at_40[0x8];
6850         u8         rqtn[0x18];
6851
6852         u8         reserved_at_60[0x20];
6853 };
6854
6855 struct mlx5_ifc_create_rqt_in_bits {
6856         u8         opcode[0x10];
6857         u8         uid[0x10];
6858
6859         u8         reserved_at_20[0x10];
6860         u8         op_mod[0x10];
6861
6862         u8         reserved_at_40[0xc0];
6863
6864         struct mlx5_ifc_rqtc_bits rqt_context;
6865 };
6866
6867 struct mlx5_ifc_create_rq_out_bits {
6868         u8         status[0x8];
6869         u8         reserved_at_8[0x18];
6870
6871         u8         syndrome[0x20];
6872
6873         u8         reserved_at_40[0x8];
6874         u8         rqn[0x18];
6875
6876         u8         reserved_at_60[0x20];
6877 };
6878
6879 struct mlx5_ifc_create_rq_in_bits {
6880         u8         opcode[0x10];
6881         u8         uid[0x10];
6882
6883         u8         reserved_at_20[0x10];
6884         u8         op_mod[0x10];
6885
6886         u8         reserved_at_40[0xc0];
6887
6888         struct mlx5_ifc_rqc_bits ctx;
6889 };
6890
6891 struct mlx5_ifc_create_rmp_out_bits {
6892         u8         status[0x8];
6893         u8         reserved_at_8[0x18];
6894
6895         u8         syndrome[0x20];
6896
6897         u8         reserved_at_40[0x8];
6898         u8         rmpn[0x18];
6899
6900         u8         reserved_at_60[0x20];
6901 };
6902
6903 struct mlx5_ifc_create_rmp_in_bits {
6904         u8         opcode[0x10];
6905         u8         uid[0x10];
6906
6907         u8         reserved_at_20[0x10];
6908         u8         op_mod[0x10];
6909
6910         u8         reserved_at_40[0xc0];
6911
6912         struct mlx5_ifc_rmpc_bits ctx;
6913 };
6914
6915 struct mlx5_ifc_create_qp_out_bits {
6916         u8         status[0x8];
6917         u8         reserved_at_8[0x18];
6918
6919         u8         syndrome[0x20];
6920
6921         u8         reserved_at_40[0x8];
6922         u8         qpn[0x18];
6923
6924         u8         reserved_at_60[0x20];
6925 };
6926
6927 struct mlx5_ifc_create_qp_in_bits {
6928         u8         opcode[0x10];
6929         u8         uid[0x10];
6930
6931         u8         reserved_at_20[0x10];
6932         u8         op_mod[0x10];
6933
6934         u8         reserved_at_40[0x40];
6935
6936         u8         opt_param_mask[0x20];
6937
6938         u8         reserved_at_a0[0x20];
6939
6940         struct mlx5_ifc_qpc_bits qpc;
6941
6942         u8         reserved_at_800[0x60];
6943
6944         u8         wq_umem_valid[0x1];
6945         u8         reserved_at_861[0x1f];
6946
6947         u8         pas[0][0x40];
6948 };
6949
6950 struct mlx5_ifc_create_psv_out_bits {
6951         u8         status[0x8];
6952         u8         reserved_at_8[0x18];
6953
6954         u8         syndrome[0x20];
6955
6956         u8         reserved_at_40[0x40];
6957
6958         u8         reserved_at_80[0x8];
6959         u8         psv0_index[0x18];
6960
6961         u8         reserved_at_a0[0x8];
6962         u8         psv1_index[0x18];
6963
6964         u8         reserved_at_c0[0x8];
6965         u8         psv2_index[0x18];
6966
6967         u8         reserved_at_e0[0x8];
6968         u8         psv3_index[0x18];
6969 };
6970
6971 struct mlx5_ifc_create_psv_in_bits {
6972         u8         opcode[0x10];
6973         u8         reserved_at_10[0x10];
6974
6975         u8         reserved_at_20[0x10];
6976         u8         op_mod[0x10];
6977
6978         u8         num_psv[0x4];
6979         u8         reserved_at_44[0x4];
6980         u8         pd[0x18];
6981
6982         u8         reserved_at_60[0x20];
6983 };
6984
6985 struct mlx5_ifc_create_mkey_out_bits {
6986         u8         status[0x8];
6987         u8         reserved_at_8[0x18];
6988
6989         u8         syndrome[0x20];
6990
6991         u8         reserved_at_40[0x8];
6992         u8         mkey_index[0x18];
6993
6994         u8         reserved_at_60[0x20];
6995 };
6996
6997 struct mlx5_ifc_create_mkey_in_bits {
6998         u8         opcode[0x10];
6999         u8         reserved_at_10[0x10];
7000
7001         u8         reserved_at_20[0x10];
7002         u8         op_mod[0x10];
7003
7004         u8         reserved_at_40[0x20];
7005
7006         u8         pg_access[0x1];
7007         u8         mkey_umem_valid[0x1];
7008         u8         reserved_at_62[0x1e];
7009
7010         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7011
7012         u8         reserved_at_280[0x80];
7013
7014         u8         translations_octword_actual_size[0x20];
7015
7016         u8         reserved_at_320[0x560];
7017
7018         u8         klm_pas_mtt[0][0x20];
7019 };
7020
7021 struct mlx5_ifc_create_flow_table_out_bits {
7022         u8         status[0x8];
7023         u8         reserved_at_8[0x18];
7024
7025         u8         syndrome[0x20];
7026
7027         u8         reserved_at_40[0x8];
7028         u8         table_id[0x18];
7029
7030         u8         reserved_at_60[0x20];
7031 };
7032
7033 struct mlx5_ifc_flow_table_context_bits {
7034         u8         reformat_en[0x1];
7035         u8         decap_en[0x1];
7036         u8         reserved_at_2[0x2];
7037         u8         table_miss_action[0x4];
7038         u8         level[0x8];
7039         u8         reserved_at_10[0x8];
7040         u8         log_size[0x8];
7041
7042         u8         reserved_at_20[0x8];
7043         u8         table_miss_id[0x18];
7044
7045         u8         reserved_at_40[0x8];
7046         u8         lag_master_next_table_id[0x18];
7047
7048         u8         reserved_at_60[0xe0];
7049 };
7050
7051 struct mlx5_ifc_create_flow_table_in_bits {
7052         u8         opcode[0x10];
7053         u8         reserved_at_10[0x10];
7054
7055         u8         reserved_at_20[0x10];
7056         u8         op_mod[0x10];
7057
7058         u8         other_vport[0x1];
7059         u8         reserved_at_41[0xf];
7060         u8         vport_number[0x10];
7061
7062         u8         reserved_at_60[0x20];
7063
7064         u8         table_type[0x8];
7065         u8         reserved_at_88[0x18];
7066
7067         u8         reserved_at_a0[0x20];
7068
7069         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7070 };
7071
7072 struct mlx5_ifc_create_flow_group_out_bits {
7073         u8         status[0x8];
7074         u8         reserved_at_8[0x18];
7075
7076         u8         syndrome[0x20];
7077
7078         u8         reserved_at_40[0x8];
7079         u8         group_id[0x18];
7080
7081         u8         reserved_at_60[0x20];
7082 };
7083
7084 enum {
7085         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7086         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7087         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7088         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7089 };
7090
7091 struct mlx5_ifc_create_flow_group_in_bits {
7092         u8         opcode[0x10];
7093         u8         reserved_at_10[0x10];
7094
7095         u8         reserved_at_20[0x10];
7096         u8         op_mod[0x10];
7097
7098         u8         other_vport[0x1];
7099         u8         reserved_at_41[0xf];
7100         u8         vport_number[0x10];
7101
7102         u8         reserved_at_60[0x20];
7103
7104         u8         table_type[0x8];
7105         u8         reserved_at_88[0x18];
7106
7107         u8         reserved_at_a0[0x8];
7108         u8         table_id[0x18];
7109
7110         u8         source_eswitch_owner_vhca_id_valid[0x1];
7111
7112         u8         reserved_at_c1[0x1f];
7113
7114         u8         start_flow_index[0x20];
7115
7116         u8         reserved_at_100[0x20];
7117
7118         u8         end_flow_index[0x20];
7119
7120         u8         reserved_at_140[0xa0];
7121
7122         u8         reserved_at_1e0[0x18];
7123         u8         match_criteria_enable[0x8];
7124
7125         struct mlx5_ifc_fte_match_param_bits match_criteria;
7126
7127         u8         reserved_at_1200[0xe00];
7128 };
7129
7130 struct mlx5_ifc_create_eq_out_bits {
7131         u8         status[0x8];
7132         u8         reserved_at_8[0x18];
7133
7134         u8         syndrome[0x20];
7135
7136         u8         reserved_at_40[0x18];
7137         u8         eq_number[0x8];
7138
7139         u8         reserved_at_60[0x20];
7140 };
7141
7142 struct mlx5_ifc_create_eq_in_bits {
7143         u8         opcode[0x10];
7144         u8         reserved_at_10[0x10];
7145
7146         u8         reserved_at_20[0x10];
7147         u8         op_mod[0x10];
7148
7149         u8         reserved_at_40[0x40];
7150
7151         struct mlx5_ifc_eqc_bits eq_context_entry;
7152
7153         u8         reserved_at_280[0x40];
7154
7155         u8         event_bitmask[0x40];
7156
7157         u8         reserved_at_300[0x580];
7158
7159         u8         pas[0][0x40];
7160 };
7161
7162 struct mlx5_ifc_create_dct_out_bits {
7163         u8         status[0x8];
7164         u8         reserved_at_8[0x18];
7165
7166         u8         syndrome[0x20];
7167
7168         u8         reserved_at_40[0x8];
7169         u8         dctn[0x18];
7170
7171         u8         reserved_at_60[0x20];
7172 };
7173
7174 struct mlx5_ifc_create_dct_in_bits {
7175         u8         opcode[0x10];
7176         u8         uid[0x10];
7177
7178         u8         reserved_at_20[0x10];
7179         u8         op_mod[0x10];
7180
7181         u8         reserved_at_40[0x40];
7182
7183         struct mlx5_ifc_dctc_bits dct_context_entry;
7184
7185         u8         reserved_at_280[0x180];
7186 };
7187
7188 struct mlx5_ifc_create_cq_out_bits {
7189         u8         status[0x8];
7190         u8         reserved_at_8[0x18];
7191
7192         u8         syndrome[0x20];
7193
7194         u8         reserved_at_40[0x8];
7195         u8         cqn[0x18];
7196
7197         u8         reserved_at_60[0x20];
7198 };
7199
7200 struct mlx5_ifc_create_cq_in_bits {
7201         u8         opcode[0x10];
7202         u8         uid[0x10];
7203
7204         u8         reserved_at_20[0x10];
7205         u8         op_mod[0x10];
7206
7207         u8         reserved_at_40[0x40];
7208
7209         struct mlx5_ifc_cqc_bits cq_context;
7210
7211         u8         reserved_at_280[0x60];
7212
7213         u8         cq_umem_valid[0x1];
7214         u8         reserved_at_2e1[0x59f];
7215
7216         u8         pas[0][0x40];
7217 };
7218
7219 struct mlx5_ifc_config_int_moderation_out_bits {
7220         u8         status[0x8];
7221         u8         reserved_at_8[0x18];
7222
7223         u8         syndrome[0x20];
7224
7225         u8         reserved_at_40[0x4];
7226         u8         min_delay[0xc];
7227         u8         int_vector[0x10];
7228
7229         u8         reserved_at_60[0x20];
7230 };
7231
7232 enum {
7233         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7234         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7235 };
7236
7237 struct mlx5_ifc_config_int_moderation_in_bits {
7238         u8         opcode[0x10];
7239         u8         reserved_at_10[0x10];
7240
7241         u8         reserved_at_20[0x10];
7242         u8         op_mod[0x10];
7243
7244         u8         reserved_at_40[0x4];
7245         u8         min_delay[0xc];
7246         u8         int_vector[0x10];
7247
7248         u8         reserved_at_60[0x20];
7249 };
7250
7251 struct mlx5_ifc_attach_to_mcg_out_bits {
7252         u8         status[0x8];
7253         u8         reserved_at_8[0x18];
7254
7255         u8         syndrome[0x20];
7256
7257         u8         reserved_at_40[0x40];
7258 };
7259
7260 struct mlx5_ifc_attach_to_mcg_in_bits {
7261         u8         opcode[0x10];
7262         u8         uid[0x10];
7263
7264         u8         reserved_at_20[0x10];
7265         u8         op_mod[0x10];
7266
7267         u8         reserved_at_40[0x8];
7268         u8         qpn[0x18];
7269
7270         u8         reserved_at_60[0x20];
7271
7272         u8         multicast_gid[16][0x8];
7273 };
7274
7275 struct mlx5_ifc_arm_xrq_out_bits {
7276         u8         status[0x8];
7277         u8         reserved_at_8[0x18];
7278
7279         u8         syndrome[0x20];
7280
7281         u8         reserved_at_40[0x40];
7282 };
7283
7284 struct mlx5_ifc_arm_xrq_in_bits {
7285         u8         opcode[0x10];
7286         u8         reserved_at_10[0x10];
7287
7288         u8         reserved_at_20[0x10];
7289         u8         op_mod[0x10];
7290
7291         u8         reserved_at_40[0x8];
7292         u8         xrqn[0x18];
7293
7294         u8         reserved_at_60[0x10];
7295         u8         lwm[0x10];
7296 };
7297
7298 struct mlx5_ifc_arm_xrc_srq_out_bits {
7299         u8         status[0x8];
7300         u8         reserved_at_8[0x18];
7301
7302         u8         syndrome[0x20];
7303
7304         u8         reserved_at_40[0x40];
7305 };
7306
7307 enum {
7308         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7309 };
7310
7311 struct mlx5_ifc_arm_xrc_srq_in_bits {
7312         u8         opcode[0x10];
7313         u8         uid[0x10];
7314
7315         u8         reserved_at_20[0x10];
7316         u8         op_mod[0x10];
7317
7318         u8         reserved_at_40[0x8];
7319         u8         xrc_srqn[0x18];
7320
7321         u8         reserved_at_60[0x10];
7322         u8         lwm[0x10];
7323 };
7324
7325 struct mlx5_ifc_arm_rq_out_bits {
7326         u8         status[0x8];
7327         u8         reserved_at_8[0x18];
7328
7329         u8         syndrome[0x20];
7330
7331         u8         reserved_at_40[0x40];
7332 };
7333
7334 enum {
7335         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7336         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7337 };
7338
7339 struct mlx5_ifc_arm_rq_in_bits {
7340         u8         opcode[0x10];
7341         u8         uid[0x10];
7342
7343         u8         reserved_at_20[0x10];
7344         u8         op_mod[0x10];
7345
7346         u8         reserved_at_40[0x8];
7347         u8         srq_number[0x18];
7348
7349         u8         reserved_at_60[0x10];
7350         u8         lwm[0x10];
7351 };
7352
7353 struct mlx5_ifc_arm_dct_out_bits {
7354         u8         status[0x8];
7355         u8         reserved_at_8[0x18];
7356
7357         u8         syndrome[0x20];
7358
7359         u8         reserved_at_40[0x40];
7360 };
7361
7362 struct mlx5_ifc_arm_dct_in_bits {
7363         u8         opcode[0x10];
7364         u8         reserved_at_10[0x10];
7365
7366         u8         reserved_at_20[0x10];
7367         u8         op_mod[0x10];
7368
7369         u8         reserved_at_40[0x8];
7370         u8         dct_number[0x18];
7371
7372         u8         reserved_at_60[0x20];
7373 };
7374
7375 struct mlx5_ifc_alloc_xrcd_out_bits {
7376         u8         status[0x8];
7377         u8         reserved_at_8[0x18];
7378
7379         u8         syndrome[0x20];
7380
7381         u8         reserved_at_40[0x8];
7382         u8         xrcd[0x18];
7383
7384         u8         reserved_at_60[0x20];
7385 };
7386
7387 struct mlx5_ifc_alloc_xrcd_in_bits {
7388         u8         opcode[0x10];
7389         u8         uid[0x10];
7390
7391         u8         reserved_at_20[0x10];
7392         u8         op_mod[0x10];
7393
7394         u8         reserved_at_40[0x40];
7395 };
7396
7397 struct mlx5_ifc_alloc_uar_out_bits {
7398         u8         status[0x8];
7399         u8         reserved_at_8[0x18];
7400
7401         u8         syndrome[0x20];
7402
7403         u8         reserved_at_40[0x8];
7404         u8         uar[0x18];
7405
7406         u8         reserved_at_60[0x20];
7407 };
7408
7409 struct mlx5_ifc_alloc_uar_in_bits {
7410         u8         opcode[0x10];
7411         u8         reserved_at_10[0x10];
7412
7413         u8         reserved_at_20[0x10];
7414         u8         op_mod[0x10];
7415
7416         u8         reserved_at_40[0x40];
7417 };
7418
7419 struct mlx5_ifc_alloc_transport_domain_out_bits {
7420         u8         status[0x8];
7421         u8         reserved_at_8[0x18];
7422
7423         u8         syndrome[0x20];
7424
7425         u8         reserved_at_40[0x8];
7426         u8         transport_domain[0x18];
7427
7428         u8         reserved_at_60[0x20];
7429 };
7430
7431 struct mlx5_ifc_alloc_transport_domain_in_bits {
7432         u8         opcode[0x10];
7433         u8         reserved_at_10[0x10];
7434
7435         u8         reserved_at_20[0x10];
7436         u8         op_mod[0x10];
7437
7438         u8         reserved_at_40[0x40];
7439 };
7440
7441 struct mlx5_ifc_alloc_q_counter_out_bits {
7442         u8         status[0x8];
7443         u8         reserved_at_8[0x18];
7444
7445         u8         syndrome[0x20];
7446
7447         u8         reserved_at_40[0x18];
7448         u8         counter_set_id[0x8];
7449
7450         u8         reserved_at_60[0x20];
7451 };
7452
7453 struct mlx5_ifc_alloc_q_counter_in_bits {
7454         u8         opcode[0x10];
7455         u8         reserved_at_10[0x10];
7456
7457         u8         reserved_at_20[0x10];
7458         u8         op_mod[0x10];
7459
7460         u8         reserved_at_40[0x40];
7461 };
7462
7463 struct mlx5_ifc_alloc_pd_out_bits {
7464         u8         status[0x8];
7465         u8         reserved_at_8[0x18];
7466
7467         u8         syndrome[0x20];
7468
7469         u8         reserved_at_40[0x8];
7470         u8         pd[0x18];
7471
7472         u8         reserved_at_60[0x20];
7473 };
7474
7475 struct mlx5_ifc_alloc_pd_in_bits {
7476         u8         opcode[0x10];
7477         u8         uid[0x10];
7478
7479         u8         reserved_at_20[0x10];
7480         u8         op_mod[0x10];
7481
7482         u8         reserved_at_40[0x40];
7483 };
7484
7485 struct mlx5_ifc_alloc_flow_counter_out_bits {
7486         u8         status[0x8];
7487         u8         reserved_at_8[0x18];
7488
7489         u8         syndrome[0x20];
7490
7491         u8         flow_counter_id[0x20];
7492
7493         u8         reserved_at_60[0x20];
7494 };
7495
7496 struct mlx5_ifc_alloc_flow_counter_in_bits {
7497         u8         opcode[0x10];
7498         u8         reserved_at_10[0x10];
7499
7500         u8         reserved_at_20[0x10];
7501         u8         op_mod[0x10];
7502
7503         u8         reserved_at_40[0x40];
7504 };
7505
7506 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7507         u8         status[0x8];
7508         u8         reserved_at_8[0x18];
7509
7510         u8         syndrome[0x20];
7511
7512         u8         reserved_at_40[0x40];
7513 };
7514
7515 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7516         u8         opcode[0x10];
7517         u8         reserved_at_10[0x10];
7518
7519         u8         reserved_at_20[0x10];
7520         u8         op_mod[0x10];
7521
7522         u8         reserved_at_40[0x20];
7523
7524         u8         reserved_at_60[0x10];
7525         u8         vxlan_udp_port[0x10];
7526 };
7527
7528 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7529         u8         status[0x8];
7530         u8         reserved_at_8[0x18];
7531
7532         u8         syndrome[0x20];
7533
7534         u8         reserved_at_40[0x40];
7535 };
7536
7537 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7538         u8         opcode[0x10];
7539         u8         reserved_at_10[0x10];
7540
7541         u8         reserved_at_20[0x10];
7542         u8         op_mod[0x10];
7543
7544         u8         reserved_at_40[0x10];
7545         u8         rate_limit_index[0x10];
7546
7547         u8         reserved_at_60[0x20];
7548
7549         u8         rate_limit[0x20];
7550
7551         u8         burst_upper_bound[0x20];
7552
7553         u8         reserved_at_c0[0x10];
7554         u8         typical_packet_size[0x10];
7555
7556         u8         reserved_at_e0[0x120];
7557 };
7558
7559 struct mlx5_ifc_access_register_out_bits {
7560         u8         status[0x8];
7561         u8         reserved_at_8[0x18];
7562
7563         u8         syndrome[0x20];
7564
7565         u8         reserved_at_40[0x40];
7566
7567         u8         register_data[0][0x20];
7568 };
7569
7570 enum {
7571         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7572         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7573 };
7574
7575 struct mlx5_ifc_access_register_in_bits {
7576         u8         opcode[0x10];
7577         u8         reserved_at_10[0x10];
7578
7579         u8         reserved_at_20[0x10];
7580         u8         op_mod[0x10];
7581
7582         u8         reserved_at_40[0x10];
7583         u8         register_id[0x10];
7584
7585         u8         argument[0x20];
7586
7587         u8         register_data[0][0x20];
7588 };
7589
7590 struct mlx5_ifc_sltp_reg_bits {
7591         u8         status[0x4];
7592         u8         version[0x4];
7593         u8         local_port[0x8];
7594         u8         pnat[0x2];
7595         u8         reserved_at_12[0x2];
7596         u8         lane[0x4];
7597         u8         reserved_at_18[0x8];
7598
7599         u8         reserved_at_20[0x20];
7600
7601         u8         reserved_at_40[0x7];
7602         u8         polarity[0x1];
7603         u8         ob_tap0[0x8];
7604         u8         ob_tap1[0x8];
7605         u8         ob_tap2[0x8];
7606
7607         u8         reserved_at_60[0xc];
7608         u8         ob_preemp_mode[0x4];
7609         u8         ob_reg[0x8];
7610         u8         ob_bias[0x8];
7611
7612         u8         reserved_at_80[0x20];
7613 };
7614
7615 struct mlx5_ifc_slrg_reg_bits {
7616         u8         status[0x4];
7617         u8         version[0x4];
7618         u8         local_port[0x8];
7619         u8         pnat[0x2];
7620         u8         reserved_at_12[0x2];
7621         u8         lane[0x4];
7622         u8         reserved_at_18[0x8];
7623
7624         u8         time_to_link_up[0x10];
7625         u8         reserved_at_30[0xc];
7626         u8         grade_lane_speed[0x4];
7627
7628         u8         grade_version[0x8];
7629         u8         grade[0x18];
7630
7631         u8         reserved_at_60[0x4];
7632         u8         height_grade_type[0x4];
7633         u8         height_grade[0x18];
7634
7635         u8         height_dz[0x10];
7636         u8         height_dv[0x10];
7637
7638         u8         reserved_at_a0[0x10];
7639         u8         height_sigma[0x10];
7640
7641         u8         reserved_at_c0[0x20];
7642
7643         u8         reserved_at_e0[0x4];
7644         u8         phase_grade_type[0x4];
7645         u8         phase_grade[0x18];
7646
7647         u8         reserved_at_100[0x8];
7648         u8         phase_eo_pos[0x8];
7649         u8         reserved_at_110[0x8];
7650         u8         phase_eo_neg[0x8];
7651
7652         u8         ffe_set_tested[0x10];
7653         u8         test_errors_per_lane[0x10];
7654 };
7655
7656 struct mlx5_ifc_pvlc_reg_bits {
7657         u8         reserved_at_0[0x8];
7658         u8         local_port[0x8];
7659         u8         reserved_at_10[0x10];
7660
7661         u8         reserved_at_20[0x1c];
7662         u8         vl_hw_cap[0x4];
7663
7664         u8         reserved_at_40[0x1c];
7665         u8         vl_admin[0x4];
7666
7667         u8         reserved_at_60[0x1c];
7668         u8         vl_operational[0x4];
7669 };
7670
7671 struct mlx5_ifc_pude_reg_bits {
7672         u8         swid[0x8];
7673         u8         local_port[0x8];
7674         u8         reserved_at_10[0x4];
7675         u8         admin_status[0x4];
7676         u8         reserved_at_18[0x4];
7677         u8         oper_status[0x4];
7678
7679         u8         reserved_at_20[0x60];
7680 };
7681
7682 struct mlx5_ifc_ptys_reg_bits {
7683         u8         reserved_at_0[0x1];
7684         u8         an_disable_admin[0x1];
7685         u8         an_disable_cap[0x1];
7686         u8         reserved_at_3[0x5];
7687         u8         local_port[0x8];
7688         u8         reserved_at_10[0xd];
7689         u8         proto_mask[0x3];
7690
7691         u8         an_status[0x4];
7692         u8         reserved_at_24[0x3c];
7693
7694         u8         eth_proto_capability[0x20];
7695
7696         u8         ib_link_width_capability[0x10];
7697         u8         ib_proto_capability[0x10];
7698
7699         u8         reserved_at_a0[0x20];
7700
7701         u8         eth_proto_admin[0x20];
7702
7703         u8         ib_link_width_admin[0x10];
7704         u8         ib_proto_admin[0x10];
7705
7706         u8         reserved_at_100[0x20];
7707
7708         u8         eth_proto_oper[0x20];
7709
7710         u8         ib_link_width_oper[0x10];
7711         u8         ib_proto_oper[0x10];
7712
7713         u8         reserved_at_160[0x1c];
7714         u8         connector_type[0x4];
7715
7716         u8         eth_proto_lp_advertise[0x20];
7717
7718         u8         reserved_at_1a0[0x60];
7719 };
7720
7721 struct mlx5_ifc_mlcr_reg_bits {
7722         u8         reserved_at_0[0x8];
7723         u8         local_port[0x8];
7724         u8         reserved_at_10[0x20];
7725
7726         u8         beacon_duration[0x10];
7727         u8         reserved_at_40[0x10];
7728
7729         u8         beacon_remain[0x10];
7730 };
7731
7732 struct mlx5_ifc_ptas_reg_bits {
7733         u8         reserved_at_0[0x20];
7734
7735         u8         algorithm_options[0x10];
7736         u8         reserved_at_30[0x4];
7737         u8         repetitions_mode[0x4];
7738         u8         num_of_repetitions[0x8];
7739
7740         u8         grade_version[0x8];
7741         u8         height_grade_type[0x4];
7742         u8         phase_grade_type[0x4];
7743         u8         height_grade_weight[0x8];
7744         u8         phase_grade_weight[0x8];
7745
7746         u8         gisim_measure_bits[0x10];
7747         u8         adaptive_tap_measure_bits[0x10];
7748
7749         u8         ber_bath_high_error_threshold[0x10];
7750         u8         ber_bath_mid_error_threshold[0x10];
7751
7752         u8         ber_bath_low_error_threshold[0x10];
7753         u8         one_ratio_high_threshold[0x10];
7754
7755         u8         one_ratio_high_mid_threshold[0x10];
7756         u8         one_ratio_low_mid_threshold[0x10];
7757
7758         u8         one_ratio_low_threshold[0x10];
7759         u8         ndeo_error_threshold[0x10];
7760
7761         u8         mixer_offset_step_size[0x10];
7762         u8         reserved_at_110[0x8];
7763         u8         mix90_phase_for_voltage_bath[0x8];
7764
7765         u8         mixer_offset_start[0x10];
7766         u8         mixer_offset_end[0x10];
7767
7768         u8         reserved_at_140[0x15];
7769         u8         ber_test_time[0xb];
7770 };
7771
7772 struct mlx5_ifc_pspa_reg_bits {
7773         u8         swid[0x8];
7774         u8         local_port[0x8];
7775         u8         sub_port[0x8];
7776         u8         reserved_at_18[0x8];
7777
7778         u8         reserved_at_20[0x20];
7779 };
7780
7781 struct mlx5_ifc_pqdr_reg_bits {
7782         u8         reserved_at_0[0x8];
7783         u8         local_port[0x8];
7784         u8         reserved_at_10[0x5];
7785         u8         prio[0x3];
7786         u8         reserved_at_18[0x6];
7787         u8         mode[0x2];
7788
7789         u8         reserved_at_20[0x20];
7790
7791         u8         reserved_at_40[0x10];
7792         u8         min_threshold[0x10];
7793
7794         u8         reserved_at_60[0x10];
7795         u8         max_threshold[0x10];
7796
7797         u8         reserved_at_80[0x10];
7798         u8         mark_probability_denominator[0x10];
7799
7800         u8         reserved_at_a0[0x60];
7801 };
7802
7803 struct mlx5_ifc_ppsc_reg_bits {
7804         u8         reserved_at_0[0x8];
7805         u8         local_port[0x8];
7806         u8         reserved_at_10[0x10];
7807
7808         u8         reserved_at_20[0x60];
7809
7810         u8         reserved_at_80[0x1c];
7811         u8         wrps_admin[0x4];
7812
7813         u8         reserved_at_a0[0x1c];
7814         u8         wrps_status[0x4];
7815
7816         u8         reserved_at_c0[0x8];
7817         u8         up_threshold[0x8];
7818         u8         reserved_at_d0[0x8];
7819         u8         down_threshold[0x8];
7820
7821         u8         reserved_at_e0[0x20];
7822
7823         u8         reserved_at_100[0x1c];
7824         u8         srps_admin[0x4];
7825
7826         u8         reserved_at_120[0x1c];
7827         u8         srps_status[0x4];
7828
7829         u8         reserved_at_140[0x40];
7830 };
7831
7832 struct mlx5_ifc_pplr_reg_bits {
7833         u8         reserved_at_0[0x8];
7834         u8         local_port[0x8];
7835         u8         reserved_at_10[0x10];
7836
7837         u8         reserved_at_20[0x8];
7838         u8         lb_cap[0x8];
7839         u8         reserved_at_30[0x8];
7840         u8         lb_en[0x8];
7841 };
7842
7843 struct mlx5_ifc_pplm_reg_bits {
7844         u8         reserved_at_0[0x8];
7845         u8         local_port[0x8];
7846         u8         reserved_at_10[0x10];
7847
7848         u8         reserved_at_20[0x20];
7849
7850         u8         port_profile_mode[0x8];
7851         u8         static_port_profile[0x8];
7852         u8         active_port_profile[0x8];
7853         u8         reserved_at_58[0x8];
7854
7855         u8         retransmission_active[0x8];
7856         u8         fec_mode_active[0x18];
7857
7858         u8         rs_fec_correction_bypass_cap[0x4];
7859         u8         reserved_at_84[0x8];
7860         u8         fec_override_cap_56g[0x4];
7861         u8         fec_override_cap_100g[0x4];
7862         u8         fec_override_cap_50g[0x4];
7863         u8         fec_override_cap_25g[0x4];
7864         u8         fec_override_cap_10g_40g[0x4];
7865
7866         u8         rs_fec_correction_bypass_admin[0x4];
7867         u8         reserved_at_a4[0x8];
7868         u8         fec_override_admin_56g[0x4];
7869         u8         fec_override_admin_100g[0x4];
7870         u8         fec_override_admin_50g[0x4];
7871         u8         fec_override_admin_25g[0x4];
7872         u8         fec_override_admin_10g_40g[0x4];
7873 };
7874
7875 struct mlx5_ifc_ppcnt_reg_bits {
7876         u8         swid[0x8];
7877         u8         local_port[0x8];
7878         u8         pnat[0x2];
7879         u8         reserved_at_12[0x8];
7880         u8         grp[0x6];
7881
7882         u8         clr[0x1];
7883         u8         reserved_at_21[0x1c];
7884         u8         prio_tc[0x3];
7885
7886         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7887 };
7888
7889 struct mlx5_ifc_mpcnt_reg_bits {
7890         u8         reserved_at_0[0x8];
7891         u8         pcie_index[0x8];
7892         u8         reserved_at_10[0xa];
7893         u8         grp[0x6];
7894
7895         u8         clr[0x1];
7896         u8         reserved_at_21[0x1f];
7897
7898         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7899 };
7900
7901 struct mlx5_ifc_ppad_reg_bits {
7902         u8         reserved_at_0[0x3];
7903         u8         single_mac[0x1];
7904         u8         reserved_at_4[0x4];
7905         u8         local_port[0x8];
7906         u8         mac_47_32[0x10];
7907
7908         u8         mac_31_0[0x20];
7909
7910         u8         reserved_at_40[0x40];
7911 };
7912
7913 struct mlx5_ifc_pmtu_reg_bits {
7914         u8         reserved_at_0[0x8];
7915         u8         local_port[0x8];
7916         u8         reserved_at_10[0x10];
7917
7918         u8         max_mtu[0x10];
7919         u8         reserved_at_30[0x10];
7920
7921         u8         admin_mtu[0x10];
7922         u8         reserved_at_50[0x10];
7923
7924         u8         oper_mtu[0x10];
7925         u8         reserved_at_70[0x10];
7926 };
7927
7928 struct mlx5_ifc_pmpr_reg_bits {
7929         u8         reserved_at_0[0x8];
7930         u8         module[0x8];
7931         u8         reserved_at_10[0x10];
7932
7933         u8         reserved_at_20[0x18];
7934         u8         attenuation_5g[0x8];
7935
7936         u8         reserved_at_40[0x18];
7937         u8         attenuation_7g[0x8];
7938
7939         u8         reserved_at_60[0x18];
7940         u8         attenuation_12g[0x8];
7941 };
7942
7943 struct mlx5_ifc_pmpe_reg_bits {
7944         u8         reserved_at_0[0x8];
7945         u8         module[0x8];
7946         u8         reserved_at_10[0xc];
7947         u8         module_status[0x4];
7948
7949         u8         reserved_at_20[0x60];
7950 };
7951
7952 struct mlx5_ifc_pmpc_reg_bits {
7953         u8         module_state_updated[32][0x8];
7954 };
7955
7956 struct mlx5_ifc_pmlpn_reg_bits {
7957         u8         reserved_at_0[0x4];
7958         u8         mlpn_status[0x4];
7959         u8         local_port[0x8];
7960         u8         reserved_at_10[0x10];
7961
7962         u8         e[0x1];
7963         u8         reserved_at_21[0x1f];
7964 };
7965
7966 struct mlx5_ifc_pmlp_reg_bits {
7967         u8         rxtx[0x1];
7968         u8         reserved_at_1[0x7];
7969         u8         local_port[0x8];
7970         u8         reserved_at_10[0x8];
7971         u8         width[0x8];
7972
7973         u8         lane0_module_mapping[0x20];
7974
7975         u8         lane1_module_mapping[0x20];
7976
7977         u8         lane2_module_mapping[0x20];
7978
7979         u8         lane3_module_mapping[0x20];
7980
7981         u8         reserved_at_a0[0x160];
7982 };
7983
7984 struct mlx5_ifc_pmaos_reg_bits {
7985         u8         reserved_at_0[0x8];
7986         u8         module[0x8];
7987         u8         reserved_at_10[0x4];
7988         u8         admin_status[0x4];
7989         u8         reserved_at_18[0x4];
7990         u8         oper_status[0x4];
7991
7992         u8         ase[0x1];
7993         u8         ee[0x1];
7994         u8         reserved_at_22[0x1c];
7995         u8         e[0x2];
7996
7997         u8         reserved_at_40[0x40];
7998 };
7999
8000 struct mlx5_ifc_plpc_reg_bits {
8001         u8         reserved_at_0[0x4];
8002         u8         profile_id[0xc];
8003         u8         reserved_at_10[0x4];
8004         u8         proto_mask[0x4];
8005         u8         reserved_at_18[0x8];
8006
8007         u8         reserved_at_20[0x10];
8008         u8         lane_speed[0x10];
8009
8010         u8         reserved_at_40[0x17];
8011         u8         lpbf[0x1];
8012         u8         fec_mode_policy[0x8];
8013
8014         u8         retransmission_capability[0x8];
8015         u8         fec_mode_capability[0x18];
8016
8017         u8         retransmission_support_admin[0x8];
8018         u8         fec_mode_support_admin[0x18];
8019
8020         u8         retransmission_request_admin[0x8];
8021         u8         fec_mode_request_admin[0x18];
8022
8023         u8         reserved_at_c0[0x80];
8024 };
8025
8026 struct mlx5_ifc_plib_reg_bits {
8027         u8         reserved_at_0[0x8];
8028         u8         local_port[0x8];
8029         u8         reserved_at_10[0x8];
8030         u8         ib_port[0x8];
8031
8032         u8         reserved_at_20[0x60];
8033 };
8034
8035 struct mlx5_ifc_plbf_reg_bits {
8036         u8         reserved_at_0[0x8];
8037         u8         local_port[0x8];
8038         u8         reserved_at_10[0xd];
8039         u8         lbf_mode[0x3];
8040
8041         u8         reserved_at_20[0x20];
8042 };
8043
8044 struct mlx5_ifc_pipg_reg_bits {
8045         u8         reserved_at_0[0x8];
8046         u8         local_port[0x8];
8047         u8         reserved_at_10[0x10];
8048
8049         u8         dic[0x1];
8050         u8         reserved_at_21[0x19];
8051         u8         ipg[0x4];
8052         u8         reserved_at_3e[0x2];
8053 };
8054
8055 struct mlx5_ifc_pifr_reg_bits {
8056         u8         reserved_at_0[0x8];
8057         u8         local_port[0x8];
8058         u8         reserved_at_10[0x10];
8059
8060         u8         reserved_at_20[0xe0];
8061
8062         u8         port_filter[8][0x20];
8063
8064         u8         port_filter_update_en[8][0x20];
8065 };
8066
8067 struct mlx5_ifc_pfcc_reg_bits {
8068         u8         reserved_at_0[0x8];
8069         u8         local_port[0x8];
8070         u8         reserved_at_10[0xb];
8071         u8         ppan_mask_n[0x1];
8072         u8         minor_stall_mask[0x1];
8073         u8         critical_stall_mask[0x1];
8074         u8         reserved_at_1e[0x2];
8075
8076         u8         ppan[0x4];
8077         u8         reserved_at_24[0x4];
8078         u8         prio_mask_tx[0x8];
8079         u8         reserved_at_30[0x8];
8080         u8         prio_mask_rx[0x8];
8081
8082         u8         pptx[0x1];
8083         u8         aptx[0x1];
8084         u8         pptx_mask_n[0x1];
8085         u8         reserved_at_43[0x5];
8086         u8         pfctx[0x8];
8087         u8         reserved_at_50[0x10];
8088
8089         u8         pprx[0x1];
8090         u8         aprx[0x1];
8091         u8         pprx_mask_n[0x1];
8092         u8         reserved_at_63[0x5];
8093         u8         pfcrx[0x8];
8094         u8         reserved_at_70[0x10];
8095
8096         u8         device_stall_minor_watermark[0x10];
8097         u8         device_stall_critical_watermark[0x10];
8098
8099         u8         reserved_at_a0[0x60];
8100 };
8101
8102 struct mlx5_ifc_pelc_reg_bits {
8103         u8         op[0x4];
8104         u8         reserved_at_4[0x4];
8105         u8         local_port[0x8];
8106         u8         reserved_at_10[0x10];
8107
8108         u8         op_admin[0x8];
8109         u8         op_capability[0x8];
8110         u8         op_request[0x8];
8111         u8         op_active[0x8];
8112
8113         u8         admin[0x40];
8114
8115         u8         capability[0x40];
8116
8117         u8         request[0x40];
8118
8119         u8         active[0x40];
8120
8121         u8         reserved_at_140[0x80];
8122 };
8123
8124 struct mlx5_ifc_peir_reg_bits {
8125         u8         reserved_at_0[0x8];
8126         u8         local_port[0x8];
8127         u8         reserved_at_10[0x10];
8128
8129         u8         reserved_at_20[0xc];
8130         u8         error_count[0x4];
8131         u8         reserved_at_30[0x10];
8132
8133         u8         reserved_at_40[0xc];
8134         u8         lane[0x4];
8135         u8         reserved_at_50[0x8];
8136         u8         error_type[0x8];
8137 };
8138
8139 struct mlx5_ifc_mpegc_reg_bits {
8140         u8         reserved_at_0[0x30];
8141         u8         field_select[0x10];
8142
8143         u8         tx_overflow_sense[0x1];
8144         u8         mark_cqe[0x1];
8145         u8         mark_cnp[0x1];
8146         u8         reserved_at_43[0x1b];
8147         u8         tx_lossy_overflow_oper[0x2];
8148
8149         u8         reserved_at_60[0x100];
8150 };
8151
8152 struct mlx5_ifc_pcam_enhanced_features_bits {
8153         u8         reserved_at_0[0x6d];
8154         u8         rx_icrc_encapsulated_counter[0x1];
8155         u8         reserved_at_6e[0x8];
8156         u8         pfcc_mask[0x1];
8157         u8         reserved_at_77[0x3];
8158         u8         per_lane_error_counters[0x1];
8159         u8         rx_buffer_fullness_counters[0x1];
8160         u8         ptys_connector_type[0x1];
8161         u8         reserved_at_7d[0x1];
8162         u8         ppcnt_discard_group[0x1];
8163         u8         ppcnt_statistical_group[0x1];
8164 };
8165
8166 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8167         u8         port_access_reg_cap_mask_127_to_96[0x20];
8168         u8         port_access_reg_cap_mask_95_to_64[0x20];
8169
8170         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8171         u8         pplm[0x1];
8172         u8         port_access_reg_cap_mask_34_to_32[0x3];
8173
8174         u8         port_access_reg_cap_mask_31_to_13[0x13];
8175         u8         pbmc[0x1];
8176         u8         pptb[0x1];
8177         u8         port_access_reg_cap_mask_10_to_0[0xb];
8178 };
8179
8180 struct mlx5_ifc_pcam_reg_bits {
8181         u8         reserved_at_0[0x8];
8182         u8         feature_group[0x8];
8183         u8         reserved_at_10[0x8];
8184         u8         access_reg_group[0x8];
8185
8186         u8         reserved_at_20[0x20];
8187
8188         union {
8189                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8190                 u8         reserved_at_0[0x80];
8191         } port_access_reg_cap_mask;
8192
8193         u8         reserved_at_c0[0x80];
8194
8195         union {
8196                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8197                 u8         reserved_at_0[0x80];
8198         } feature_cap_mask;
8199
8200         u8         reserved_at_1c0[0xc0];
8201 };
8202
8203 struct mlx5_ifc_mcam_enhanced_features_bits {
8204         u8         reserved_at_0[0x74];
8205         u8         mark_tx_action_cnp[0x1];
8206         u8         mark_tx_action_cqe[0x1];
8207         u8         dynamic_tx_overflow[0x1];
8208         u8         reserved_at_77[0x4];
8209         u8         pcie_outbound_stalled[0x1];
8210         u8         tx_overflow_buffer_pkt[0x1];
8211         u8         mtpps_enh_out_per_adj[0x1];
8212         u8         mtpps_fs[0x1];
8213         u8         pcie_performance_group[0x1];
8214 };
8215
8216 struct mlx5_ifc_mcam_access_reg_bits {
8217         u8         reserved_at_0[0x1c];
8218         u8         mcda[0x1];
8219         u8         mcc[0x1];
8220         u8         mcqi[0x1];
8221         u8         reserved_at_1f[0x1];
8222
8223         u8         regs_95_to_87[0x9];
8224         u8         mpegc[0x1];
8225         u8         regs_85_to_68[0x12];
8226         u8         tracer_registers[0x4];
8227
8228         u8         regs_63_to_32[0x20];
8229         u8         regs_31_to_0[0x20];
8230 };
8231
8232 struct mlx5_ifc_mcam_reg_bits {
8233         u8         reserved_at_0[0x8];
8234         u8         feature_group[0x8];
8235         u8         reserved_at_10[0x8];
8236         u8         access_reg_group[0x8];
8237
8238         u8         reserved_at_20[0x20];
8239
8240         union {
8241                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8242                 u8         reserved_at_0[0x80];
8243         } mng_access_reg_cap_mask;
8244
8245         u8         reserved_at_c0[0x80];
8246
8247         union {
8248                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8249                 u8         reserved_at_0[0x80];
8250         } mng_feature_cap_mask;
8251
8252         u8         reserved_at_1c0[0x80];
8253 };
8254
8255 struct mlx5_ifc_qcam_access_reg_cap_mask {
8256         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8257         u8         qpdpm[0x1];
8258         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8259         u8         qdpm[0x1];
8260         u8         qpts[0x1];
8261         u8         qcap[0x1];
8262         u8         qcam_access_reg_cap_mask_0[0x1];
8263 };
8264
8265 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8266         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8267         u8         qpts_trust_both[0x1];
8268 };
8269
8270 struct mlx5_ifc_qcam_reg_bits {
8271         u8         reserved_at_0[0x8];
8272         u8         feature_group[0x8];
8273         u8         reserved_at_10[0x8];
8274         u8         access_reg_group[0x8];
8275         u8         reserved_at_20[0x20];
8276
8277         union {
8278                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8279                 u8  reserved_at_0[0x80];
8280         } qos_access_reg_cap_mask;
8281
8282         u8         reserved_at_c0[0x80];
8283
8284         union {
8285                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8286                 u8  reserved_at_0[0x80];
8287         } qos_feature_cap_mask;
8288
8289         u8         reserved_at_1c0[0x80];
8290 };
8291
8292 struct mlx5_ifc_pcap_reg_bits {
8293         u8         reserved_at_0[0x8];
8294         u8         local_port[0x8];
8295         u8         reserved_at_10[0x10];
8296
8297         u8         port_capability_mask[4][0x20];
8298 };
8299
8300 struct mlx5_ifc_paos_reg_bits {
8301         u8         swid[0x8];
8302         u8         local_port[0x8];
8303         u8         reserved_at_10[0x4];
8304         u8         admin_status[0x4];
8305         u8         reserved_at_18[0x4];
8306         u8         oper_status[0x4];
8307
8308         u8         ase[0x1];
8309         u8         ee[0x1];
8310         u8         reserved_at_22[0x1c];
8311         u8         e[0x2];
8312
8313         u8         reserved_at_40[0x40];
8314 };
8315
8316 struct mlx5_ifc_pamp_reg_bits {
8317         u8         reserved_at_0[0x8];
8318         u8         opamp_group[0x8];
8319         u8         reserved_at_10[0xc];
8320         u8         opamp_group_type[0x4];
8321
8322         u8         start_index[0x10];
8323         u8         reserved_at_30[0x4];
8324         u8         num_of_indices[0xc];
8325
8326         u8         index_data[18][0x10];
8327 };
8328
8329 struct mlx5_ifc_pcmr_reg_bits {
8330         u8         reserved_at_0[0x8];
8331         u8         local_port[0x8];
8332         u8         reserved_at_10[0x2e];
8333         u8         fcs_cap[0x1];
8334         u8         reserved_at_3f[0x1f];
8335         u8         fcs_chk[0x1];
8336         u8         reserved_at_5f[0x1];
8337 };
8338
8339 struct mlx5_ifc_lane_2_module_mapping_bits {
8340         u8         reserved_at_0[0x6];
8341         u8         rx_lane[0x2];
8342         u8         reserved_at_8[0x6];
8343         u8         tx_lane[0x2];
8344         u8         reserved_at_10[0x8];
8345         u8         module[0x8];
8346 };
8347
8348 struct mlx5_ifc_bufferx_reg_bits {
8349         u8         reserved_at_0[0x6];
8350         u8         lossy[0x1];
8351         u8         epsb[0x1];
8352         u8         reserved_at_8[0xc];
8353         u8         size[0xc];
8354
8355         u8         xoff_threshold[0x10];
8356         u8         xon_threshold[0x10];
8357 };
8358
8359 struct mlx5_ifc_set_node_in_bits {
8360         u8         node_description[64][0x8];
8361 };
8362
8363 struct mlx5_ifc_register_power_settings_bits {
8364         u8         reserved_at_0[0x18];
8365         u8         power_settings_level[0x8];
8366
8367         u8         reserved_at_20[0x60];
8368 };
8369
8370 struct mlx5_ifc_register_host_endianness_bits {
8371         u8         he[0x1];
8372         u8         reserved_at_1[0x1f];
8373
8374         u8         reserved_at_20[0x60];
8375 };
8376
8377 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8378         u8         reserved_at_0[0x20];
8379
8380         u8         mkey[0x20];
8381
8382         u8         addressh_63_32[0x20];
8383
8384         u8         addressl_31_0[0x20];
8385 };
8386
8387 struct mlx5_ifc_ud_adrs_vector_bits {
8388         u8         dc_key[0x40];
8389
8390         u8         ext[0x1];
8391         u8         reserved_at_41[0x7];
8392         u8         destination_qp_dct[0x18];
8393
8394         u8         static_rate[0x4];
8395         u8         sl_eth_prio[0x4];
8396         u8         fl[0x1];
8397         u8         mlid[0x7];
8398         u8         rlid_udp_sport[0x10];
8399
8400         u8         reserved_at_80[0x20];
8401
8402         u8         rmac_47_16[0x20];
8403
8404         u8         rmac_15_0[0x10];
8405         u8         tclass[0x8];
8406         u8         hop_limit[0x8];
8407
8408         u8         reserved_at_e0[0x1];
8409         u8         grh[0x1];
8410         u8         reserved_at_e2[0x2];
8411         u8         src_addr_index[0x8];
8412         u8         flow_label[0x14];
8413
8414         u8         rgid_rip[16][0x8];
8415 };
8416
8417 struct mlx5_ifc_pages_req_event_bits {
8418         u8         reserved_at_0[0x10];
8419         u8         function_id[0x10];
8420
8421         u8         num_pages[0x20];
8422
8423         u8         reserved_at_40[0xa0];
8424 };
8425
8426 struct mlx5_ifc_eqe_bits {
8427         u8         reserved_at_0[0x8];
8428         u8         event_type[0x8];
8429         u8         reserved_at_10[0x8];
8430         u8         event_sub_type[0x8];
8431
8432         u8         reserved_at_20[0xe0];
8433
8434         union mlx5_ifc_event_auto_bits event_data;
8435
8436         u8         reserved_at_1e0[0x10];
8437         u8         signature[0x8];
8438         u8         reserved_at_1f8[0x7];
8439         u8         owner[0x1];
8440 };
8441
8442 enum {
8443         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8444 };
8445
8446 struct mlx5_ifc_cmd_queue_entry_bits {
8447         u8         type[0x8];
8448         u8         reserved_at_8[0x18];
8449
8450         u8         input_length[0x20];
8451
8452         u8         input_mailbox_pointer_63_32[0x20];
8453
8454         u8         input_mailbox_pointer_31_9[0x17];
8455         u8         reserved_at_77[0x9];
8456
8457         u8         command_input_inline_data[16][0x8];
8458
8459         u8         command_output_inline_data[16][0x8];
8460
8461         u8         output_mailbox_pointer_63_32[0x20];
8462
8463         u8         output_mailbox_pointer_31_9[0x17];
8464         u8         reserved_at_1b7[0x9];
8465
8466         u8         output_length[0x20];
8467
8468         u8         token[0x8];
8469         u8         signature[0x8];
8470         u8         reserved_at_1f0[0x8];
8471         u8         status[0x7];
8472         u8         ownership[0x1];
8473 };
8474
8475 struct mlx5_ifc_cmd_out_bits {
8476         u8         status[0x8];
8477         u8         reserved_at_8[0x18];
8478
8479         u8         syndrome[0x20];
8480
8481         u8         command_output[0x20];
8482 };
8483
8484 struct mlx5_ifc_cmd_in_bits {
8485         u8         opcode[0x10];
8486         u8         reserved_at_10[0x10];
8487
8488         u8         reserved_at_20[0x10];
8489         u8         op_mod[0x10];
8490
8491         u8         command[0][0x20];
8492 };
8493
8494 struct mlx5_ifc_cmd_if_box_bits {
8495         u8         mailbox_data[512][0x8];
8496
8497         u8         reserved_at_1000[0x180];
8498
8499         u8         next_pointer_63_32[0x20];
8500
8501         u8         next_pointer_31_10[0x16];
8502         u8         reserved_at_11b6[0xa];
8503
8504         u8         block_number[0x20];
8505
8506         u8         reserved_at_11e0[0x8];
8507         u8         token[0x8];
8508         u8         ctrl_signature[0x8];
8509         u8         signature[0x8];
8510 };
8511
8512 struct mlx5_ifc_mtt_bits {
8513         u8         ptag_63_32[0x20];
8514
8515         u8         ptag_31_8[0x18];
8516         u8         reserved_at_38[0x6];
8517         u8         wr_en[0x1];
8518         u8         rd_en[0x1];
8519 };
8520
8521 struct mlx5_ifc_query_wol_rol_out_bits {
8522         u8         status[0x8];
8523         u8         reserved_at_8[0x18];
8524
8525         u8         syndrome[0x20];
8526
8527         u8         reserved_at_40[0x10];
8528         u8         rol_mode[0x8];
8529         u8         wol_mode[0x8];
8530
8531         u8         reserved_at_60[0x20];
8532 };
8533
8534 struct mlx5_ifc_query_wol_rol_in_bits {
8535         u8         opcode[0x10];
8536         u8         reserved_at_10[0x10];
8537
8538         u8         reserved_at_20[0x10];
8539         u8         op_mod[0x10];
8540
8541         u8         reserved_at_40[0x40];
8542 };
8543
8544 struct mlx5_ifc_set_wol_rol_out_bits {
8545         u8         status[0x8];
8546         u8         reserved_at_8[0x18];
8547
8548         u8         syndrome[0x20];
8549
8550         u8         reserved_at_40[0x40];
8551 };
8552
8553 struct mlx5_ifc_set_wol_rol_in_bits {
8554         u8         opcode[0x10];
8555         u8         reserved_at_10[0x10];
8556
8557         u8         reserved_at_20[0x10];
8558         u8         op_mod[0x10];
8559
8560         u8         rol_mode_valid[0x1];
8561         u8         wol_mode_valid[0x1];
8562         u8         reserved_at_42[0xe];
8563         u8         rol_mode[0x8];
8564         u8         wol_mode[0x8];
8565
8566         u8         reserved_at_60[0x20];
8567 };
8568
8569 enum {
8570         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8571         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8572         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8573 };
8574
8575 enum {
8576         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8577         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8578         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8579 };
8580
8581 enum {
8582         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8583         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8584         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8585         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8586         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8587         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8588         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8589         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8590         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8591         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8592         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8593 };
8594
8595 struct mlx5_ifc_initial_seg_bits {
8596         u8         fw_rev_minor[0x10];
8597         u8         fw_rev_major[0x10];
8598
8599         u8         cmd_interface_rev[0x10];
8600         u8         fw_rev_subminor[0x10];
8601
8602         u8         reserved_at_40[0x40];
8603
8604         u8         cmdq_phy_addr_63_32[0x20];
8605
8606         u8         cmdq_phy_addr_31_12[0x14];
8607         u8         reserved_at_b4[0x2];
8608         u8         nic_interface[0x2];
8609         u8         log_cmdq_size[0x4];
8610         u8         log_cmdq_stride[0x4];
8611
8612         u8         command_doorbell_vector[0x20];
8613
8614         u8         reserved_at_e0[0xf00];
8615
8616         u8         initializing[0x1];
8617         u8         reserved_at_fe1[0x4];
8618         u8         nic_interface_supported[0x3];
8619         u8         reserved_at_fe8[0x18];
8620
8621         struct mlx5_ifc_health_buffer_bits health_buffer;
8622
8623         u8         no_dram_nic_offset[0x20];
8624
8625         u8         reserved_at_1220[0x6e40];
8626
8627         u8         reserved_at_8060[0x1f];
8628         u8         clear_int[0x1];
8629
8630         u8         health_syndrome[0x8];
8631         u8         health_counter[0x18];
8632
8633         u8         reserved_at_80a0[0x17fc0];
8634 };
8635
8636 struct mlx5_ifc_mtpps_reg_bits {
8637         u8         reserved_at_0[0xc];
8638         u8         cap_number_of_pps_pins[0x4];
8639         u8         reserved_at_10[0x4];
8640         u8         cap_max_num_of_pps_in_pins[0x4];
8641         u8         reserved_at_18[0x4];
8642         u8         cap_max_num_of_pps_out_pins[0x4];
8643
8644         u8         reserved_at_20[0x24];
8645         u8         cap_pin_3_mode[0x4];
8646         u8         reserved_at_48[0x4];
8647         u8         cap_pin_2_mode[0x4];
8648         u8         reserved_at_50[0x4];
8649         u8         cap_pin_1_mode[0x4];
8650         u8         reserved_at_58[0x4];
8651         u8         cap_pin_0_mode[0x4];
8652
8653         u8         reserved_at_60[0x4];
8654         u8         cap_pin_7_mode[0x4];
8655         u8         reserved_at_68[0x4];
8656         u8         cap_pin_6_mode[0x4];
8657         u8         reserved_at_70[0x4];
8658         u8         cap_pin_5_mode[0x4];
8659         u8         reserved_at_78[0x4];
8660         u8         cap_pin_4_mode[0x4];
8661
8662         u8         field_select[0x20];
8663         u8         reserved_at_a0[0x60];
8664
8665         u8         enable[0x1];
8666         u8         reserved_at_101[0xb];
8667         u8         pattern[0x4];
8668         u8         reserved_at_110[0x4];
8669         u8         pin_mode[0x4];
8670         u8         pin[0x8];
8671
8672         u8         reserved_at_120[0x20];
8673
8674         u8         time_stamp[0x40];
8675
8676         u8         out_pulse_duration[0x10];
8677         u8         out_periodic_adjustment[0x10];
8678         u8         enhanced_out_periodic_adjustment[0x20];
8679
8680         u8         reserved_at_1c0[0x20];
8681 };
8682
8683 struct mlx5_ifc_mtppse_reg_bits {
8684         u8         reserved_at_0[0x18];
8685         u8         pin[0x8];
8686         u8         event_arm[0x1];
8687         u8         reserved_at_21[0x1b];
8688         u8         event_generation_mode[0x4];
8689         u8         reserved_at_40[0x40];
8690 };
8691
8692 struct mlx5_ifc_mcqi_cap_bits {
8693         u8         supported_info_bitmask[0x20];
8694
8695         u8         component_size[0x20];
8696
8697         u8         max_component_size[0x20];
8698
8699         u8         log_mcda_word_size[0x4];
8700         u8         reserved_at_64[0xc];
8701         u8         mcda_max_write_size[0x10];
8702
8703         u8         rd_en[0x1];
8704         u8         reserved_at_81[0x1];
8705         u8         match_chip_id[0x1];
8706         u8         match_psid[0x1];
8707         u8         check_user_timestamp[0x1];
8708         u8         match_base_guid_mac[0x1];
8709         u8         reserved_at_86[0x1a];
8710 };
8711
8712 struct mlx5_ifc_mcqi_reg_bits {
8713         u8         read_pending_component[0x1];
8714         u8         reserved_at_1[0xf];
8715         u8         component_index[0x10];
8716
8717         u8         reserved_at_20[0x20];
8718
8719         u8         reserved_at_40[0x1b];
8720         u8         info_type[0x5];
8721
8722         u8         info_size[0x20];
8723
8724         u8         offset[0x20];
8725
8726         u8         reserved_at_a0[0x10];
8727         u8         data_size[0x10];
8728
8729         u8         data[0][0x20];
8730 };
8731
8732 struct mlx5_ifc_mcc_reg_bits {
8733         u8         reserved_at_0[0x4];
8734         u8         time_elapsed_since_last_cmd[0xc];
8735         u8         reserved_at_10[0x8];
8736         u8         instruction[0x8];
8737
8738         u8         reserved_at_20[0x10];
8739         u8         component_index[0x10];
8740
8741         u8         reserved_at_40[0x8];
8742         u8         update_handle[0x18];
8743
8744         u8         handle_owner_type[0x4];
8745         u8         handle_owner_host_id[0x4];
8746         u8         reserved_at_68[0x1];
8747         u8         control_progress[0x7];
8748         u8         error_code[0x8];
8749         u8         reserved_at_78[0x4];
8750         u8         control_state[0x4];
8751
8752         u8         component_size[0x20];
8753
8754         u8         reserved_at_a0[0x60];
8755 };
8756
8757 struct mlx5_ifc_mcda_reg_bits {
8758         u8         reserved_at_0[0x8];
8759         u8         update_handle[0x18];
8760
8761         u8         offset[0x20];
8762
8763         u8         reserved_at_40[0x10];
8764         u8         size[0x10];
8765
8766         u8         reserved_at_60[0x20];
8767
8768         u8         data[0][0x20];
8769 };
8770
8771 union mlx5_ifc_ports_control_registers_document_bits {
8772         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8773         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8774         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8775         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8776         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8777         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8778         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8779         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8780         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8781         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8782         struct mlx5_ifc_paos_reg_bits paos_reg;
8783         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8784         struct mlx5_ifc_peir_reg_bits peir_reg;
8785         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8786         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8787         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8788         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8789         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8790         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8791         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8792         struct mlx5_ifc_plib_reg_bits plib_reg;
8793         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8794         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8795         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8796         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8797         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8798         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8799         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8800         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8801         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8802         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8803         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8804         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8805         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8806         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8807         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8808         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8809         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8810         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8811         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8812         struct mlx5_ifc_pude_reg_bits pude_reg;
8813         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8814         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8815         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8816         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8817         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8818         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8819         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8820         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8821         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8822         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8823         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8824         u8         reserved_at_0[0x60e0];
8825 };
8826
8827 union mlx5_ifc_debug_enhancements_document_bits {
8828         struct mlx5_ifc_health_buffer_bits health_buffer;
8829         u8         reserved_at_0[0x200];
8830 };
8831
8832 union mlx5_ifc_uplink_pci_interface_document_bits {
8833         struct mlx5_ifc_initial_seg_bits initial_seg;
8834         u8         reserved_at_0[0x20060];
8835 };
8836
8837 struct mlx5_ifc_set_flow_table_root_out_bits {
8838         u8         status[0x8];
8839         u8         reserved_at_8[0x18];
8840
8841         u8         syndrome[0x20];
8842
8843         u8         reserved_at_40[0x40];
8844 };
8845
8846 struct mlx5_ifc_set_flow_table_root_in_bits {
8847         u8         opcode[0x10];
8848         u8         reserved_at_10[0x10];
8849
8850         u8         reserved_at_20[0x10];
8851         u8         op_mod[0x10];
8852
8853         u8         other_vport[0x1];
8854         u8         reserved_at_41[0xf];
8855         u8         vport_number[0x10];
8856
8857         u8         reserved_at_60[0x20];
8858
8859         u8         table_type[0x8];
8860         u8         reserved_at_88[0x18];
8861
8862         u8         reserved_at_a0[0x8];
8863         u8         table_id[0x18];
8864
8865         u8         reserved_at_c0[0x8];
8866         u8         underlay_qpn[0x18];
8867         u8         reserved_at_e0[0x120];
8868 };
8869
8870 enum {
8871         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8872         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8873 };
8874
8875 struct mlx5_ifc_modify_flow_table_out_bits {
8876         u8         status[0x8];
8877         u8         reserved_at_8[0x18];
8878
8879         u8         syndrome[0x20];
8880
8881         u8         reserved_at_40[0x40];
8882 };
8883
8884 struct mlx5_ifc_modify_flow_table_in_bits {
8885         u8         opcode[0x10];
8886         u8         reserved_at_10[0x10];
8887
8888         u8         reserved_at_20[0x10];
8889         u8         op_mod[0x10];
8890
8891         u8         other_vport[0x1];
8892         u8         reserved_at_41[0xf];
8893         u8         vport_number[0x10];
8894
8895         u8         reserved_at_60[0x10];
8896         u8         modify_field_select[0x10];
8897
8898         u8         table_type[0x8];
8899         u8         reserved_at_88[0x18];
8900
8901         u8         reserved_at_a0[0x8];
8902         u8         table_id[0x18];
8903
8904         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8905 };
8906
8907 struct mlx5_ifc_ets_tcn_config_reg_bits {
8908         u8         g[0x1];
8909         u8         b[0x1];
8910         u8         r[0x1];
8911         u8         reserved_at_3[0x9];
8912         u8         group[0x4];
8913         u8         reserved_at_10[0x9];
8914         u8         bw_allocation[0x7];
8915
8916         u8         reserved_at_20[0xc];
8917         u8         max_bw_units[0x4];
8918         u8         reserved_at_30[0x8];
8919         u8         max_bw_value[0x8];
8920 };
8921
8922 struct mlx5_ifc_ets_global_config_reg_bits {
8923         u8         reserved_at_0[0x2];
8924         u8         r[0x1];
8925         u8         reserved_at_3[0x1d];
8926
8927         u8         reserved_at_20[0xc];
8928         u8         max_bw_units[0x4];
8929         u8         reserved_at_30[0x8];
8930         u8         max_bw_value[0x8];
8931 };
8932
8933 struct mlx5_ifc_qetc_reg_bits {
8934         u8                                         reserved_at_0[0x8];
8935         u8                                         port_number[0x8];
8936         u8                                         reserved_at_10[0x30];
8937
8938         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8939         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8940 };
8941
8942 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8943         u8         e[0x1];
8944         u8         reserved_at_01[0x0b];
8945         u8         prio[0x04];
8946 };
8947
8948 struct mlx5_ifc_qpdpm_reg_bits {
8949         u8                                     reserved_at_0[0x8];
8950         u8                                     local_port[0x8];
8951         u8                                     reserved_at_10[0x10];
8952         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
8953 };
8954
8955 struct mlx5_ifc_qpts_reg_bits {
8956         u8         reserved_at_0[0x8];
8957         u8         local_port[0x8];
8958         u8         reserved_at_10[0x2d];
8959         u8         trust_state[0x3];
8960 };
8961
8962 struct mlx5_ifc_pptb_reg_bits {
8963         u8         reserved_at_0[0x2];
8964         u8         mm[0x2];
8965         u8         reserved_at_4[0x4];
8966         u8         local_port[0x8];
8967         u8         reserved_at_10[0x6];
8968         u8         cm[0x1];
8969         u8         um[0x1];
8970         u8         pm[0x8];
8971
8972         u8         prio_x_buff[0x20];
8973
8974         u8         pm_msb[0x8];
8975         u8         reserved_at_48[0x10];
8976         u8         ctrl_buff[0x4];
8977         u8         untagged_buff[0x4];
8978 };
8979
8980 struct mlx5_ifc_pbmc_reg_bits {
8981         u8         reserved_at_0[0x8];
8982         u8         local_port[0x8];
8983         u8         reserved_at_10[0x10];
8984
8985         u8         xoff_timer_value[0x10];
8986         u8         xoff_refresh[0x10];
8987
8988         u8         reserved_at_40[0x9];
8989         u8         fullness_threshold[0x7];
8990         u8         port_buffer_size[0x10];
8991
8992         struct mlx5_ifc_bufferx_reg_bits buffer[10];
8993
8994         u8         reserved_at_2e0[0x40];
8995 };
8996
8997 struct mlx5_ifc_qtct_reg_bits {
8998         u8         reserved_at_0[0x8];
8999         u8         port_number[0x8];
9000         u8         reserved_at_10[0xd];
9001         u8         prio[0x3];
9002
9003         u8         reserved_at_20[0x1d];
9004         u8         tclass[0x3];
9005 };
9006
9007 struct mlx5_ifc_mcia_reg_bits {
9008         u8         l[0x1];
9009         u8         reserved_at_1[0x7];
9010         u8         module[0x8];
9011         u8         reserved_at_10[0x8];
9012         u8         status[0x8];
9013
9014         u8         i2c_device_address[0x8];
9015         u8         page_number[0x8];
9016         u8         device_address[0x10];
9017
9018         u8         reserved_at_40[0x10];
9019         u8         size[0x10];
9020
9021         u8         reserved_at_60[0x20];
9022
9023         u8         dword_0[0x20];
9024         u8         dword_1[0x20];
9025         u8         dword_2[0x20];
9026         u8         dword_3[0x20];
9027         u8         dword_4[0x20];
9028         u8         dword_5[0x20];
9029         u8         dword_6[0x20];
9030         u8         dword_7[0x20];
9031         u8         dword_8[0x20];
9032         u8         dword_9[0x20];
9033         u8         dword_10[0x20];
9034         u8         dword_11[0x20];
9035 };
9036
9037 struct mlx5_ifc_dcbx_param_bits {
9038         u8         dcbx_cee_cap[0x1];
9039         u8         dcbx_ieee_cap[0x1];
9040         u8         dcbx_standby_cap[0x1];
9041         u8         reserved_at_3[0x5];
9042         u8         port_number[0x8];
9043         u8         reserved_at_10[0xa];
9044         u8         max_application_table_size[6];
9045         u8         reserved_at_20[0x15];
9046         u8         version_oper[0x3];
9047         u8         reserved_at_38[5];
9048         u8         version_admin[0x3];
9049         u8         willing_admin[0x1];
9050         u8         reserved_at_41[0x3];
9051         u8         pfc_cap_oper[0x4];
9052         u8         reserved_at_48[0x4];
9053         u8         pfc_cap_admin[0x4];
9054         u8         reserved_at_50[0x4];
9055         u8         num_of_tc_oper[0x4];
9056         u8         reserved_at_58[0x4];
9057         u8         num_of_tc_admin[0x4];
9058         u8         remote_willing[0x1];
9059         u8         reserved_at_61[3];
9060         u8         remote_pfc_cap[4];
9061         u8         reserved_at_68[0x14];
9062         u8         remote_num_of_tc[0x4];
9063         u8         reserved_at_80[0x18];
9064         u8         error[0x8];
9065         u8         reserved_at_a0[0x160];
9066 };
9067
9068 struct mlx5_ifc_lagc_bits {
9069         u8         reserved_at_0[0x1d];
9070         u8         lag_state[0x3];
9071
9072         u8         reserved_at_20[0x14];
9073         u8         tx_remap_affinity_2[0x4];
9074         u8         reserved_at_38[0x4];
9075         u8         tx_remap_affinity_1[0x4];
9076 };
9077
9078 struct mlx5_ifc_create_lag_out_bits {
9079         u8         status[0x8];
9080         u8         reserved_at_8[0x18];
9081
9082         u8         syndrome[0x20];
9083
9084         u8         reserved_at_40[0x40];
9085 };
9086
9087 struct mlx5_ifc_create_lag_in_bits {
9088         u8         opcode[0x10];
9089         u8         reserved_at_10[0x10];
9090
9091         u8         reserved_at_20[0x10];
9092         u8         op_mod[0x10];
9093
9094         struct mlx5_ifc_lagc_bits ctx;
9095 };
9096
9097 struct mlx5_ifc_modify_lag_out_bits {
9098         u8         status[0x8];
9099         u8         reserved_at_8[0x18];
9100
9101         u8         syndrome[0x20];
9102
9103         u8         reserved_at_40[0x40];
9104 };
9105
9106 struct mlx5_ifc_modify_lag_in_bits {
9107         u8         opcode[0x10];
9108         u8         reserved_at_10[0x10];
9109
9110         u8         reserved_at_20[0x10];
9111         u8         op_mod[0x10];
9112
9113         u8         reserved_at_40[0x20];
9114         u8         field_select[0x20];
9115
9116         struct mlx5_ifc_lagc_bits ctx;
9117 };
9118
9119 struct mlx5_ifc_query_lag_out_bits {
9120         u8         status[0x8];
9121         u8         reserved_at_8[0x18];
9122
9123         u8         syndrome[0x20];
9124
9125         u8         reserved_at_40[0x40];
9126
9127         struct mlx5_ifc_lagc_bits ctx;
9128 };
9129
9130 struct mlx5_ifc_query_lag_in_bits {
9131         u8         opcode[0x10];
9132         u8         reserved_at_10[0x10];
9133
9134         u8         reserved_at_20[0x10];
9135         u8         op_mod[0x10];
9136
9137         u8         reserved_at_40[0x40];
9138 };
9139
9140 struct mlx5_ifc_destroy_lag_out_bits {
9141         u8         status[0x8];
9142         u8         reserved_at_8[0x18];
9143
9144         u8         syndrome[0x20];
9145
9146         u8         reserved_at_40[0x40];
9147 };
9148
9149 struct mlx5_ifc_destroy_lag_in_bits {
9150         u8         opcode[0x10];
9151         u8         reserved_at_10[0x10];
9152
9153         u8         reserved_at_20[0x10];
9154         u8         op_mod[0x10];
9155
9156         u8         reserved_at_40[0x40];
9157 };
9158
9159 struct mlx5_ifc_create_vport_lag_out_bits {
9160         u8         status[0x8];
9161         u8         reserved_at_8[0x18];
9162
9163         u8         syndrome[0x20];
9164
9165         u8         reserved_at_40[0x40];
9166 };
9167
9168 struct mlx5_ifc_create_vport_lag_in_bits {
9169         u8         opcode[0x10];
9170         u8         reserved_at_10[0x10];
9171
9172         u8         reserved_at_20[0x10];
9173         u8         op_mod[0x10];
9174
9175         u8         reserved_at_40[0x40];
9176 };
9177
9178 struct mlx5_ifc_destroy_vport_lag_out_bits {
9179         u8         status[0x8];
9180         u8         reserved_at_8[0x18];
9181
9182         u8         syndrome[0x20];
9183
9184         u8         reserved_at_40[0x40];
9185 };
9186
9187 struct mlx5_ifc_destroy_vport_lag_in_bits {
9188         u8         opcode[0x10];
9189         u8         reserved_at_10[0x10];
9190
9191         u8         reserved_at_20[0x10];
9192         u8         op_mod[0x10];
9193
9194         u8         reserved_at_40[0x40];
9195 };
9196
9197 struct mlx5_ifc_alloc_memic_in_bits {
9198         u8         opcode[0x10];
9199         u8         reserved_at_10[0x10];
9200
9201         u8         reserved_at_20[0x10];
9202         u8         op_mod[0x10];
9203
9204         u8         reserved_at_30[0x20];
9205
9206         u8         reserved_at_40[0x18];
9207         u8         log_memic_addr_alignment[0x8];
9208
9209         u8         range_start_addr[0x40];
9210
9211         u8         range_size[0x20];
9212
9213         u8         memic_size[0x20];
9214 };
9215
9216 struct mlx5_ifc_alloc_memic_out_bits {
9217         u8         status[0x8];
9218         u8         reserved_at_8[0x18];
9219
9220         u8         syndrome[0x20];
9221
9222         u8         memic_start_addr[0x40];
9223 };
9224
9225 struct mlx5_ifc_dealloc_memic_in_bits {
9226         u8         opcode[0x10];
9227         u8         reserved_at_10[0x10];
9228
9229         u8         reserved_at_20[0x10];
9230         u8         op_mod[0x10];
9231
9232         u8         reserved_at_40[0x40];
9233
9234         u8         memic_start_addr[0x40];
9235
9236         u8         memic_size[0x20];
9237
9238         u8         reserved_at_e0[0x20];
9239 };
9240
9241 struct mlx5_ifc_dealloc_memic_out_bits {
9242         u8         status[0x8];
9243         u8         reserved_at_8[0x18];
9244
9245         u8         syndrome[0x20];
9246
9247         u8         reserved_at_40[0x40];
9248 };
9249
9250 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9251         u8         opcode[0x10];
9252         u8         uid[0x10];
9253
9254         u8         reserved_at_20[0x10];
9255         u8         obj_type[0x10];
9256
9257         u8         obj_id[0x20];
9258
9259         u8         reserved_at_60[0x20];
9260 };
9261
9262 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9263         u8         status[0x8];
9264         u8         reserved_at_8[0x18];
9265
9266         u8         syndrome[0x20];
9267
9268         u8         obj_id[0x20];
9269
9270         u8         reserved_at_60[0x20];
9271 };
9272
9273 struct mlx5_ifc_umem_bits {
9274         u8         modify_field_select[0x40];
9275
9276         u8         reserved_at_40[0x5b];
9277         u8         log_page_size[0x5];
9278
9279         u8         page_offset[0x20];
9280
9281         u8         num_of_mtt[0x40];
9282
9283         struct mlx5_ifc_mtt_bits  mtt[0];
9284 };
9285
9286 struct mlx5_ifc_uctx_bits {
9287         u8         modify_field_select[0x40];
9288
9289         u8         cap[0x20];
9290
9291         u8         reserved_at_60[0x1a0];
9292 };
9293
9294 struct mlx5_ifc_create_umem_in_bits {
9295         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9296         struct mlx5_ifc_umem_bits                     umem;
9297 };
9298
9299 struct mlx5_ifc_create_uctx_in_bits {
9300         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9301         struct mlx5_ifc_uctx_bits                     uctx;
9302 };
9303
9304 struct mlx5_ifc_mtrc_string_db_param_bits {
9305         u8         string_db_base_address[0x20];
9306
9307         u8         reserved_at_20[0x8];
9308         u8         string_db_size[0x18];
9309 };
9310
9311 struct mlx5_ifc_mtrc_cap_bits {
9312         u8         trace_owner[0x1];
9313         u8         trace_to_memory[0x1];
9314         u8         reserved_at_2[0x4];
9315         u8         trc_ver[0x2];
9316         u8         reserved_at_8[0x14];
9317         u8         num_string_db[0x4];
9318
9319         u8         first_string_trace[0x8];
9320         u8         num_string_trace[0x8];
9321         u8         reserved_at_30[0x28];
9322
9323         u8         log_max_trace_buffer_size[0x8];
9324
9325         u8         reserved_at_60[0x20];
9326
9327         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9328
9329         u8         reserved_at_280[0x180];
9330 };
9331
9332 struct mlx5_ifc_mtrc_conf_bits {
9333         u8         reserved_at_0[0x1c];
9334         u8         trace_mode[0x4];
9335         u8         reserved_at_20[0x18];
9336         u8         log_trace_buffer_size[0x8];
9337         u8         trace_mkey[0x20];
9338         u8         reserved_at_60[0x3a0];
9339 };
9340
9341 struct mlx5_ifc_mtrc_stdb_bits {
9342         u8         string_db_index[0x4];
9343         u8         reserved_at_4[0x4];
9344         u8         read_size[0x18];
9345         u8         start_offset[0x20];
9346         u8         string_db_data[0];
9347 };
9348
9349 struct mlx5_ifc_mtrc_ctrl_bits {
9350         u8         trace_status[0x2];
9351         u8         reserved_at_2[0x2];
9352         u8         arm_event[0x1];
9353         u8         reserved_at_5[0xb];
9354         u8         modify_field_select[0x10];
9355         u8         reserved_at_20[0x2b];
9356         u8         current_timestamp52_32[0x15];
9357         u8         current_timestamp31_0[0x20];
9358         u8         reserved_at_80[0x180];
9359 };
9360
9361 #endif /* MLX5_IFC_H */