2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4),
80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5),
84 MLX5_OBJ_TYPE_UCTX = 0x0004,
85 MLX5_OBJ_TYPE_UMEM = 0x0005,
89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
91 MLX5_CMD_OP_INIT_HCA = 0x102,
92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
93 MLX5_CMD_OP_ENABLE_HCA = 0x104,
94 MLX5_CMD_OP_DISABLE_HCA = 0x105,
95 MLX5_CMD_OP_QUERY_PAGES = 0x107,
96 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
97 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
98 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
99 MLX5_CMD_OP_SET_ISSI = 0x10b,
100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
101 MLX5_CMD_OP_CREATE_MKEY = 0x200,
102 MLX5_CMD_OP_QUERY_MKEY = 0x201,
103 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
108 MLX5_CMD_OP_CREATE_EQ = 0x301,
109 MLX5_CMD_OP_DESTROY_EQ = 0x302,
110 MLX5_CMD_OP_QUERY_EQ = 0x303,
111 MLX5_CMD_OP_GEN_EQE = 0x304,
112 MLX5_CMD_OP_CREATE_CQ = 0x400,
113 MLX5_CMD_OP_DESTROY_CQ = 0x401,
114 MLX5_CMD_OP_QUERY_CQ = 0x402,
115 MLX5_CMD_OP_MODIFY_CQ = 0x403,
116 MLX5_CMD_OP_CREATE_QP = 0x500,
117 MLX5_CMD_OP_DESTROY_QP = 0x501,
118 MLX5_CMD_OP_RST2INIT_QP = 0x502,
119 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
120 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
121 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
123 MLX5_CMD_OP_2ERR_QP = 0x507,
124 MLX5_CMD_OP_2RST_QP = 0x50a,
125 MLX5_CMD_OP_QUERY_QP = 0x50b,
126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
128 MLX5_CMD_OP_CREATE_PSV = 0x600,
129 MLX5_CMD_OP_DESTROY_PSV = 0x601,
130 MLX5_CMD_OP_CREATE_SRQ = 0x700,
131 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
132 MLX5_CMD_OP_QUERY_SRQ = 0x702,
133 MLX5_CMD_OP_ARM_RQ = 0x703,
134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
138 MLX5_CMD_OP_CREATE_DCT = 0x710,
139 MLX5_CMD_OP_DESTROY_DCT = 0x711,
140 MLX5_CMD_OP_DRAIN_DCT = 0x712,
141 MLX5_CMD_OP_QUERY_DCT = 0x713,
142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
143 MLX5_CMD_OP_CREATE_XRQ = 0x717,
144 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
145 MLX5_CMD_OP_QUERY_XRQ = 0x719,
146 MLX5_CMD_OP_ARM_XRQ = 0x71a,
147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
172 MLX5_CMD_OP_ALLOC_PD = 0x800,
173 MLX5_CMD_OP_DEALLOC_PD = 0x801,
174 MLX5_CMD_OP_ALLOC_UAR = 0x802,
175 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
177 MLX5_CMD_OP_ACCESS_REG = 0x805,
178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
181 MLX5_CMD_OP_MAD_IFC = 0x50d,
182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
184 MLX5_CMD_OP_NOP = 0x80d,
185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
199 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
201 MLX5_CMD_OP_CREATE_LAG = 0x840,
202 MLX5_CMD_OP_MODIFY_LAG = 0x841,
203 MLX5_CMD_OP_QUERY_LAG = 0x842,
204 MLX5_CMD_OP_DESTROY_LAG = 0x843,
205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
207 MLX5_CMD_OP_CREATE_TIR = 0x900,
208 MLX5_CMD_OP_MODIFY_TIR = 0x901,
209 MLX5_CMD_OP_DESTROY_TIR = 0x902,
210 MLX5_CMD_OP_QUERY_TIR = 0x903,
211 MLX5_CMD_OP_CREATE_SQ = 0x904,
212 MLX5_CMD_OP_MODIFY_SQ = 0x905,
213 MLX5_CMD_OP_DESTROY_SQ = 0x906,
214 MLX5_CMD_OP_QUERY_SQ = 0x907,
215 MLX5_CMD_OP_CREATE_RQ = 0x908,
216 MLX5_CMD_OP_MODIFY_RQ = 0x909,
217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
218 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
219 MLX5_CMD_OP_QUERY_RQ = 0x90b,
220 MLX5_CMD_OP_CREATE_RMP = 0x90c,
221 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
222 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
223 MLX5_CMD_OP_QUERY_RMP = 0x90f,
224 MLX5_CMD_OP_CREATE_TIS = 0x912,
225 MLX5_CMD_OP_MODIFY_TIS = 0x913,
226 MLX5_CMD_OP_DESTROY_TIS = 0x914,
227 MLX5_CMD_OP_QUERY_TIS = 0x915,
228 MLX5_CMD_OP_CREATE_RQT = 0x916,
229 MLX5_CMD_OP_MODIFY_RQT = 0x917,
230 MLX5_CMD_OP_DESTROY_RQT = 0x918,
231 MLX5_CMD_OP_QUERY_RQT = 0x919,
232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
246 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
247 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
263 struct mlx5_ifc_flow_table_fields_supported_bits {
266 u8 outer_ether_type[0x1];
267 u8 outer_ip_version[0x1];
268 u8 outer_first_prio[0x1];
269 u8 outer_first_cfi[0x1];
270 u8 outer_first_vid[0x1];
271 u8 outer_ipv4_ttl[0x1];
272 u8 outer_second_prio[0x1];
273 u8 outer_second_cfi[0x1];
274 u8 outer_second_vid[0x1];
275 u8 reserved_at_b[0x1];
279 u8 outer_ip_protocol[0x1];
280 u8 outer_ip_ecn[0x1];
281 u8 outer_ip_dscp[0x1];
282 u8 outer_udp_sport[0x1];
283 u8 outer_udp_dport[0x1];
284 u8 outer_tcp_sport[0x1];
285 u8 outer_tcp_dport[0x1];
286 u8 outer_tcp_flags[0x1];
287 u8 outer_gre_protocol[0x1];
288 u8 outer_gre_key[0x1];
289 u8 outer_vxlan_vni[0x1];
290 u8 reserved_at_1a[0x5];
291 u8 source_eswitch_port[0x1];
295 u8 inner_ether_type[0x1];
296 u8 inner_ip_version[0x1];
297 u8 inner_first_prio[0x1];
298 u8 inner_first_cfi[0x1];
299 u8 inner_first_vid[0x1];
300 u8 reserved_at_27[0x1];
301 u8 inner_second_prio[0x1];
302 u8 inner_second_cfi[0x1];
303 u8 inner_second_vid[0x1];
304 u8 reserved_at_2b[0x1];
308 u8 inner_ip_protocol[0x1];
309 u8 inner_ip_ecn[0x1];
310 u8 inner_ip_dscp[0x1];
311 u8 inner_udp_sport[0x1];
312 u8 inner_udp_dport[0x1];
313 u8 inner_tcp_sport[0x1];
314 u8 inner_tcp_dport[0x1];
315 u8 inner_tcp_flags[0x1];
316 u8 reserved_at_37[0x9];
318 u8 reserved_at_40[0x5];
319 u8 outer_first_mpls_over_udp[0x4];
320 u8 outer_first_mpls_over_gre[0x4];
321 u8 inner_first_mpls[0x4];
322 u8 outer_first_mpls[0x4];
323 u8 reserved_at_55[0x2];
324 u8 outer_esp_spi[0x1];
325 u8 reserved_at_58[0x2];
328 u8 reserved_at_5b[0x25];
331 struct mlx5_ifc_flow_table_prop_layout_bits {
333 u8 reserved_at_1[0x1];
334 u8 flow_counter[0x1];
335 u8 flow_modify_en[0x1];
337 u8 identified_miss_table_mode[0x1];
338 u8 flow_table_modify[0x1];
341 u8 reserved_at_9[0x1];
344 u8 reserved_at_c[0x1];
347 u8 reformat_and_vlan_action[0x1];
348 u8 reserved_at_10[0x2];
349 u8 reformat_l3_tunnel_to_l2[0x1];
350 u8 reformat_l2_to_l3_tunnel[0x1];
351 u8 reformat_and_modify_action[0x1];
352 u8 reserved_at_15[0xb];
353 u8 reserved_at_20[0x2];
354 u8 log_max_ft_size[0x6];
355 u8 log_max_modify_header_context[0x8];
356 u8 max_modify_header_actions[0x8];
357 u8 max_ft_level[0x8];
359 u8 reserved_at_40[0x20];
361 u8 reserved_at_60[0x18];
362 u8 log_max_ft_num[0x8];
364 u8 reserved_at_80[0x18];
365 u8 log_max_destination[0x8];
367 u8 log_max_flow_counter[0x8];
368 u8 reserved_at_a8[0x10];
369 u8 log_max_flow[0x8];
371 u8 reserved_at_c0[0x40];
373 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
375 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
378 struct mlx5_ifc_odp_per_transport_service_cap_bits {
385 u8 reserved_at_6[0x1a];
388 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
413 u8 reserved_at_c0[0x18];
414 u8 ttl_hoplimit[0x8];
419 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
421 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
424 struct mlx5_ifc_fte_match_set_misc_bits {
425 u8 reserved_at_0[0x8];
428 u8 source_eswitch_owner_vhca_id[0x10];
429 u8 source_port[0x10];
431 u8 outer_second_prio[0x3];
432 u8 outer_second_cfi[0x1];
433 u8 outer_second_vid[0xc];
434 u8 inner_second_prio[0x3];
435 u8 inner_second_cfi[0x1];
436 u8 inner_second_vid[0xc];
438 u8 outer_second_cvlan_tag[0x1];
439 u8 inner_second_cvlan_tag[0x1];
440 u8 outer_second_svlan_tag[0x1];
441 u8 inner_second_svlan_tag[0x1];
442 u8 reserved_at_64[0xc];
443 u8 gre_protocol[0x10];
449 u8 reserved_at_b8[0x8];
451 u8 reserved_at_c0[0x20];
453 u8 reserved_at_e0[0xc];
454 u8 outer_ipv6_flow_label[0x14];
456 u8 reserved_at_100[0xc];
457 u8 inner_ipv6_flow_label[0x14];
459 u8 reserved_at_120[0x28];
461 u8 reserved_at_160[0x20];
462 u8 outer_esp_spi[0x20];
463 u8 reserved_at_1a0[0x60];
466 struct mlx5_ifc_fte_match_mpls_bits {
473 struct mlx5_ifc_fte_match_set_misc2_bits {
474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
476 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
478 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
480 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
482 u8 reserved_at_80[0x100];
484 u8 metadata_reg_a[0x20];
486 u8 reserved_at_1a0[0x60];
489 struct mlx5_ifc_cmd_pas_bits {
493 u8 reserved_at_34[0xc];
496 struct mlx5_ifc_uint64_bits {
503 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
504 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
505 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
506 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
507 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
508 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
509 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
510 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
511 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
512 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
515 struct mlx5_ifc_ads_bits {
518 u8 reserved_at_2[0xe];
521 u8 reserved_at_20[0x8];
527 u8 reserved_at_45[0x3];
528 u8 src_addr_index[0x8];
529 u8 reserved_at_50[0x4];
533 u8 reserved_at_60[0x4];
537 u8 rgid_rip[16][0x8];
539 u8 reserved_at_100[0x4];
542 u8 reserved_at_106[0x1];
551 u8 vhca_port_num[0x8];
557 struct mlx5_ifc_flow_table_nic_cap_bits {
558 u8 nic_rx_multi_path_tirs[0x1];
559 u8 nic_rx_multi_path_tirs_fts[0x1];
560 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
561 u8 reserved_at_3[0x1d];
562 u8 encap_general_header[0x1];
563 u8 reserved_at_21[0xa];
564 u8 log_max_packet_reformat_context[0x5];
565 u8 reserved_at_30[0x6];
566 u8 max_encap_header_size[0xa];
567 u8 reserved_at_40[0x1c0];
569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
571 u8 reserved_at_400[0x200];
573 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
575 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
577 u8 reserved_at_a00[0x200];
579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
581 u8 reserved_at_e00[0x7200];
584 struct mlx5_ifc_flow_table_eswitch_cap_bits {
585 u8 reserved_at_0[0x1c];
586 u8 fdb_multi_path_to_table[0x1];
587 u8 reserved_at_1d[0x1];
588 u8 multi_fdb_encap[0x1];
589 u8 reserved_at_1f[0x1e1];
591 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
593 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
595 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
597 u8 reserved_at_800[0x7800];
600 struct mlx5_ifc_e_switch_cap_bits {
601 u8 vport_svlan_strip[0x1];
602 u8 vport_cvlan_strip[0x1];
603 u8 vport_svlan_insert[0x1];
604 u8 vport_cvlan_insert_if_not_exist[0x1];
605 u8 vport_cvlan_insert_overwrite[0x1];
606 u8 reserved_at_5[0x18];
607 u8 merged_eswitch[0x1];
608 u8 nic_vport_node_guid_modify[0x1];
609 u8 nic_vport_port_guid_modify[0x1];
611 u8 vxlan_encap_decap[0x1];
612 u8 nvgre_encap_decap[0x1];
613 u8 reserved_at_22[0x9];
614 u8 log_max_packet_reformat_context[0x5];
616 u8 max_encap_header_size[0xa];
618 u8 reserved_40[0x7c0];
622 struct mlx5_ifc_qos_cap_bits {
623 u8 packet_pacing[0x1];
624 u8 esw_scheduling[0x1];
625 u8 esw_bw_share[0x1];
626 u8 esw_rate_limit[0x1];
627 u8 reserved_at_4[0x1];
628 u8 packet_pacing_burst_bound[0x1];
629 u8 packet_pacing_typical_size[0x1];
630 u8 reserved_at_7[0x19];
632 u8 reserved_at_20[0x20];
634 u8 packet_pacing_max_rate[0x20];
636 u8 packet_pacing_min_rate[0x20];
638 u8 reserved_at_80[0x10];
639 u8 packet_pacing_rate_table_size[0x10];
641 u8 esw_element_type[0x10];
642 u8 esw_tsar_type[0x10];
644 u8 reserved_at_c0[0x10];
645 u8 max_qos_para_vport[0x10];
647 u8 max_tsar_bw_share[0x20];
649 u8 reserved_at_100[0x700];
652 struct mlx5_ifc_debug_cap_bits {
653 u8 reserved_at_0[0x20];
655 u8 reserved_at_20[0x2];
656 u8 stall_detect[0x1];
657 u8 reserved_at_23[0x1d];
659 u8 reserved_at_40[0x7c0];
662 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
666 u8 lro_psh_flag[0x1];
667 u8 lro_time_stamp[0x1];
668 u8 reserved_at_5[0x2];
669 u8 wqe_vlan_insert[0x1];
670 u8 self_lb_en_modifiable[0x1];
671 u8 reserved_at_9[0x2];
673 u8 multi_pkt_send_wqe[0x2];
674 u8 wqe_inline_mode[0x2];
675 u8 rss_ind_tbl_cap[0x4];
678 u8 enhanced_multi_pkt_send_wqe[0x1];
679 u8 tunnel_lso_const_out_ip_id[0x1];
680 u8 reserved_at_1c[0x2];
681 u8 tunnel_stateless_gre[0x1];
682 u8 tunnel_stateless_vxlan[0x1];
687 u8 reserved_at_23[0xd];
688 u8 max_vxlan_udp_ports[0x8];
689 u8 reserved_at_38[0x6];
690 u8 max_geneve_opt_len[0x1];
691 u8 tunnel_stateless_geneve_rx[0x1];
693 u8 reserved_at_40[0x10];
694 u8 lro_min_mss_size[0x10];
696 u8 reserved_at_60[0x120];
698 u8 lro_timer_supported_periods[4][0x20];
700 u8 reserved_at_200[0x600];
703 struct mlx5_ifc_roce_cap_bits {
705 u8 reserved_at_1[0x1f];
707 u8 reserved_at_20[0x60];
709 u8 reserved_at_80[0xc];
711 u8 reserved_at_90[0x8];
712 u8 roce_version[0x8];
714 u8 reserved_at_a0[0x10];
715 u8 r_roce_dest_udp_port[0x10];
717 u8 r_roce_max_src_udp_port[0x10];
718 u8 r_roce_min_src_udp_port[0x10];
720 u8 reserved_at_e0[0x10];
721 u8 roce_address_table_size[0x10];
723 u8 reserved_at_100[0x700];
726 struct mlx5_ifc_device_mem_cap_bits {
728 u8 reserved_at_1[0x1f];
730 u8 reserved_at_20[0xb];
731 u8 log_min_memic_alloc_size[0x5];
732 u8 reserved_at_30[0x8];
733 u8 log_max_memic_addr_alignment[0x8];
735 u8 memic_bar_start_addr[0x40];
737 u8 memic_bar_size[0x20];
739 u8 max_memic_size[0x20];
741 u8 reserved_at_c0[0x740];
745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
749 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
750 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
751 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
757 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
758 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
759 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
760 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
761 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
762 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
763 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
764 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
765 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
768 struct mlx5_ifc_atomic_caps_bits {
769 u8 reserved_at_0[0x40];
771 u8 atomic_req_8B_endianness_mode[0x2];
772 u8 reserved_at_42[0x4];
773 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
775 u8 reserved_at_47[0x19];
777 u8 reserved_at_60[0x20];
779 u8 reserved_at_80[0x10];
780 u8 atomic_operations[0x10];
782 u8 reserved_at_a0[0x10];
783 u8 atomic_size_qp[0x10];
785 u8 reserved_at_c0[0x10];
786 u8 atomic_size_dc[0x10];
788 u8 reserved_at_e0[0x720];
791 struct mlx5_ifc_odp_cap_bits {
792 u8 reserved_at_0[0x40];
795 u8 reserved_at_41[0x1f];
797 u8 reserved_at_60[0x20];
799 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
801 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
803 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
805 u8 reserved_at_e0[0x720];
808 struct mlx5_ifc_calc_op {
809 u8 reserved_at_0[0x10];
810 u8 reserved_at_10[0x9];
811 u8 op_swap_endianness[0x1];
820 struct mlx5_ifc_vector_calc_cap_bits {
822 u8 reserved_at_1[0x1f];
823 u8 reserved_at_20[0x8];
824 u8 max_vec_count[0x8];
825 u8 reserved_at_30[0xd];
826 u8 max_chunk_size[0x3];
827 struct mlx5_ifc_calc_op calc0;
828 struct mlx5_ifc_calc_op calc1;
829 struct mlx5_ifc_calc_op calc2;
830 struct mlx5_ifc_calc_op calc3;
832 u8 reserved_at_c0[0x720];
836 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
837 MLX5_WQ_TYPE_CYCLIC = 0x1,
838 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
839 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
843 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
844 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
848 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
849 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
850 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
851 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
852 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
856 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
857 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
858 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
859 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
860 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
861 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
865 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
866 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
870 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
871 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
872 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
876 MLX5_CAP_PORT_TYPE_IB = 0x0,
877 MLX5_CAP_PORT_TYPE_ETH = 0x1,
881 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
882 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
883 MLX5_CAP_UMR_FENCE_NONE = 0x2,
887 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
890 struct mlx5_ifc_cmd_hca_cap_bits {
891 u8 reserved_at_0[0x30];
894 u8 reserved_at_40[0x40];
896 u8 log_max_srq_sz[0x8];
897 u8 log_max_qp_sz[0x8];
898 u8 reserved_at_90[0xb];
901 u8 reserved_at_a0[0xb];
903 u8 reserved_at_b0[0x10];
905 u8 reserved_at_c0[0x8];
906 u8 log_max_cq_sz[0x8];
907 u8 reserved_at_d0[0xb];
910 u8 log_max_eq_sz[0x8];
911 u8 reserved_at_e8[0x2];
912 u8 log_max_mkey[0x6];
913 u8 reserved_at_f0[0x8];
914 u8 dump_fill_mkey[0x1];
915 u8 reserved_at_f9[0x2];
916 u8 fast_teardown[0x1];
919 u8 max_indirection[0x8];
920 u8 fixed_buffer_size[0x1];
921 u8 log_max_mrw_sz[0x7];
922 u8 force_teardown[0x1];
923 u8 reserved_at_111[0x1];
924 u8 log_max_bsf_list_size[0x6];
925 u8 umr_extended_translation_offset[0x1];
927 u8 log_max_klm_list_size[0x6];
929 u8 reserved_at_120[0xa];
930 u8 log_max_ra_req_dc[0x6];
931 u8 reserved_at_130[0xa];
932 u8 log_max_ra_res_dc[0x6];
934 u8 reserved_at_140[0xa];
935 u8 log_max_ra_req_qp[0x6];
936 u8 reserved_at_150[0xa];
937 u8 log_max_ra_res_qp[0x6];
940 u8 cc_query_allowed[0x1];
941 u8 cc_modify_allowed[0x1];
943 u8 cache_line_128byte[0x1];
944 u8 reserved_at_165[0xa];
946 u8 gid_table_size[0x10];
948 u8 out_of_seq_cnt[0x1];
949 u8 vport_counters[0x1];
950 u8 retransmission_q_counters[0x1];
952 u8 modify_rq_counter_set_id[0x1];
953 u8 rq_delay_drop[0x1];
955 u8 pkey_table_size[0x10];
957 u8 vport_group_manager[0x1];
958 u8 vhca_group_manager[0x1];
961 u8 vnic_env_queue_counters[0x1];
963 u8 nic_flow_table[0x1];
964 u8 eswitch_manager[0x1];
965 u8 device_memory[0x1];
968 u8 local_ca_ack_delay[0x5];
969 u8 port_module_event[0x1];
970 u8 enhanced_error_q_counters[0x1];
972 u8 reserved_at_1b3[0x1];
973 u8 disable_link_up[0x1];
978 u8 reserved_at_1c0[0x1];
982 u8 reserved_at_1c8[0x4];
984 u8 temp_warn_event[0x1];
986 u8 general_notification_event[0x1];
987 u8 reserved_at_1d3[0x2];
991 u8 reserved_at_1d8[0x1];
1000 u8 stat_rate_support[0x10];
1001 u8 reserved_at_1f0[0xc];
1002 u8 cqe_version[0x4];
1004 u8 compact_address_vector[0x1];
1005 u8 striding_rq[0x1];
1006 u8 reserved_at_202[0x1];
1007 u8 ipoib_enhanced_offloads[0x1];
1008 u8 ipoib_basic_offloads[0x1];
1009 u8 reserved_at_205[0x1];
1010 u8 repeated_block_disabled[0x1];
1011 u8 umr_modify_entity_size_disabled[0x1];
1012 u8 umr_modify_atomic_disabled[0x1];
1013 u8 umr_indirect_mkey_disabled[0x1];
1015 u8 dc_req_scat_data_cqe[0x1];
1016 u8 reserved_at_20d[0x2];
1017 u8 drain_sigerr[0x1];
1018 u8 cmdif_checksum[0x2];
1020 u8 reserved_at_213[0x1];
1021 u8 wq_signature[0x1];
1022 u8 sctr_data_cqe[0x1];
1023 u8 reserved_at_216[0x1];
1029 u8 eth_net_offloads[0x1];
1032 u8 reserved_at_21f[0x1];
1036 u8 cq_moderation[0x1];
1037 u8 reserved_at_223[0x3];
1038 u8 cq_eq_remap[0x1];
1040 u8 block_lb_mc[0x1];
1041 u8 reserved_at_229[0x1];
1042 u8 scqe_break_moderation[0x1];
1043 u8 cq_period_start_from_cqe[0x1];
1045 u8 reserved_at_22d[0x1];
1047 u8 vector_calc[0x1];
1048 u8 umr_ptr_rlky[0x1];
1050 u8 reserved_at_232[0x4];
1053 u8 set_deth_sqpn[0x1];
1054 u8 reserved_at_239[0x3];
1061 u8 reserved_at_241[0x9];
1063 u8 reserved_at_250[0x8];
1067 u8 driver_version[0x1];
1068 u8 pad_tx_eth_packet[0x1];
1069 u8 reserved_at_263[0x8];
1070 u8 log_bf_reg_size[0x5];
1072 u8 reserved_at_270[0xb];
1074 u8 num_lag_ports[0x4];
1076 u8 reserved_at_280[0x10];
1077 u8 max_wqe_sz_sq[0x10];
1079 u8 reserved_at_2a0[0x10];
1080 u8 max_wqe_sz_rq[0x10];
1082 u8 max_flow_counter_31_16[0x10];
1083 u8 max_wqe_sz_sq_dc[0x10];
1085 u8 reserved_at_2e0[0x7];
1086 u8 max_qp_mcg[0x19];
1088 u8 reserved_at_300[0x18];
1089 u8 log_max_mcg[0x8];
1091 u8 reserved_at_320[0x3];
1092 u8 log_max_transport_domain[0x5];
1093 u8 reserved_at_328[0x3];
1095 u8 reserved_at_330[0xb];
1096 u8 log_max_xrcd[0x5];
1098 u8 nic_receive_steering_discard[0x1];
1099 u8 receive_discard_vport_down[0x1];
1100 u8 transmit_discard_vport_down[0x1];
1101 u8 reserved_at_343[0x5];
1102 u8 log_max_flow_counter_bulk[0x8];
1103 u8 max_flow_counter_15_0[0x10];
1106 u8 reserved_at_360[0x3];
1108 u8 reserved_at_368[0x3];
1110 u8 reserved_at_370[0x3];
1111 u8 log_max_tir[0x5];
1112 u8 reserved_at_378[0x3];
1113 u8 log_max_tis[0x5];
1115 u8 basic_cyclic_rcv_wqe[0x1];
1116 u8 reserved_at_381[0x2];
1117 u8 log_max_rmp[0x5];
1118 u8 reserved_at_388[0x3];
1119 u8 log_max_rqt[0x5];
1120 u8 reserved_at_390[0x3];
1121 u8 log_max_rqt_size[0x5];
1122 u8 reserved_at_398[0x3];
1123 u8 log_max_tis_per_sq[0x5];
1125 u8 ext_stride_num_range[0x1];
1126 u8 reserved_at_3a1[0x2];
1127 u8 log_max_stride_sz_rq[0x5];
1128 u8 reserved_at_3a8[0x3];
1129 u8 log_min_stride_sz_rq[0x5];
1130 u8 reserved_at_3b0[0x3];
1131 u8 log_max_stride_sz_sq[0x5];
1132 u8 reserved_at_3b8[0x3];
1133 u8 log_min_stride_sz_sq[0x5];
1136 u8 reserved_at_3c1[0x2];
1137 u8 log_max_hairpin_queues[0x5];
1138 u8 reserved_at_3c8[0x3];
1139 u8 log_max_hairpin_wq_data_sz[0x5];
1140 u8 reserved_at_3d0[0x3];
1141 u8 log_max_hairpin_num_packets[0x5];
1142 u8 reserved_at_3d8[0x3];
1143 u8 log_max_wq_sz[0x5];
1145 u8 nic_vport_change_event[0x1];
1146 u8 disable_local_lb_uc[0x1];
1147 u8 disable_local_lb_mc[0x1];
1148 u8 log_min_hairpin_wq_data_sz[0x5];
1149 u8 reserved_at_3e8[0x3];
1150 u8 log_max_vlan_list[0x5];
1151 u8 reserved_at_3f0[0x3];
1152 u8 log_max_current_mc_list[0x5];
1153 u8 reserved_at_3f8[0x3];
1154 u8 log_max_current_uc_list[0x5];
1156 u8 general_obj_types[0x40];
1158 u8 reserved_at_440[0x20];
1160 u8 reserved_at_460[0x10];
1161 u8 max_num_eqs[0x10];
1163 u8 reserved_at_480[0x3];
1164 u8 log_max_l2_table[0x5];
1165 u8 reserved_at_488[0x8];
1166 u8 log_uar_page_sz[0x10];
1168 u8 reserved_at_4a0[0x20];
1169 u8 device_frequency_mhz[0x20];
1170 u8 device_frequency_khz[0x20];
1172 u8 reserved_at_500[0x20];
1173 u8 num_of_uars_per_page[0x20];
1175 u8 flex_parser_protocols[0x20];
1176 u8 reserved_at_560[0x20];
1178 u8 reserved_at_580[0x3c];
1179 u8 mini_cqe_resp_stride_index[0x1];
1180 u8 cqe_128_always[0x1];
1181 u8 cqe_compression_128[0x1];
1182 u8 cqe_compression[0x1];
1184 u8 cqe_compression_timeout[0x10];
1185 u8 cqe_compression_max_num[0x10];
1187 u8 reserved_at_5e0[0x10];
1188 u8 tag_matching[0x1];
1189 u8 rndv_offload_rc[0x1];
1190 u8 rndv_offload_dc[0x1];
1191 u8 log_tag_matching_list_sz[0x5];
1192 u8 reserved_at_5f8[0x3];
1193 u8 log_max_xrq[0x5];
1195 u8 affiliate_nic_vport_criteria[0x8];
1196 u8 native_port_num[0x8];
1197 u8 num_vhca_ports[0x8];
1198 u8 reserved_at_618[0x6];
1199 u8 sw_owner_id[0x1];
1200 u8 reserved_at_61f[0x1];
1202 u8 reserved_at_620[0x80];
1206 u8 reserved_at_6c0[0x140];
1209 enum mlx5_flow_destination_type {
1210 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1211 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1212 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1214 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1215 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1216 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1219 struct mlx5_ifc_dest_format_struct_bits {
1220 u8 destination_type[0x8];
1221 u8 destination_id[0x18];
1222 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1223 u8 reserved_at_21[0xf];
1224 u8 destination_eswitch_owner_vhca_id[0x10];
1227 struct mlx5_ifc_flow_counter_list_bits {
1228 u8 flow_counter_id[0x20];
1230 u8 reserved_at_20[0x20];
1233 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1234 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1235 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1236 u8 reserved_at_0[0x40];
1239 struct mlx5_ifc_fte_match_param_bits {
1240 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1242 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1244 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1246 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1248 u8 reserved_at_800[0x800];
1252 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1253 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1254 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1255 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1256 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1259 struct mlx5_ifc_rx_hash_field_select_bits {
1260 u8 l3_prot_type[0x1];
1261 u8 l4_prot_type[0x1];
1262 u8 selected_fields[0x1e];
1266 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1267 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1271 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1272 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1275 struct mlx5_ifc_wq_bits {
1277 u8 wq_signature[0x1];
1278 u8 end_padding_mode[0x2];
1280 u8 reserved_at_8[0x18];
1282 u8 hds_skip_first_sge[0x1];
1283 u8 log2_hds_buf_size[0x3];
1284 u8 reserved_at_24[0x7];
1285 u8 page_offset[0x5];
1288 u8 reserved_at_40[0x8];
1291 u8 reserved_at_60[0x8];
1296 u8 hw_counter[0x20];
1298 u8 sw_counter[0x20];
1300 u8 reserved_at_100[0xc];
1301 u8 log_wq_stride[0x4];
1302 u8 reserved_at_110[0x3];
1303 u8 log_wq_pg_sz[0x5];
1304 u8 reserved_at_118[0x3];
1307 u8 dbr_umem_valid[0x1];
1308 u8 wq_umem_valid[0x1];
1309 u8 reserved_at_122[0x1];
1310 u8 log_hairpin_num_packets[0x5];
1311 u8 reserved_at_128[0x3];
1312 u8 log_hairpin_data_sz[0x5];
1314 u8 reserved_at_130[0x4];
1315 u8 log_wqe_num_of_strides[0x4];
1316 u8 two_byte_shift_en[0x1];
1317 u8 reserved_at_139[0x4];
1318 u8 log_wqe_stride_size[0x3];
1320 u8 reserved_at_140[0x4c0];
1322 struct mlx5_ifc_cmd_pas_bits pas[0];
1325 struct mlx5_ifc_rq_num_bits {
1326 u8 reserved_at_0[0x8];
1330 struct mlx5_ifc_mac_address_layout_bits {
1331 u8 reserved_at_0[0x10];
1332 u8 mac_addr_47_32[0x10];
1334 u8 mac_addr_31_0[0x20];
1337 struct mlx5_ifc_vlan_layout_bits {
1338 u8 reserved_at_0[0x14];
1341 u8 reserved_at_20[0x20];
1344 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1345 u8 reserved_at_0[0xa0];
1347 u8 min_time_between_cnps[0x20];
1349 u8 reserved_at_c0[0x12];
1351 u8 reserved_at_d8[0x4];
1352 u8 cnp_prio_mode[0x1];
1353 u8 cnp_802p_prio[0x3];
1355 u8 reserved_at_e0[0x720];
1358 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1359 u8 reserved_at_0[0x60];
1361 u8 reserved_at_60[0x4];
1362 u8 clamp_tgt_rate[0x1];
1363 u8 reserved_at_65[0x3];
1364 u8 clamp_tgt_rate_after_time_inc[0x1];
1365 u8 reserved_at_69[0x17];
1367 u8 reserved_at_80[0x20];
1369 u8 rpg_time_reset[0x20];
1371 u8 rpg_byte_reset[0x20];
1373 u8 rpg_threshold[0x20];
1375 u8 rpg_max_rate[0x20];
1377 u8 rpg_ai_rate[0x20];
1379 u8 rpg_hai_rate[0x20];
1383 u8 rpg_min_dec_fac[0x20];
1385 u8 rpg_min_rate[0x20];
1387 u8 reserved_at_1c0[0xe0];
1389 u8 rate_to_set_on_first_cnp[0x20];
1393 u8 dce_tcp_rtt[0x20];
1395 u8 rate_reduce_monitor_period[0x20];
1397 u8 reserved_at_320[0x20];
1399 u8 initial_alpha_value[0x20];
1401 u8 reserved_at_360[0x4a0];
1404 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1405 u8 reserved_at_0[0x80];
1407 u8 rppp_max_rps[0x20];
1409 u8 rpg_time_reset[0x20];
1411 u8 rpg_byte_reset[0x20];
1413 u8 rpg_threshold[0x20];
1415 u8 rpg_max_rate[0x20];
1417 u8 rpg_ai_rate[0x20];
1419 u8 rpg_hai_rate[0x20];
1423 u8 rpg_min_dec_fac[0x20];
1425 u8 rpg_min_rate[0x20];
1427 u8 reserved_at_1c0[0x640];
1431 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1432 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1433 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1436 struct mlx5_ifc_resize_field_select_bits {
1437 u8 resize_field_select[0x20];
1441 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1442 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1443 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1444 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1447 struct mlx5_ifc_modify_field_select_bits {
1448 u8 modify_field_select[0x20];
1451 struct mlx5_ifc_field_select_r_roce_np_bits {
1452 u8 field_select_r_roce_np[0x20];
1455 struct mlx5_ifc_field_select_r_roce_rp_bits {
1456 u8 field_select_r_roce_rp[0x20];
1460 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1461 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1462 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1463 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1464 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1465 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1466 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1467 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1468 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1469 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1472 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1473 u8 field_select_8021qaurp[0x20];
1476 struct mlx5_ifc_phys_layer_cntrs_bits {
1477 u8 time_since_last_clear_high[0x20];
1479 u8 time_since_last_clear_low[0x20];
1481 u8 symbol_errors_high[0x20];
1483 u8 symbol_errors_low[0x20];
1485 u8 sync_headers_errors_high[0x20];
1487 u8 sync_headers_errors_low[0x20];
1489 u8 edpl_bip_errors_lane0_high[0x20];
1491 u8 edpl_bip_errors_lane0_low[0x20];
1493 u8 edpl_bip_errors_lane1_high[0x20];
1495 u8 edpl_bip_errors_lane1_low[0x20];
1497 u8 edpl_bip_errors_lane2_high[0x20];
1499 u8 edpl_bip_errors_lane2_low[0x20];
1501 u8 edpl_bip_errors_lane3_high[0x20];
1503 u8 edpl_bip_errors_lane3_low[0x20];
1505 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1507 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1509 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1511 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1513 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1515 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1517 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1519 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1521 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1523 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1525 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1527 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1529 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1531 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1533 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1535 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1537 u8 rs_fec_corrected_blocks_high[0x20];
1539 u8 rs_fec_corrected_blocks_low[0x20];
1541 u8 rs_fec_uncorrectable_blocks_high[0x20];
1543 u8 rs_fec_uncorrectable_blocks_low[0x20];
1545 u8 rs_fec_no_errors_blocks_high[0x20];
1547 u8 rs_fec_no_errors_blocks_low[0x20];
1549 u8 rs_fec_single_error_blocks_high[0x20];
1551 u8 rs_fec_single_error_blocks_low[0x20];
1553 u8 rs_fec_corrected_symbols_total_high[0x20];
1555 u8 rs_fec_corrected_symbols_total_low[0x20];
1557 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1559 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1561 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1563 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1565 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1567 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1569 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1571 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1573 u8 link_down_events[0x20];
1575 u8 successful_recovery_events[0x20];
1577 u8 reserved_at_640[0x180];
1580 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1581 u8 time_since_last_clear_high[0x20];
1583 u8 time_since_last_clear_low[0x20];
1585 u8 phy_received_bits_high[0x20];
1587 u8 phy_received_bits_low[0x20];
1589 u8 phy_symbol_errors_high[0x20];
1591 u8 phy_symbol_errors_low[0x20];
1593 u8 phy_corrected_bits_high[0x20];
1595 u8 phy_corrected_bits_low[0x20];
1597 u8 phy_corrected_bits_lane0_high[0x20];
1599 u8 phy_corrected_bits_lane0_low[0x20];
1601 u8 phy_corrected_bits_lane1_high[0x20];
1603 u8 phy_corrected_bits_lane1_low[0x20];
1605 u8 phy_corrected_bits_lane2_high[0x20];
1607 u8 phy_corrected_bits_lane2_low[0x20];
1609 u8 phy_corrected_bits_lane3_high[0x20];
1611 u8 phy_corrected_bits_lane3_low[0x20];
1613 u8 reserved_at_200[0x5c0];
1616 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1617 u8 symbol_error_counter[0x10];
1619 u8 link_error_recovery_counter[0x8];
1621 u8 link_downed_counter[0x8];
1623 u8 port_rcv_errors[0x10];
1625 u8 port_rcv_remote_physical_errors[0x10];
1627 u8 port_rcv_switch_relay_errors[0x10];
1629 u8 port_xmit_discards[0x10];
1631 u8 port_xmit_constraint_errors[0x8];
1633 u8 port_rcv_constraint_errors[0x8];
1635 u8 reserved_at_70[0x8];
1637 u8 link_overrun_errors[0x8];
1639 u8 reserved_at_80[0x10];
1641 u8 vl_15_dropped[0x10];
1643 u8 reserved_at_a0[0x80];
1645 u8 port_xmit_wait[0x20];
1648 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1649 u8 transmit_queue_high[0x20];
1651 u8 transmit_queue_low[0x20];
1653 u8 reserved_at_40[0x780];
1656 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1657 u8 rx_octets_high[0x20];
1659 u8 rx_octets_low[0x20];
1661 u8 reserved_at_40[0xc0];
1663 u8 rx_frames_high[0x20];
1665 u8 rx_frames_low[0x20];
1667 u8 tx_octets_high[0x20];
1669 u8 tx_octets_low[0x20];
1671 u8 reserved_at_180[0xc0];
1673 u8 tx_frames_high[0x20];
1675 u8 tx_frames_low[0x20];
1677 u8 rx_pause_high[0x20];
1679 u8 rx_pause_low[0x20];
1681 u8 rx_pause_duration_high[0x20];
1683 u8 rx_pause_duration_low[0x20];
1685 u8 tx_pause_high[0x20];
1687 u8 tx_pause_low[0x20];
1689 u8 tx_pause_duration_high[0x20];
1691 u8 tx_pause_duration_low[0x20];
1693 u8 rx_pause_transition_high[0x20];
1695 u8 rx_pause_transition_low[0x20];
1697 u8 reserved_at_3c0[0x40];
1699 u8 device_stall_minor_watermark_cnt_high[0x20];
1701 u8 device_stall_minor_watermark_cnt_low[0x20];
1703 u8 device_stall_critical_watermark_cnt_high[0x20];
1705 u8 device_stall_critical_watermark_cnt_low[0x20];
1707 u8 reserved_at_480[0x340];
1710 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1711 u8 port_transmit_wait_high[0x20];
1713 u8 port_transmit_wait_low[0x20];
1715 u8 reserved_at_40[0x100];
1717 u8 rx_buffer_almost_full_high[0x20];
1719 u8 rx_buffer_almost_full_low[0x20];
1721 u8 rx_buffer_full_high[0x20];
1723 u8 rx_buffer_full_low[0x20];
1725 u8 rx_icrc_encapsulated_high[0x20];
1727 u8 rx_icrc_encapsulated_low[0x20];
1729 u8 reserved_at_200[0x5c0];
1732 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1733 u8 dot3stats_alignment_errors_high[0x20];
1735 u8 dot3stats_alignment_errors_low[0x20];
1737 u8 dot3stats_fcs_errors_high[0x20];
1739 u8 dot3stats_fcs_errors_low[0x20];
1741 u8 dot3stats_single_collision_frames_high[0x20];
1743 u8 dot3stats_single_collision_frames_low[0x20];
1745 u8 dot3stats_multiple_collision_frames_high[0x20];
1747 u8 dot3stats_multiple_collision_frames_low[0x20];
1749 u8 dot3stats_sqe_test_errors_high[0x20];
1751 u8 dot3stats_sqe_test_errors_low[0x20];
1753 u8 dot3stats_deferred_transmissions_high[0x20];
1755 u8 dot3stats_deferred_transmissions_low[0x20];
1757 u8 dot3stats_late_collisions_high[0x20];
1759 u8 dot3stats_late_collisions_low[0x20];
1761 u8 dot3stats_excessive_collisions_high[0x20];
1763 u8 dot3stats_excessive_collisions_low[0x20];
1765 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1767 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1769 u8 dot3stats_carrier_sense_errors_high[0x20];
1771 u8 dot3stats_carrier_sense_errors_low[0x20];
1773 u8 dot3stats_frame_too_longs_high[0x20];
1775 u8 dot3stats_frame_too_longs_low[0x20];
1777 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1779 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1781 u8 dot3stats_symbol_errors_high[0x20];
1783 u8 dot3stats_symbol_errors_low[0x20];
1785 u8 dot3control_in_unknown_opcodes_high[0x20];
1787 u8 dot3control_in_unknown_opcodes_low[0x20];
1789 u8 dot3in_pause_frames_high[0x20];
1791 u8 dot3in_pause_frames_low[0x20];
1793 u8 dot3out_pause_frames_high[0x20];
1795 u8 dot3out_pause_frames_low[0x20];
1797 u8 reserved_at_400[0x3c0];
1800 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1801 u8 ether_stats_drop_events_high[0x20];
1803 u8 ether_stats_drop_events_low[0x20];
1805 u8 ether_stats_octets_high[0x20];
1807 u8 ether_stats_octets_low[0x20];
1809 u8 ether_stats_pkts_high[0x20];
1811 u8 ether_stats_pkts_low[0x20];
1813 u8 ether_stats_broadcast_pkts_high[0x20];
1815 u8 ether_stats_broadcast_pkts_low[0x20];
1817 u8 ether_stats_multicast_pkts_high[0x20];
1819 u8 ether_stats_multicast_pkts_low[0x20];
1821 u8 ether_stats_crc_align_errors_high[0x20];
1823 u8 ether_stats_crc_align_errors_low[0x20];
1825 u8 ether_stats_undersize_pkts_high[0x20];
1827 u8 ether_stats_undersize_pkts_low[0x20];
1829 u8 ether_stats_oversize_pkts_high[0x20];
1831 u8 ether_stats_oversize_pkts_low[0x20];
1833 u8 ether_stats_fragments_high[0x20];
1835 u8 ether_stats_fragments_low[0x20];
1837 u8 ether_stats_jabbers_high[0x20];
1839 u8 ether_stats_jabbers_low[0x20];
1841 u8 ether_stats_collisions_high[0x20];
1843 u8 ether_stats_collisions_low[0x20];
1845 u8 ether_stats_pkts64octets_high[0x20];
1847 u8 ether_stats_pkts64octets_low[0x20];
1849 u8 ether_stats_pkts65to127octets_high[0x20];
1851 u8 ether_stats_pkts65to127octets_low[0x20];
1853 u8 ether_stats_pkts128to255octets_high[0x20];
1855 u8 ether_stats_pkts128to255octets_low[0x20];
1857 u8 ether_stats_pkts256to511octets_high[0x20];
1859 u8 ether_stats_pkts256to511octets_low[0x20];
1861 u8 ether_stats_pkts512to1023octets_high[0x20];
1863 u8 ether_stats_pkts512to1023octets_low[0x20];
1865 u8 ether_stats_pkts1024to1518octets_high[0x20];
1867 u8 ether_stats_pkts1024to1518octets_low[0x20];
1869 u8 ether_stats_pkts1519to2047octets_high[0x20];
1871 u8 ether_stats_pkts1519to2047octets_low[0x20];
1873 u8 ether_stats_pkts2048to4095octets_high[0x20];
1875 u8 ether_stats_pkts2048to4095octets_low[0x20];
1877 u8 ether_stats_pkts4096to8191octets_high[0x20];
1879 u8 ether_stats_pkts4096to8191octets_low[0x20];
1881 u8 ether_stats_pkts8192to10239octets_high[0x20];
1883 u8 ether_stats_pkts8192to10239octets_low[0x20];
1885 u8 reserved_at_540[0x280];
1888 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1889 u8 if_in_octets_high[0x20];
1891 u8 if_in_octets_low[0x20];
1893 u8 if_in_ucast_pkts_high[0x20];
1895 u8 if_in_ucast_pkts_low[0x20];
1897 u8 if_in_discards_high[0x20];
1899 u8 if_in_discards_low[0x20];
1901 u8 if_in_errors_high[0x20];
1903 u8 if_in_errors_low[0x20];
1905 u8 if_in_unknown_protos_high[0x20];
1907 u8 if_in_unknown_protos_low[0x20];
1909 u8 if_out_octets_high[0x20];
1911 u8 if_out_octets_low[0x20];
1913 u8 if_out_ucast_pkts_high[0x20];
1915 u8 if_out_ucast_pkts_low[0x20];
1917 u8 if_out_discards_high[0x20];
1919 u8 if_out_discards_low[0x20];
1921 u8 if_out_errors_high[0x20];
1923 u8 if_out_errors_low[0x20];
1925 u8 if_in_multicast_pkts_high[0x20];
1927 u8 if_in_multicast_pkts_low[0x20];
1929 u8 if_in_broadcast_pkts_high[0x20];
1931 u8 if_in_broadcast_pkts_low[0x20];
1933 u8 if_out_multicast_pkts_high[0x20];
1935 u8 if_out_multicast_pkts_low[0x20];
1937 u8 if_out_broadcast_pkts_high[0x20];
1939 u8 if_out_broadcast_pkts_low[0x20];
1941 u8 reserved_at_340[0x480];
1944 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1945 u8 a_frames_transmitted_ok_high[0x20];
1947 u8 a_frames_transmitted_ok_low[0x20];
1949 u8 a_frames_received_ok_high[0x20];
1951 u8 a_frames_received_ok_low[0x20];
1953 u8 a_frame_check_sequence_errors_high[0x20];
1955 u8 a_frame_check_sequence_errors_low[0x20];
1957 u8 a_alignment_errors_high[0x20];
1959 u8 a_alignment_errors_low[0x20];
1961 u8 a_octets_transmitted_ok_high[0x20];
1963 u8 a_octets_transmitted_ok_low[0x20];
1965 u8 a_octets_received_ok_high[0x20];
1967 u8 a_octets_received_ok_low[0x20];
1969 u8 a_multicast_frames_xmitted_ok_high[0x20];
1971 u8 a_multicast_frames_xmitted_ok_low[0x20];
1973 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1975 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1977 u8 a_multicast_frames_received_ok_high[0x20];
1979 u8 a_multicast_frames_received_ok_low[0x20];
1981 u8 a_broadcast_frames_received_ok_high[0x20];
1983 u8 a_broadcast_frames_received_ok_low[0x20];
1985 u8 a_in_range_length_errors_high[0x20];
1987 u8 a_in_range_length_errors_low[0x20];
1989 u8 a_out_of_range_length_field_high[0x20];
1991 u8 a_out_of_range_length_field_low[0x20];
1993 u8 a_frame_too_long_errors_high[0x20];
1995 u8 a_frame_too_long_errors_low[0x20];
1997 u8 a_symbol_error_during_carrier_high[0x20];
1999 u8 a_symbol_error_during_carrier_low[0x20];
2001 u8 a_mac_control_frames_transmitted_high[0x20];
2003 u8 a_mac_control_frames_transmitted_low[0x20];
2005 u8 a_mac_control_frames_received_high[0x20];
2007 u8 a_mac_control_frames_received_low[0x20];
2009 u8 a_unsupported_opcodes_received_high[0x20];
2011 u8 a_unsupported_opcodes_received_low[0x20];
2013 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2015 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2017 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2019 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2021 u8 reserved_at_4c0[0x300];
2024 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2025 u8 life_time_counter_high[0x20];
2027 u8 life_time_counter_low[0x20];
2033 u8 l0_to_recovery_eieos[0x20];
2035 u8 l0_to_recovery_ts[0x20];
2037 u8 l0_to_recovery_framing[0x20];
2039 u8 l0_to_recovery_retrain[0x20];
2041 u8 crc_error_dllp[0x20];
2043 u8 crc_error_tlp[0x20];
2045 u8 tx_overflow_buffer_pkt_high[0x20];
2047 u8 tx_overflow_buffer_pkt_low[0x20];
2049 u8 outbound_stalled_reads[0x20];
2051 u8 outbound_stalled_writes[0x20];
2053 u8 outbound_stalled_reads_events[0x20];
2055 u8 outbound_stalled_writes_events[0x20];
2057 u8 reserved_at_200[0x5c0];
2060 struct mlx5_ifc_cmd_inter_comp_event_bits {
2061 u8 command_completion_vector[0x20];
2063 u8 reserved_at_20[0xc0];
2066 struct mlx5_ifc_stall_vl_event_bits {
2067 u8 reserved_at_0[0x18];
2069 u8 reserved_at_19[0x3];
2072 u8 reserved_at_20[0xa0];
2075 struct mlx5_ifc_db_bf_congestion_event_bits {
2076 u8 event_subtype[0x8];
2077 u8 reserved_at_8[0x8];
2078 u8 congestion_level[0x8];
2079 u8 reserved_at_18[0x8];
2081 u8 reserved_at_20[0xa0];
2084 struct mlx5_ifc_gpio_event_bits {
2085 u8 reserved_at_0[0x60];
2087 u8 gpio_event_hi[0x20];
2089 u8 gpio_event_lo[0x20];
2091 u8 reserved_at_a0[0x40];
2094 struct mlx5_ifc_port_state_change_event_bits {
2095 u8 reserved_at_0[0x40];
2098 u8 reserved_at_44[0x1c];
2100 u8 reserved_at_60[0x80];
2103 struct mlx5_ifc_dropped_packet_logged_bits {
2104 u8 reserved_at_0[0xe0];
2108 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2109 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2112 struct mlx5_ifc_cq_error_bits {
2113 u8 reserved_at_0[0x8];
2116 u8 reserved_at_20[0x20];
2118 u8 reserved_at_40[0x18];
2121 u8 reserved_at_60[0x80];
2124 struct mlx5_ifc_rdma_page_fault_event_bits {
2125 u8 bytes_committed[0x20];
2129 u8 reserved_at_40[0x10];
2130 u8 packet_len[0x10];
2132 u8 rdma_op_len[0x20];
2136 u8 reserved_at_c0[0x5];
2143 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2144 u8 bytes_committed[0x20];
2146 u8 reserved_at_20[0x10];
2149 u8 reserved_at_40[0x10];
2152 u8 reserved_at_60[0x60];
2154 u8 reserved_at_c0[0x5];
2161 struct mlx5_ifc_qp_events_bits {
2162 u8 reserved_at_0[0xa0];
2165 u8 reserved_at_a8[0x18];
2167 u8 reserved_at_c0[0x8];
2168 u8 qpn_rqn_sqn[0x18];
2171 struct mlx5_ifc_dct_events_bits {
2172 u8 reserved_at_0[0xc0];
2174 u8 reserved_at_c0[0x8];
2175 u8 dct_number[0x18];
2178 struct mlx5_ifc_comp_event_bits {
2179 u8 reserved_at_0[0xc0];
2181 u8 reserved_at_c0[0x8];
2186 MLX5_QPC_STATE_RST = 0x0,
2187 MLX5_QPC_STATE_INIT = 0x1,
2188 MLX5_QPC_STATE_RTR = 0x2,
2189 MLX5_QPC_STATE_RTS = 0x3,
2190 MLX5_QPC_STATE_SQER = 0x4,
2191 MLX5_QPC_STATE_ERR = 0x6,
2192 MLX5_QPC_STATE_SQD = 0x7,
2193 MLX5_QPC_STATE_SUSPENDED = 0x9,
2197 MLX5_QPC_ST_RC = 0x0,
2198 MLX5_QPC_ST_UC = 0x1,
2199 MLX5_QPC_ST_UD = 0x2,
2200 MLX5_QPC_ST_XRC = 0x3,
2201 MLX5_QPC_ST_DCI = 0x5,
2202 MLX5_QPC_ST_QP0 = 0x7,
2203 MLX5_QPC_ST_QP1 = 0x8,
2204 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2205 MLX5_QPC_ST_REG_UMR = 0xc,
2209 MLX5_QPC_PM_STATE_ARMED = 0x0,
2210 MLX5_QPC_PM_STATE_REARM = 0x1,
2211 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2212 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2216 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2220 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2221 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2225 MLX5_QPC_MTU_256_BYTES = 0x1,
2226 MLX5_QPC_MTU_512_BYTES = 0x2,
2227 MLX5_QPC_MTU_1K_BYTES = 0x3,
2228 MLX5_QPC_MTU_2K_BYTES = 0x4,
2229 MLX5_QPC_MTU_4K_BYTES = 0x5,
2230 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2234 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2235 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2236 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2237 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2238 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2239 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2240 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2241 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2245 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2246 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2247 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2251 MLX5_QPC_CS_RES_DISABLE = 0x0,
2252 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2253 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2256 struct mlx5_ifc_qpc_bits {
2258 u8 lag_tx_port_affinity[0x4];
2260 u8 reserved_at_10[0x3];
2262 u8 reserved_at_15[0x3];
2263 u8 offload_type[0x4];
2264 u8 end_padding_mode[0x2];
2265 u8 reserved_at_1e[0x2];
2267 u8 wq_signature[0x1];
2268 u8 block_lb_mc[0x1];
2269 u8 atomic_like_write_en[0x1];
2270 u8 latency_sensitive[0x1];
2271 u8 reserved_at_24[0x1];
2272 u8 drain_sigerr[0x1];
2273 u8 reserved_at_26[0x2];
2277 u8 log_msg_max[0x5];
2278 u8 reserved_at_48[0x1];
2279 u8 log_rq_size[0x4];
2280 u8 log_rq_stride[0x3];
2282 u8 log_sq_size[0x4];
2283 u8 reserved_at_55[0x6];
2285 u8 ulp_stateless_offload_mode[0x4];
2287 u8 counter_set_id[0x8];
2290 u8 reserved_at_80[0x8];
2291 u8 user_index[0x18];
2293 u8 reserved_at_a0[0x3];
2294 u8 log_page_size[0x5];
2295 u8 remote_qpn[0x18];
2297 struct mlx5_ifc_ads_bits primary_address_path;
2299 struct mlx5_ifc_ads_bits secondary_address_path;
2301 u8 log_ack_req_freq[0x4];
2302 u8 reserved_at_384[0x4];
2303 u8 log_sra_max[0x3];
2304 u8 reserved_at_38b[0x2];
2305 u8 retry_count[0x3];
2307 u8 reserved_at_393[0x1];
2309 u8 cur_rnr_retry[0x3];
2310 u8 cur_retry_count[0x3];
2311 u8 reserved_at_39b[0x5];
2313 u8 reserved_at_3a0[0x20];
2315 u8 reserved_at_3c0[0x8];
2316 u8 next_send_psn[0x18];
2318 u8 reserved_at_3e0[0x8];
2321 u8 reserved_at_400[0x8];
2324 u8 reserved_at_420[0x20];
2326 u8 reserved_at_440[0x8];
2327 u8 last_acked_psn[0x18];
2329 u8 reserved_at_460[0x8];
2332 u8 reserved_at_480[0x8];
2333 u8 log_rra_max[0x3];
2334 u8 reserved_at_48b[0x1];
2335 u8 atomic_mode[0x4];
2339 u8 reserved_at_493[0x1];
2340 u8 page_offset[0x6];
2341 u8 reserved_at_49a[0x3];
2342 u8 cd_slave_receive[0x1];
2343 u8 cd_slave_send[0x1];
2346 u8 reserved_at_4a0[0x3];
2347 u8 min_rnr_nak[0x5];
2348 u8 next_rcv_psn[0x18];
2350 u8 reserved_at_4c0[0x8];
2353 u8 reserved_at_4e0[0x8];
2360 u8 reserved_at_560[0x5];
2362 u8 srqn_rmpn_xrqn[0x18];
2364 u8 reserved_at_580[0x8];
2367 u8 hw_sq_wqebb_counter[0x10];
2368 u8 sw_sq_wqebb_counter[0x10];
2370 u8 hw_rq_counter[0x20];
2372 u8 sw_rq_counter[0x20];
2374 u8 reserved_at_600[0x20];
2376 u8 reserved_at_620[0xf];
2381 u8 dc_access_key[0x40];
2383 u8 reserved_at_680[0x3];
2384 u8 dbr_umem_valid[0x1];
2386 u8 reserved_at_684[0xbc];
2389 struct mlx5_ifc_roce_addr_layout_bits {
2390 u8 source_l3_address[16][0x8];
2392 u8 reserved_at_80[0x3];
2395 u8 source_mac_47_32[0x10];
2397 u8 source_mac_31_0[0x20];
2399 u8 reserved_at_c0[0x14];
2400 u8 roce_l3_type[0x4];
2401 u8 roce_version[0x8];
2403 u8 reserved_at_e0[0x20];
2406 union mlx5_ifc_hca_cap_union_bits {
2407 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2408 struct mlx5_ifc_odp_cap_bits odp_cap;
2409 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2410 struct mlx5_ifc_roce_cap_bits roce_cap;
2411 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2412 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2413 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2414 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2415 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2416 struct mlx5_ifc_qos_cap_bits qos_cap;
2417 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2418 u8 reserved_at_0[0x8000];
2422 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2423 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2424 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2425 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2426 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2427 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2428 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2429 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2430 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2431 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2432 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2435 struct mlx5_ifc_vlan_bits {
2442 struct mlx5_ifc_flow_context_bits {
2443 struct mlx5_ifc_vlan_bits push_vlan;
2447 u8 reserved_at_40[0x8];
2450 u8 reserved_at_60[0x10];
2453 u8 reserved_at_80[0x8];
2454 u8 destination_list_size[0x18];
2456 u8 reserved_at_a0[0x8];
2457 u8 flow_counter_list_size[0x18];
2459 u8 packet_reformat_id[0x20];
2461 u8 modify_header_id[0x20];
2463 struct mlx5_ifc_vlan_bits push_vlan_2;
2465 u8 reserved_at_120[0xe0];
2467 struct mlx5_ifc_fte_match_param_bits match_value;
2469 u8 reserved_at_1200[0x600];
2471 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2475 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2476 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2479 struct mlx5_ifc_xrc_srqc_bits {
2481 u8 log_xrc_srq_size[0x4];
2482 u8 reserved_at_8[0x18];
2484 u8 wq_signature[0x1];
2486 u8 reserved_at_22[0x1];
2488 u8 basic_cyclic_rcv_wqe[0x1];
2489 u8 log_rq_stride[0x3];
2492 u8 page_offset[0x6];
2493 u8 reserved_at_46[0x1];
2494 u8 dbr_umem_valid[0x1];
2497 u8 reserved_at_60[0x20];
2499 u8 user_index_equal_xrc_srqn[0x1];
2500 u8 reserved_at_81[0x1];
2501 u8 log_page_size[0x6];
2502 u8 user_index[0x18];
2504 u8 reserved_at_a0[0x20];
2506 u8 reserved_at_c0[0x8];
2512 u8 reserved_at_100[0x40];
2514 u8 db_record_addr_h[0x20];
2516 u8 db_record_addr_l[0x1e];
2517 u8 reserved_at_17e[0x2];
2519 u8 reserved_at_180[0x80];
2522 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2523 u8 counter_error_queues[0x20];
2525 u8 total_error_queues[0x20];
2527 u8 send_queue_priority_update_flow[0x20];
2529 u8 reserved_at_60[0x20];
2531 u8 nic_receive_steering_discard[0x40];
2533 u8 receive_discard_vport_down[0x40];
2535 u8 transmit_discard_vport_down[0x40];
2537 u8 reserved_at_140[0xec0];
2540 struct mlx5_ifc_traffic_counter_bits {
2546 struct mlx5_ifc_tisc_bits {
2547 u8 strict_lag_tx_port_affinity[0x1];
2548 u8 reserved_at_1[0x3];
2549 u8 lag_tx_port_affinity[0x04];
2551 u8 reserved_at_8[0x4];
2553 u8 reserved_at_10[0x10];
2555 u8 reserved_at_20[0x100];
2557 u8 reserved_at_120[0x8];
2558 u8 transport_domain[0x18];
2560 u8 reserved_at_140[0x8];
2561 u8 underlay_qpn[0x18];
2562 u8 reserved_at_160[0x3a0];
2566 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2567 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2571 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2572 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2576 MLX5_RX_HASH_FN_NONE = 0x0,
2577 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2578 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2582 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2583 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2586 struct mlx5_ifc_tirc_bits {
2587 u8 reserved_at_0[0x20];
2590 u8 reserved_at_24[0x1c];
2592 u8 reserved_at_40[0x40];
2594 u8 reserved_at_80[0x4];
2595 u8 lro_timeout_period_usecs[0x10];
2596 u8 lro_enable_mask[0x4];
2597 u8 lro_max_ip_payload_size[0x8];
2599 u8 reserved_at_a0[0x40];
2601 u8 reserved_at_e0[0x8];
2602 u8 inline_rqn[0x18];
2604 u8 rx_hash_symmetric[0x1];
2605 u8 reserved_at_101[0x1];
2606 u8 tunneled_offload_en[0x1];
2607 u8 reserved_at_103[0x5];
2608 u8 indirect_table[0x18];
2611 u8 reserved_at_124[0x2];
2612 u8 self_lb_block[0x2];
2613 u8 transport_domain[0x18];
2615 u8 rx_hash_toeplitz_key[10][0x20];
2617 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2619 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2621 u8 reserved_at_2c0[0x4c0];
2625 MLX5_SRQC_STATE_GOOD = 0x0,
2626 MLX5_SRQC_STATE_ERROR = 0x1,
2629 struct mlx5_ifc_srqc_bits {
2631 u8 log_srq_size[0x4];
2632 u8 reserved_at_8[0x18];
2634 u8 wq_signature[0x1];
2636 u8 reserved_at_22[0x1];
2638 u8 reserved_at_24[0x1];
2639 u8 log_rq_stride[0x3];
2642 u8 page_offset[0x6];
2643 u8 reserved_at_46[0x2];
2646 u8 reserved_at_60[0x20];
2648 u8 reserved_at_80[0x2];
2649 u8 log_page_size[0x6];
2650 u8 reserved_at_88[0x18];
2652 u8 reserved_at_a0[0x20];
2654 u8 reserved_at_c0[0x8];
2660 u8 reserved_at_100[0x40];
2664 u8 reserved_at_180[0x80];
2668 MLX5_SQC_STATE_RST = 0x0,
2669 MLX5_SQC_STATE_RDY = 0x1,
2670 MLX5_SQC_STATE_ERR = 0x3,
2673 struct mlx5_ifc_sqc_bits {
2677 u8 flush_in_error_en[0x1];
2678 u8 allow_multi_pkt_send_wqe[0x1];
2679 u8 min_wqe_inline_mode[0x3];
2684 u8 reserved_at_f[0x11];
2686 u8 reserved_at_20[0x8];
2687 u8 user_index[0x18];
2689 u8 reserved_at_40[0x8];
2692 u8 reserved_at_60[0x8];
2693 u8 hairpin_peer_rq[0x18];
2695 u8 reserved_at_80[0x10];
2696 u8 hairpin_peer_vhca[0x10];
2698 u8 reserved_at_a0[0x50];
2700 u8 packet_pacing_rate_limit_index[0x10];
2701 u8 tis_lst_sz[0x10];
2702 u8 reserved_at_110[0x10];
2704 u8 reserved_at_120[0x40];
2706 u8 reserved_at_160[0x8];
2709 struct mlx5_ifc_wq_bits wq;
2713 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2714 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2715 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2716 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2719 struct mlx5_ifc_scheduling_context_bits {
2720 u8 element_type[0x8];
2721 u8 reserved_at_8[0x18];
2723 u8 element_attributes[0x20];
2725 u8 parent_element_id[0x20];
2727 u8 reserved_at_60[0x40];
2731 u8 max_average_bw[0x20];
2733 u8 reserved_at_e0[0x120];
2736 struct mlx5_ifc_rqtc_bits {
2737 u8 reserved_at_0[0xa0];
2739 u8 reserved_at_a0[0x10];
2740 u8 rqt_max_size[0x10];
2742 u8 reserved_at_c0[0x10];
2743 u8 rqt_actual_size[0x10];
2745 u8 reserved_at_e0[0x6a0];
2747 struct mlx5_ifc_rq_num_bits rq_num[0];
2751 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2752 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2756 MLX5_RQC_STATE_RST = 0x0,
2757 MLX5_RQC_STATE_RDY = 0x1,
2758 MLX5_RQC_STATE_ERR = 0x3,
2761 struct mlx5_ifc_rqc_bits {
2763 u8 delay_drop_en[0x1];
2764 u8 scatter_fcs[0x1];
2766 u8 mem_rq_type[0x4];
2768 u8 reserved_at_c[0x1];
2769 u8 flush_in_error_en[0x1];
2771 u8 reserved_at_f[0x11];
2773 u8 reserved_at_20[0x8];
2774 u8 user_index[0x18];
2776 u8 reserved_at_40[0x8];
2779 u8 counter_set_id[0x8];
2780 u8 reserved_at_68[0x18];
2782 u8 reserved_at_80[0x8];
2785 u8 reserved_at_a0[0x8];
2786 u8 hairpin_peer_sq[0x18];
2788 u8 reserved_at_c0[0x10];
2789 u8 hairpin_peer_vhca[0x10];
2791 u8 reserved_at_e0[0xa0];
2793 struct mlx5_ifc_wq_bits wq;
2797 MLX5_RMPC_STATE_RDY = 0x1,
2798 MLX5_RMPC_STATE_ERR = 0x3,
2801 struct mlx5_ifc_rmpc_bits {
2802 u8 reserved_at_0[0x8];
2804 u8 reserved_at_c[0x14];
2806 u8 basic_cyclic_rcv_wqe[0x1];
2807 u8 reserved_at_21[0x1f];
2809 u8 reserved_at_40[0x140];
2811 struct mlx5_ifc_wq_bits wq;
2814 struct mlx5_ifc_nic_vport_context_bits {
2815 u8 reserved_at_0[0x5];
2816 u8 min_wqe_inline_mode[0x3];
2817 u8 reserved_at_8[0x15];
2818 u8 disable_mc_local_lb[0x1];
2819 u8 disable_uc_local_lb[0x1];
2822 u8 arm_change_event[0x1];
2823 u8 reserved_at_21[0x1a];
2824 u8 event_on_mtu[0x1];
2825 u8 event_on_promisc_change[0x1];
2826 u8 event_on_vlan_change[0x1];
2827 u8 event_on_mc_address_change[0x1];
2828 u8 event_on_uc_address_change[0x1];
2830 u8 reserved_at_40[0xc];
2832 u8 affiliation_criteria[0x4];
2833 u8 affiliated_vhca_id[0x10];
2835 u8 reserved_at_60[0xd0];
2839 u8 system_image_guid[0x40];
2843 u8 reserved_at_200[0x140];
2844 u8 qkey_violation_counter[0x10];
2845 u8 reserved_at_350[0x430];
2849 u8 promisc_all[0x1];
2850 u8 reserved_at_783[0x2];
2851 u8 allowed_list_type[0x3];
2852 u8 reserved_at_788[0xc];
2853 u8 allowed_list_size[0xc];
2855 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2857 u8 reserved_at_7e0[0x20];
2859 u8 current_uc_mac_address[0][0x40];
2863 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2864 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2865 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2866 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2867 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2870 struct mlx5_ifc_mkc_bits {
2871 u8 reserved_at_0[0x1];
2873 u8 reserved_at_2[0x1];
2874 u8 access_mode_4_2[0x3];
2875 u8 reserved_at_6[0x7];
2876 u8 relaxed_ordering_write[0x1];
2877 u8 reserved_at_e[0x1];
2878 u8 small_fence_on_rdma_read_response[0x1];
2885 u8 access_mode_1_0[0x2];
2886 u8 reserved_at_18[0x8];
2891 u8 reserved_at_40[0x20];
2896 u8 reserved_at_63[0x2];
2897 u8 expected_sigerr_count[0x1];
2898 u8 reserved_at_66[0x1];
2902 u8 start_addr[0x40];
2906 u8 bsf_octword_size[0x20];
2908 u8 reserved_at_120[0x80];
2910 u8 translations_octword_size[0x20];
2912 u8 reserved_at_1c0[0x1b];
2913 u8 log_page_size[0x5];
2915 u8 reserved_at_1e0[0x20];
2918 struct mlx5_ifc_pkey_bits {
2919 u8 reserved_at_0[0x10];
2923 struct mlx5_ifc_array128_auto_bits {
2924 u8 array128_auto[16][0x8];
2927 struct mlx5_ifc_hca_vport_context_bits {
2928 u8 field_select[0x20];
2930 u8 reserved_at_20[0xe0];
2932 u8 sm_virt_aware[0x1];
2935 u8 grh_required[0x1];
2936 u8 reserved_at_104[0xc];
2937 u8 port_physical_state[0x4];
2938 u8 vport_state_policy[0x4];
2940 u8 vport_state[0x4];
2942 u8 reserved_at_120[0x20];
2944 u8 system_image_guid[0x40];
2952 u8 cap_mask1_field_select[0x20];
2956 u8 cap_mask2_field_select[0x20];
2958 u8 reserved_at_280[0x80];
2961 u8 reserved_at_310[0x4];
2962 u8 init_type_reply[0x4];
2964 u8 subnet_timeout[0x5];
2968 u8 reserved_at_334[0xc];
2970 u8 qkey_violation_counter[0x10];
2971 u8 pkey_violation_counter[0x10];
2973 u8 reserved_at_360[0xca0];
2976 struct mlx5_ifc_esw_vport_context_bits {
2977 u8 reserved_at_0[0x3];
2978 u8 vport_svlan_strip[0x1];
2979 u8 vport_cvlan_strip[0x1];
2980 u8 vport_svlan_insert[0x1];
2981 u8 vport_cvlan_insert[0x2];
2982 u8 reserved_at_8[0x18];
2984 u8 reserved_at_20[0x20];
2993 u8 reserved_at_60[0x7a0];
2997 MLX5_EQC_STATUS_OK = 0x0,
2998 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3002 MLX5_EQC_ST_ARMED = 0x9,
3003 MLX5_EQC_ST_FIRED = 0xa,
3006 struct mlx5_ifc_eqc_bits {
3008 u8 reserved_at_4[0x9];
3011 u8 reserved_at_f[0x5];
3013 u8 reserved_at_18[0x8];
3015 u8 reserved_at_20[0x20];
3017 u8 reserved_at_40[0x14];
3018 u8 page_offset[0x6];
3019 u8 reserved_at_5a[0x6];
3021 u8 reserved_at_60[0x3];
3022 u8 log_eq_size[0x5];
3025 u8 reserved_at_80[0x20];
3027 u8 reserved_at_a0[0x18];
3030 u8 reserved_at_c0[0x3];
3031 u8 log_page_size[0x5];
3032 u8 reserved_at_c8[0x18];
3034 u8 reserved_at_e0[0x60];
3036 u8 reserved_at_140[0x8];
3037 u8 consumer_counter[0x18];
3039 u8 reserved_at_160[0x8];
3040 u8 producer_counter[0x18];
3042 u8 reserved_at_180[0x80];
3046 MLX5_DCTC_STATE_ACTIVE = 0x0,
3047 MLX5_DCTC_STATE_DRAINING = 0x1,
3048 MLX5_DCTC_STATE_DRAINED = 0x2,
3052 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3053 MLX5_DCTC_CS_RES_NA = 0x1,
3054 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3058 MLX5_DCTC_MTU_256_BYTES = 0x1,
3059 MLX5_DCTC_MTU_512_BYTES = 0x2,
3060 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3061 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3062 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3065 struct mlx5_ifc_dctc_bits {
3066 u8 reserved_at_0[0x4];
3068 u8 reserved_at_8[0x18];
3070 u8 reserved_at_20[0x8];
3071 u8 user_index[0x18];
3073 u8 reserved_at_40[0x8];
3076 u8 counter_set_id[0x8];
3077 u8 atomic_mode[0x4];
3081 u8 atomic_like_write_en[0x1];
3082 u8 latency_sensitive[0x1];
3085 u8 reserved_at_73[0xd];
3087 u8 reserved_at_80[0x8];
3089 u8 reserved_at_90[0x3];
3090 u8 min_rnr_nak[0x5];
3091 u8 reserved_at_98[0x8];
3093 u8 reserved_at_a0[0x8];
3096 u8 reserved_at_c0[0x8];
3100 u8 reserved_at_e8[0x4];
3101 u8 flow_label[0x14];
3103 u8 dc_access_key[0x40];
3105 u8 reserved_at_140[0x5];
3108 u8 pkey_index[0x10];
3110 u8 reserved_at_160[0x8];
3111 u8 my_addr_index[0x8];
3112 u8 reserved_at_170[0x8];
3115 u8 dc_access_key_violation_count[0x20];
3117 u8 reserved_at_1a0[0x14];
3123 u8 reserved_at_1c0[0x40];
3127 MLX5_CQC_STATUS_OK = 0x0,
3128 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3129 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3133 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3134 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3138 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3139 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3140 MLX5_CQC_ST_FIRED = 0xa,
3144 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3145 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3146 MLX5_CQ_PERIOD_NUM_MODES
3149 struct mlx5_ifc_cqc_bits {
3151 u8 reserved_at_4[0x2];
3152 u8 dbr_umem_valid[0x1];
3153 u8 reserved_at_7[0x1];
3156 u8 reserved_at_c[0x1];
3157 u8 scqe_break_moderation_en[0x1];
3159 u8 cq_period_mode[0x2];
3160 u8 cqe_comp_en[0x1];
3161 u8 mini_cqe_res_format[0x2];
3163 u8 reserved_at_18[0x8];
3165 u8 reserved_at_20[0x20];
3167 u8 reserved_at_40[0x14];
3168 u8 page_offset[0x6];
3169 u8 reserved_at_5a[0x6];
3171 u8 reserved_at_60[0x3];
3172 u8 log_cq_size[0x5];
3175 u8 reserved_at_80[0x4];
3177 u8 cq_max_count[0x10];
3179 u8 reserved_at_a0[0x18];
3182 u8 reserved_at_c0[0x3];
3183 u8 log_page_size[0x5];
3184 u8 reserved_at_c8[0x18];
3186 u8 reserved_at_e0[0x20];
3188 u8 reserved_at_100[0x8];
3189 u8 last_notified_index[0x18];
3191 u8 reserved_at_120[0x8];
3192 u8 last_solicit_index[0x18];
3194 u8 reserved_at_140[0x8];
3195 u8 consumer_counter[0x18];
3197 u8 reserved_at_160[0x8];
3198 u8 producer_counter[0x18];
3200 u8 reserved_at_180[0x40];
3205 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3206 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3207 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3208 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3209 u8 reserved_at_0[0x800];
3212 struct mlx5_ifc_query_adapter_param_block_bits {
3213 u8 reserved_at_0[0xc0];
3215 u8 reserved_at_c0[0x8];
3216 u8 ieee_vendor_id[0x18];
3218 u8 reserved_at_e0[0x10];
3219 u8 vsd_vendor_id[0x10];
3223 u8 vsd_contd_psid[16][0x8];
3227 MLX5_XRQC_STATE_GOOD = 0x0,
3228 MLX5_XRQC_STATE_ERROR = 0x1,
3232 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3233 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3237 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3240 struct mlx5_ifc_tag_matching_topology_context_bits {
3241 u8 log_matching_list_sz[0x4];
3242 u8 reserved_at_4[0xc];
3243 u8 append_next_index[0x10];
3245 u8 sw_phase_cnt[0x10];
3246 u8 hw_phase_cnt[0x10];
3248 u8 reserved_at_40[0x40];
3251 struct mlx5_ifc_xrqc_bits {
3254 u8 reserved_at_5[0xf];
3256 u8 reserved_at_18[0x4];
3259 u8 reserved_at_20[0x8];
3260 u8 user_index[0x18];
3262 u8 reserved_at_40[0x8];
3265 u8 reserved_at_60[0xa0];
3267 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3269 u8 reserved_at_180[0x280];
3271 struct mlx5_ifc_wq_bits wq;
3274 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3275 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3276 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3277 u8 reserved_at_0[0x20];
3280 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3281 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3282 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3283 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3284 u8 reserved_at_0[0x20];
3287 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3288 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3289 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3290 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3291 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3292 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3293 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3294 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3295 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3296 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3297 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3298 u8 reserved_at_0[0x7c0];
3301 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3302 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3303 u8 reserved_at_0[0x7c0];
3306 union mlx5_ifc_event_auto_bits {
3307 struct mlx5_ifc_comp_event_bits comp_event;
3308 struct mlx5_ifc_dct_events_bits dct_events;
3309 struct mlx5_ifc_qp_events_bits qp_events;
3310 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3311 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3312 struct mlx5_ifc_cq_error_bits cq_error;
3313 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3314 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3315 struct mlx5_ifc_gpio_event_bits gpio_event;
3316 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3317 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3318 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3319 u8 reserved_at_0[0xe0];
3322 struct mlx5_ifc_health_buffer_bits {
3323 u8 reserved_at_0[0x100];
3325 u8 assert_existptr[0x20];
3327 u8 assert_callra[0x20];
3329 u8 reserved_at_140[0x40];
3331 u8 fw_version[0x20];
3335 u8 reserved_at_1c0[0x20];
3337 u8 irisc_index[0x8];
3342 struct mlx5_ifc_register_loopback_control_bits {
3344 u8 reserved_at_1[0x7];
3346 u8 reserved_at_10[0x10];
3348 u8 reserved_at_20[0x60];
3351 struct mlx5_ifc_vport_tc_element_bits {
3352 u8 traffic_class[0x4];
3353 u8 reserved_at_4[0xc];
3354 u8 vport_number[0x10];
3357 struct mlx5_ifc_vport_element_bits {
3358 u8 reserved_at_0[0x10];
3359 u8 vport_number[0x10];
3363 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3364 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3365 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3368 struct mlx5_ifc_tsar_element_bits {
3369 u8 reserved_at_0[0x8];
3371 u8 reserved_at_10[0x10];
3375 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3376 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3379 struct mlx5_ifc_teardown_hca_out_bits {
3381 u8 reserved_at_8[0x18];
3385 u8 reserved_at_40[0x3f];
3391 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3392 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3393 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3396 struct mlx5_ifc_teardown_hca_in_bits {
3398 u8 reserved_at_10[0x10];
3400 u8 reserved_at_20[0x10];
3403 u8 reserved_at_40[0x10];
3406 u8 reserved_at_60[0x20];
3409 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3411 u8 reserved_at_8[0x18];
3415 u8 reserved_at_40[0x40];
3418 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3422 u8 reserved_at_20[0x10];
3425 u8 reserved_at_40[0x8];
3428 u8 reserved_at_60[0x20];
3430 u8 opt_param_mask[0x20];
3432 u8 reserved_at_a0[0x20];
3434 struct mlx5_ifc_qpc_bits qpc;
3436 u8 reserved_at_800[0x80];
3439 struct mlx5_ifc_sqd2rts_qp_out_bits {
3441 u8 reserved_at_8[0x18];
3445 u8 reserved_at_40[0x40];
3448 struct mlx5_ifc_sqd2rts_qp_in_bits {
3452 u8 reserved_at_20[0x10];
3455 u8 reserved_at_40[0x8];
3458 u8 reserved_at_60[0x20];
3460 u8 opt_param_mask[0x20];
3462 u8 reserved_at_a0[0x20];
3464 struct mlx5_ifc_qpc_bits qpc;
3466 u8 reserved_at_800[0x80];
3469 struct mlx5_ifc_set_roce_address_out_bits {
3471 u8 reserved_at_8[0x18];
3475 u8 reserved_at_40[0x40];
3478 struct mlx5_ifc_set_roce_address_in_bits {
3480 u8 reserved_at_10[0x10];
3482 u8 reserved_at_20[0x10];
3485 u8 roce_address_index[0x10];
3486 u8 reserved_at_50[0xc];
3487 u8 vhca_port_num[0x4];
3489 u8 reserved_at_60[0x20];
3491 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3494 struct mlx5_ifc_set_mad_demux_out_bits {
3496 u8 reserved_at_8[0x18];
3500 u8 reserved_at_40[0x40];
3504 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3505 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3508 struct mlx5_ifc_set_mad_demux_in_bits {
3510 u8 reserved_at_10[0x10];
3512 u8 reserved_at_20[0x10];
3515 u8 reserved_at_40[0x20];
3517 u8 reserved_at_60[0x6];
3519 u8 reserved_at_68[0x18];
3522 struct mlx5_ifc_set_l2_table_entry_out_bits {
3524 u8 reserved_at_8[0x18];
3528 u8 reserved_at_40[0x40];
3531 struct mlx5_ifc_set_l2_table_entry_in_bits {
3533 u8 reserved_at_10[0x10];
3535 u8 reserved_at_20[0x10];
3538 u8 reserved_at_40[0x60];
3540 u8 reserved_at_a0[0x8];
3541 u8 table_index[0x18];
3543 u8 reserved_at_c0[0x20];
3545 u8 reserved_at_e0[0x13];
3549 struct mlx5_ifc_mac_address_layout_bits mac_address;
3551 u8 reserved_at_140[0xc0];
3554 struct mlx5_ifc_set_issi_out_bits {
3556 u8 reserved_at_8[0x18];
3560 u8 reserved_at_40[0x40];
3563 struct mlx5_ifc_set_issi_in_bits {
3565 u8 reserved_at_10[0x10];
3567 u8 reserved_at_20[0x10];
3570 u8 reserved_at_40[0x10];
3571 u8 current_issi[0x10];
3573 u8 reserved_at_60[0x20];
3576 struct mlx5_ifc_set_hca_cap_out_bits {
3578 u8 reserved_at_8[0x18];
3582 u8 reserved_at_40[0x40];
3585 struct mlx5_ifc_set_hca_cap_in_bits {
3587 u8 reserved_at_10[0x10];
3589 u8 reserved_at_20[0x10];
3592 u8 reserved_at_40[0x40];
3594 union mlx5_ifc_hca_cap_union_bits capability;
3598 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3599 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3600 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3601 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3604 struct mlx5_ifc_set_fte_out_bits {
3606 u8 reserved_at_8[0x18];
3610 u8 reserved_at_40[0x40];
3613 struct mlx5_ifc_set_fte_in_bits {
3615 u8 reserved_at_10[0x10];
3617 u8 reserved_at_20[0x10];
3620 u8 other_vport[0x1];
3621 u8 reserved_at_41[0xf];
3622 u8 vport_number[0x10];
3624 u8 reserved_at_60[0x20];
3627 u8 reserved_at_88[0x18];
3629 u8 reserved_at_a0[0x8];
3632 u8 reserved_at_c0[0x18];
3633 u8 modify_enable_mask[0x8];
3635 u8 reserved_at_e0[0x20];
3637 u8 flow_index[0x20];
3639 u8 reserved_at_120[0xe0];
3641 struct mlx5_ifc_flow_context_bits flow_context;
3644 struct mlx5_ifc_rts2rts_qp_out_bits {
3646 u8 reserved_at_8[0x18];
3650 u8 reserved_at_40[0x40];
3653 struct mlx5_ifc_rts2rts_qp_in_bits {
3657 u8 reserved_at_20[0x10];
3660 u8 reserved_at_40[0x8];
3663 u8 reserved_at_60[0x20];
3665 u8 opt_param_mask[0x20];
3667 u8 reserved_at_a0[0x20];
3669 struct mlx5_ifc_qpc_bits qpc;
3671 u8 reserved_at_800[0x80];
3674 struct mlx5_ifc_rtr2rts_qp_out_bits {
3676 u8 reserved_at_8[0x18];
3680 u8 reserved_at_40[0x40];
3683 struct mlx5_ifc_rtr2rts_qp_in_bits {
3687 u8 reserved_at_20[0x10];
3690 u8 reserved_at_40[0x8];
3693 u8 reserved_at_60[0x20];
3695 u8 opt_param_mask[0x20];
3697 u8 reserved_at_a0[0x20];
3699 struct mlx5_ifc_qpc_bits qpc;
3701 u8 reserved_at_800[0x80];
3704 struct mlx5_ifc_rst2init_qp_out_bits {
3706 u8 reserved_at_8[0x18];
3710 u8 reserved_at_40[0x40];
3713 struct mlx5_ifc_rst2init_qp_in_bits {
3717 u8 reserved_at_20[0x10];
3720 u8 reserved_at_40[0x8];
3723 u8 reserved_at_60[0x20];
3725 u8 opt_param_mask[0x20];
3727 u8 reserved_at_a0[0x20];
3729 struct mlx5_ifc_qpc_bits qpc;
3731 u8 reserved_at_800[0x80];
3734 struct mlx5_ifc_query_xrq_out_bits {
3736 u8 reserved_at_8[0x18];
3740 u8 reserved_at_40[0x40];
3742 struct mlx5_ifc_xrqc_bits xrq_context;
3745 struct mlx5_ifc_query_xrq_in_bits {
3747 u8 reserved_at_10[0x10];
3749 u8 reserved_at_20[0x10];
3752 u8 reserved_at_40[0x8];
3755 u8 reserved_at_60[0x20];
3758 struct mlx5_ifc_query_xrc_srq_out_bits {
3760 u8 reserved_at_8[0x18];
3764 u8 reserved_at_40[0x40];
3766 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3768 u8 reserved_at_280[0x600];
3773 struct mlx5_ifc_query_xrc_srq_in_bits {
3775 u8 reserved_at_10[0x10];
3777 u8 reserved_at_20[0x10];
3780 u8 reserved_at_40[0x8];
3783 u8 reserved_at_60[0x20];
3787 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3788 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3791 struct mlx5_ifc_query_vport_state_out_bits {
3793 u8 reserved_at_8[0x18];
3797 u8 reserved_at_40[0x20];
3799 u8 reserved_at_60[0x18];
3800 u8 admin_state[0x4];
3805 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
3806 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
3809 struct mlx5_ifc_query_vport_state_in_bits {
3811 u8 reserved_at_10[0x10];
3813 u8 reserved_at_20[0x10];
3816 u8 other_vport[0x1];
3817 u8 reserved_at_41[0xf];
3818 u8 vport_number[0x10];
3820 u8 reserved_at_60[0x20];
3823 struct mlx5_ifc_query_vnic_env_out_bits {
3825 u8 reserved_at_8[0x18];
3829 u8 reserved_at_40[0x40];
3831 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3835 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3838 struct mlx5_ifc_query_vnic_env_in_bits {
3840 u8 reserved_at_10[0x10];
3842 u8 reserved_at_20[0x10];
3845 u8 other_vport[0x1];
3846 u8 reserved_at_41[0xf];
3847 u8 vport_number[0x10];
3849 u8 reserved_at_60[0x20];
3852 struct mlx5_ifc_query_vport_counter_out_bits {
3854 u8 reserved_at_8[0x18];
3858 u8 reserved_at_40[0x40];
3860 struct mlx5_ifc_traffic_counter_bits received_errors;
3862 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3864 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3866 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3868 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3870 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3872 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3874 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3876 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3878 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3880 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3882 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3884 u8 reserved_at_680[0xa00];
3888 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3891 struct mlx5_ifc_query_vport_counter_in_bits {
3893 u8 reserved_at_10[0x10];
3895 u8 reserved_at_20[0x10];
3898 u8 other_vport[0x1];
3899 u8 reserved_at_41[0xb];
3901 u8 vport_number[0x10];
3903 u8 reserved_at_60[0x60];
3906 u8 reserved_at_c1[0x1f];
3908 u8 reserved_at_e0[0x20];
3911 struct mlx5_ifc_query_tis_out_bits {
3913 u8 reserved_at_8[0x18];
3917 u8 reserved_at_40[0x40];
3919 struct mlx5_ifc_tisc_bits tis_context;
3922 struct mlx5_ifc_query_tis_in_bits {
3924 u8 reserved_at_10[0x10];
3926 u8 reserved_at_20[0x10];
3929 u8 reserved_at_40[0x8];
3932 u8 reserved_at_60[0x20];
3935 struct mlx5_ifc_query_tir_out_bits {
3937 u8 reserved_at_8[0x18];
3941 u8 reserved_at_40[0xc0];
3943 struct mlx5_ifc_tirc_bits tir_context;
3946 struct mlx5_ifc_query_tir_in_bits {
3948 u8 reserved_at_10[0x10];
3950 u8 reserved_at_20[0x10];
3953 u8 reserved_at_40[0x8];
3956 u8 reserved_at_60[0x20];
3959 struct mlx5_ifc_query_srq_out_bits {
3961 u8 reserved_at_8[0x18];
3965 u8 reserved_at_40[0x40];
3967 struct mlx5_ifc_srqc_bits srq_context_entry;
3969 u8 reserved_at_280[0x600];
3974 struct mlx5_ifc_query_srq_in_bits {
3976 u8 reserved_at_10[0x10];
3978 u8 reserved_at_20[0x10];
3981 u8 reserved_at_40[0x8];
3984 u8 reserved_at_60[0x20];
3987 struct mlx5_ifc_query_sq_out_bits {
3989 u8 reserved_at_8[0x18];
3993 u8 reserved_at_40[0xc0];
3995 struct mlx5_ifc_sqc_bits sq_context;
3998 struct mlx5_ifc_query_sq_in_bits {
4000 u8 reserved_at_10[0x10];
4002 u8 reserved_at_20[0x10];
4005 u8 reserved_at_40[0x8];
4008 u8 reserved_at_60[0x20];
4011 struct mlx5_ifc_query_special_contexts_out_bits {
4013 u8 reserved_at_8[0x18];
4017 u8 dump_fill_mkey[0x20];
4023 u8 reserved_at_a0[0x60];
4026 struct mlx5_ifc_query_special_contexts_in_bits {
4028 u8 reserved_at_10[0x10];
4030 u8 reserved_at_20[0x10];
4033 u8 reserved_at_40[0x40];
4036 struct mlx5_ifc_query_scheduling_element_out_bits {
4038 u8 reserved_at_10[0x10];
4040 u8 reserved_at_20[0x10];
4043 u8 reserved_at_40[0xc0];
4045 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4047 u8 reserved_at_300[0x100];
4051 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4054 struct mlx5_ifc_query_scheduling_element_in_bits {
4056 u8 reserved_at_10[0x10];
4058 u8 reserved_at_20[0x10];
4061 u8 scheduling_hierarchy[0x8];
4062 u8 reserved_at_48[0x18];
4064 u8 scheduling_element_id[0x20];
4066 u8 reserved_at_80[0x180];
4069 struct mlx5_ifc_query_rqt_out_bits {
4071 u8 reserved_at_8[0x18];
4075 u8 reserved_at_40[0xc0];
4077 struct mlx5_ifc_rqtc_bits rqt_context;
4080 struct mlx5_ifc_query_rqt_in_bits {
4082 u8 reserved_at_10[0x10];
4084 u8 reserved_at_20[0x10];
4087 u8 reserved_at_40[0x8];
4090 u8 reserved_at_60[0x20];
4093 struct mlx5_ifc_query_rq_out_bits {
4095 u8 reserved_at_8[0x18];
4099 u8 reserved_at_40[0xc0];
4101 struct mlx5_ifc_rqc_bits rq_context;
4104 struct mlx5_ifc_query_rq_in_bits {
4106 u8 reserved_at_10[0x10];
4108 u8 reserved_at_20[0x10];
4111 u8 reserved_at_40[0x8];
4114 u8 reserved_at_60[0x20];
4117 struct mlx5_ifc_query_roce_address_out_bits {
4119 u8 reserved_at_8[0x18];
4123 u8 reserved_at_40[0x40];
4125 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4128 struct mlx5_ifc_query_roce_address_in_bits {
4130 u8 reserved_at_10[0x10];
4132 u8 reserved_at_20[0x10];
4135 u8 roce_address_index[0x10];
4136 u8 reserved_at_50[0xc];
4137 u8 vhca_port_num[0x4];
4139 u8 reserved_at_60[0x20];
4142 struct mlx5_ifc_query_rmp_out_bits {
4144 u8 reserved_at_8[0x18];
4148 u8 reserved_at_40[0xc0];
4150 struct mlx5_ifc_rmpc_bits rmp_context;
4153 struct mlx5_ifc_query_rmp_in_bits {
4155 u8 reserved_at_10[0x10];
4157 u8 reserved_at_20[0x10];
4160 u8 reserved_at_40[0x8];
4163 u8 reserved_at_60[0x20];
4166 struct mlx5_ifc_query_qp_out_bits {
4168 u8 reserved_at_8[0x18];
4172 u8 reserved_at_40[0x40];
4174 u8 opt_param_mask[0x20];
4176 u8 reserved_at_a0[0x20];
4178 struct mlx5_ifc_qpc_bits qpc;
4180 u8 reserved_at_800[0x80];
4185 struct mlx5_ifc_query_qp_in_bits {
4187 u8 reserved_at_10[0x10];
4189 u8 reserved_at_20[0x10];
4192 u8 reserved_at_40[0x8];
4195 u8 reserved_at_60[0x20];
4198 struct mlx5_ifc_query_q_counter_out_bits {
4200 u8 reserved_at_8[0x18];
4204 u8 reserved_at_40[0x40];
4206 u8 rx_write_requests[0x20];
4208 u8 reserved_at_a0[0x20];
4210 u8 rx_read_requests[0x20];
4212 u8 reserved_at_e0[0x20];
4214 u8 rx_atomic_requests[0x20];
4216 u8 reserved_at_120[0x20];
4218 u8 rx_dct_connect[0x20];
4220 u8 reserved_at_160[0x20];
4222 u8 out_of_buffer[0x20];
4224 u8 reserved_at_1a0[0x20];
4226 u8 out_of_sequence[0x20];
4228 u8 reserved_at_1e0[0x20];
4230 u8 duplicate_request[0x20];
4232 u8 reserved_at_220[0x20];
4234 u8 rnr_nak_retry_err[0x20];
4236 u8 reserved_at_260[0x20];
4238 u8 packet_seq_err[0x20];
4240 u8 reserved_at_2a0[0x20];
4242 u8 implied_nak_seq_err[0x20];
4244 u8 reserved_at_2e0[0x20];
4246 u8 local_ack_timeout_err[0x20];
4248 u8 reserved_at_320[0xa0];
4250 u8 resp_local_length_error[0x20];
4252 u8 req_local_length_error[0x20];
4254 u8 resp_local_qp_error[0x20];
4256 u8 local_operation_error[0x20];
4258 u8 resp_local_protection[0x20];
4260 u8 req_local_protection[0x20];
4262 u8 resp_cqe_error[0x20];
4264 u8 req_cqe_error[0x20];
4266 u8 req_mw_binding[0x20];
4268 u8 req_bad_response[0x20];
4270 u8 req_remote_invalid_request[0x20];
4272 u8 resp_remote_invalid_request[0x20];
4274 u8 req_remote_access_errors[0x20];
4276 u8 resp_remote_access_errors[0x20];
4278 u8 req_remote_operation_errors[0x20];
4280 u8 req_transport_retries_exceeded[0x20];
4282 u8 cq_overflow[0x20];
4284 u8 resp_cqe_flush_error[0x20];
4286 u8 req_cqe_flush_error[0x20];
4288 u8 reserved_at_620[0x1e0];
4291 struct mlx5_ifc_query_q_counter_in_bits {
4293 u8 reserved_at_10[0x10];
4295 u8 reserved_at_20[0x10];
4298 u8 reserved_at_40[0x80];
4301 u8 reserved_at_c1[0x1f];
4303 u8 reserved_at_e0[0x18];
4304 u8 counter_set_id[0x8];
4307 struct mlx5_ifc_query_pages_out_bits {
4309 u8 reserved_at_8[0x18];
4313 u8 reserved_at_40[0x10];
4314 u8 function_id[0x10];
4320 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4321 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4322 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4325 struct mlx5_ifc_query_pages_in_bits {
4327 u8 reserved_at_10[0x10];
4329 u8 reserved_at_20[0x10];
4332 u8 reserved_at_40[0x10];
4333 u8 function_id[0x10];
4335 u8 reserved_at_60[0x20];
4338 struct mlx5_ifc_query_nic_vport_context_out_bits {
4340 u8 reserved_at_8[0x18];
4344 u8 reserved_at_40[0x40];
4346 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4349 struct mlx5_ifc_query_nic_vport_context_in_bits {
4351 u8 reserved_at_10[0x10];
4353 u8 reserved_at_20[0x10];
4356 u8 other_vport[0x1];
4357 u8 reserved_at_41[0xf];
4358 u8 vport_number[0x10];
4360 u8 reserved_at_60[0x5];
4361 u8 allowed_list_type[0x3];
4362 u8 reserved_at_68[0x18];
4365 struct mlx5_ifc_query_mkey_out_bits {
4367 u8 reserved_at_8[0x18];
4371 u8 reserved_at_40[0x40];
4373 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4375 u8 reserved_at_280[0x600];
4377 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4379 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4382 struct mlx5_ifc_query_mkey_in_bits {
4384 u8 reserved_at_10[0x10];
4386 u8 reserved_at_20[0x10];
4389 u8 reserved_at_40[0x8];
4390 u8 mkey_index[0x18];
4393 u8 reserved_at_61[0x1f];
4396 struct mlx5_ifc_query_mad_demux_out_bits {
4398 u8 reserved_at_8[0x18];
4402 u8 reserved_at_40[0x40];
4404 u8 mad_dumux_parameters_block[0x20];
4407 struct mlx5_ifc_query_mad_demux_in_bits {
4409 u8 reserved_at_10[0x10];
4411 u8 reserved_at_20[0x10];
4414 u8 reserved_at_40[0x40];
4417 struct mlx5_ifc_query_l2_table_entry_out_bits {
4419 u8 reserved_at_8[0x18];
4423 u8 reserved_at_40[0xa0];
4425 u8 reserved_at_e0[0x13];
4429 struct mlx5_ifc_mac_address_layout_bits mac_address;
4431 u8 reserved_at_140[0xc0];
4434 struct mlx5_ifc_query_l2_table_entry_in_bits {
4436 u8 reserved_at_10[0x10];
4438 u8 reserved_at_20[0x10];
4441 u8 reserved_at_40[0x60];
4443 u8 reserved_at_a0[0x8];
4444 u8 table_index[0x18];
4446 u8 reserved_at_c0[0x140];
4449 struct mlx5_ifc_query_issi_out_bits {
4451 u8 reserved_at_8[0x18];
4455 u8 reserved_at_40[0x10];
4456 u8 current_issi[0x10];
4458 u8 reserved_at_60[0xa0];
4460 u8 reserved_at_100[76][0x8];
4461 u8 supported_issi_dw0[0x20];
4464 struct mlx5_ifc_query_issi_in_bits {
4466 u8 reserved_at_10[0x10];
4468 u8 reserved_at_20[0x10];
4471 u8 reserved_at_40[0x40];
4474 struct mlx5_ifc_set_driver_version_out_bits {
4476 u8 reserved_0[0x18];
4479 u8 reserved_1[0x40];
4482 struct mlx5_ifc_set_driver_version_in_bits {
4484 u8 reserved_0[0x10];
4486 u8 reserved_1[0x10];
4489 u8 reserved_2[0x40];
4490 u8 driver_version[64][0x8];
4493 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4495 u8 reserved_at_8[0x18];
4499 u8 reserved_at_40[0x40];
4501 struct mlx5_ifc_pkey_bits pkey[0];
4504 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4506 u8 reserved_at_10[0x10];
4508 u8 reserved_at_20[0x10];
4511 u8 other_vport[0x1];
4512 u8 reserved_at_41[0xb];
4514 u8 vport_number[0x10];
4516 u8 reserved_at_60[0x10];
4517 u8 pkey_index[0x10];
4521 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4522 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4523 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4526 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4528 u8 reserved_at_8[0x18];
4532 u8 reserved_at_40[0x20];
4535 u8 reserved_at_70[0x10];
4537 struct mlx5_ifc_array128_auto_bits gid[0];
4540 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4542 u8 reserved_at_10[0x10];
4544 u8 reserved_at_20[0x10];
4547 u8 other_vport[0x1];
4548 u8 reserved_at_41[0xb];
4550 u8 vport_number[0x10];
4552 u8 reserved_at_60[0x10];
4556 struct mlx5_ifc_query_hca_vport_context_out_bits {
4558 u8 reserved_at_8[0x18];
4562 u8 reserved_at_40[0x40];
4564 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4567 struct mlx5_ifc_query_hca_vport_context_in_bits {
4569 u8 reserved_at_10[0x10];
4571 u8 reserved_at_20[0x10];
4574 u8 other_vport[0x1];
4575 u8 reserved_at_41[0xb];
4577 u8 vport_number[0x10];
4579 u8 reserved_at_60[0x20];
4582 struct mlx5_ifc_query_hca_cap_out_bits {
4584 u8 reserved_at_8[0x18];
4588 u8 reserved_at_40[0x40];
4590 union mlx5_ifc_hca_cap_union_bits capability;
4593 struct mlx5_ifc_query_hca_cap_in_bits {
4595 u8 reserved_at_10[0x10];
4597 u8 reserved_at_20[0x10];
4600 u8 reserved_at_40[0x40];
4603 struct mlx5_ifc_query_flow_table_out_bits {
4605 u8 reserved_at_8[0x18];
4609 u8 reserved_at_40[0x80];
4611 u8 reserved_at_c0[0x8];
4613 u8 reserved_at_d0[0x8];
4616 u8 reserved_at_e0[0x120];
4619 struct mlx5_ifc_query_flow_table_in_bits {
4621 u8 reserved_at_10[0x10];
4623 u8 reserved_at_20[0x10];
4626 u8 reserved_at_40[0x40];
4629 u8 reserved_at_88[0x18];
4631 u8 reserved_at_a0[0x8];
4634 u8 reserved_at_c0[0x140];
4637 struct mlx5_ifc_query_fte_out_bits {
4639 u8 reserved_at_8[0x18];
4643 u8 reserved_at_40[0x1c0];
4645 struct mlx5_ifc_flow_context_bits flow_context;
4648 struct mlx5_ifc_query_fte_in_bits {
4650 u8 reserved_at_10[0x10];
4652 u8 reserved_at_20[0x10];
4655 u8 reserved_at_40[0x40];
4658 u8 reserved_at_88[0x18];
4660 u8 reserved_at_a0[0x8];
4663 u8 reserved_at_c0[0x40];
4665 u8 flow_index[0x20];
4667 u8 reserved_at_120[0xe0];
4671 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4672 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4673 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4674 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4677 struct mlx5_ifc_query_flow_group_out_bits {
4679 u8 reserved_at_8[0x18];
4683 u8 reserved_at_40[0xa0];
4685 u8 start_flow_index[0x20];
4687 u8 reserved_at_100[0x20];
4689 u8 end_flow_index[0x20];
4691 u8 reserved_at_140[0xa0];
4693 u8 reserved_at_1e0[0x18];
4694 u8 match_criteria_enable[0x8];
4696 struct mlx5_ifc_fte_match_param_bits match_criteria;
4698 u8 reserved_at_1200[0xe00];
4701 struct mlx5_ifc_query_flow_group_in_bits {
4703 u8 reserved_at_10[0x10];
4705 u8 reserved_at_20[0x10];
4708 u8 reserved_at_40[0x40];
4711 u8 reserved_at_88[0x18];
4713 u8 reserved_at_a0[0x8];
4718 u8 reserved_at_e0[0x120];
4721 struct mlx5_ifc_query_flow_counter_out_bits {
4723 u8 reserved_at_8[0x18];
4727 u8 reserved_at_40[0x40];
4729 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4732 struct mlx5_ifc_query_flow_counter_in_bits {
4734 u8 reserved_at_10[0x10];
4736 u8 reserved_at_20[0x10];
4739 u8 reserved_at_40[0x80];
4742 u8 reserved_at_c1[0xf];
4743 u8 num_of_counters[0x10];
4745 u8 flow_counter_id[0x20];
4748 struct mlx5_ifc_query_esw_vport_context_out_bits {
4750 u8 reserved_at_8[0x18];
4754 u8 reserved_at_40[0x40];
4756 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4759 struct mlx5_ifc_query_esw_vport_context_in_bits {
4761 u8 reserved_at_10[0x10];
4763 u8 reserved_at_20[0x10];
4766 u8 other_vport[0x1];
4767 u8 reserved_at_41[0xf];
4768 u8 vport_number[0x10];
4770 u8 reserved_at_60[0x20];
4773 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4775 u8 reserved_at_8[0x18];
4779 u8 reserved_at_40[0x40];
4782 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4783 u8 reserved_at_0[0x1c];
4784 u8 vport_cvlan_insert[0x1];
4785 u8 vport_svlan_insert[0x1];
4786 u8 vport_cvlan_strip[0x1];
4787 u8 vport_svlan_strip[0x1];
4790 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4792 u8 reserved_at_10[0x10];
4794 u8 reserved_at_20[0x10];
4797 u8 other_vport[0x1];
4798 u8 reserved_at_41[0xf];
4799 u8 vport_number[0x10];
4801 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4803 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4806 struct mlx5_ifc_query_eq_out_bits {
4808 u8 reserved_at_8[0x18];
4812 u8 reserved_at_40[0x40];
4814 struct mlx5_ifc_eqc_bits eq_context_entry;
4816 u8 reserved_at_280[0x40];
4818 u8 event_bitmask[0x40];
4820 u8 reserved_at_300[0x580];
4825 struct mlx5_ifc_query_eq_in_bits {
4827 u8 reserved_at_10[0x10];
4829 u8 reserved_at_20[0x10];
4832 u8 reserved_at_40[0x18];
4835 u8 reserved_at_60[0x20];
4838 struct mlx5_ifc_packet_reformat_context_in_bits {
4839 u8 reserved_at_0[0x5];
4840 u8 reformat_type[0x3];
4841 u8 reserved_at_8[0xe];
4842 u8 reformat_data_size[0xa];
4844 u8 reserved_at_20[0x10];
4845 u8 reformat_data[2][0x8];
4847 u8 more_reformat_data[0][0x8];
4850 struct mlx5_ifc_query_packet_reformat_context_out_bits {
4852 u8 reserved_at_8[0x18];
4856 u8 reserved_at_40[0xa0];
4858 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
4861 struct mlx5_ifc_query_packet_reformat_context_in_bits {
4863 u8 reserved_at_10[0x10];
4865 u8 reserved_at_20[0x10];
4868 u8 packet_reformat_id[0x20];
4870 u8 reserved_at_60[0xa0];
4873 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
4875 u8 reserved_at_8[0x18];
4879 u8 packet_reformat_id[0x20];
4881 u8 reserved_at_60[0x20];
4885 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
4886 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
4887 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
4888 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
4889 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
4892 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
4894 u8 reserved_at_10[0x10];
4896 u8 reserved_at_20[0x10];
4899 u8 reserved_at_40[0xa0];
4901 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
4904 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
4906 u8 reserved_at_8[0x18];
4910 u8 reserved_at_40[0x40];
4913 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
4915 u8 reserved_at_10[0x10];
4917 u8 reserved_20[0x10];
4920 u8 packet_reformat_id[0x20];
4922 u8 reserved_60[0x20];
4925 struct mlx5_ifc_set_action_in_bits {
4926 u8 action_type[0x4];
4928 u8 reserved_at_10[0x3];
4930 u8 reserved_at_18[0x3];
4936 struct mlx5_ifc_add_action_in_bits {
4937 u8 action_type[0x4];
4939 u8 reserved_at_10[0x10];
4944 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4945 struct mlx5_ifc_set_action_in_bits set_action_in;
4946 struct mlx5_ifc_add_action_in_bits add_action_in;
4947 u8 reserved_at_0[0x40];
4951 MLX5_ACTION_TYPE_SET = 0x1,
4952 MLX5_ACTION_TYPE_ADD = 0x2,
4956 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4957 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4958 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4959 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4960 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4961 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4962 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4963 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4964 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4965 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4966 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4967 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4968 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4969 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4970 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4971 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4972 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4973 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4974 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4975 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4976 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4977 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4978 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4981 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4983 u8 reserved_at_8[0x18];
4987 u8 modify_header_id[0x20];
4989 u8 reserved_at_60[0x20];
4992 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4994 u8 reserved_at_10[0x10];
4996 u8 reserved_at_20[0x10];
4999 u8 reserved_at_40[0x20];
5002 u8 reserved_at_68[0x10];
5003 u8 num_of_actions[0x8];
5005 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5008 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5010 u8 reserved_at_8[0x18];
5014 u8 reserved_at_40[0x40];
5017 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5019 u8 reserved_at_10[0x10];
5021 u8 reserved_at_20[0x10];
5024 u8 modify_header_id[0x20];
5026 u8 reserved_at_60[0x20];
5029 struct mlx5_ifc_query_dct_out_bits {
5031 u8 reserved_at_8[0x18];
5035 u8 reserved_at_40[0x40];
5037 struct mlx5_ifc_dctc_bits dct_context_entry;
5039 u8 reserved_at_280[0x180];
5042 struct mlx5_ifc_query_dct_in_bits {
5044 u8 reserved_at_10[0x10];
5046 u8 reserved_at_20[0x10];
5049 u8 reserved_at_40[0x8];
5052 u8 reserved_at_60[0x20];
5055 struct mlx5_ifc_query_cq_out_bits {
5057 u8 reserved_at_8[0x18];
5061 u8 reserved_at_40[0x40];
5063 struct mlx5_ifc_cqc_bits cq_context;
5065 u8 reserved_at_280[0x600];
5070 struct mlx5_ifc_query_cq_in_bits {
5072 u8 reserved_at_10[0x10];
5074 u8 reserved_at_20[0x10];
5077 u8 reserved_at_40[0x8];
5080 u8 reserved_at_60[0x20];
5083 struct mlx5_ifc_query_cong_status_out_bits {
5085 u8 reserved_at_8[0x18];
5089 u8 reserved_at_40[0x20];
5093 u8 reserved_at_62[0x1e];
5096 struct mlx5_ifc_query_cong_status_in_bits {
5098 u8 reserved_at_10[0x10];
5100 u8 reserved_at_20[0x10];
5103 u8 reserved_at_40[0x18];
5105 u8 cong_protocol[0x4];
5107 u8 reserved_at_60[0x20];
5110 struct mlx5_ifc_query_cong_statistics_out_bits {
5112 u8 reserved_at_8[0x18];
5116 u8 reserved_at_40[0x40];
5118 u8 rp_cur_flows[0x20];
5122 u8 rp_cnp_ignored_high[0x20];
5124 u8 rp_cnp_ignored_low[0x20];
5126 u8 rp_cnp_handled_high[0x20];
5128 u8 rp_cnp_handled_low[0x20];
5130 u8 reserved_at_140[0x100];
5132 u8 time_stamp_high[0x20];
5134 u8 time_stamp_low[0x20];
5136 u8 accumulators_period[0x20];
5138 u8 np_ecn_marked_roce_packets_high[0x20];
5140 u8 np_ecn_marked_roce_packets_low[0x20];
5142 u8 np_cnp_sent_high[0x20];
5144 u8 np_cnp_sent_low[0x20];
5146 u8 reserved_at_320[0x560];
5149 struct mlx5_ifc_query_cong_statistics_in_bits {
5151 u8 reserved_at_10[0x10];
5153 u8 reserved_at_20[0x10];
5157 u8 reserved_at_41[0x1f];
5159 u8 reserved_at_60[0x20];
5162 struct mlx5_ifc_query_cong_params_out_bits {
5164 u8 reserved_at_8[0x18];
5168 u8 reserved_at_40[0x40];
5170 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5173 struct mlx5_ifc_query_cong_params_in_bits {
5175 u8 reserved_at_10[0x10];
5177 u8 reserved_at_20[0x10];
5180 u8 reserved_at_40[0x1c];
5181 u8 cong_protocol[0x4];
5183 u8 reserved_at_60[0x20];
5186 struct mlx5_ifc_query_adapter_out_bits {
5188 u8 reserved_at_8[0x18];
5192 u8 reserved_at_40[0x40];
5194 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5197 struct mlx5_ifc_query_adapter_in_bits {
5199 u8 reserved_at_10[0x10];
5201 u8 reserved_at_20[0x10];
5204 u8 reserved_at_40[0x40];
5207 struct mlx5_ifc_qp_2rst_out_bits {
5209 u8 reserved_at_8[0x18];
5213 u8 reserved_at_40[0x40];
5216 struct mlx5_ifc_qp_2rst_in_bits {
5220 u8 reserved_at_20[0x10];
5223 u8 reserved_at_40[0x8];
5226 u8 reserved_at_60[0x20];
5229 struct mlx5_ifc_qp_2err_out_bits {
5231 u8 reserved_at_8[0x18];
5235 u8 reserved_at_40[0x40];
5238 struct mlx5_ifc_qp_2err_in_bits {
5242 u8 reserved_at_20[0x10];
5245 u8 reserved_at_40[0x8];
5248 u8 reserved_at_60[0x20];
5251 struct mlx5_ifc_page_fault_resume_out_bits {
5253 u8 reserved_at_8[0x18];
5257 u8 reserved_at_40[0x40];
5260 struct mlx5_ifc_page_fault_resume_in_bits {
5262 u8 reserved_at_10[0x10];
5264 u8 reserved_at_20[0x10];
5268 u8 reserved_at_41[0x4];
5269 u8 page_fault_type[0x3];
5272 u8 reserved_at_60[0x8];
5276 struct mlx5_ifc_nop_out_bits {
5278 u8 reserved_at_8[0x18];
5282 u8 reserved_at_40[0x40];
5285 struct mlx5_ifc_nop_in_bits {
5287 u8 reserved_at_10[0x10];
5289 u8 reserved_at_20[0x10];
5292 u8 reserved_at_40[0x40];
5295 struct mlx5_ifc_modify_vport_state_out_bits {
5297 u8 reserved_at_8[0x18];
5301 u8 reserved_at_40[0x40];
5304 struct mlx5_ifc_modify_vport_state_in_bits {
5306 u8 reserved_at_10[0x10];
5308 u8 reserved_at_20[0x10];
5311 u8 other_vport[0x1];
5312 u8 reserved_at_41[0xf];
5313 u8 vport_number[0x10];
5315 u8 reserved_at_60[0x18];
5316 u8 admin_state[0x4];
5317 u8 reserved_at_7c[0x4];
5320 struct mlx5_ifc_modify_tis_out_bits {
5322 u8 reserved_at_8[0x18];
5326 u8 reserved_at_40[0x40];
5329 struct mlx5_ifc_modify_tis_bitmask_bits {
5330 u8 reserved_at_0[0x20];
5332 u8 reserved_at_20[0x1d];
5333 u8 lag_tx_port_affinity[0x1];
5334 u8 strict_lag_tx_port_affinity[0x1];
5338 struct mlx5_ifc_modify_tis_in_bits {
5342 u8 reserved_at_20[0x10];
5345 u8 reserved_at_40[0x8];
5348 u8 reserved_at_60[0x20];
5350 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5352 u8 reserved_at_c0[0x40];
5354 struct mlx5_ifc_tisc_bits ctx;
5357 struct mlx5_ifc_modify_tir_bitmask_bits {
5358 u8 reserved_at_0[0x20];
5360 u8 reserved_at_20[0x1b];
5362 u8 reserved_at_3c[0x1];
5364 u8 reserved_at_3e[0x1];
5368 struct mlx5_ifc_modify_tir_out_bits {
5370 u8 reserved_at_8[0x18];
5374 u8 reserved_at_40[0x40];
5377 struct mlx5_ifc_modify_tir_in_bits {
5381 u8 reserved_at_20[0x10];
5384 u8 reserved_at_40[0x8];
5387 u8 reserved_at_60[0x20];
5389 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5391 u8 reserved_at_c0[0x40];
5393 struct mlx5_ifc_tirc_bits ctx;
5396 struct mlx5_ifc_modify_sq_out_bits {
5398 u8 reserved_at_8[0x18];
5402 u8 reserved_at_40[0x40];
5405 struct mlx5_ifc_modify_sq_in_bits {
5409 u8 reserved_at_20[0x10];
5413 u8 reserved_at_44[0x4];
5416 u8 reserved_at_60[0x20];
5418 u8 modify_bitmask[0x40];
5420 u8 reserved_at_c0[0x40];
5422 struct mlx5_ifc_sqc_bits ctx;
5425 struct mlx5_ifc_modify_scheduling_element_out_bits {
5427 u8 reserved_at_8[0x18];
5431 u8 reserved_at_40[0x1c0];
5435 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5436 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5439 struct mlx5_ifc_modify_scheduling_element_in_bits {
5441 u8 reserved_at_10[0x10];
5443 u8 reserved_at_20[0x10];
5446 u8 scheduling_hierarchy[0x8];
5447 u8 reserved_at_48[0x18];
5449 u8 scheduling_element_id[0x20];
5451 u8 reserved_at_80[0x20];
5453 u8 modify_bitmask[0x20];
5455 u8 reserved_at_c0[0x40];
5457 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5459 u8 reserved_at_300[0x100];
5462 struct mlx5_ifc_modify_rqt_out_bits {
5464 u8 reserved_at_8[0x18];
5468 u8 reserved_at_40[0x40];
5471 struct mlx5_ifc_rqt_bitmask_bits {
5472 u8 reserved_at_0[0x20];
5474 u8 reserved_at_20[0x1f];
5478 struct mlx5_ifc_modify_rqt_in_bits {
5482 u8 reserved_at_20[0x10];
5485 u8 reserved_at_40[0x8];
5488 u8 reserved_at_60[0x20];
5490 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5492 u8 reserved_at_c0[0x40];
5494 struct mlx5_ifc_rqtc_bits ctx;
5497 struct mlx5_ifc_modify_rq_out_bits {
5499 u8 reserved_at_8[0x18];
5503 u8 reserved_at_40[0x40];
5507 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5508 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5509 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5512 struct mlx5_ifc_modify_rq_in_bits {
5516 u8 reserved_at_20[0x10];
5520 u8 reserved_at_44[0x4];
5523 u8 reserved_at_60[0x20];
5525 u8 modify_bitmask[0x40];
5527 u8 reserved_at_c0[0x40];
5529 struct mlx5_ifc_rqc_bits ctx;
5532 struct mlx5_ifc_modify_rmp_out_bits {
5534 u8 reserved_at_8[0x18];
5538 u8 reserved_at_40[0x40];
5541 struct mlx5_ifc_rmp_bitmask_bits {
5542 u8 reserved_at_0[0x20];
5544 u8 reserved_at_20[0x1f];
5548 struct mlx5_ifc_modify_rmp_in_bits {
5552 u8 reserved_at_20[0x10];
5556 u8 reserved_at_44[0x4];
5559 u8 reserved_at_60[0x20];
5561 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5563 u8 reserved_at_c0[0x40];
5565 struct mlx5_ifc_rmpc_bits ctx;
5568 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5570 u8 reserved_at_8[0x18];
5574 u8 reserved_at_40[0x40];
5577 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5578 u8 reserved_at_0[0x12];
5579 u8 affiliation[0x1];
5580 u8 reserved_at_13[0x1];
5581 u8 disable_uc_local_lb[0x1];
5582 u8 disable_mc_local_lb[0x1];
5587 u8 change_event[0x1];
5589 u8 permanent_address[0x1];
5590 u8 addresses_list[0x1];
5592 u8 reserved_at_1f[0x1];
5595 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5597 u8 reserved_at_10[0x10];
5599 u8 reserved_at_20[0x10];
5602 u8 other_vport[0x1];
5603 u8 reserved_at_41[0xf];
5604 u8 vport_number[0x10];
5606 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5608 u8 reserved_at_80[0x780];
5610 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5613 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5615 u8 reserved_at_8[0x18];
5619 u8 reserved_at_40[0x40];
5622 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5624 u8 reserved_at_10[0x10];
5626 u8 reserved_at_20[0x10];
5629 u8 other_vport[0x1];
5630 u8 reserved_at_41[0xb];
5632 u8 vport_number[0x10];
5634 u8 reserved_at_60[0x20];
5636 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5639 struct mlx5_ifc_modify_cq_out_bits {
5641 u8 reserved_at_8[0x18];
5645 u8 reserved_at_40[0x40];
5649 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5650 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5653 struct mlx5_ifc_modify_cq_in_bits {
5657 u8 reserved_at_20[0x10];
5660 u8 reserved_at_40[0x8];
5663 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5665 struct mlx5_ifc_cqc_bits cq_context;
5667 u8 reserved_at_280[0x40];
5669 u8 cq_umem_valid[0x1];
5670 u8 reserved_at_2c1[0x5bf];
5675 struct mlx5_ifc_modify_cong_status_out_bits {
5677 u8 reserved_at_8[0x18];
5681 u8 reserved_at_40[0x40];
5684 struct mlx5_ifc_modify_cong_status_in_bits {
5686 u8 reserved_at_10[0x10];
5688 u8 reserved_at_20[0x10];
5691 u8 reserved_at_40[0x18];
5693 u8 cong_protocol[0x4];
5697 u8 reserved_at_62[0x1e];
5700 struct mlx5_ifc_modify_cong_params_out_bits {
5702 u8 reserved_at_8[0x18];
5706 u8 reserved_at_40[0x40];
5709 struct mlx5_ifc_modify_cong_params_in_bits {
5711 u8 reserved_at_10[0x10];
5713 u8 reserved_at_20[0x10];
5716 u8 reserved_at_40[0x1c];
5717 u8 cong_protocol[0x4];
5719 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5721 u8 reserved_at_80[0x80];
5723 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5726 struct mlx5_ifc_manage_pages_out_bits {
5728 u8 reserved_at_8[0x18];
5732 u8 output_num_entries[0x20];
5734 u8 reserved_at_60[0x20];
5740 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5741 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5742 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5745 struct mlx5_ifc_manage_pages_in_bits {
5747 u8 reserved_at_10[0x10];
5749 u8 reserved_at_20[0x10];
5752 u8 reserved_at_40[0x10];
5753 u8 function_id[0x10];
5755 u8 input_num_entries[0x20];
5760 struct mlx5_ifc_mad_ifc_out_bits {
5762 u8 reserved_at_8[0x18];
5766 u8 reserved_at_40[0x40];
5768 u8 response_mad_packet[256][0x8];
5771 struct mlx5_ifc_mad_ifc_in_bits {
5773 u8 reserved_at_10[0x10];
5775 u8 reserved_at_20[0x10];
5778 u8 remote_lid[0x10];
5779 u8 reserved_at_50[0x8];
5782 u8 reserved_at_60[0x20];
5787 struct mlx5_ifc_init_hca_out_bits {
5789 u8 reserved_at_8[0x18];
5793 u8 reserved_at_40[0x40];
5796 struct mlx5_ifc_init_hca_in_bits {
5798 u8 reserved_at_10[0x10];
5800 u8 reserved_at_20[0x10];
5803 u8 reserved_at_40[0x40];
5804 u8 sw_owner_id[4][0x20];
5807 struct mlx5_ifc_init2rtr_qp_out_bits {
5809 u8 reserved_at_8[0x18];
5813 u8 reserved_at_40[0x40];
5816 struct mlx5_ifc_init2rtr_qp_in_bits {
5820 u8 reserved_at_20[0x10];
5823 u8 reserved_at_40[0x8];
5826 u8 reserved_at_60[0x20];
5828 u8 opt_param_mask[0x20];
5830 u8 reserved_at_a0[0x20];
5832 struct mlx5_ifc_qpc_bits qpc;
5834 u8 reserved_at_800[0x80];
5837 struct mlx5_ifc_init2init_qp_out_bits {
5839 u8 reserved_at_8[0x18];
5843 u8 reserved_at_40[0x40];
5846 struct mlx5_ifc_init2init_qp_in_bits {
5850 u8 reserved_at_20[0x10];
5853 u8 reserved_at_40[0x8];
5856 u8 reserved_at_60[0x20];
5858 u8 opt_param_mask[0x20];
5860 u8 reserved_at_a0[0x20];
5862 struct mlx5_ifc_qpc_bits qpc;
5864 u8 reserved_at_800[0x80];
5867 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5869 u8 reserved_at_8[0x18];
5873 u8 reserved_at_40[0x40];
5875 u8 packet_headers_log[128][0x8];
5877 u8 packet_syndrome[64][0x8];
5880 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5882 u8 reserved_at_10[0x10];
5884 u8 reserved_at_20[0x10];
5887 u8 reserved_at_40[0x40];
5890 struct mlx5_ifc_gen_eqe_in_bits {
5892 u8 reserved_at_10[0x10];
5894 u8 reserved_at_20[0x10];
5897 u8 reserved_at_40[0x18];
5900 u8 reserved_at_60[0x20];
5905 struct mlx5_ifc_gen_eq_out_bits {
5907 u8 reserved_at_8[0x18];
5911 u8 reserved_at_40[0x40];
5914 struct mlx5_ifc_enable_hca_out_bits {
5916 u8 reserved_at_8[0x18];
5920 u8 reserved_at_40[0x20];
5923 struct mlx5_ifc_enable_hca_in_bits {
5925 u8 reserved_at_10[0x10];
5927 u8 reserved_at_20[0x10];
5930 u8 reserved_at_40[0x10];
5931 u8 function_id[0x10];
5933 u8 reserved_at_60[0x20];
5936 struct mlx5_ifc_drain_dct_out_bits {
5938 u8 reserved_at_8[0x18];
5942 u8 reserved_at_40[0x40];
5945 struct mlx5_ifc_drain_dct_in_bits {
5949 u8 reserved_at_20[0x10];
5952 u8 reserved_at_40[0x8];
5955 u8 reserved_at_60[0x20];
5958 struct mlx5_ifc_disable_hca_out_bits {
5960 u8 reserved_at_8[0x18];
5964 u8 reserved_at_40[0x20];
5967 struct mlx5_ifc_disable_hca_in_bits {
5969 u8 reserved_at_10[0x10];
5971 u8 reserved_at_20[0x10];
5974 u8 reserved_at_40[0x10];
5975 u8 function_id[0x10];
5977 u8 reserved_at_60[0x20];
5980 struct mlx5_ifc_detach_from_mcg_out_bits {
5982 u8 reserved_at_8[0x18];
5986 u8 reserved_at_40[0x40];
5989 struct mlx5_ifc_detach_from_mcg_in_bits {
5993 u8 reserved_at_20[0x10];
5996 u8 reserved_at_40[0x8];
5999 u8 reserved_at_60[0x20];
6001 u8 multicast_gid[16][0x8];
6004 struct mlx5_ifc_destroy_xrq_out_bits {
6006 u8 reserved_at_8[0x18];
6010 u8 reserved_at_40[0x40];
6013 struct mlx5_ifc_destroy_xrq_in_bits {
6017 u8 reserved_at_20[0x10];
6020 u8 reserved_at_40[0x8];
6023 u8 reserved_at_60[0x20];
6026 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6028 u8 reserved_at_8[0x18];
6032 u8 reserved_at_40[0x40];
6035 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6039 u8 reserved_at_20[0x10];
6042 u8 reserved_at_40[0x8];
6045 u8 reserved_at_60[0x20];
6048 struct mlx5_ifc_destroy_tis_out_bits {
6050 u8 reserved_at_8[0x18];
6054 u8 reserved_at_40[0x40];
6057 struct mlx5_ifc_destroy_tis_in_bits {
6061 u8 reserved_at_20[0x10];
6064 u8 reserved_at_40[0x8];
6067 u8 reserved_at_60[0x20];
6070 struct mlx5_ifc_destroy_tir_out_bits {
6072 u8 reserved_at_8[0x18];
6076 u8 reserved_at_40[0x40];
6079 struct mlx5_ifc_destroy_tir_in_bits {
6083 u8 reserved_at_20[0x10];
6086 u8 reserved_at_40[0x8];
6089 u8 reserved_at_60[0x20];
6092 struct mlx5_ifc_destroy_srq_out_bits {
6094 u8 reserved_at_8[0x18];
6098 u8 reserved_at_40[0x40];
6101 struct mlx5_ifc_destroy_srq_in_bits {
6105 u8 reserved_at_20[0x10];
6108 u8 reserved_at_40[0x8];
6111 u8 reserved_at_60[0x20];
6114 struct mlx5_ifc_destroy_sq_out_bits {
6116 u8 reserved_at_8[0x18];
6120 u8 reserved_at_40[0x40];
6123 struct mlx5_ifc_destroy_sq_in_bits {
6127 u8 reserved_at_20[0x10];
6130 u8 reserved_at_40[0x8];
6133 u8 reserved_at_60[0x20];
6136 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6138 u8 reserved_at_8[0x18];
6142 u8 reserved_at_40[0x1c0];
6145 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6147 u8 reserved_at_10[0x10];
6149 u8 reserved_at_20[0x10];
6152 u8 scheduling_hierarchy[0x8];
6153 u8 reserved_at_48[0x18];
6155 u8 scheduling_element_id[0x20];
6157 u8 reserved_at_80[0x180];
6160 struct mlx5_ifc_destroy_rqt_out_bits {
6162 u8 reserved_at_8[0x18];
6166 u8 reserved_at_40[0x40];
6169 struct mlx5_ifc_destroy_rqt_in_bits {
6173 u8 reserved_at_20[0x10];
6176 u8 reserved_at_40[0x8];
6179 u8 reserved_at_60[0x20];
6182 struct mlx5_ifc_destroy_rq_out_bits {
6184 u8 reserved_at_8[0x18];
6188 u8 reserved_at_40[0x40];
6191 struct mlx5_ifc_destroy_rq_in_bits {
6195 u8 reserved_at_20[0x10];
6198 u8 reserved_at_40[0x8];
6201 u8 reserved_at_60[0x20];
6204 struct mlx5_ifc_set_delay_drop_params_in_bits {
6206 u8 reserved_at_10[0x10];
6208 u8 reserved_at_20[0x10];
6211 u8 reserved_at_40[0x20];
6213 u8 reserved_at_60[0x10];
6214 u8 delay_drop_timeout[0x10];
6217 struct mlx5_ifc_set_delay_drop_params_out_bits {
6219 u8 reserved_at_8[0x18];
6223 u8 reserved_at_40[0x40];
6226 struct mlx5_ifc_destroy_rmp_out_bits {
6228 u8 reserved_at_8[0x18];
6232 u8 reserved_at_40[0x40];
6235 struct mlx5_ifc_destroy_rmp_in_bits {
6239 u8 reserved_at_20[0x10];
6242 u8 reserved_at_40[0x8];
6245 u8 reserved_at_60[0x20];
6248 struct mlx5_ifc_destroy_qp_out_bits {
6250 u8 reserved_at_8[0x18];
6254 u8 reserved_at_40[0x40];
6257 struct mlx5_ifc_destroy_qp_in_bits {
6261 u8 reserved_at_20[0x10];
6264 u8 reserved_at_40[0x8];
6267 u8 reserved_at_60[0x20];
6270 struct mlx5_ifc_destroy_psv_out_bits {
6272 u8 reserved_at_8[0x18];
6276 u8 reserved_at_40[0x40];
6279 struct mlx5_ifc_destroy_psv_in_bits {
6281 u8 reserved_at_10[0x10];
6283 u8 reserved_at_20[0x10];
6286 u8 reserved_at_40[0x8];
6289 u8 reserved_at_60[0x20];
6292 struct mlx5_ifc_destroy_mkey_out_bits {
6294 u8 reserved_at_8[0x18];
6298 u8 reserved_at_40[0x40];
6301 struct mlx5_ifc_destroy_mkey_in_bits {
6303 u8 reserved_at_10[0x10];
6305 u8 reserved_at_20[0x10];
6308 u8 reserved_at_40[0x8];
6309 u8 mkey_index[0x18];
6311 u8 reserved_at_60[0x20];
6314 struct mlx5_ifc_destroy_flow_table_out_bits {
6316 u8 reserved_at_8[0x18];
6320 u8 reserved_at_40[0x40];
6323 struct mlx5_ifc_destroy_flow_table_in_bits {
6325 u8 reserved_at_10[0x10];
6327 u8 reserved_at_20[0x10];
6330 u8 other_vport[0x1];
6331 u8 reserved_at_41[0xf];
6332 u8 vport_number[0x10];
6334 u8 reserved_at_60[0x20];
6337 u8 reserved_at_88[0x18];
6339 u8 reserved_at_a0[0x8];
6342 u8 reserved_at_c0[0x140];
6345 struct mlx5_ifc_destroy_flow_group_out_bits {
6347 u8 reserved_at_8[0x18];
6351 u8 reserved_at_40[0x40];
6354 struct mlx5_ifc_destroy_flow_group_in_bits {
6356 u8 reserved_at_10[0x10];
6358 u8 reserved_at_20[0x10];
6361 u8 other_vport[0x1];
6362 u8 reserved_at_41[0xf];
6363 u8 vport_number[0x10];
6365 u8 reserved_at_60[0x20];
6368 u8 reserved_at_88[0x18];
6370 u8 reserved_at_a0[0x8];
6375 u8 reserved_at_e0[0x120];
6378 struct mlx5_ifc_destroy_eq_out_bits {
6380 u8 reserved_at_8[0x18];
6384 u8 reserved_at_40[0x40];
6387 struct mlx5_ifc_destroy_eq_in_bits {
6389 u8 reserved_at_10[0x10];
6391 u8 reserved_at_20[0x10];
6394 u8 reserved_at_40[0x18];
6397 u8 reserved_at_60[0x20];
6400 struct mlx5_ifc_destroy_dct_out_bits {
6402 u8 reserved_at_8[0x18];
6406 u8 reserved_at_40[0x40];
6409 struct mlx5_ifc_destroy_dct_in_bits {
6413 u8 reserved_at_20[0x10];
6416 u8 reserved_at_40[0x8];
6419 u8 reserved_at_60[0x20];
6422 struct mlx5_ifc_destroy_cq_out_bits {
6424 u8 reserved_at_8[0x18];
6428 u8 reserved_at_40[0x40];
6431 struct mlx5_ifc_destroy_cq_in_bits {
6435 u8 reserved_at_20[0x10];
6438 u8 reserved_at_40[0x8];
6441 u8 reserved_at_60[0x20];
6444 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6446 u8 reserved_at_8[0x18];
6450 u8 reserved_at_40[0x40];
6453 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6455 u8 reserved_at_10[0x10];
6457 u8 reserved_at_20[0x10];
6460 u8 reserved_at_40[0x20];
6462 u8 reserved_at_60[0x10];
6463 u8 vxlan_udp_port[0x10];
6466 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6468 u8 reserved_at_8[0x18];
6472 u8 reserved_at_40[0x40];
6475 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6477 u8 reserved_at_10[0x10];
6479 u8 reserved_at_20[0x10];
6482 u8 reserved_at_40[0x60];
6484 u8 reserved_at_a0[0x8];
6485 u8 table_index[0x18];
6487 u8 reserved_at_c0[0x140];
6490 struct mlx5_ifc_delete_fte_out_bits {
6492 u8 reserved_at_8[0x18];
6496 u8 reserved_at_40[0x40];
6499 struct mlx5_ifc_delete_fte_in_bits {
6501 u8 reserved_at_10[0x10];
6503 u8 reserved_at_20[0x10];
6506 u8 other_vport[0x1];
6507 u8 reserved_at_41[0xf];
6508 u8 vport_number[0x10];
6510 u8 reserved_at_60[0x20];
6513 u8 reserved_at_88[0x18];
6515 u8 reserved_at_a0[0x8];
6518 u8 reserved_at_c0[0x40];
6520 u8 flow_index[0x20];
6522 u8 reserved_at_120[0xe0];
6525 struct mlx5_ifc_dealloc_xrcd_out_bits {
6527 u8 reserved_at_8[0x18];
6531 u8 reserved_at_40[0x40];
6534 struct mlx5_ifc_dealloc_xrcd_in_bits {
6538 u8 reserved_at_20[0x10];
6541 u8 reserved_at_40[0x8];
6544 u8 reserved_at_60[0x20];
6547 struct mlx5_ifc_dealloc_uar_out_bits {
6549 u8 reserved_at_8[0x18];
6553 u8 reserved_at_40[0x40];
6556 struct mlx5_ifc_dealloc_uar_in_bits {
6558 u8 reserved_at_10[0x10];
6560 u8 reserved_at_20[0x10];
6563 u8 reserved_at_40[0x8];
6566 u8 reserved_at_60[0x20];
6569 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6571 u8 reserved_at_8[0x18];
6575 u8 reserved_at_40[0x40];
6578 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6580 u8 reserved_at_10[0x10];
6582 u8 reserved_at_20[0x10];
6585 u8 reserved_at_40[0x8];
6586 u8 transport_domain[0x18];
6588 u8 reserved_at_60[0x20];
6591 struct mlx5_ifc_dealloc_q_counter_out_bits {
6593 u8 reserved_at_8[0x18];
6597 u8 reserved_at_40[0x40];
6600 struct mlx5_ifc_dealloc_q_counter_in_bits {
6602 u8 reserved_at_10[0x10];
6604 u8 reserved_at_20[0x10];
6607 u8 reserved_at_40[0x18];
6608 u8 counter_set_id[0x8];
6610 u8 reserved_at_60[0x20];
6613 struct mlx5_ifc_dealloc_pd_out_bits {
6615 u8 reserved_at_8[0x18];
6619 u8 reserved_at_40[0x40];
6622 struct mlx5_ifc_dealloc_pd_in_bits {
6626 u8 reserved_at_20[0x10];
6629 u8 reserved_at_40[0x8];
6632 u8 reserved_at_60[0x20];
6635 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6637 u8 reserved_at_8[0x18];
6641 u8 reserved_at_40[0x40];
6644 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6646 u8 reserved_at_10[0x10];
6648 u8 reserved_at_20[0x10];
6651 u8 flow_counter_id[0x20];
6653 u8 reserved_at_60[0x20];
6656 struct mlx5_ifc_create_xrq_out_bits {
6658 u8 reserved_at_8[0x18];
6662 u8 reserved_at_40[0x8];
6665 u8 reserved_at_60[0x20];
6668 struct mlx5_ifc_create_xrq_in_bits {
6672 u8 reserved_at_20[0x10];
6675 u8 reserved_at_40[0x40];
6677 struct mlx5_ifc_xrqc_bits xrq_context;
6680 struct mlx5_ifc_create_xrc_srq_out_bits {
6682 u8 reserved_at_8[0x18];
6686 u8 reserved_at_40[0x8];
6689 u8 reserved_at_60[0x20];
6692 struct mlx5_ifc_create_xrc_srq_in_bits {
6696 u8 reserved_at_20[0x10];
6699 u8 reserved_at_40[0x40];
6701 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6703 u8 reserved_at_280[0x60];
6705 u8 xrc_srq_umem_valid[0x1];
6706 u8 reserved_at_2e1[0x1f];
6708 u8 reserved_at_300[0x580];
6713 struct mlx5_ifc_create_tis_out_bits {
6715 u8 reserved_at_8[0x18];
6719 u8 reserved_at_40[0x8];
6722 u8 reserved_at_60[0x20];
6725 struct mlx5_ifc_create_tis_in_bits {
6729 u8 reserved_at_20[0x10];
6732 u8 reserved_at_40[0xc0];
6734 struct mlx5_ifc_tisc_bits ctx;
6737 struct mlx5_ifc_create_tir_out_bits {
6739 u8 reserved_at_8[0x18];
6743 u8 reserved_at_40[0x8];
6746 u8 reserved_at_60[0x20];
6749 struct mlx5_ifc_create_tir_in_bits {
6753 u8 reserved_at_20[0x10];
6756 u8 reserved_at_40[0xc0];
6758 struct mlx5_ifc_tirc_bits ctx;
6761 struct mlx5_ifc_create_srq_out_bits {
6763 u8 reserved_at_8[0x18];
6767 u8 reserved_at_40[0x8];
6770 u8 reserved_at_60[0x20];
6773 struct mlx5_ifc_create_srq_in_bits {
6777 u8 reserved_at_20[0x10];
6780 u8 reserved_at_40[0x40];
6782 struct mlx5_ifc_srqc_bits srq_context_entry;
6784 u8 reserved_at_280[0x600];
6789 struct mlx5_ifc_create_sq_out_bits {
6791 u8 reserved_at_8[0x18];
6795 u8 reserved_at_40[0x8];
6798 u8 reserved_at_60[0x20];
6801 struct mlx5_ifc_create_sq_in_bits {
6805 u8 reserved_at_20[0x10];
6808 u8 reserved_at_40[0xc0];
6810 struct mlx5_ifc_sqc_bits ctx;
6813 struct mlx5_ifc_create_scheduling_element_out_bits {
6815 u8 reserved_at_8[0x18];
6819 u8 reserved_at_40[0x40];
6821 u8 scheduling_element_id[0x20];
6823 u8 reserved_at_a0[0x160];
6826 struct mlx5_ifc_create_scheduling_element_in_bits {
6828 u8 reserved_at_10[0x10];
6830 u8 reserved_at_20[0x10];
6833 u8 scheduling_hierarchy[0x8];
6834 u8 reserved_at_48[0x18];
6836 u8 reserved_at_60[0xa0];
6838 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6840 u8 reserved_at_300[0x100];
6843 struct mlx5_ifc_create_rqt_out_bits {
6845 u8 reserved_at_8[0x18];
6849 u8 reserved_at_40[0x8];
6852 u8 reserved_at_60[0x20];
6855 struct mlx5_ifc_create_rqt_in_bits {
6859 u8 reserved_at_20[0x10];
6862 u8 reserved_at_40[0xc0];
6864 struct mlx5_ifc_rqtc_bits rqt_context;
6867 struct mlx5_ifc_create_rq_out_bits {
6869 u8 reserved_at_8[0x18];
6873 u8 reserved_at_40[0x8];
6876 u8 reserved_at_60[0x20];
6879 struct mlx5_ifc_create_rq_in_bits {
6883 u8 reserved_at_20[0x10];
6886 u8 reserved_at_40[0xc0];
6888 struct mlx5_ifc_rqc_bits ctx;
6891 struct mlx5_ifc_create_rmp_out_bits {
6893 u8 reserved_at_8[0x18];
6897 u8 reserved_at_40[0x8];
6900 u8 reserved_at_60[0x20];
6903 struct mlx5_ifc_create_rmp_in_bits {
6907 u8 reserved_at_20[0x10];
6910 u8 reserved_at_40[0xc0];
6912 struct mlx5_ifc_rmpc_bits ctx;
6915 struct mlx5_ifc_create_qp_out_bits {
6917 u8 reserved_at_8[0x18];
6921 u8 reserved_at_40[0x8];
6924 u8 reserved_at_60[0x20];
6927 struct mlx5_ifc_create_qp_in_bits {
6931 u8 reserved_at_20[0x10];
6934 u8 reserved_at_40[0x40];
6936 u8 opt_param_mask[0x20];
6938 u8 reserved_at_a0[0x20];
6940 struct mlx5_ifc_qpc_bits qpc;
6942 u8 reserved_at_800[0x60];
6944 u8 wq_umem_valid[0x1];
6945 u8 reserved_at_861[0x1f];
6950 struct mlx5_ifc_create_psv_out_bits {
6952 u8 reserved_at_8[0x18];
6956 u8 reserved_at_40[0x40];
6958 u8 reserved_at_80[0x8];
6959 u8 psv0_index[0x18];
6961 u8 reserved_at_a0[0x8];
6962 u8 psv1_index[0x18];
6964 u8 reserved_at_c0[0x8];
6965 u8 psv2_index[0x18];
6967 u8 reserved_at_e0[0x8];
6968 u8 psv3_index[0x18];
6971 struct mlx5_ifc_create_psv_in_bits {
6973 u8 reserved_at_10[0x10];
6975 u8 reserved_at_20[0x10];
6979 u8 reserved_at_44[0x4];
6982 u8 reserved_at_60[0x20];
6985 struct mlx5_ifc_create_mkey_out_bits {
6987 u8 reserved_at_8[0x18];
6991 u8 reserved_at_40[0x8];
6992 u8 mkey_index[0x18];
6994 u8 reserved_at_60[0x20];
6997 struct mlx5_ifc_create_mkey_in_bits {
6999 u8 reserved_at_10[0x10];
7001 u8 reserved_at_20[0x10];
7004 u8 reserved_at_40[0x20];
7007 u8 mkey_umem_valid[0x1];
7008 u8 reserved_at_62[0x1e];
7010 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7012 u8 reserved_at_280[0x80];
7014 u8 translations_octword_actual_size[0x20];
7016 u8 reserved_at_320[0x560];
7018 u8 klm_pas_mtt[0][0x20];
7021 struct mlx5_ifc_create_flow_table_out_bits {
7023 u8 reserved_at_8[0x18];
7027 u8 reserved_at_40[0x8];
7030 u8 reserved_at_60[0x20];
7033 struct mlx5_ifc_flow_table_context_bits {
7034 u8 reformat_en[0x1];
7036 u8 reserved_at_2[0x2];
7037 u8 table_miss_action[0x4];
7039 u8 reserved_at_10[0x8];
7042 u8 reserved_at_20[0x8];
7043 u8 table_miss_id[0x18];
7045 u8 reserved_at_40[0x8];
7046 u8 lag_master_next_table_id[0x18];
7048 u8 reserved_at_60[0xe0];
7051 struct mlx5_ifc_create_flow_table_in_bits {
7053 u8 reserved_at_10[0x10];
7055 u8 reserved_at_20[0x10];
7058 u8 other_vport[0x1];
7059 u8 reserved_at_41[0xf];
7060 u8 vport_number[0x10];
7062 u8 reserved_at_60[0x20];
7065 u8 reserved_at_88[0x18];
7067 u8 reserved_at_a0[0x20];
7069 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7072 struct mlx5_ifc_create_flow_group_out_bits {
7074 u8 reserved_at_8[0x18];
7078 u8 reserved_at_40[0x8];
7081 u8 reserved_at_60[0x20];
7085 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7086 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7087 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7088 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7091 struct mlx5_ifc_create_flow_group_in_bits {
7093 u8 reserved_at_10[0x10];
7095 u8 reserved_at_20[0x10];
7098 u8 other_vport[0x1];
7099 u8 reserved_at_41[0xf];
7100 u8 vport_number[0x10];
7102 u8 reserved_at_60[0x20];
7105 u8 reserved_at_88[0x18];
7107 u8 reserved_at_a0[0x8];
7110 u8 source_eswitch_owner_vhca_id_valid[0x1];
7112 u8 reserved_at_c1[0x1f];
7114 u8 start_flow_index[0x20];
7116 u8 reserved_at_100[0x20];
7118 u8 end_flow_index[0x20];
7120 u8 reserved_at_140[0xa0];
7122 u8 reserved_at_1e0[0x18];
7123 u8 match_criteria_enable[0x8];
7125 struct mlx5_ifc_fte_match_param_bits match_criteria;
7127 u8 reserved_at_1200[0xe00];
7130 struct mlx5_ifc_create_eq_out_bits {
7132 u8 reserved_at_8[0x18];
7136 u8 reserved_at_40[0x18];
7139 u8 reserved_at_60[0x20];
7142 struct mlx5_ifc_create_eq_in_bits {
7144 u8 reserved_at_10[0x10];
7146 u8 reserved_at_20[0x10];
7149 u8 reserved_at_40[0x40];
7151 struct mlx5_ifc_eqc_bits eq_context_entry;
7153 u8 reserved_at_280[0x40];
7155 u8 event_bitmask[0x40];
7157 u8 reserved_at_300[0x580];
7162 struct mlx5_ifc_create_dct_out_bits {
7164 u8 reserved_at_8[0x18];
7168 u8 reserved_at_40[0x8];
7171 u8 reserved_at_60[0x20];
7174 struct mlx5_ifc_create_dct_in_bits {
7178 u8 reserved_at_20[0x10];
7181 u8 reserved_at_40[0x40];
7183 struct mlx5_ifc_dctc_bits dct_context_entry;
7185 u8 reserved_at_280[0x180];
7188 struct mlx5_ifc_create_cq_out_bits {
7190 u8 reserved_at_8[0x18];
7194 u8 reserved_at_40[0x8];
7197 u8 reserved_at_60[0x20];
7200 struct mlx5_ifc_create_cq_in_bits {
7204 u8 reserved_at_20[0x10];
7207 u8 reserved_at_40[0x40];
7209 struct mlx5_ifc_cqc_bits cq_context;
7211 u8 reserved_at_280[0x60];
7213 u8 cq_umem_valid[0x1];
7214 u8 reserved_at_2e1[0x59f];
7219 struct mlx5_ifc_config_int_moderation_out_bits {
7221 u8 reserved_at_8[0x18];
7225 u8 reserved_at_40[0x4];
7227 u8 int_vector[0x10];
7229 u8 reserved_at_60[0x20];
7233 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7234 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7237 struct mlx5_ifc_config_int_moderation_in_bits {
7239 u8 reserved_at_10[0x10];
7241 u8 reserved_at_20[0x10];
7244 u8 reserved_at_40[0x4];
7246 u8 int_vector[0x10];
7248 u8 reserved_at_60[0x20];
7251 struct mlx5_ifc_attach_to_mcg_out_bits {
7253 u8 reserved_at_8[0x18];
7257 u8 reserved_at_40[0x40];
7260 struct mlx5_ifc_attach_to_mcg_in_bits {
7264 u8 reserved_at_20[0x10];
7267 u8 reserved_at_40[0x8];
7270 u8 reserved_at_60[0x20];
7272 u8 multicast_gid[16][0x8];
7275 struct mlx5_ifc_arm_xrq_out_bits {
7277 u8 reserved_at_8[0x18];
7281 u8 reserved_at_40[0x40];
7284 struct mlx5_ifc_arm_xrq_in_bits {
7286 u8 reserved_at_10[0x10];
7288 u8 reserved_at_20[0x10];
7291 u8 reserved_at_40[0x8];
7294 u8 reserved_at_60[0x10];
7298 struct mlx5_ifc_arm_xrc_srq_out_bits {
7300 u8 reserved_at_8[0x18];
7304 u8 reserved_at_40[0x40];
7308 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7311 struct mlx5_ifc_arm_xrc_srq_in_bits {
7315 u8 reserved_at_20[0x10];
7318 u8 reserved_at_40[0x8];
7321 u8 reserved_at_60[0x10];
7325 struct mlx5_ifc_arm_rq_out_bits {
7327 u8 reserved_at_8[0x18];
7331 u8 reserved_at_40[0x40];
7335 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7336 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7339 struct mlx5_ifc_arm_rq_in_bits {
7343 u8 reserved_at_20[0x10];
7346 u8 reserved_at_40[0x8];
7347 u8 srq_number[0x18];
7349 u8 reserved_at_60[0x10];
7353 struct mlx5_ifc_arm_dct_out_bits {
7355 u8 reserved_at_8[0x18];
7359 u8 reserved_at_40[0x40];
7362 struct mlx5_ifc_arm_dct_in_bits {
7364 u8 reserved_at_10[0x10];
7366 u8 reserved_at_20[0x10];
7369 u8 reserved_at_40[0x8];
7370 u8 dct_number[0x18];
7372 u8 reserved_at_60[0x20];
7375 struct mlx5_ifc_alloc_xrcd_out_bits {
7377 u8 reserved_at_8[0x18];
7381 u8 reserved_at_40[0x8];
7384 u8 reserved_at_60[0x20];
7387 struct mlx5_ifc_alloc_xrcd_in_bits {
7391 u8 reserved_at_20[0x10];
7394 u8 reserved_at_40[0x40];
7397 struct mlx5_ifc_alloc_uar_out_bits {
7399 u8 reserved_at_8[0x18];
7403 u8 reserved_at_40[0x8];
7406 u8 reserved_at_60[0x20];
7409 struct mlx5_ifc_alloc_uar_in_bits {
7411 u8 reserved_at_10[0x10];
7413 u8 reserved_at_20[0x10];
7416 u8 reserved_at_40[0x40];
7419 struct mlx5_ifc_alloc_transport_domain_out_bits {
7421 u8 reserved_at_8[0x18];
7425 u8 reserved_at_40[0x8];
7426 u8 transport_domain[0x18];
7428 u8 reserved_at_60[0x20];
7431 struct mlx5_ifc_alloc_transport_domain_in_bits {
7433 u8 reserved_at_10[0x10];
7435 u8 reserved_at_20[0x10];
7438 u8 reserved_at_40[0x40];
7441 struct mlx5_ifc_alloc_q_counter_out_bits {
7443 u8 reserved_at_8[0x18];
7447 u8 reserved_at_40[0x18];
7448 u8 counter_set_id[0x8];
7450 u8 reserved_at_60[0x20];
7453 struct mlx5_ifc_alloc_q_counter_in_bits {
7455 u8 reserved_at_10[0x10];
7457 u8 reserved_at_20[0x10];
7460 u8 reserved_at_40[0x40];
7463 struct mlx5_ifc_alloc_pd_out_bits {
7465 u8 reserved_at_8[0x18];
7469 u8 reserved_at_40[0x8];
7472 u8 reserved_at_60[0x20];
7475 struct mlx5_ifc_alloc_pd_in_bits {
7479 u8 reserved_at_20[0x10];
7482 u8 reserved_at_40[0x40];
7485 struct mlx5_ifc_alloc_flow_counter_out_bits {
7487 u8 reserved_at_8[0x18];
7491 u8 flow_counter_id[0x20];
7493 u8 reserved_at_60[0x20];
7496 struct mlx5_ifc_alloc_flow_counter_in_bits {
7498 u8 reserved_at_10[0x10];
7500 u8 reserved_at_20[0x10];
7503 u8 reserved_at_40[0x40];
7506 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7508 u8 reserved_at_8[0x18];
7512 u8 reserved_at_40[0x40];
7515 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7517 u8 reserved_at_10[0x10];
7519 u8 reserved_at_20[0x10];
7522 u8 reserved_at_40[0x20];
7524 u8 reserved_at_60[0x10];
7525 u8 vxlan_udp_port[0x10];
7528 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7530 u8 reserved_at_8[0x18];
7534 u8 reserved_at_40[0x40];
7537 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7539 u8 reserved_at_10[0x10];
7541 u8 reserved_at_20[0x10];
7544 u8 reserved_at_40[0x10];
7545 u8 rate_limit_index[0x10];
7547 u8 reserved_at_60[0x20];
7549 u8 rate_limit[0x20];
7551 u8 burst_upper_bound[0x20];
7553 u8 reserved_at_c0[0x10];
7554 u8 typical_packet_size[0x10];
7556 u8 reserved_at_e0[0x120];
7559 struct mlx5_ifc_access_register_out_bits {
7561 u8 reserved_at_8[0x18];
7565 u8 reserved_at_40[0x40];
7567 u8 register_data[0][0x20];
7571 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7572 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7575 struct mlx5_ifc_access_register_in_bits {
7577 u8 reserved_at_10[0x10];
7579 u8 reserved_at_20[0x10];
7582 u8 reserved_at_40[0x10];
7583 u8 register_id[0x10];
7587 u8 register_data[0][0x20];
7590 struct mlx5_ifc_sltp_reg_bits {
7595 u8 reserved_at_12[0x2];
7597 u8 reserved_at_18[0x8];
7599 u8 reserved_at_20[0x20];
7601 u8 reserved_at_40[0x7];
7607 u8 reserved_at_60[0xc];
7608 u8 ob_preemp_mode[0x4];
7612 u8 reserved_at_80[0x20];
7615 struct mlx5_ifc_slrg_reg_bits {
7620 u8 reserved_at_12[0x2];
7622 u8 reserved_at_18[0x8];
7624 u8 time_to_link_up[0x10];
7625 u8 reserved_at_30[0xc];
7626 u8 grade_lane_speed[0x4];
7628 u8 grade_version[0x8];
7631 u8 reserved_at_60[0x4];
7632 u8 height_grade_type[0x4];
7633 u8 height_grade[0x18];
7638 u8 reserved_at_a0[0x10];
7639 u8 height_sigma[0x10];
7641 u8 reserved_at_c0[0x20];
7643 u8 reserved_at_e0[0x4];
7644 u8 phase_grade_type[0x4];
7645 u8 phase_grade[0x18];
7647 u8 reserved_at_100[0x8];
7648 u8 phase_eo_pos[0x8];
7649 u8 reserved_at_110[0x8];
7650 u8 phase_eo_neg[0x8];
7652 u8 ffe_set_tested[0x10];
7653 u8 test_errors_per_lane[0x10];
7656 struct mlx5_ifc_pvlc_reg_bits {
7657 u8 reserved_at_0[0x8];
7659 u8 reserved_at_10[0x10];
7661 u8 reserved_at_20[0x1c];
7664 u8 reserved_at_40[0x1c];
7667 u8 reserved_at_60[0x1c];
7668 u8 vl_operational[0x4];
7671 struct mlx5_ifc_pude_reg_bits {
7674 u8 reserved_at_10[0x4];
7675 u8 admin_status[0x4];
7676 u8 reserved_at_18[0x4];
7677 u8 oper_status[0x4];
7679 u8 reserved_at_20[0x60];
7682 struct mlx5_ifc_ptys_reg_bits {
7683 u8 reserved_at_0[0x1];
7684 u8 an_disable_admin[0x1];
7685 u8 an_disable_cap[0x1];
7686 u8 reserved_at_3[0x5];
7688 u8 reserved_at_10[0xd];
7692 u8 reserved_at_24[0x3c];
7694 u8 eth_proto_capability[0x20];
7696 u8 ib_link_width_capability[0x10];
7697 u8 ib_proto_capability[0x10];
7699 u8 reserved_at_a0[0x20];
7701 u8 eth_proto_admin[0x20];
7703 u8 ib_link_width_admin[0x10];
7704 u8 ib_proto_admin[0x10];
7706 u8 reserved_at_100[0x20];
7708 u8 eth_proto_oper[0x20];
7710 u8 ib_link_width_oper[0x10];
7711 u8 ib_proto_oper[0x10];
7713 u8 reserved_at_160[0x1c];
7714 u8 connector_type[0x4];
7716 u8 eth_proto_lp_advertise[0x20];
7718 u8 reserved_at_1a0[0x60];
7721 struct mlx5_ifc_mlcr_reg_bits {
7722 u8 reserved_at_0[0x8];
7724 u8 reserved_at_10[0x20];
7726 u8 beacon_duration[0x10];
7727 u8 reserved_at_40[0x10];
7729 u8 beacon_remain[0x10];
7732 struct mlx5_ifc_ptas_reg_bits {
7733 u8 reserved_at_0[0x20];
7735 u8 algorithm_options[0x10];
7736 u8 reserved_at_30[0x4];
7737 u8 repetitions_mode[0x4];
7738 u8 num_of_repetitions[0x8];
7740 u8 grade_version[0x8];
7741 u8 height_grade_type[0x4];
7742 u8 phase_grade_type[0x4];
7743 u8 height_grade_weight[0x8];
7744 u8 phase_grade_weight[0x8];
7746 u8 gisim_measure_bits[0x10];
7747 u8 adaptive_tap_measure_bits[0x10];
7749 u8 ber_bath_high_error_threshold[0x10];
7750 u8 ber_bath_mid_error_threshold[0x10];
7752 u8 ber_bath_low_error_threshold[0x10];
7753 u8 one_ratio_high_threshold[0x10];
7755 u8 one_ratio_high_mid_threshold[0x10];
7756 u8 one_ratio_low_mid_threshold[0x10];
7758 u8 one_ratio_low_threshold[0x10];
7759 u8 ndeo_error_threshold[0x10];
7761 u8 mixer_offset_step_size[0x10];
7762 u8 reserved_at_110[0x8];
7763 u8 mix90_phase_for_voltage_bath[0x8];
7765 u8 mixer_offset_start[0x10];
7766 u8 mixer_offset_end[0x10];
7768 u8 reserved_at_140[0x15];
7769 u8 ber_test_time[0xb];
7772 struct mlx5_ifc_pspa_reg_bits {
7776 u8 reserved_at_18[0x8];
7778 u8 reserved_at_20[0x20];
7781 struct mlx5_ifc_pqdr_reg_bits {
7782 u8 reserved_at_0[0x8];
7784 u8 reserved_at_10[0x5];
7786 u8 reserved_at_18[0x6];
7789 u8 reserved_at_20[0x20];
7791 u8 reserved_at_40[0x10];
7792 u8 min_threshold[0x10];
7794 u8 reserved_at_60[0x10];
7795 u8 max_threshold[0x10];
7797 u8 reserved_at_80[0x10];
7798 u8 mark_probability_denominator[0x10];
7800 u8 reserved_at_a0[0x60];
7803 struct mlx5_ifc_ppsc_reg_bits {
7804 u8 reserved_at_0[0x8];
7806 u8 reserved_at_10[0x10];
7808 u8 reserved_at_20[0x60];
7810 u8 reserved_at_80[0x1c];
7813 u8 reserved_at_a0[0x1c];
7814 u8 wrps_status[0x4];
7816 u8 reserved_at_c0[0x8];
7817 u8 up_threshold[0x8];
7818 u8 reserved_at_d0[0x8];
7819 u8 down_threshold[0x8];
7821 u8 reserved_at_e0[0x20];
7823 u8 reserved_at_100[0x1c];
7826 u8 reserved_at_120[0x1c];
7827 u8 srps_status[0x4];
7829 u8 reserved_at_140[0x40];
7832 struct mlx5_ifc_pplr_reg_bits {
7833 u8 reserved_at_0[0x8];
7835 u8 reserved_at_10[0x10];
7837 u8 reserved_at_20[0x8];
7839 u8 reserved_at_30[0x8];
7843 struct mlx5_ifc_pplm_reg_bits {
7844 u8 reserved_at_0[0x8];
7846 u8 reserved_at_10[0x10];
7848 u8 reserved_at_20[0x20];
7850 u8 port_profile_mode[0x8];
7851 u8 static_port_profile[0x8];
7852 u8 active_port_profile[0x8];
7853 u8 reserved_at_58[0x8];
7855 u8 retransmission_active[0x8];
7856 u8 fec_mode_active[0x18];
7858 u8 rs_fec_correction_bypass_cap[0x4];
7859 u8 reserved_at_84[0x8];
7860 u8 fec_override_cap_56g[0x4];
7861 u8 fec_override_cap_100g[0x4];
7862 u8 fec_override_cap_50g[0x4];
7863 u8 fec_override_cap_25g[0x4];
7864 u8 fec_override_cap_10g_40g[0x4];
7866 u8 rs_fec_correction_bypass_admin[0x4];
7867 u8 reserved_at_a4[0x8];
7868 u8 fec_override_admin_56g[0x4];
7869 u8 fec_override_admin_100g[0x4];
7870 u8 fec_override_admin_50g[0x4];
7871 u8 fec_override_admin_25g[0x4];
7872 u8 fec_override_admin_10g_40g[0x4];
7875 struct mlx5_ifc_ppcnt_reg_bits {
7879 u8 reserved_at_12[0x8];
7883 u8 reserved_at_21[0x1c];
7886 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7889 struct mlx5_ifc_mpcnt_reg_bits {
7890 u8 reserved_at_0[0x8];
7892 u8 reserved_at_10[0xa];
7896 u8 reserved_at_21[0x1f];
7898 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7901 struct mlx5_ifc_ppad_reg_bits {
7902 u8 reserved_at_0[0x3];
7904 u8 reserved_at_4[0x4];
7910 u8 reserved_at_40[0x40];
7913 struct mlx5_ifc_pmtu_reg_bits {
7914 u8 reserved_at_0[0x8];
7916 u8 reserved_at_10[0x10];
7919 u8 reserved_at_30[0x10];
7922 u8 reserved_at_50[0x10];
7925 u8 reserved_at_70[0x10];
7928 struct mlx5_ifc_pmpr_reg_bits {
7929 u8 reserved_at_0[0x8];
7931 u8 reserved_at_10[0x10];
7933 u8 reserved_at_20[0x18];
7934 u8 attenuation_5g[0x8];
7936 u8 reserved_at_40[0x18];
7937 u8 attenuation_7g[0x8];
7939 u8 reserved_at_60[0x18];
7940 u8 attenuation_12g[0x8];
7943 struct mlx5_ifc_pmpe_reg_bits {
7944 u8 reserved_at_0[0x8];
7946 u8 reserved_at_10[0xc];
7947 u8 module_status[0x4];
7949 u8 reserved_at_20[0x60];
7952 struct mlx5_ifc_pmpc_reg_bits {
7953 u8 module_state_updated[32][0x8];
7956 struct mlx5_ifc_pmlpn_reg_bits {
7957 u8 reserved_at_0[0x4];
7958 u8 mlpn_status[0x4];
7960 u8 reserved_at_10[0x10];
7963 u8 reserved_at_21[0x1f];
7966 struct mlx5_ifc_pmlp_reg_bits {
7968 u8 reserved_at_1[0x7];
7970 u8 reserved_at_10[0x8];
7973 u8 lane0_module_mapping[0x20];
7975 u8 lane1_module_mapping[0x20];
7977 u8 lane2_module_mapping[0x20];
7979 u8 lane3_module_mapping[0x20];
7981 u8 reserved_at_a0[0x160];
7984 struct mlx5_ifc_pmaos_reg_bits {
7985 u8 reserved_at_0[0x8];
7987 u8 reserved_at_10[0x4];
7988 u8 admin_status[0x4];
7989 u8 reserved_at_18[0x4];
7990 u8 oper_status[0x4];
7994 u8 reserved_at_22[0x1c];
7997 u8 reserved_at_40[0x40];
8000 struct mlx5_ifc_plpc_reg_bits {
8001 u8 reserved_at_0[0x4];
8003 u8 reserved_at_10[0x4];
8005 u8 reserved_at_18[0x8];
8007 u8 reserved_at_20[0x10];
8008 u8 lane_speed[0x10];
8010 u8 reserved_at_40[0x17];
8012 u8 fec_mode_policy[0x8];
8014 u8 retransmission_capability[0x8];
8015 u8 fec_mode_capability[0x18];
8017 u8 retransmission_support_admin[0x8];
8018 u8 fec_mode_support_admin[0x18];
8020 u8 retransmission_request_admin[0x8];
8021 u8 fec_mode_request_admin[0x18];
8023 u8 reserved_at_c0[0x80];
8026 struct mlx5_ifc_plib_reg_bits {
8027 u8 reserved_at_0[0x8];
8029 u8 reserved_at_10[0x8];
8032 u8 reserved_at_20[0x60];
8035 struct mlx5_ifc_plbf_reg_bits {
8036 u8 reserved_at_0[0x8];
8038 u8 reserved_at_10[0xd];
8041 u8 reserved_at_20[0x20];
8044 struct mlx5_ifc_pipg_reg_bits {
8045 u8 reserved_at_0[0x8];
8047 u8 reserved_at_10[0x10];
8050 u8 reserved_at_21[0x19];
8052 u8 reserved_at_3e[0x2];
8055 struct mlx5_ifc_pifr_reg_bits {
8056 u8 reserved_at_0[0x8];
8058 u8 reserved_at_10[0x10];
8060 u8 reserved_at_20[0xe0];
8062 u8 port_filter[8][0x20];
8064 u8 port_filter_update_en[8][0x20];
8067 struct mlx5_ifc_pfcc_reg_bits {
8068 u8 reserved_at_0[0x8];
8070 u8 reserved_at_10[0xb];
8071 u8 ppan_mask_n[0x1];
8072 u8 minor_stall_mask[0x1];
8073 u8 critical_stall_mask[0x1];
8074 u8 reserved_at_1e[0x2];
8077 u8 reserved_at_24[0x4];
8078 u8 prio_mask_tx[0x8];
8079 u8 reserved_at_30[0x8];
8080 u8 prio_mask_rx[0x8];
8084 u8 pptx_mask_n[0x1];
8085 u8 reserved_at_43[0x5];
8087 u8 reserved_at_50[0x10];
8091 u8 pprx_mask_n[0x1];
8092 u8 reserved_at_63[0x5];
8094 u8 reserved_at_70[0x10];
8096 u8 device_stall_minor_watermark[0x10];
8097 u8 device_stall_critical_watermark[0x10];
8099 u8 reserved_at_a0[0x60];
8102 struct mlx5_ifc_pelc_reg_bits {
8104 u8 reserved_at_4[0x4];
8106 u8 reserved_at_10[0x10];
8109 u8 op_capability[0x8];
8115 u8 capability[0x40];
8121 u8 reserved_at_140[0x80];
8124 struct mlx5_ifc_peir_reg_bits {
8125 u8 reserved_at_0[0x8];
8127 u8 reserved_at_10[0x10];
8129 u8 reserved_at_20[0xc];
8130 u8 error_count[0x4];
8131 u8 reserved_at_30[0x10];
8133 u8 reserved_at_40[0xc];
8135 u8 reserved_at_50[0x8];
8139 struct mlx5_ifc_mpegc_reg_bits {
8140 u8 reserved_at_0[0x30];
8141 u8 field_select[0x10];
8143 u8 tx_overflow_sense[0x1];
8146 u8 reserved_at_43[0x1b];
8147 u8 tx_lossy_overflow_oper[0x2];
8149 u8 reserved_at_60[0x100];
8152 struct mlx5_ifc_pcam_enhanced_features_bits {
8153 u8 reserved_at_0[0x6d];
8154 u8 rx_icrc_encapsulated_counter[0x1];
8155 u8 reserved_at_6e[0x8];
8157 u8 reserved_at_77[0x3];
8158 u8 per_lane_error_counters[0x1];
8159 u8 rx_buffer_fullness_counters[0x1];
8160 u8 ptys_connector_type[0x1];
8161 u8 reserved_at_7d[0x1];
8162 u8 ppcnt_discard_group[0x1];
8163 u8 ppcnt_statistical_group[0x1];
8166 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8167 u8 port_access_reg_cap_mask_127_to_96[0x20];
8168 u8 port_access_reg_cap_mask_95_to_64[0x20];
8170 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8172 u8 port_access_reg_cap_mask_34_to_32[0x3];
8174 u8 port_access_reg_cap_mask_31_to_13[0x13];
8177 u8 port_access_reg_cap_mask_10_to_0[0xb];
8180 struct mlx5_ifc_pcam_reg_bits {
8181 u8 reserved_at_0[0x8];
8182 u8 feature_group[0x8];
8183 u8 reserved_at_10[0x8];
8184 u8 access_reg_group[0x8];
8186 u8 reserved_at_20[0x20];
8189 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8190 u8 reserved_at_0[0x80];
8191 } port_access_reg_cap_mask;
8193 u8 reserved_at_c0[0x80];
8196 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8197 u8 reserved_at_0[0x80];
8200 u8 reserved_at_1c0[0xc0];
8203 struct mlx5_ifc_mcam_enhanced_features_bits {
8204 u8 reserved_at_0[0x74];
8205 u8 mark_tx_action_cnp[0x1];
8206 u8 mark_tx_action_cqe[0x1];
8207 u8 dynamic_tx_overflow[0x1];
8208 u8 reserved_at_77[0x4];
8209 u8 pcie_outbound_stalled[0x1];
8210 u8 tx_overflow_buffer_pkt[0x1];
8211 u8 mtpps_enh_out_per_adj[0x1];
8213 u8 pcie_performance_group[0x1];
8216 struct mlx5_ifc_mcam_access_reg_bits {
8217 u8 reserved_at_0[0x1c];
8221 u8 reserved_at_1f[0x1];
8223 u8 regs_95_to_87[0x9];
8225 u8 regs_85_to_68[0x12];
8226 u8 tracer_registers[0x4];
8228 u8 regs_63_to_32[0x20];
8229 u8 regs_31_to_0[0x20];
8232 struct mlx5_ifc_mcam_reg_bits {
8233 u8 reserved_at_0[0x8];
8234 u8 feature_group[0x8];
8235 u8 reserved_at_10[0x8];
8236 u8 access_reg_group[0x8];
8238 u8 reserved_at_20[0x20];
8241 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8242 u8 reserved_at_0[0x80];
8243 } mng_access_reg_cap_mask;
8245 u8 reserved_at_c0[0x80];
8248 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8249 u8 reserved_at_0[0x80];
8250 } mng_feature_cap_mask;
8252 u8 reserved_at_1c0[0x80];
8255 struct mlx5_ifc_qcam_access_reg_cap_mask {
8256 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8258 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8262 u8 qcam_access_reg_cap_mask_0[0x1];
8265 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8266 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8267 u8 qpts_trust_both[0x1];
8270 struct mlx5_ifc_qcam_reg_bits {
8271 u8 reserved_at_0[0x8];
8272 u8 feature_group[0x8];
8273 u8 reserved_at_10[0x8];
8274 u8 access_reg_group[0x8];
8275 u8 reserved_at_20[0x20];
8278 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8279 u8 reserved_at_0[0x80];
8280 } qos_access_reg_cap_mask;
8282 u8 reserved_at_c0[0x80];
8285 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8286 u8 reserved_at_0[0x80];
8287 } qos_feature_cap_mask;
8289 u8 reserved_at_1c0[0x80];
8292 struct mlx5_ifc_pcap_reg_bits {
8293 u8 reserved_at_0[0x8];
8295 u8 reserved_at_10[0x10];
8297 u8 port_capability_mask[4][0x20];
8300 struct mlx5_ifc_paos_reg_bits {
8303 u8 reserved_at_10[0x4];
8304 u8 admin_status[0x4];
8305 u8 reserved_at_18[0x4];
8306 u8 oper_status[0x4];
8310 u8 reserved_at_22[0x1c];
8313 u8 reserved_at_40[0x40];
8316 struct mlx5_ifc_pamp_reg_bits {
8317 u8 reserved_at_0[0x8];
8318 u8 opamp_group[0x8];
8319 u8 reserved_at_10[0xc];
8320 u8 opamp_group_type[0x4];
8322 u8 start_index[0x10];
8323 u8 reserved_at_30[0x4];
8324 u8 num_of_indices[0xc];
8326 u8 index_data[18][0x10];
8329 struct mlx5_ifc_pcmr_reg_bits {
8330 u8 reserved_at_0[0x8];
8332 u8 reserved_at_10[0x2e];
8334 u8 reserved_at_3f[0x1f];
8336 u8 reserved_at_5f[0x1];
8339 struct mlx5_ifc_lane_2_module_mapping_bits {
8340 u8 reserved_at_0[0x6];
8342 u8 reserved_at_8[0x6];
8344 u8 reserved_at_10[0x8];
8348 struct mlx5_ifc_bufferx_reg_bits {
8349 u8 reserved_at_0[0x6];
8352 u8 reserved_at_8[0xc];
8355 u8 xoff_threshold[0x10];
8356 u8 xon_threshold[0x10];
8359 struct mlx5_ifc_set_node_in_bits {
8360 u8 node_description[64][0x8];
8363 struct mlx5_ifc_register_power_settings_bits {
8364 u8 reserved_at_0[0x18];
8365 u8 power_settings_level[0x8];
8367 u8 reserved_at_20[0x60];
8370 struct mlx5_ifc_register_host_endianness_bits {
8372 u8 reserved_at_1[0x1f];
8374 u8 reserved_at_20[0x60];
8377 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8378 u8 reserved_at_0[0x20];
8382 u8 addressh_63_32[0x20];
8384 u8 addressl_31_0[0x20];
8387 struct mlx5_ifc_ud_adrs_vector_bits {
8391 u8 reserved_at_41[0x7];
8392 u8 destination_qp_dct[0x18];
8394 u8 static_rate[0x4];
8395 u8 sl_eth_prio[0x4];
8398 u8 rlid_udp_sport[0x10];
8400 u8 reserved_at_80[0x20];
8402 u8 rmac_47_16[0x20];
8408 u8 reserved_at_e0[0x1];
8410 u8 reserved_at_e2[0x2];
8411 u8 src_addr_index[0x8];
8412 u8 flow_label[0x14];
8414 u8 rgid_rip[16][0x8];
8417 struct mlx5_ifc_pages_req_event_bits {
8418 u8 reserved_at_0[0x10];
8419 u8 function_id[0x10];
8423 u8 reserved_at_40[0xa0];
8426 struct mlx5_ifc_eqe_bits {
8427 u8 reserved_at_0[0x8];
8429 u8 reserved_at_10[0x8];
8430 u8 event_sub_type[0x8];
8432 u8 reserved_at_20[0xe0];
8434 union mlx5_ifc_event_auto_bits event_data;
8436 u8 reserved_at_1e0[0x10];
8438 u8 reserved_at_1f8[0x7];
8443 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8446 struct mlx5_ifc_cmd_queue_entry_bits {
8448 u8 reserved_at_8[0x18];
8450 u8 input_length[0x20];
8452 u8 input_mailbox_pointer_63_32[0x20];
8454 u8 input_mailbox_pointer_31_9[0x17];
8455 u8 reserved_at_77[0x9];
8457 u8 command_input_inline_data[16][0x8];
8459 u8 command_output_inline_data[16][0x8];
8461 u8 output_mailbox_pointer_63_32[0x20];
8463 u8 output_mailbox_pointer_31_9[0x17];
8464 u8 reserved_at_1b7[0x9];
8466 u8 output_length[0x20];
8470 u8 reserved_at_1f0[0x8];
8475 struct mlx5_ifc_cmd_out_bits {
8477 u8 reserved_at_8[0x18];
8481 u8 command_output[0x20];
8484 struct mlx5_ifc_cmd_in_bits {
8486 u8 reserved_at_10[0x10];
8488 u8 reserved_at_20[0x10];
8491 u8 command[0][0x20];
8494 struct mlx5_ifc_cmd_if_box_bits {
8495 u8 mailbox_data[512][0x8];
8497 u8 reserved_at_1000[0x180];
8499 u8 next_pointer_63_32[0x20];
8501 u8 next_pointer_31_10[0x16];
8502 u8 reserved_at_11b6[0xa];
8504 u8 block_number[0x20];
8506 u8 reserved_at_11e0[0x8];
8508 u8 ctrl_signature[0x8];
8512 struct mlx5_ifc_mtt_bits {
8513 u8 ptag_63_32[0x20];
8516 u8 reserved_at_38[0x6];
8521 struct mlx5_ifc_query_wol_rol_out_bits {
8523 u8 reserved_at_8[0x18];
8527 u8 reserved_at_40[0x10];
8531 u8 reserved_at_60[0x20];
8534 struct mlx5_ifc_query_wol_rol_in_bits {
8536 u8 reserved_at_10[0x10];
8538 u8 reserved_at_20[0x10];
8541 u8 reserved_at_40[0x40];
8544 struct mlx5_ifc_set_wol_rol_out_bits {
8546 u8 reserved_at_8[0x18];
8550 u8 reserved_at_40[0x40];
8553 struct mlx5_ifc_set_wol_rol_in_bits {
8555 u8 reserved_at_10[0x10];
8557 u8 reserved_at_20[0x10];
8560 u8 rol_mode_valid[0x1];
8561 u8 wol_mode_valid[0x1];
8562 u8 reserved_at_42[0xe];
8566 u8 reserved_at_60[0x20];
8570 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8571 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8572 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8576 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8577 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8578 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8582 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8583 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8584 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8585 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8586 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8587 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8588 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8589 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8590 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8591 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8592 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8595 struct mlx5_ifc_initial_seg_bits {
8596 u8 fw_rev_minor[0x10];
8597 u8 fw_rev_major[0x10];
8599 u8 cmd_interface_rev[0x10];
8600 u8 fw_rev_subminor[0x10];
8602 u8 reserved_at_40[0x40];
8604 u8 cmdq_phy_addr_63_32[0x20];
8606 u8 cmdq_phy_addr_31_12[0x14];
8607 u8 reserved_at_b4[0x2];
8608 u8 nic_interface[0x2];
8609 u8 log_cmdq_size[0x4];
8610 u8 log_cmdq_stride[0x4];
8612 u8 command_doorbell_vector[0x20];
8614 u8 reserved_at_e0[0xf00];
8616 u8 initializing[0x1];
8617 u8 reserved_at_fe1[0x4];
8618 u8 nic_interface_supported[0x3];
8619 u8 reserved_at_fe8[0x18];
8621 struct mlx5_ifc_health_buffer_bits health_buffer;
8623 u8 no_dram_nic_offset[0x20];
8625 u8 reserved_at_1220[0x6e40];
8627 u8 reserved_at_8060[0x1f];
8630 u8 health_syndrome[0x8];
8631 u8 health_counter[0x18];
8633 u8 reserved_at_80a0[0x17fc0];
8636 struct mlx5_ifc_mtpps_reg_bits {
8637 u8 reserved_at_0[0xc];
8638 u8 cap_number_of_pps_pins[0x4];
8639 u8 reserved_at_10[0x4];
8640 u8 cap_max_num_of_pps_in_pins[0x4];
8641 u8 reserved_at_18[0x4];
8642 u8 cap_max_num_of_pps_out_pins[0x4];
8644 u8 reserved_at_20[0x24];
8645 u8 cap_pin_3_mode[0x4];
8646 u8 reserved_at_48[0x4];
8647 u8 cap_pin_2_mode[0x4];
8648 u8 reserved_at_50[0x4];
8649 u8 cap_pin_1_mode[0x4];
8650 u8 reserved_at_58[0x4];
8651 u8 cap_pin_0_mode[0x4];
8653 u8 reserved_at_60[0x4];
8654 u8 cap_pin_7_mode[0x4];
8655 u8 reserved_at_68[0x4];
8656 u8 cap_pin_6_mode[0x4];
8657 u8 reserved_at_70[0x4];
8658 u8 cap_pin_5_mode[0x4];
8659 u8 reserved_at_78[0x4];
8660 u8 cap_pin_4_mode[0x4];
8662 u8 field_select[0x20];
8663 u8 reserved_at_a0[0x60];
8666 u8 reserved_at_101[0xb];
8668 u8 reserved_at_110[0x4];
8672 u8 reserved_at_120[0x20];
8674 u8 time_stamp[0x40];
8676 u8 out_pulse_duration[0x10];
8677 u8 out_periodic_adjustment[0x10];
8678 u8 enhanced_out_periodic_adjustment[0x20];
8680 u8 reserved_at_1c0[0x20];
8683 struct mlx5_ifc_mtppse_reg_bits {
8684 u8 reserved_at_0[0x18];
8687 u8 reserved_at_21[0x1b];
8688 u8 event_generation_mode[0x4];
8689 u8 reserved_at_40[0x40];
8692 struct mlx5_ifc_mcqi_cap_bits {
8693 u8 supported_info_bitmask[0x20];
8695 u8 component_size[0x20];
8697 u8 max_component_size[0x20];
8699 u8 log_mcda_word_size[0x4];
8700 u8 reserved_at_64[0xc];
8701 u8 mcda_max_write_size[0x10];
8704 u8 reserved_at_81[0x1];
8705 u8 match_chip_id[0x1];
8707 u8 check_user_timestamp[0x1];
8708 u8 match_base_guid_mac[0x1];
8709 u8 reserved_at_86[0x1a];
8712 struct mlx5_ifc_mcqi_reg_bits {
8713 u8 read_pending_component[0x1];
8714 u8 reserved_at_1[0xf];
8715 u8 component_index[0x10];
8717 u8 reserved_at_20[0x20];
8719 u8 reserved_at_40[0x1b];
8726 u8 reserved_at_a0[0x10];
8732 struct mlx5_ifc_mcc_reg_bits {
8733 u8 reserved_at_0[0x4];
8734 u8 time_elapsed_since_last_cmd[0xc];
8735 u8 reserved_at_10[0x8];
8736 u8 instruction[0x8];
8738 u8 reserved_at_20[0x10];
8739 u8 component_index[0x10];
8741 u8 reserved_at_40[0x8];
8742 u8 update_handle[0x18];
8744 u8 handle_owner_type[0x4];
8745 u8 handle_owner_host_id[0x4];
8746 u8 reserved_at_68[0x1];
8747 u8 control_progress[0x7];
8749 u8 reserved_at_78[0x4];
8750 u8 control_state[0x4];
8752 u8 component_size[0x20];
8754 u8 reserved_at_a0[0x60];
8757 struct mlx5_ifc_mcda_reg_bits {
8758 u8 reserved_at_0[0x8];
8759 u8 update_handle[0x18];
8763 u8 reserved_at_40[0x10];
8766 u8 reserved_at_60[0x20];
8771 union mlx5_ifc_ports_control_registers_document_bits {
8772 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8773 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8774 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8775 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8776 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8777 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8778 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8779 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8780 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8781 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8782 struct mlx5_ifc_paos_reg_bits paos_reg;
8783 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8784 struct mlx5_ifc_peir_reg_bits peir_reg;
8785 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8786 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8787 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8788 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8789 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8790 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8791 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8792 struct mlx5_ifc_plib_reg_bits plib_reg;
8793 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8794 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8795 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8796 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8797 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8798 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8799 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8800 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8801 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8802 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8803 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8804 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8805 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8806 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8807 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8808 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8809 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8810 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8811 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8812 struct mlx5_ifc_pude_reg_bits pude_reg;
8813 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8814 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8815 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8816 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8817 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8818 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8819 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8820 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8821 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8822 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8823 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8824 u8 reserved_at_0[0x60e0];
8827 union mlx5_ifc_debug_enhancements_document_bits {
8828 struct mlx5_ifc_health_buffer_bits health_buffer;
8829 u8 reserved_at_0[0x200];
8832 union mlx5_ifc_uplink_pci_interface_document_bits {
8833 struct mlx5_ifc_initial_seg_bits initial_seg;
8834 u8 reserved_at_0[0x20060];
8837 struct mlx5_ifc_set_flow_table_root_out_bits {
8839 u8 reserved_at_8[0x18];
8843 u8 reserved_at_40[0x40];
8846 struct mlx5_ifc_set_flow_table_root_in_bits {
8848 u8 reserved_at_10[0x10];
8850 u8 reserved_at_20[0x10];
8853 u8 other_vport[0x1];
8854 u8 reserved_at_41[0xf];
8855 u8 vport_number[0x10];
8857 u8 reserved_at_60[0x20];
8860 u8 reserved_at_88[0x18];
8862 u8 reserved_at_a0[0x8];
8865 u8 reserved_at_c0[0x8];
8866 u8 underlay_qpn[0x18];
8867 u8 reserved_at_e0[0x120];
8871 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8872 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8875 struct mlx5_ifc_modify_flow_table_out_bits {
8877 u8 reserved_at_8[0x18];
8881 u8 reserved_at_40[0x40];
8884 struct mlx5_ifc_modify_flow_table_in_bits {
8886 u8 reserved_at_10[0x10];
8888 u8 reserved_at_20[0x10];
8891 u8 other_vport[0x1];
8892 u8 reserved_at_41[0xf];
8893 u8 vport_number[0x10];
8895 u8 reserved_at_60[0x10];
8896 u8 modify_field_select[0x10];
8899 u8 reserved_at_88[0x18];
8901 u8 reserved_at_a0[0x8];
8904 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8907 struct mlx5_ifc_ets_tcn_config_reg_bits {
8911 u8 reserved_at_3[0x9];
8913 u8 reserved_at_10[0x9];
8914 u8 bw_allocation[0x7];
8916 u8 reserved_at_20[0xc];
8917 u8 max_bw_units[0x4];
8918 u8 reserved_at_30[0x8];
8919 u8 max_bw_value[0x8];
8922 struct mlx5_ifc_ets_global_config_reg_bits {
8923 u8 reserved_at_0[0x2];
8925 u8 reserved_at_3[0x1d];
8927 u8 reserved_at_20[0xc];
8928 u8 max_bw_units[0x4];
8929 u8 reserved_at_30[0x8];
8930 u8 max_bw_value[0x8];
8933 struct mlx5_ifc_qetc_reg_bits {
8934 u8 reserved_at_0[0x8];
8935 u8 port_number[0x8];
8936 u8 reserved_at_10[0x30];
8938 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8939 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8942 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8944 u8 reserved_at_01[0x0b];
8948 struct mlx5_ifc_qpdpm_reg_bits {
8949 u8 reserved_at_0[0x8];
8951 u8 reserved_at_10[0x10];
8952 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8955 struct mlx5_ifc_qpts_reg_bits {
8956 u8 reserved_at_0[0x8];
8958 u8 reserved_at_10[0x2d];
8959 u8 trust_state[0x3];
8962 struct mlx5_ifc_pptb_reg_bits {
8963 u8 reserved_at_0[0x2];
8965 u8 reserved_at_4[0x4];
8967 u8 reserved_at_10[0x6];
8972 u8 prio_x_buff[0x20];
8975 u8 reserved_at_48[0x10];
8977 u8 untagged_buff[0x4];
8980 struct mlx5_ifc_pbmc_reg_bits {
8981 u8 reserved_at_0[0x8];
8983 u8 reserved_at_10[0x10];
8985 u8 xoff_timer_value[0x10];
8986 u8 xoff_refresh[0x10];
8988 u8 reserved_at_40[0x9];
8989 u8 fullness_threshold[0x7];
8990 u8 port_buffer_size[0x10];
8992 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8994 u8 reserved_at_2e0[0x40];
8997 struct mlx5_ifc_qtct_reg_bits {
8998 u8 reserved_at_0[0x8];
8999 u8 port_number[0x8];
9000 u8 reserved_at_10[0xd];
9003 u8 reserved_at_20[0x1d];
9007 struct mlx5_ifc_mcia_reg_bits {
9009 u8 reserved_at_1[0x7];
9011 u8 reserved_at_10[0x8];
9014 u8 i2c_device_address[0x8];
9015 u8 page_number[0x8];
9016 u8 device_address[0x10];
9018 u8 reserved_at_40[0x10];
9021 u8 reserved_at_60[0x20];
9037 struct mlx5_ifc_dcbx_param_bits {
9038 u8 dcbx_cee_cap[0x1];
9039 u8 dcbx_ieee_cap[0x1];
9040 u8 dcbx_standby_cap[0x1];
9041 u8 reserved_at_3[0x5];
9042 u8 port_number[0x8];
9043 u8 reserved_at_10[0xa];
9044 u8 max_application_table_size[6];
9045 u8 reserved_at_20[0x15];
9046 u8 version_oper[0x3];
9047 u8 reserved_at_38[5];
9048 u8 version_admin[0x3];
9049 u8 willing_admin[0x1];
9050 u8 reserved_at_41[0x3];
9051 u8 pfc_cap_oper[0x4];
9052 u8 reserved_at_48[0x4];
9053 u8 pfc_cap_admin[0x4];
9054 u8 reserved_at_50[0x4];
9055 u8 num_of_tc_oper[0x4];
9056 u8 reserved_at_58[0x4];
9057 u8 num_of_tc_admin[0x4];
9058 u8 remote_willing[0x1];
9059 u8 reserved_at_61[3];
9060 u8 remote_pfc_cap[4];
9061 u8 reserved_at_68[0x14];
9062 u8 remote_num_of_tc[0x4];
9063 u8 reserved_at_80[0x18];
9065 u8 reserved_at_a0[0x160];
9068 struct mlx5_ifc_lagc_bits {
9069 u8 reserved_at_0[0x1d];
9072 u8 reserved_at_20[0x14];
9073 u8 tx_remap_affinity_2[0x4];
9074 u8 reserved_at_38[0x4];
9075 u8 tx_remap_affinity_1[0x4];
9078 struct mlx5_ifc_create_lag_out_bits {
9080 u8 reserved_at_8[0x18];
9084 u8 reserved_at_40[0x40];
9087 struct mlx5_ifc_create_lag_in_bits {
9089 u8 reserved_at_10[0x10];
9091 u8 reserved_at_20[0x10];
9094 struct mlx5_ifc_lagc_bits ctx;
9097 struct mlx5_ifc_modify_lag_out_bits {
9099 u8 reserved_at_8[0x18];
9103 u8 reserved_at_40[0x40];
9106 struct mlx5_ifc_modify_lag_in_bits {
9108 u8 reserved_at_10[0x10];
9110 u8 reserved_at_20[0x10];
9113 u8 reserved_at_40[0x20];
9114 u8 field_select[0x20];
9116 struct mlx5_ifc_lagc_bits ctx;
9119 struct mlx5_ifc_query_lag_out_bits {
9121 u8 reserved_at_8[0x18];
9125 u8 reserved_at_40[0x40];
9127 struct mlx5_ifc_lagc_bits ctx;
9130 struct mlx5_ifc_query_lag_in_bits {
9132 u8 reserved_at_10[0x10];
9134 u8 reserved_at_20[0x10];
9137 u8 reserved_at_40[0x40];
9140 struct mlx5_ifc_destroy_lag_out_bits {
9142 u8 reserved_at_8[0x18];
9146 u8 reserved_at_40[0x40];
9149 struct mlx5_ifc_destroy_lag_in_bits {
9151 u8 reserved_at_10[0x10];
9153 u8 reserved_at_20[0x10];
9156 u8 reserved_at_40[0x40];
9159 struct mlx5_ifc_create_vport_lag_out_bits {
9161 u8 reserved_at_8[0x18];
9165 u8 reserved_at_40[0x40];
9168 struct mlx5_ifc_create_vport_lag_in_bits {
9170 u8 reserved_at_10[0x10];
9172 u8 reserved_at_20[0x10];
9175 u8 reserved_at_40[0x40];
9178 struct mlx5_ifc_destroy_vport_lag_out_bits {
9180 u8 reserved_at_8[0x18];
9184 u8 reserved_at_40[0x40];
9187 struct mlx5_ifc_destroy_vport_lag_in_bits {
9189 u8 reserved_at_10[0x10];
9191 u8 reserved_at_20[0x10];
9194 u8 reserved_at_40[0x40];
9197 struct mlx5_ifc_alloc_memic_in_bits {
9199 u8 reserved_at_10[0x10];
9201 u8 reserved_at_20[0x10];
9204 u8 reserved_at_30[0x20];
9206 u8 reserved_at_40[0x18];
9207 u8 log_memic_addr_alignment[0x8];
9209 u8 range_start_addr[0x40];
9211 u8 range_size[0x20];
9213 u8 memic_size[0x20];
9216 struct mlx5_ifc_alloc_memic_out_bits {
9218 u8 reserved_at_8[0x18];
9222 u8 memic_start_addr[0x40];
9225 struct mlx5_ifc_dealloc_memic_in_bits {
9227 u8 reserved_at_10[0x10];
9229 u8 reserved_at_20[0x10];
9232 u8 reserved_at_40[0x40];
9234 u8 memic_start_addr[0x40];
9236 u8 memic_size[0x20];
9238 u8 reserved_at_e0[0x20];
9241 struct mlx5_ifc_dealloc_memic_out_bits {
9243 u8 reserved_at_8[0x18];
9247 u8 reserved_at_40[0x40];
9250 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9254 u8 reserved_at_20[0x10];
9259 u8 reserved_at_60[0x20];
9262 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9264 u8 reserved_at_8[0x18];
9270 u8 reserved_at_60[0x20];
9273 struct mlx5_ifc_umem_bits {
9274 u8 modify_field_select[0x40];
9276 u8 reserved_at_40[0x5b];
9277 u8 log_page_size[0x5];
9279 u8 page_offset[0x20];
9281 u8 num_of_mtt[0x40];
9283 struct mlx5_ifc_mtt_bits mtt[0];
9286 struct mlx5_ifc_uctx_bits {
9287 u8 modify_field_select[0x40];
9291 u8 reserved_at_60[0x1a0];
9294 struct mlx5_ifc_create_umem_in_bits {
9295 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9296 struct mlx5_ifc_umem_bits umem;
9299 struct mlx5_ifc_create_uctx_in_bits {
9300 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9301 struct mlx5_ifc_uctx_bits uctx;
9304 struct mlx5_ifc_mtrc_string_db_param_bits {
9305 u8 string_db_base_address[0x20];
9307 u8 reserved_at_20[0x8];
9308 u8 string_db_size[0x18];
9311 struct mlx5_ifc_mtrc_cap_bits {
9312 u8 trace_owner[0x1];
9313 u8 trace_to_memory[0x1];
9314 u8 reserved_at_2[0x4];
9316 u8 reserved_at_8[0x14];
9317 u8 num_string_db[0x4];
9319 u8 first_string_trace[0x8];
9320 u8 num_string_trace[0x8];
9321 u8 reserved_at_30[0x28];
9323 u8 log_max_trace_buffer_size[0x8];
9325 u8 reserved_at_60[0x20];
9327 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9329 u8 reserved_at_280[0x180];
9332 struct mlx5_ifc_mtrc_conf_bits {
9333 u8 reserved_at_0[0x1c];
9335 u8 reserved_at_20[0x18];
9336 u8 log_trace_buffer_size[0x8];
9337 u8 trace_mkey[0x20];
9338 u8 reserved_at_60[0x3a0];
9341 struct mlx5_ifc_mtrc_stdb_bits {
9342 u8 string_db_index[0x4];
9343 u8 reserved_at_4[0x4];
9345 u8 start_offset[0x20];
9346 u8 string_db_data[0];
9349 struct mlx5_ifc_mtrc_ctrl_bits {
9350 u8 trace_status[0x2];
9351 u8 reserved_at_2[0x2];
9353 u8 reserved_at_5[0xb];
9354 u8 modify_field_select[0x10];
9355 u8 reserved_at_20[0x2b];
9356 u8 current_timestamp52_32[0x15];
9357 u8 current_timestamp31_0[0x20];
9358 u8 reserved_at_80[0x180];
9361 #endif /* MLX5_IFC_H */