1 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/list.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/idr.h>
22 #include <soc/qcom/socinfo.h>
24 extern pgprot_t pgprot_kernel;
25 extern struct bus_type msm_iommu_sec_bus_type;
26 extern struct bus_type *msm_iommu_non_sec_bus_type;
27 extern struct iommu_access_ops iommu_access_ops_v0;
28 extern struct iommu_access_ops iommu_access_ops_v1;
30 /* Domain attributes */
31 #define MSM_IOMMU_DOMAIN_PT_CACHEABLE 0x1
32 #define MSM_IOMMU_DOMAIN_PT_SECURE 0x2
34 /* Mask for the cache policy attribute */
35 #define MSM_IOMMU_CP_MASK 0x03
37 /* Maximum number of Machine IDs that we are allowing to be mapped to the same
38 * context bank. The number of MIDs mapped to the same CB does not affect
39 * performance, but there is a practical limit on how many distinct MIDs may
40 * be present. These mappings are typically determined at design time and are
41 * not expected to change at run time.
43 #define MAX_NUM_MIDS 32
45 /* Maximum number of SMT entries allowed by the system */
46 #define MAX_NUM_SMR 128
48 #define MAX_NUM_BFB_REGS 32
51 * struct msm_iommu_dev - a single IOMMU hardware instance
52 * name Human-readable name given to this IOMMU HW instance
53 * ncb Number of context banks present on this IOMMU HW instance
55 struct msm_iommu_dev {
62 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
63 * name Human-readable name given to this context bank
64 * num Index of this context bank within the hardware
65 * mids List of Machine IDs that are to be mapped into this context
66 * bank, terminated by -1. The MID is a set of signals on the
67 * AXI bus that identifies the function associated with a specific
68 * memory request. (See ARM spec).
70 struct msm_iommu_ctx_dev {
73 int mids[MAX_NUM_MIDS];
77 * struct msm_iommu_bfb_settings - a set of IOMMU BFB tuning parameters
78 * regs An array of register offsets to configure
79 * data Values to write to corresponding registers
80 * length Number of valid entries in the offset/val arrays
82 struct msm_iommu_bfb_settings {
83 unsigned int regs[MAX_NUM_BFB_REGS];
84 unsigned int data[MAX_NUM_BFB_REGS];
89 * struct msm_iommu_drvdata - A single IOMMU hardware instance
90 * @base: IOMMU config port base address (VA)
91 * @glb_base: IOMMU config port base address for global register space (VA)
92 * @phys_base: IOMMU physical base address.
93 * @ncb The number of contexts on this IOMMU
94 * @irq: Interrupt number
95 * @clk: The bus clock for this IOMMU hardware instance
96 * @pclk: The clock for the IOMMU bus interconnect
97 * @aclk: Alternate core clock for this IOMMU core, if any
98 * @aiclk: Alternate interface clock for this IOMMU core, if any
99 * @name: Human-readable name of this IOMMU device
100 * @gdsc: Regulator needed to power this HW block (v2 only)
101 * @bfb_settings: Optional BFB performance tuning parameters
102 * @dev: Struct device this hardware instance is tied to
103 * @list: List head to link all iommus together
104 * @clk_reg_virt: Optional clock register virtual address.
105 * @halt_enabled: Set to 1 if IOMMU halt is supported in the IOMMU, 0 otherwise.
106 * @ctx_attach_count: Count of how many context are attached.
107 * @bus_client : Bus client needed to vote for bus bandwidth.
108 * @needs_rem_spinlock : 1 if remote spinlock is needed, 0 otherwise
109 * @powered_on: Powered status of the IOMMU. 0 means powered off.
111 * A msm_iommu_drvdata holds the global driver data about a single piece
112 * of an IOMMU hardware instance.
114 struct msm_iommu_drvdata {
116 phys_addr_t phys_base;
117 void __iomem *glb_base;
118 void __iomem *cb_base;
119 void __iomem *smmu_local_base;
120 void __iomem *vbif_base;
128 struct regulator *gdsc;
129 struct regulator *alt_gdsc;
130 struct msm_iommu_bfb_settings *bfb_settings;
133 struct list_head list;
134 void __iomem *clk_reg_virt;
136 unsigned int ctx_attach_count;
137 unsigned int bus_client;
138 int needs_rem_spinlock;
145 * struct iommu_access_ops - Callbacks for accessing IOMMU
146 * @iommu_power_on: Turn on power to unit
147 * @iommu_power_off: Turn off power to unit
148 * @iommu_bus_vote: Vote for bus bandwidth
149 * @iommu_clk_on: Turn on clks to unit
150 * @iommu_clk_off: Turn off clks to unit
151 * @iommu_lock_initialize: Initialize the remote lock
152 * @iommu_lock_acquire: Acquire any locks needed
153 * @iommu_lock_release: Release locks needed
155 struct iommu_access_ops {
156 int (*iommu_power_on)(struct msm_iommu_drvdata *);
157 void (*iommu_power_off)(struct msm_iommu_drvdata *);
158 int (*iommu_bus_vote)(struct msm_iommu_drvdata *drvdata,
160 int (*iommu_clk_on)(struct msm_iommu_drvdata *);
161 void (*iommu_clk_off)(struct msm_iommu_drvdata *);
162 void * (*iommu_lock_initialize)(void);
163 void (*iommu_lock_acquire)(unsigned int need_extra_lock);
164 void (*iommu_lock_release)(unsigned int need_extra_lock);
167 void msm_iommu_add_drv(struct msm_iommu_drvdata *drv);
168 void msm_iommu_remove_drv(struct msm_iommu_drvdata *drv);
169 void program_iommu_bfb_settings(void __iomem *base,
170 const struct msm_iommu_bfb_settings *bfb_settings);
171 void iommu_halt(const struct msm_iommu_drvdata *iommu_drvdata);
172 void iommu_resume(const struct msm_iommu_drvdata *iommu_drvdata);
175 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
176 * @num: Hardware context number of this context
177 * @pdev: Platform device associated wit this HW instance
178 * @attached_elm: List element for domains to track which devices are
180 * @attached_domain Domain currently attached to this context (if any)
181 * @name Human-readable name of this context device
182 * @sids List of Stream IDs mapped to this context
183 * @nsid Number of Stream IDs mapped to this context
184 * @secure_context true if this is a secure context programmed by
185 the secure environment, false otherwise
186 * @asid ASID used with this context.
187 * @attach_count Number of time this context has been attached.
188 * @report_error_on_fault - true if error is returned back to master
189 * @dynamic true if any dynamic domain is ever attached to this CB
191 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
192 * within each IOMMU hardware instance
194 struct msm_iommu_ctx_drvdata {
196 struct platform_device *pdev;
197 struct list_head attached_elm;
198 struct iommu_domain *attached_domain;
200 u32 sids[MAX_NUM_SMR];
202 unsigned int secure_context;
205 u32 sid_mask[MAX_NUM_SMR];
206 unsigned int n_sid_mask;
207 bool report_error_on_fault;
208 unsigned int prefetch_depth;
214 DUMP_REG_FAR0 = DUMP_REG_FIRST,
228 DUMP_REG_MAIR0 = DUMP_REG_PRRR,
230 DUMP_REG_MAIR1 = DUMP_REG_NMRR,
232 DUMP_REG_CBFRSYNRA_N,
249 struct dump_regs_tbl_entry {
251 * To keep things context-bank-agnostic, we only store the
252 * register offset in `reg_offset'
254 unsigned int reg_offset;
257 enum dump_reg_type dump_reg_type;
259 extern struct dump_regs_tbl_entry dump_regs_tbl[MAX_DUMP_REGS];
261 #define COMBINE_DUMP_REG(upper, lower) (((u64) upper << 32) | lower)
263 struct msm_iommu_context_reg {
268 void print_ctx_regs(struct msm_iommu_context_reg regs[]);
271 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
272 * interrupt is not supported in the API yet, but this will print an error
273 * message and dump useful IOMMU registers.
275 irqreturn_t msm_iommu_global_fault_handler(int irq, void *dev_id);
276 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
277 irqreturn_t msm_iommu_fault_handler_v2(int irq, void *dev_id);
278 irqreturn_t msm_iommu_secure_fault_handler_v2(int irq, void *dev_id);
286 /* Expose structure to allow kgsl iommu driver to use the same structure to
287 * communicate to GPU the addresses of the flag and turn variables.
289 struct remote_iommu_petersons_spinlock {
290 uint32_t flag[PROC_MAX];
294 #ifdef CONFIG_MSM_IOMMU
295 void *msm_iommu_lock_initialize(void);
296 void msm_iommu_mutex_lock(void);
297 void msm_iommu_mutex_unlock(void);
298 void msm_set_iommu_access_ops(struct iommu_access_ops *ops);
299 struct iommu_access_ops *msm_get_iommu_access_ops(void);
301 static inline void *msm_iommu_lock_initialize(void)
305 static inline void msm_iommu_mutex_lock(void) { }
306 static inline void msm_iommu_mutex_unlock(void) { }
307 static inline void msm_set_iommu_access_ops(struct iommu_access_ops *ops)
311 static inline struct iommu_access_ops *msm_get_iommu_access_ops(void)
317 #ifdef CONFIG_MSM_IOMMU_SYNC
318 void msm_iommu_remote_p0_spin_lock(unsigned int need_lock);
319 void msm_iommu_remote_p0_spin_unlock(unsigned int need_lock);
321 #define msm_iommu_remote_lock_init() _msm_iommu_remote_spin_lock_init()
322 #define msm_iommu_remote_spin_lock(need_lock) \
323 msm_iommu_remote_p0_spin_lock(need_lock)
324 #define msm_iommu_remote_spin_unlock(need_lock) \
325 msm_iommu_remote_p0_spin_unlock(need_lock)
327 #define msm_iommu_remote_lock_init()
328 #define msm_iommu_remote_spin_lock(need_lock)
329 #define msm_iommu_remote_spin_unlock(need_lock)
332 #ifdef CONFIG_MSM_IOMMU
334 * Look up an IOMMU context device by its context name. NULL if none found.
335 * Useful for testing and drivers that do not yet fully have IOMMU stuff in
336 * their platform devices.
338 struct device *msm_iommu_get_ctx(const char *ctx_name);
339 struct bus_type *msm_iommu_get_bus(struct device *dev);
340 int msm_iommu_bus_register(void);
341 void msm_access_control(void);
343 static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
348 static inline struct bus_type *msm_iommu_get_bus(struct device *dev)
350 return &platform_bus_type;
353 static inline void msm_access_control(void)
359 * Function to program the global registers of an IOMMU securely.
360 * This should only be called on IOMMUs for which kernel programming
361 * of global registers is not possible
363 void msm_iommu_sec_set_access_ops(struct iommu_access_ops *access_ops);
364 int msm_iommu_sec_program_iommu(struct msm_iommu_drvdata *drvdata,
365 struct msm_iommu_ctx_drvdata *ctx_drvdata);
366 int is_vfe_secure(void);
368 #ifdef CONFIG_MSM_IOMMU_V0
369 static inline int msm_soc_version_supports_iommu_v0(void)
371 static int soc_supports_v0 = -1;
373 struct device_node *node;
376 if (soc_supports_v0 != -1)
377 return soc_supports_v0;
380 node = of_find_compatible_node(NULL, NULL, "qcom,msm-smmu-v0");
387 if (cpu_is_msm8960() &&
388 SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 2) {
393 if (cpu_is_msm8x60() &&
394 (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2 ||
395 SOCINFO_VERSION_MINOR(socinfo_get_version()) < 1)) {
404 static inline int msm_soc_version_supports_iommu_v0(void)
410 int msm_iommu_get_scm_call_avail(void);
411 void msm_iommu_check_scm_call_avail(void);
413 u32 msm_iommu_get_mair0(void);
414 u32 msm_iommu_get_mair1(void);
415 u32 msm_iommu_get_prrr(void);
416 u32 msm_iommu_get_nmrr(void);
418 /* events for notifiers passed to msm_iommu_register_notify */
419 #define TLB_SYNC_TIMEOUT 1
421 #ifdef CONFIG_MSM_IOMMU_V1
422 void msm_iommu_register_notify(struct notifier_block *nb);
424 static inline void msm_iommu_register_notify(struct notifier_block *nb)