1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/netdevice.h>
39 #include <linux/pci.h>
40 #include <linux/skbuff.h>
41 #include <linux/types.h>
42 #include <asm/byteorder.h>
44 #include <linux/compiler.h>
45 #include <linux/kernel.h>
46 #include <linux/list.h>
47 #include <linux/slab.h>
48 #include <linux/qed/common_hsi.h>
49 #include <linux/qed/qed_chain.h>
51 enum dcbx_protocol_type {
55 DCBX_PROTOCOL_ROCE_V2,
57 DCBX_MAX_PROTOCOL_TYPE
60 #define QED_ROCE_PROTOCOL_INDEX (3)
62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
63 #define QED_LLDP_PORT_ID_STAT_LEN 4
64 #define QED_DCBX_MAX_APP_PROTOCOL 32
65 #define QED_MAX_PFC_PRIORITIES 8
66 #define QED_DCBX_DSCP_SIZE 64
68 struct qed_dcbx_lldp_remote {
69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
77 struct qed_dcbx_lldp_local {
78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
82 struct qed_dcbx_app_prio {
90 struct qed_dbcx_pfc_params {
93 u8 prio[QED_MAX_PFC_PRIORITIES];
97 enum qed_dcbx_sf_ieee_type {
98 QED_DCBX_SF_IEEE_ETHTYPE,
99 QED_DCBX_SF_IEEE_TCP_PORT,
100 QED_DCBX_SF_IEEE_UDP_PORT,
101 QED_DCBX_SF_IEEE_TCP_UDP_PORT
104 struct qed_app_entry {
106 enum qed_dcbx_sf_ieee_type sf_ieee;
110 enum dcbx_protocol_type proto_type;
113 struct qed_dcbx_params {
114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
126 struct qed_dbcx_pfc_params pfc;
130 struct qed_dcbx_admin_params {
131 struct qed_dcbx_params params;
135 struct qed_dcbx_remote_params {
136 struct qed_dcbx_params params;
140 struct qed_dcbx_operational_params {
141 struct qed_dcbx_app_prio app_prio;
142 struct qed_dcbx_params params;
151 struct qed_dcbx_get {
152 struct qed_dcbx_operational_params operational;
153 struct qed_dcbx_lldp_remote lldp_remote;
154 struct qed_dcbx_lldp_local lldp_local;
155 struct qed_dcbx_remote_params remote;
156 struct qed_dcbx_admin_params local;
159 enum qed_nvm_images {
160 QED_NVM_IMAGE_ISCSI_CFG,
161 QED_NVM_IMAGE_FCOE_CFG,
162 QED_NVM_IMAGE_NVM_CFG1,
163 QED_NVM_IMAGE_DEFAULT_CFG,
164 QED_NVM_IMAGE_NVM_META,
167 struct qed_link_eee_params {
169 #define QED_EEE_1G_ADV BIT(0)
170 #define QED_EEE_10G_ADV BIT(1)
172 /* Capabilities are represented using QED_EEE_*_ADV values */
185 struct qed_mfw_tlv_eth {
187 bool lso_maxoff_size_set;
189 bool lso_minseg_size_set;
193 bool tx_descr_size_set;
195 bool rx_descr_size_set;
199 bool tcp4_offloads_set;
201 bool tcp6_offloads_set;
203 bool tx_descr_qdepth_set;
205 bool rx_descr_qdepth_set;
207 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
208 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
209 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
210 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
211 bool iov_offload_set;
217 bool num_txqs_full_set;
219 bool num_rxqs_full_set;
222 #define QED_MFW_TLV_TIME_SIZE 14
223 struct qed_mfw_tlv_time {
233 struct qed_mfw_tlv_fcoe {
235 bool scsi_timeout_set;
249 bool num_npiv_ids_set;
251 bool switch_name_set;
253 bool switch_portnum_set;
255 bool switch_portid_set;
257 bool vendor_name_set;
259 bool switch_model_set;
260 u8 switch_fw_version[8];
261 bool switch_fw_version_set;
267 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
268 #define QED_MFW_TLV_PORT_STATE_LOOP (1)
269 #define QED_MFW_TLV_PORT_STATE_P2P (2)
270 #define QED_MFW_TLV_PORT_STATE_FABRIC (3)
272 u16 fip_tx_descr_size;
273 bool fip_tx_descr_size_set;
274 u16 fip_rx_descr_size;
275 bool fip_rx_descr_size_set;
277 bool link_failures_set;
278 u8 fcoe_boot_progress;
279 bool fcoe_boot_progress_set;
285 bool fcoe_txq_depth_set;
287 bool fcoe_rxq_depth_set;
289 bool fcoe_rx_frames_set;
291 bool fcoe_rx_bytes_set;
293 bool fcoe_tx_frames_set;
295 bool fcoe_tx_bytes_set;
298 u32 crc_err_src_fcid[5];
299 bool crc_err_src_fcid_set[5];
300 struct qed_mfw_tlv_time crc_err[5];
306 bool primtive_err_set;
308 bool disparity_err_set;
309 u16 code_violation_err;
310 bool code_violation_err_set;
312 bool flogi_param_set[4];
313 struct qed_mfw_tlv_time flogi_tstamp;
314 u32 flogi_acc_param[4];
315 bool flogi_acc_param_set[4];
316 struct qed_mfw_tlv_time flogi_acc_tstamp;
319 struct qed_mfw_tlv_time flogi_rjt_tstamp;
332 u32 plogi_dst_fcid[5];
333 bool plogi_dst_fcid_set[5];
334 struct qed_mfw_tlv_time plogi_tstamp[5];
335 u32 plogi_acc_src_fcid[5];
336 bool plogi_acc_src_fcid_set[5];
337 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
344 u32 plogo_src_fcid[5];
345 bool plogo_src_fcid_set[5];
346 struct qed_mfw_tlv_time plogo_tstamp[5];
358 bool rx_abts_acc_set;
360 bool rx_abts_rjt_set;
361 u32 abts_dst_fcid[5];
362 bool abts_dst_fcid_set[5];
363 struct qed_mfw_tlv_time abts_tstamp[5];
366 u32 rx_rscn_nport[4];
367 bool rx_rscn_nport_set[4];
371 bool abort_task_sets_set;
395 bool scsi_cond_met_set;
400 u8 scsi_inter_cond_met;
401 bool scsi_inter_cond_met_set;
402 u8 scsi_rsv_conflicts;
403 bool scsi_rsv_conflicts_set;
405 bool scsi_tsk_full_set;
407 bool scsi_aca_active_set;
409 bool scsi_tsk_abort_set;
411 bool scsi_rx_chk_set[5];
412 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
415 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
416 (void __iomem *)(reg_addr))
418 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
420 #define QED_COALESCE_MAX 0x1FF
421 #define QED_DEFAULT_RX_USECS 12
422 #define QED_DEFAULT_TX_USECS 48
427 struct qed_eth_pf_params {
428 /* The following parameters are used during HW-init
429 * and these parameters need to be passed as arguments
430 * to update_pf_params routine invoked before slowpath start
434 /* per-VF number of CIDs */
436 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
438 /* To enable arfs, previous to HW-init a positive number needs to be
439 * set [as filters require allocated searcher ILT memory].
440 * This will set the maximal number of configured steering-filters.
442 u32 num_arfs_filters;
445 struct qed_fcoe_pf_params {
446 /* The following parameters are used during protocol-init */
447 u64 glbl_q_params_addr;
448 u64 bdq_pbl_base_addr[2];
450 /* The following parameters are used during HW-init
451 * and these parameters need to be passed as arguments
452 * to update_pf_params routine invoked before slowpath start
457 /* The following parameters are used during protocol-init */
458 u16 sq_num_pbl_pages;
461 u16 cmdq_num_entries;
462 u16 rq_buffer_log_size;
465 u16 bdq_xoff_threshold[2];
466 u16 bdq_xon_threshold[2];
468 u8 num_cqs; /* num of global CQs */
474 u8 bdq_pbl_num_entries[2];
477 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
478 struct qed_iscsi_pf_params {
479 u64 glbl_q_params_addr;
480 u64 bdq_pbl_base_addr[3];
482 u16 cmdq_num_entries;
486 /* The following parameters are used during HW-init
487 * and these parameters need to be passed as arguments
488 * to update_pf_params routine invoked before slowpath start
493 /* The following parameters are used during protocol-init */
494 u16 half_way_close_timeout;
495 u16 bdq_xoff_threshold[3];
496 u16 bdq_xon_threshold[3];
497 u16 cmdq_xoff_threshold;
498 u16 cmdq_xon_threshold;
501 u8 num_sq_pages_in_ring;
502 u8 num_r2tq_pages_in_ring;
503 u8 num_uhq_pages_in_ring;
515 u8 soc_num_of_blocks_log;
516 u8 bdq_pbl_num_entries[3];
519 struct qed_rdma_pf_params {
520 /* Supplied to QED during resource allocation (may affect the ILT and
523 u32 min_dpis; /* number of requested DPIs */
524 u32 num_qps; /* number of requested Queue Pairs */
525 u32 num_srqs; /* number of requested SRQ */
526 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
527 u8 gl_pi; /* protocol index */
529 /* Will allocate rate limiters to be used with QPs */
533 struct qed_pf_params {
534 struct qed_eth_pf_params eth_pf_params;
535 struct qed_fcoe_pf_params fcoe_pf_params;
536 struct qed_iscsi_pf_params iscsi_pf_params;
537 struct qed_rdma_pf_params rdma_pf_params;
548 struct status_block_e4 *sb_virt;
550 u32 sb_ack; /* Last given ack */
552 void __iomem *igu_addr;
554 #define QED_SB_INFO_INIT 0x1
555 #define QED_SB_INFO_SETUP 0x2
557 struct qed_dev *cdev;
565 struct qed_dev_info {
566 unsigned long pci_mem_start;
567 unsigned long pci_mem_end;
568 unsigned int pci_irq;
581 #define QED_MFW_VERSION_0_MASK 0x000000FF
582 #define QED_MFW_VERSION_0_OFFSET 0
583 #define QED_MFW_VERSION_1_MASK 0x0000FF00
584 #define QED_MFW_VERSION_1_OFFSET 8
585 #define QED_MFW_VERSION_2_MASK 0x00FF0000
586 #define QED_MFW_VERSION_2_OFFSET 16
587 #define QED_MFW_VERSION_3_MASK 0xFF000000
588 #define QED_MFW_VERSION_3_OFFSET 24
591 bool b_inter_pf_switch;
600 #define QED_MBI_VERSION_0_MASK 0x000000FF
601 #define QED_MBI_VERSION_0_OFFSET 0
602 #define QED_MBI_VERSION_1_MASK 0x0000FF00
603 #define QED_MBI_VERSION_1_OFFSET 8
604 #define QED_MBI_VERSION_2_MASK 0x00FF0000
605 #define QED_MBI_VERSION_2_OFFSET 16
607 enum qed_dev_type dev_type;
609 /* Output parameters for qede */
618 QED_SB_TYPE_L2_QUEUE,
629 enum qed_link_mode_bits {
630 QED_LM_FIBRE_BIT = BIT(0),
631 QED_LM_Autoneg_BIT = BIT(1),
632 QED_LM_Asym_Pause_BIT = BIT(2),
633 QED_LM_Pause_BIT = BIT(3),
634 QED_LM_1000baseT_Half_BIT = BIT(4),
635 QED_LM_1000baseT_Full_BIT = BIT(5),
636 QED_LM_10000baseKR_Full_BIT = BIT(6),
637 QED_LM_25000baseKR_Full_BIT = BIT(7),
638 QED_LM_40000baseLR4_Full_BIT = BIT(8),
639 QED_LM_50000baseKR2_Full_BIT = BIT(9),
640 QED_LM_100000baseKR4_Full_BIT = BIT(10),
644 struct qed_link_params {
647 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
648 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
649 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
650 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
651 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
652 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
657 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
658 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
659 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
661 #define QED_LINK_LOOPBACK_NONE BIT(0)
662 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
663 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
664 #define QED_LINK_LOOPBACK_EXT BIT(3)
665 #define QED_LINK_LOOPBACK_MAC BIT(4)
667 struct qed_link_eee_params eee;
670 struct qed_link_output {
673 /* In QED_LM_* defs */
678 u32 speed; /* In Mb/s */
679 u8 duplex; /* In DUPLEX defs */
680 u8 port; /* In PORT defs */
684 /* EEE - capability & param */
688 struct qed_link_eee_params eee;
691 struct qed_probe_params {
692 enum qed_protocol protocol;
698 #define QED_DRV_VER_STR_SIZE 12
699 struct qed_slowpath_params {
705 u8 name[QED_DRV_VER_STR_SIZE];
708 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
710 struct qed_int_info {
711 struct msix_entry *msix;
714 /* This should be updated by the protocol driver */
718 #define QED_NVM_SIGNATURE 0x12435687
720 enum qed_nvm_flash_cmd {
721 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
722 QED_NVM_FLASH_CMD_FILE_START = 0x3,
723 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
724 QED_NVM_FLASH_CMD_NVM_MAX,
727 struct qed_common_cb_ops {
728 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
729 void (*link_update)(void *dev,
730 struct qed_link_output *link);
731 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
734 struct qed_selftest_ops {
736 * @brief selftest_interrupt - Perform interrupt test
740 * @return 0 on success, error otherwise.
742 int (*selftest_interrupt)(struct qed_dev *cdev);
745 * @brief selftest_memory - Perform memory test
749 * @return 0 on success, error otherwise.
751 int (*selftest_memory)(struct qed_dev *cdev);
754 * @brief selftest_register - Perform register test
758 * @return 0 on success, error otherwise.
760 int (*selftest_register)(struct qed_dev *cdev);
763 * @brief selftest_clock - Perform clock test
767 * @return 0 on success, error otherwise.
769 int (*selftest_clock)(struct qed_dev *cdev);
772 * @brief selftest_nvram - Perform nvram test
776 * @return 0 on success, error otherwise.
778 int (*selftest_nvram) (struct qed_dev *cdev);
781 struct qed_common_ops {
782 struct qed_selftest_ops *selftest;
784 struct qed_dev* (*probe)(struct pci_dev *dev,
785 struct qed_probe_params *params);
787 void (*remove)(struct qed_dev *cdev);
789 int (*set_power_state)(struct qed_dev *cdev,
792 void (*set_name) (struct qed_dev *cdev, char name[]);
794 /* Client drivers need to make this call before slowpath_start.
795 * PF params required for the call before slowpath_start is
796 * documented within the qed_pf_params structure definition.
798 void (*update_pf_params)(struct qed_dev *cdev,
799 struct qed_pf_params *params);
800 int (*slowpath_start)(struct qed_dev *cdev,
801 struct qed_slowpath_params *params);
803 int (*slowpath_stop)(struct qed_dev *cdev);
805 /* Requests to use `cnt' interrupts for fastpath.
806 * upon success, returns number of interrupts allocated for fastpath.
808 int (*set_fp_int)(struct qed_dev *cdev,
811 /* Fills `info' with pointers required for utilizing interrupts */
812 int (*get_fp_int)(struct qed_dev *cdev,
813 struct qed_int_info *info);
815 u32 (*sb_init)(struct qed_dev *cdev,
816 struct qed_sb_info *sb_info,
818 dma_addr_t sb_phy_addr,
820 enum qed_sb_type type);
822 u32 (*sb_release)(struct qed_dev *cdev,
823 struct qed_sb_info *sb_info,
826 void (*simd_handler_config)(struct qed_dev *cdev,
829 void (*handler)(void *));
831 void (*simd_handler_clean)(struct qed_dev *cdev,
833 int (*dbg_grc)(struct qed_dev *cdev,
834 void *buffer, u32 *num_dumped_bytes);
836 int (*dbg_grc_size)(struct qed_dev *cdev);
838 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
840 int (*dbg_all_data_size) (struct qed_dev *cdev);
843 * @brief can_link_change - can the instance change the link or not
847 * @return true if link-change is allowed, false otherwise.
849 bool (*can_link_change)(struct qed_dev *cdev);
852 * @brief set_link - set links according to params
855 * @param params - values used to override the default link configuration
857 * @return 0 on success, error otherwise.
859 int (*set_link)(struct qed_dev *cdev,
860 struct qed_link_params *params);
863 * @brief get_link - returns the current link state.
866 * @param if_link - structure to be filled with current link configuration.
868 void (*get_link)(struct qed_dev *cdev,
869 struct qed_link_output *if_link);
872 * @brief - drains chip in case Tx completions fail to arrive due to pause.
876 int (*drain)(struct qed_dev *cdev);
879 * @brief update_msglvl - update module debug level
885 void (*update_msglvl)(struct qed_dev *cdev,
889 int (*chain_alloc)(struct qed_dev *cdev,
890 enum qed_chain_use_mode intended_use,
891 enum qed_chain_mode mode,
892 enum qed_chain_cnt_type cnt_type,
895 struct qed_chain *p_chain,
896 struct qed_chain_ext_pbl *ext_pbl);
898 void (*chain_free)(struct qed_dev *cdev,
899 struct qed_chain *p_chain);
902 * @brief nvm_flash - Flash nvm data.
905 * @param name - file containing the data
907 * @return 0 on success, error otherwise.
909 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
912 * @brief nvm_get_image - reads an entire image from nvram
915 * @param type - type of the request nvram image
916 * @param buf - preallocated buffer to fill with the image
917 * @param len - length of the allocated buffer
919 * @return 0 on success, error otherwise
921 int (*nvm_get_image)(struct qed_dev *cdev,
922 enum qed_nvm_images type, u8 *buf, u16 len);
925 * @brief set_coalesce - Configure Rx coalesce value in usec
928 * @param rx_coal - Rx coalesce value in usec
929 * @param tx_coal - Tx coalesce value in usec
930 * @param qid - Queue index
931 * @param sb_id - Status Block Id
933 * @return 0 on success, error otherwise.
935 int (*set_coalesce)(struct qed_dev *cdev,
936 u16 rx_coal, u16 tx_coal, void *handle);
939 * @brief set_led - Configure LED mode
942 * @param mode - LED mode
944 * @return 0 on success, error otherwise.
946 int (*set_led)(struct qed_dev *cdev,
947 enum qed_led_mode mode);
950 * @brief update_drv_state - API to inform the change in the driver state.
956 int (*update_drv_state)(struct qed_dev *cdev, bool active);
959 * @brief update_mac - API to inform the change in the mac address
965 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
968 * @brief update_mtu - API to inform the change in the mtu
974 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
977 * @brief update_wol - update of changes in the WoL configuration
980 * @param enabled - true iff WoL should be enabled.
982 int (*update_wol) (struct qed_dev *cdev, bool enabled);
985 #define MASK_FIELD(_name, _value) \
986 ((_value) &= (_name ## _MASK))
988 #define FIELD_VALUE(_name, _value) \
989 ((_value & _name ## _MASK) << _name ## _SHIFT)
991 #define SET_FIELD(value, name, flag) \
993 (value) &= ~(name ## _MASK << name ## _SHIFT); \
994 (value) |= (((u64)flag) << (name ## _SHIFT)); \
997 #define GET_FIELD(value, name) \
998 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1000 /* Debug print definitions */
1001 #define DP_ERR(cdev, fmt, ...) \
1003 pr_err("[%s:%d(%s)]" fmt, \
1004 __func__, __LINE__, \
1005 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1009 #define DP_NOTICE(cdev, fmt, ...) \
1011 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1012 pr_notice("[%s:%d(%s)]" fmt, \
1013 __func__, __LINE__, \
1014 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1020 #define DP_INFO(cdev, fmt, ...) \
1022 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1023 pr_notice("[%s:%d(%s)]" fmt, \
1024 __func__, __LINE__, \
1025 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1030 #define DP_VERBOSE(cdev, module, fmt, ...) \
1032 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1033 ((cdev)->dp_module & module))) { \
1034 pr_notice("[%s:%d(%s)]" fmt, \
1035 __func__, __LINE__, \
1036 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1042 QED_LEVEL_VERBOSE = 0x0,
1043 QED_LEVEL_INFO = 0x1,
1044 QED_LEVEL_NOTICE = 0x2,
1045 QED_LEVEL_ERR = 0x3,
1048 #define QED_LOG_LEVEL_SHIFT (30)
1049 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
1050 #define QED_LOG_INFO_MASK (0x40000000)
1051 #define QED_LOG_NOTICE_MASK (0x80000000)
1054 QED_MSG_SPQ = 0x10000,
1055 QED_MSG_STATS = 0x20000,
1056 QED_MSG_DCB = 0x40000,
1057 QED_MSG_IOV = 0x80000,
1058 QED_MSG_SP = 0x100000,
1059 QED_MSG_STORAGE = 0x200000,
1060 QED_MSG_CXT = 0x800000,
1061 QED_MSG_LL2 = 0x1000000,
1062 QED_MSG_ILT = 0x2000000,
1063 QED_MSG_RDMA = 0x4000000,
1064 QED_MSG_DEBUG = 0x8000000,
1065 /* to be added...up to 0x8000000 */
1074 struct qed_eth_stats_common {
1075 u64 no_buff_discards;
1076 u64 packet_too_big_discard;
1084 u64 mftag_filter_discards;
1085 u64 mac_filter_discards;
1092 u64 tx_err_drop_pkts;
1093 u64 tpa_coalesced_pkts;
1094 u64 tpa_coalesced_events;
1096 u64 tpa_not_coalesced_pkts;
1097 u64 tpa_coalesced_bytes;
1100 u64 rx_64_byte_packets;
1101 u64 rx_65_to_127_byte_packets;
1102 u64 rx_128_to_255_byte_packets;
1103 u64 rx_256_to_511_byte_packets;
1104 u64 rx_512_to_1023_byte_packets;
1105 u64 rx_1024_to_1518_byte_packets;
1107 u64 rx_mac_crtl_frames;
1108 u64 rx_pause_frames;
1110 u64 rx_align_errors;
1111 u64 rx_carrier_errors;
1112 u64 rx_oversize_packets;
1114 u64 rx_undersize_packets;
1116 u64 tx_64_byte_packets;
1117 u64 tx_65_to_127_byte_packets;
1118 u64 tx_128_to_255_byte_packets;
1119 u64 tx_256_to_511_byte_packets;
1120 u64 tx_512_to_1023_byte_packets;
1121 u64 tx_1024_to_1518_byte_packets;
1122 u64 tx_pause_frames;
1127 u64 rx_mac_uc_packets;
1128 u64 rx_mac_mc_packets;
1129 u64 rx_mac_bc_packets;
1130 u64 rx_mac_frames_ok;
1132 u64 tx_mac_uc_packets;
1133 u64 tx_mac_mc_packets;
1134 u64 tx_mac_bc_packets;
1135 u64 tx_mac_ctrl_frames;
1138 struct qed_eth_stats_bb {
1139 u64 rx_1519_to_1522_byte_packets;
1140 u64 rx_1519_to_2047_byte_packets;
1141 u64 rx_2048_to_4095_byte_packets;
1142 u64 rx_4096_to_9216_byte_packets;
1143 u64 rx_9217_to_16383_byte_packets;
1144 u64 tx_1519_to_2047_byte_packets;
1145 u64 tx_2048_to_4095_byte_packets;
1146 u64 tx_4096_to_9216_byte_packets;
1147 u64 tx_9217_to_16383_byte_packets;
1148 u64 tx_lpi_entry_count;
1149 u64 tx_total_collisions;
1152 struct qed_eth_stats_ah {
1153 u64 rx_1519_to_max_byte_packets;
1154 u64 tx_1519_to_max_byte_packets;
1157 struct qed_eth_stats {
1158 struct qed_eth_stats_common common;
1161 struct qed_eth_stats_bb bb;
1162 struct qed_eth_stats_ah ah;
1166 #define QED_SB_IDX 0x0002
1169 #define TX_PI(tc) (RX_PI + 1 + tc)
1171 struct qed_sb_cnt_info {
1172 /* Original, current, and free SBs for PF */
1177 /* Original, current and free SBS for child VFs */
1183 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1188 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1189 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1190 if (sb_info->sb_ack != prod) {
1191 sb_info->sb_ack = prod;
1202 * @brief This function creates an update command for interrupts that is
1203 * written to the IGU.
1205 * @param sb_info - This is the structure allocated and
1206 * initialized per status block. Assumption is
1207 * that it was initialized using qed_sb_init
1208 * @param int_cmd - Enable/Disable/Nop
1209 * @param upd_flg - whether igu consumer should be
1212 * @return inline void
1214 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1215 enum igu_int_cmd int_cmd,
1218 struct igu_prod_cons_update igu_ack = { 0 };
1220 igu_ack.sb_id_and_flags =
1221 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1222 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1223 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1224 (IGU_SEG_ACCESS_REG <<
1225 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1227 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
1229 /* Both segments (interrupts & acks) are written to same place address;
1230 * Need to guarantee all commands will be received (in-order) by HW.
1236 static inline void __internal_ram_wr(void *p_hwfn,
1244 for (i = 0; i < size / sizeof(*data); i++)
1245 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1248 static inline void internal_ram_wr(void __iomem *addr,
1252 __internal_ram_wr(NULL, addr, size, data);
1258 QED_RSS_IPV4_TCP = 0x4,
1259 QED_RSS_IPV6_TCP = 0x8,
1260 QED_RSS_IPV4_UDP = 0x10,
1261 QED_RSS_IPV6_UDP = 0x20,
1264 #define QED_RSS_IND_TABLE_SIZE 128
1265 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */