1 //==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineMemOperand class, which is a
11 // description of a memory reference. It is used to help track dependencies
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
17 #define LLVM_CODEGEN_MACHINEMEMOPERAND_H
19 #include "llvm/ADT/BitmaskEnum.h"
20 #include "llvm/ADT/PointerUnion.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/IR/Instructions.h"
23 #include "llvm/IR/Metadata.h"
24 #include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
25 #include "llvm/Support/AtomicOrdering.h"
26 #include "llvm/Support/DataTypes.h"
30 class FoldingSetNodeID;
33 class MachineFunction;
34 class ModuleSlotTracker;
36 /// This class contains a discriminated union of information about pointers in
37 /// memory operands, relating them back to LLVM IR or to virtual locations (such
38 /// as frame indices) that are exposed during codegen.
39 struct MachinePointerInfo {
40 /// This is the IR pointer value for the access, or it is null if unknown.
41 /// If this is null, then the access is to a pointer in the default address
43 PointerUnion<const Value *, const PseudoSourceValue *> V;
45 /// Offset - This is an offset from the base Value*.
52 explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
54 : V(v), Offset(offset), StackID(ID) {
55 AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0;
58 explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0,
60 : V(v), Offset(offset), StackID(ID) {
61 AddrSpace = v ? v->getAddressSpace() : 0;
64 explicit MachinePointerInfo(unsigned AddressSpace = 0)
65 : V((const Value *)nullptr), Offset(0), StackID(0),
66 AddrSpace(AddressSpace) {}
68 MachinePointerInfo getWithOffset(int64_t O) const {
70 return MachinePointerInfo(AddrSpace);
71 if (V.is<const Value*>())
72 return MachinePointerInfo(V.get<const Value*>(), Offset+O, StackID);
73 return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset+O,
77 /// Return true if memory region [V, V+Offset+Size) is known to be
79 bool isDereferenceable(unsigned Size, LLVMContext &C,
80 const DataLayout &DL) const;
82 /// Return the LLVM IR address space number that this pointer points into.
83 unsigned getAddrSpace() const;
85 /// Return a MachinePointerInfo record that refers to the constant pool.
86 static MachinePointerInfo getConstantPool(MachineFunction &MF);
88 /// Return a MachinePointerInfo record that refers to the specified
90 static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI,
93 /// Return a MachinePointerInfo record that refers to a jump table entry.
94 static MachinePointerInfo getJumpTable(MachineFunction &MF);
96 /// Return a MachinePointerInfo record that refers to a GOT entry.
97 static MachinePointerInfo getGOT(MachineFunction &MF);
99 /// Stack pointer relative access.
100 static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset,
103 /// Stack memory without other information.
104 static MachinePointerInfo getUnknownStack(MachineFunction &MF);
108 //===----------------------------------------------------------------------===//
109 /// A description of a memory reference used in the backend.
110 /// Instead of holding a StoreInst or LoadInst, this class holds the address
111 /// Value of the reference along with a byte size and offset. This allows it
112 /// to describe lowered loads and stores. Also, the special PseudoSourceValue
113 /// objects can be used to represent loads and stores to memory locations
114 /// that aren't explicit in the regular LLVM IR.
116 class MachineMemOperand {
118 /// Flags values. These may be or'd together.
119 enum Flags : uint16_t {
122 /// The memory access reads data.
124 /// The memory access writes data.
126 /// The memory access is volatile.
127 MOVolatile = 1u << 2,
128 /// The memory access is non-temporal.
129 MONonTemporal = 1u << 3,
130 /// The memory access is dereferenceable (i.e., doesn't trap).
131 MODereferenceable = 1u << 4,
132 /// The memory access always returns the same value (or traps).
133 MOInvariant = 1u << 5,
135 // Reserved for use by target-specific passes.
136 // Targets may override getSerializableMachineMemOperandTargetFlags() to
137 // enable MIR serialization/parsing of these flags. If more of these flags
138 // are added, the MIR printing/parsing code will need to be updated as well.
139 MOTargetFlag1 = 1u << 6,
140 MOTargetFlag2 = 1u << 7,
141 MOTargetFlag3 = 1u << 8,
143 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
147 /// Atomic information for this memory operation.
148 struct MachineAtomicInfo {
149 /// Synchronization scope ID for this memory operation.
150 unsigned SSID : 8; // SyncScope::ID
151 /// Atomic ordering requirements for this memory operation. For cmpxchg
152 /// atomic operations, atomic ordering requirements when store occurs.
153 unsigned Ordering : 4; // enum AtomicOrdering
154 /// For cmpxchg atomic operations, atomic ordering requirements when store
156 unsigned FailureOrdering : 4; // enum AtomicOrdering
159 MachinePointerInfo PtrInfo;
162 uint16_t BaseAlignLog2; // log_2(base_alignment) + 1
163 MachineAtomicInfo AtomicInfo;
165 const MDNode *Ranges;
168 /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
169 /// size, and base alignment. For atomic operations the synchronization scope
170 /// and atomic ordering requirements must also be specified. For cmpxchg
171 /// atomic operations the atomic ordering requirements when store does not
172 /// occur must also be specified.
173 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
174 unsigned base_alignment,
175 const AAMDNodes &AAInfo = AAMDNodes(),
176 const MDNode *Ranges = nullptr,
177 SyncScope::ID SSID = SyncScope::System,
178 AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
179 AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
181 const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
183 /// Return the base address of the memory access. This may either be a normal
184 /// LLVM IR Value, or one of the special values used in CodeGen.
185 /// Special values are those obtained via
186 /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
187 /// other PseudoSourceValue member functions which return objects which stand
188 /// for frame/stack pointer relative references and other special references
189 /// which are not representable in the high-level IR.
190 const Value *getValue() const { return PtrInfo.V.dyn_cast<const Value*>(); }
192 const PseudoSourceValue *getPseudoValue() const {
193 return PtrInfo.V.dyn_cast<const PseudoSourceValue*>();
196 const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
198 /// Return the raw flags of the source value, \see Flags.
199 Flags getFlags() const { return FlagVals; }
201 /// Bitwise OR the current flags with the given flags.
202 void setFlags(Flags f) { FlagVals |= f; }
204 /// For normal values, this is a byte offset added to the base address.
205 /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
206 int64_t getOffset() const { return PtrInfo.Offset; }
208 unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
210 /// Return the size in bytes of the memory reference.
211 uint64_t getSize() const { return Size; }
213 /// Return the minimum known alignment in bytes of the actual memory
215 uint64_t getAlignment() const;
217 /// Return the minimum known alignment in bytes of the base address, without
219 uint64_t getBaseAlignment() const { return (1u << BaseAlignLog2) >> 1; }
221 /// Return the AA tags for the memory reference.
222 AAMDNodes getAAInfo() const { return AAInfo; }
224 /// Return the range tag for the memory reference.
225 const MDNode *getRanges() const { return Ranges; }
227 /// Returns the synchronization scope ID for this memory operation.
228 SyncScope::ID getSyncScopeID() const {
229 return static_cast<SyncScope::ID>(AtomicInfo.SSID);
232 /// Return the atomic ordering requirements for this memory operation. For
233 /// cmpxchg atomic operations, return the atomic ordering requirements when
235 AtomicOrdering getOrdering() const {
236 return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
239 /// For cmpxchg atomic operations, return the atomic ordering requirements
240 /// when store does not occur.
241 AtomicOrdering getFailureOrdering() const {
242 return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
245 bool isLoad() const { return FlagVals & MOLoad; }
246 bool isStore() const { return FlagVals & MOStore; }
247 bool isVolatile() const { return FlagVals & MOVolatile; }
248 bool isNonTemporal() const { return FlagVals & MONonTemporal; }
249 bool isDereferenceable() const { return FlagVals & MODereferenceable; }
250 bool isInvariant() const { return FlagVals & MOInvariant; }
252 /// Returns true if this operation has an atomic ordering requirement of
253 /// unordered or higher, false otherwise.
254 bool isAtomic() const { return getOrdering() != AtomicOrdering::NotAtomic; }
256 /// Returns true if this memory operation doesn't have any ordering
257 /// constraints other than normal aliasing. Volatile and atomic memory
258 /// operations can't be reordered.
260 /// Currently, we don't model the difference between volatile and atomic
261 /// operations. They should retain their ordering relative to all memory
263 bool isUnordered() const { return !isVolatile(); }
265 /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
266 /// greater alignment. This must only be used when the new alignment applies
267 /// to all users of this MachineMemOperand.
268 void refineAlignment(const MachineMemOperand *MMO);
270 /// Change the SourceValue for this MachineMemOperand. This should only be
271 /// used when an object is being relocated and all references to it are being
273 void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
274 void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
275 void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
277 /// Profile - Gather unique data for the object.
279 void Profile(FoldingSetNodeID &ID) const;
281 /// Support for operator<<.
283 void print(raw_ostream &OS) const;
284 void print(raw_ostream &OS, ModuleSlotTracker &MST) const;
287 friend bool operator==(const MachineMemOperand &LHS,
288 const MachineMemOperand &RHS) {
289 return LHS.getValue() == RHS.getValue() &&
290 LHS.getPseudoValue() == RHS.getPseudoValue() &&
291 LHS.getSize() == RHS.getSize() &&
292 LHS.getOffset() == RHS.getOffset() &&
293 LHS.getFlags() == RHS.getFlags() &&
294 LHS.getAAInfo() == RHS.getAAInfo() &&
295 LHS.getRanges() == RHS.getRanges() &&
296 LHS.getAlignment() == RHS.getAlignment() &&
297 LHS.getAddrSpace() == RHS.getAddrSpace();
300 friend bool operator!=(const MachineMemOperand &LHS,
301 const MachineMemOperand &RHS) {
302 return !(LHS == RHS);
306 inline raw_ostream &operator<<(raw_ostream &OS, const MachineMemOperand &MRO) {
311 } // End llvm namespace