1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
24 #define LLVM_CODEGEN_TARGETLOWERING_H
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/StringRef.h"
32 #include "llvm/Analysis/DivergenceAnalysis.h"
33 #include "llvm/CodeGen/DAGCombine.h"
34 #include "llvm/CodeGen/ISDOpcodes.h"
35 #include "llvm/CodeGen/MachineValueType.h"
36 #include "llvm/CodeGen/RuntimeLibcalls.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/CodeGen/SelectionDAGNodes.h"
39 #include "llvm/CodeGen/TargetCallingConv.h"
40 #include "llvm/CodeGen/ValueTypes.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/CallSite.h"
43 #include "llvm/IR/CallingConv.h"
44 #include "llvm/IR/DataLayout.h"
45 #include "llvm/IR/DerivedTypes.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/IRBuilder.h"
48 #include "llvm/IR/InlineAsm.h"
49 #include "llvm/IR/Instruction.h"
50 #include "llvm/IR/Instructions.h"
51 #include "llvm/IR/Type.h"
52 #include "llvm/MC/MCRegisterInfo.h"
53 #include "llvm/Support/AtomicOrdering.h"
54 #include "llvm/Support/Casting.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Target/TargetMachine.h"
69 class BranchProbability;
74 class FunctionLoweringInfo;
79 class MachineBasicBlock;
80 class MachineFunction;
82 class MachineJumpTableInfo;
84 class MachineRegisterInfo;
88 class TargetRegisterClass;
89 class TargetLibraryInfo;
90 class TargetRegisterInfo;
96 None, // No preference
97 Source, // Follow source order.
98 RegPressure, // Scheduling for lowest register pressure.
99 Hybrid, // Scheduling for both latency and register pressure.
100 ILP, // Scheduling for ILP in low register pressure mode.
101 VLIW // Scheduling for VLIW targets.
104 } // end namespace Sched
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
108 class TargetLoweringBase {
110 /// This enum indicates whether operations are valid for a target, and if not,
111 /// what action should be used to make them valid.
112 enum LegalizeAction : uint8_t {
113 Legal, // The target natively supports this operation.
114 Promote, // This operation should be executed in a larger type.
115 Expand, // Try to expand this to other ops, otherwise use a libcall.
116 LibCall, // Don't try to expand this to other ops, always use a libcall.
117 Custom // Use the LowerOperation hook to implement custom lowering.
120 /// This enum indicates whether a types are legal for a target, and if not,
121 /// what action should be used to make them valid.
122 enum LegalizeTypeAction : uint8_t {
123 TypeLegal, // The target natively supports this type.
124 TypePromoteInteger, // Replace this integer with a larger one.
125 TypeExpandInteger, // Split this integer into two of half the size.
126 TypeSoftenFloat, // Convert this float to a same size integer type,
127 // if an operation is not supported in target HW.
128 TypeExpandFloat, // Split this float into two of half the size.
129 TypeScalarizeVector, // Replace this one-element vector with its element.
130 TypeSplitVector, // Split this vector into two of half the size.
131 TypeWidenVector, // This vector should be widened into a larger vector.
132 TypePromoteFloat // Replace this float with a larger one.
135 /// LegalizeKind holds the legalization kind that needs to happen to EVT
136 /// in order to type-legalize it.
137 using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
139 /// Enum that describes how the target represents true/false values.
140 enum BooleanContent {
141 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
146 /// Enum that describes what type of support for selects the target has.
147 enum SelectSupportKind {
148 ScalarValSelect, // The target supports scalar selects (ex: cmov).
149 ScalarCondVectorVal, // The target supports selects with a scalar condition
150 // and vector values (ex: cmov).
151 VectorMaskSelect // The target supports vector selects with a vector
152 // mask (ex: x86 blends).
155 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156 /// to, if at all. Exists because different targets have different levels of
157 /// support for these atomic instructions, and also have different options
158 /// w.r.t. what they should expand to.
159 enum class AtomicExpansionKind {
160 None, // Don't expand the instruction.
161 LLSC, // Expand the instruction into loadlinked/storeconditional; used
163 LLOnly, // Expand the (load) instruction into just a load-linked, which has
164 // greater atomic guarantees than a normal load.
165 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
168 /// Enum that specifies when a multiplication should be expanded.
169 enum class MulExpansionKind {
170 Always, // Always expand the instruction.
171 OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
177 Value *Val = nullptr;
178 SDValue Node = SDValue();
188 bool IsSwiftSelf : 1;
189 bool IsSwiftError : 1;
190 uint16_t Alignment = 0;
193 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194 IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195 IsSwiftSelf(false), IsSwiftError(false) {}
197 void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
199 using ArgListTy = std::vector<ArgListEntry>;
201 virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
202 ArgListTy &Args) const {};
204 static ISD::NodeType getExtendForContent(BooleanContent Content) {
206 case UndefinedBooleanContent:
207 // Extend by adding rubbish bits.
208 return ISD::ANY_EXTEND;
209 case ZeroOrOneBooleanContent:
210 // Extend by adding zero bits.
211 return ISD::ZERO_EXTEND;
212 case ZeroOrNegativeOneBooleanContent:
213 // Extend by copying the sign bit.
214 return ISD::SIGN_EXTEND;
216 llvm_unreachable("Invalid content kind");
219 /// NOTE: The TargetMachine owns TLOF.
220 explicit TargetLoweringBase(const TargetMachine &TM);
221 TargetLoweringBase(const TargetLoweringBase &) = delete;
222 TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
223 virtual ~TargetLoweringBase() = default;
226 /// \brief Initialize all of the actions to default values.
230 const TargetMachine &getTargetMachine() const { return TM; }
232 virtual bool useSoftFloat() const { return false; }
234 /// Return the pointer type for the given address space, defaults to
235 /// the pointer type from the data layout.
236 /// FIXME: The default needs to be removed once all the code is updated.
237 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
238 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
241 /// Return the type for frame index, which is determined by
242 /// the alloca address space specified through the data layout.
243 MVT getFrameIndexTy(const DataLayout &DL) const {
244 return getPointerTy(DL, DL.getAllocaAddrSpace());
247 /// Return the type for operands of fence.
248 /// TODO: Let fence operands be of i32 type and remove this.
249 virtual MVT getFenceOperandTy(const DataLayout &DL) const {
250 return getPointerTy(DL);
253 /// EVT is not used in-tree, but is used by out-of-tree target.
254 /// A documentation for this function would be nice...
255 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
257 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
258 bool LegalTypes = true) const;
260 /// Returns the type to be used for the index operand of:
261 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
262 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
263 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
264 return getPointerTy(DL);
267 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
271 /// Return true if multiple condition registers are available.
272 bool hasMultipleConditionRegisters() const {
273 return HasMultipleConditionRegisters;
276 /// Return true if the target has BitExtract instructions.
277 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
279 /// Return the preferred vector type legalization action.
280 virtual TargetLoweringBase::LegalizeTypeAction
281 getPreferredVectorAction(EVT VT) const {
282 // The default action for one element vectors is to scalarize
283 if (VT.getVectorNumElements() == 1)
284 return TypeScalarizeVector;
285 // The default action for other vectors is to promote
286 return TypePromoteInteger;
289 // There are two general methods for expanding a BUILD_VECTOR node:
290 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
292 // 2. Build the vector on the stack and then load it.
293 // If this function returns true, then method (1) will be used, subject to
294 // the constraint that all of the necessary shuffles are legal (as determined
295 // by isShuffleMaskLegal). If this function returns false, then method (2) is
296 // always used. The vector type, and the number of defined values, are
299 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
300 unsigned DefinedValues) const {
301 return DefinedValues < 3;
304 /// Return true if integer divide is usually cheaper than a sequence of
305 /// several shifts, adds, and multiplies for this target.
306 /// The definition of "cheaper" may depend on whether we're optimizing
307 /// for speed or for size.
308 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
310 /// Return true if the target can handle a standalone remainder operation.
311 virtual bool hasStandaloneRem(EVT VT) const {
315 /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
316 virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
317 // Default behavior is to replace SQRT(X) with X*RSQRT(X).
321 /// Reciprocal estimate status values used by the functions below.
322 enum ReciprocalEstimate : int {
328 /// Return a ReciprocalEstimate enum value for a square root of the given type
329 /// based on the function's attributes. If the operation is not overridden by
330 /// the function's attributes, "Unspecified" is returned and target defaults
331 /// are expected to be used for instruction selection.
332 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
334 /// Return a ReciprocalEstimate enum value for a division of the given type
335 /// based on the function's attributes. If the operation is not overridden by
336 /// the function's attributes, "Unspecified" is returned and target defaults
337 /// are expected to be used for instruction selection.
338 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
340 /// Return the refinement step count for a square root of the given type based
341 /// on the function's attributes. If the operation is not overridden by
342 /// the function's attributes, "Unspecified" is returned and target defaults
343 /// are expected to be used for instruction selection.
344 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
346 /// Return the refinement step count for a division of the given type based
347 /// on the function's attributes. If the operation is not overridden by
348 /// the function's attributes, "Unspecified" is returned and target defaults
349 /// are expected to be used for instruction selection.
350 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
352 /// Returns true if target has indicated at least one type should be bypassed.
353 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
355 /// Returns map of slow types for division or remainder with corresponding
357 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
358 return BypassSlowDivWidths;
361 /// Return true if Flow Control is an expensive operation that should be
363 bool isJumpExpensive() const { return JumpIsExpensive; }
365 /// Return true if selects are only cheaper than branches if the branch is
366 /// unlikely to be predicted right.
367 bool isPredictableSelectExpensive() const {
368 return PredictableSelectIsExpensive;
371 /// If a branch or a select condition is skewed in one direction by more than
372 /// this factor, it is very likely to be predicted correctly.
373 virtual BranchProbability getPredictableBranchThreshold() const;
375 /// Return true if the following transform is beneficial:
376 /// fold (conv (load x)) -> (load (conv*)x)
377 /// On architectures that don't natively support some vector loads
378 /// efficiently, casting the load to a smaller vector of larger types and
379 /// loading is more efficient, however, this can be undone by optimizations in
381 virtual bool isLoadBitCastBeneficial(EVT LoadVT,
382 EVT BitcastVT) const {
383 // Don't do if we could do an indexed load on the original type, but not on
385 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
388 MVT LoadMVT = LoadVT.getSimpleVT();
390 // Don't bother doing this if it's just going to be promoted again later, as
391 // doing so might interfere with other combines.
392 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
393 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
399 /// Return true if the following transform is beneficial:
400 /// (store (y (conv x)), y*)) -> (store x, (x*))
401 virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
402 // Default to the same logic as loads.
403 return isLoadBitCastBeneficial(StoreVT, BitcastVT);
406 /// Return true if it is expected to be cheaper to do a store of a non-zero
407 /// vector constant with the given size and type for the address space than to
408 /// store the individual scalar element constants.
409 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
411 unsigned AddrSpace) const {
415 /// Allow store merging after legalization in addition to before legalization.
416 /// This may catch stores that do not exist earlier (eg, stores created from
418 virtual bool mergeStoresAfterLegalization() const { return true; }
420 /// Returns if it's reasonable to merge stores to MemVT size.
421 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
422 const SelectionDAG &DAG) const {
426 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
427 virtual bool isCheapToSpeculateCttz() const {
431 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
432 virtual bool isCheapToSpeculateCtlz() const {
436 /// \brief Return true if ctlz instruction is fast.
437 virtual bool isCtlzFast() const {
441 /// Return true if it is safe to transform an integer-domain bitwise operation
442 /// into the equivalent floating-point operation. This should be set to true
443 /// if the target has IEEE-754-compliant fabs/fneg operations for the input
445 virtual bool hasBitPreservingFPLogic(EVT VT) const {
449 /// \brief Return true if it is cheaper to split the store of a merged int val
450 /// from a pair of smaller values into multiple stores.
451 virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
455 /// \brief Return if the target supports combining a
458 /// %andResult = and %val1, #mask
459 /// %icmpResult = icmp %andResult, 0
461 /// into a single machine instruction of a form like:
463 /// cc = test %register, #mask
465 virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
469 /// Use bitwise logic to make pairs of compares more efficient. For example:
470 /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
471 /// This should be true when it takes more than one instruction to lower
472 /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
473 /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
474 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
478 /// Return the preferred operand type if the target has a quick way to compare
479 /// integer values of the given size. Assume that any legal integer type can
480 /// be compared efficiently. Targets may override this to allow illegal wide
481 /// types to return a vector type if there is support to compare that type.
482 virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
483 MVT VT = MVT::getIntegerVT(NumBits);
484 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
487 /// Return true if the target should transform:
488 /// (X & Y) == Y ---> (~X & Y) == 0
489 /// (X & Y) != Y ---> (~X & Y) != 0
491 /// This may be profitable if the target has a bitwise and-not operation that
492 /// sets comparison flags. A target may want to limit the transformation based
493 /// on the type of Y or if Y is a constant.
495 /// Note that the transform will not occur if Y is known to be a power-of-2
496 /// because a mask and compare of a single bit can be handled by inverting the
497 /// predicate, for example:
498 /// (X & 8) == 8 ---> (X & 8) != 0
499 virtual bool hasAndNotCompare(SDValue Y) const {
503 /// Return true if the target has a bitwise and-not operation:
505 /// This can be used to simplify select or other instructions.
506 virtual bool hasAndNot(SDValue X) const {
507 // If the target has the more complex version of this operation, assume that
508 // it has this operation too.
509 return hasAndNotCompare(X);
512 /// \brief Return true if the target wants to use the optimization that
513 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
514 /// promotedInst1(...(promotedInstN(ext(load)))).
515 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
517 /// Return true if the target can combine store(extractelement VectorTy,
519 /// \p Cost[out] gives the cost of that transformation when this is true.
520 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
521 unsigned &Cost) const {
525 /// Return true if target supports floating point exceptions.
526 bool hasFloatingPointExceptions() const {
527 return HasFloatingPointExceptions;
530 /// Return true if target always beneficiates from combining into FMA for a
531 /// given value type. This must typically return false on targets where FMA
532 /// takes more cycles to execute than FADD.
533 virtual bool enableAggressiveFMAFusion(EVT VT) const {
537 /// Return the ValueType of the result of SETCC operations.
538 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
541 /// Return the ValueType for comparison libcalls. Comparions libcalls include
542 /// floating point comparion calls, and Ordered/Unordered check calls on
543 /// floating point numbers.
545 MVT::SimpleValueType getCmpLibcallReturnType() const;
547 /// For targets without i1 registers, this gives the nature of the high-bits
548 /// of boolean values held in types wider than i1.
550 /// "Boolean values" are special true/false values produced by nodes like
551 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
552 /// Not to be confused with general values promoted from i1. Some cpus
553 /// distinguish between vectors of boolean and scalars; the isVec parameter
554 /// selects between the two kinds. For example on X86 a scalar boolean should
555 /// be zero extended from i1, while the elements of a vector of booleans
556 /// should be sign extended from i1.
558 /// Some cpus also treat floating point types the same way as they treat
559 /// vectors instead of the way they treat scalars.
560 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
562 return BooleanVectorContents;
563 return isFloat ? BooleanFloatContents : BooleanContents;
566 BooleanContent getBooleanContents(EVT Type) const {
567 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
570 /// Return target scheduling preference.
571 Sched::Preference getSchedulingPreference() const {
572 return SchedPreferenceInfo;
575 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
576 /// for different nodes. This function returns the preference (or none) for
578 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
582 /// Return the register class that should be used for the specified value
584 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
585 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
586 assert(RC && "This value type is not natively supported!");
590 /// Return the 'representative' register class for the specified value
593 /// The 'representative' register class is the largest legal super-reg
594 /// register class for the register class of the value type. For example, on
595 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
596 /// register class is GR64 on x86_64.
597 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
598 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
602 /// Return the cost of the 'representative' register class for the specified
604 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
605 return RepRegClassCostForVT[VT.SimpleTy];
608 /// Return true if the target has native support for the specified value type.
609 /// This means that it has a register that directly holds it without
610 /// promotions or expansions.
611 bool isTypeLegal(EVT VT) const {
612 assert(!VT.isSimple() ||
613 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
614 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
617 class ValueTypeActionImpl {
618 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
619 /// that indicates how instruction selection should deal with the type.
620 LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
623 ValueTypeActionImpl() {
624 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
628 LegalizeTypeAction getTypeAction(MVT VT) const {
629 return ValueTypeActions[VT.SimpleTy];
632 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
633 ValueTypeActions[VT.SimpleTy] = Action;
637 const ValueTypeActionImpl &getValueTypeActions() const {
638 return ValueTypeActions;
641 /// Return how we should legalize values of this type, either it is already
642 /// legal (return 'Legal') or we need to promote it to a larger type (return
643 /// 'Promote'), or we need to expand it into multiple registers of smaller
644 /// integer type (return 'Expand'). 'Custom' is not an option.
645 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
646 return getTypeConversion(Context, VT).first;
648 LegalizeTypeAction getTypeAction(MVT VT) const {
649 return ValueTypeActions.getTypeAction(VT);
652 /// For types supported by the target, this is an identity function. For
653 /// types that must be promoted to larger types, this returns the larger type
654 /// to promote to. For integer types that are larger than the largest integer
655 /// register, this contains one step in the expansion to get to the smaller
656 /// register. For illegal floating point types, this returns the integer type
658 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
659 return getTypeConversion(Context, VT).second;
662 /// For types supported by the target, this is an identity function. For
663 /// types that must be expanded (i.e. integer types that are larger than the
664 /// largest integer register or illegal floating point types), this returns
665 /// the largest legal type it will be expanded to.
666 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
667 assert(!VT.isVector());
669 switch (getTypeAction(Context, VT)) {
672 case TypeExpandInteger:
673 VT = getTypeToTransformTo(Context, VT);
676 llvm_unreachable("Type is not legal nor is it to be expanded!");
681 /// Vector types are broken down into some number of legal first class types.
682 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
683 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
684 /// turns into 4 EVT::i32 values with both PPC and X86.
686 /// This method returns the number of registers needed, and the VT for each
687 /// register. It also returns the VT and quantity of the intermediate values
688 /// before they are promoted/expanded.
689 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
691 unsigned &NumIntermediates,
692 MVT &RegisterVT) const;
694 /// Certain targets such as MIPS require that some types such as vectors are
695 /// always broken down into scalars in some contexts. This occurs even if the
696 /// vector type is legal.
697 virtual unsigned getVectorTypeBreakdownForCallingConv(
698 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
699 unsigned &NumIntermediates, MVT &RegisterVT) const {
700 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
704 struct IntrinsicInfo {
705 unsigned opc = 0; // target opcode
706 EVT memVT; // memory VT
708 // value representing memory location
709 PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
711 int offset = 0; // offset off of ptrVal
712 unsigned size = 0; // the size of the memory location
713 // (taken from memVT if zero)
714 unsigned align = 1; // alignment
716 MachineMemOperand::Flags flags = MachineMemOperand::MONone;
717 IntrinsicInfo() = default;
720 /// Given an intrinsic, checks if on the target the intrinsic will need to map
721 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
722 /// true and store the intrinsic information into the IntrinsicInfo that was
723 /// passed to the function.
724 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
726 unsigned /*Intrinsic*/) const {
730 /// Returns true if the target can instruction select the specified FP
731 /// immediate natively. If false, the legalizer will materialize the FP
732 /// immediate as a load from a constant pool.
733 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
737 /// Targets can use this to indicate that they only support *some*
738 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
739 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
741 virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
745 /// Returns true if the operation can trap for the value type.
747 /// VT must be a legal type. By default, we optimistically assume most
748 /// operations don't trap except for integer divide and remainder.
749 virtual bool canOpTrap(unsigned Op, EVT VT) const;
751 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
752 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
753 /// a VAND with a constant pool entry.
754 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
759 /// Return how this operation should be treated: either it is legal, needs to
760 /// be promoted to a larger size, needs to be expanded to some other code
761 /// sequence, or the target has a custom expander for it.
762 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
763 if (VT.isExtended()) return Expand;
764 // If a target-specific SDNode requires legalization, require the target
765 // to provide custom legalization for it.
766 if (Op >= array_lengthof(OpActions[0])) return Custom;
767 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
770 /// Return true if the specified operation is legal on this target or can be
771 /// made legal with custom lowering. This is used to help guide high-level
772 /// lowering decisions.
773 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
774 return (VT == MVT::Other || isTypeLegal(VT)) &&
775 (getOperationAction(Op, VT) == Legal ||
776 getOperationAction(Op, VT) == Custom);
779 /// Return true if the specified operation is legal on this target or can be
780 /// made legal using promotion. This is used to help guide high-level lowering
782 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
783 return (VT == MVT::Other || isTypeLegal(VT)) &&
784 (getOperationAction(Op, VT) == Legal ||
785 getOperationAction(Op, VT) == Promote);
788 /// Return true if the specified operation is legal on this target or can be
789 /// made legal with custom lowering or using promotion. This is used to help
790 /// guide high-level lowering decisions.
791 bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
792 return (VT == MVT::Other || isTypeLegal(VT)) &&
793 (getOperationAction(Op, VT) == Legal ||
794 getOperationAction(Op, VT) == Custom ||
795 getOperationAction(Op, VT) == Promote);
798 /// Return true if the operation uses custom lowering, regardless of whether
799 /// the type is legal or not.
800 bool isOperationCustom(unsigned Op, EVT VT) const {
801 return getOperationAction(Op, VT) == Custom;
804 /// Return true if lowering to a jump table is allowed.
805 virtual bool areJTsAllowed(const Function *Fn) const {
806 if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
809 return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
810 isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
813 /// Check whether the range [Low,High] fits in a machine word.
814 bool rangeFitsInWord(const APInt &Low, const APInt &High,
815 const DataLayout &DL) const {
816 // FIXME: Using the pointer type doesn't seem ideal.
817 uint64_t BW = DL.getIndexSizeInBits(0u);
818 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
822 /// Return true if lowering to a jump table is suitable for a set of case
823 /// clusters which may contain \p NumCases cases, \p Range range of values.
824 /// FIXME: This function check the maximum table size and density, but the
825 /// minimum size is not checked. It would be nice if the minimum size is
826 /// also combined within this function. Currently, the minimum size check is
827 /// performed in findJumpTable() in SelectionDAGBuiler and
828 /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
829 virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
830 uint64_t Range) const {
831 const bool OptForSize = SI->getParent()->getParent()->optForSize();
832 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
833 const unsigned MaxJumpTableSize =
834 OptForSize || getMaximumJumpTableSize() == 0
836 : getMaximumJumpTableSize();
837 // Check whether a range of clusters is dense enough for a jump table.
838 if (Range <= MaxJumpTableSize &&
839 (NumCases * 100 >= Range * MinDensity)) {
845 /// Return true if lowering to a bit test is suitable for a set of case
846 /// clusters which contains \p NumDests unique destinations, \p Low and
847 /// \p High as its lowest and highest case values, and expects \p NumCmps
848 /// case value comparisons. Check if the number of destinations, comparison
849 /// metric, and range are all suitable.
850 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
851 const APInt &Low, const APInt &High,
852 const DataLayout &DL) const {
853 // FIXME: I don't think NumCmps is the correct metric: a single case and a
854 // range of cases both require only one branch to lower. Just looking at the
855 // number of clusters and destinations should be enough to decide whether to
858 // To lower a range with bit tests, the range must fit the bitwidth of a
860 if (!rangeFitsInWord(Low, High, DL))
863 // Decide whether it's profitable to lower this range with bit tests. Each
864 // destination requires a bit test and branch, and there is an overall range
865 // check branch. For a small number of clusters, separate comparisons might
866 // be cheaper, and for many destinations, splitting the range might be
868 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
869 (NumDests == 3 && NumCmps >= 6);
872 /// Return true if the specified operation is illegal on this target or
873 /// unlikely to be made legal with custom lowering. This is used to help guide
874 /// high-level lowering decisions.
875 bool isOperationExpand(unsigned Op, EVT VT) const {
876 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
879 /// Return true if the specified operation is legal on this target.
880 bool isOperationLegal(unsigned Op, EVT VT) const {
881 return (VT == MVT::Other || isTypeLegal(VT)) &&
882 getOperationAction(Op, VT) == Legal;
885 /// Return how this load with extension should be treated: either it is legal,
886 /// needs to be promoted to a larger size, needs to be expanded to some other
887 /// code sequence, or the target has a custom expander for it.
888 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
890 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
891 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
892 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
893 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
894 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
895 unsigned Shift = 4 * ExtType;
896 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
899 /// Return true if the specified load with extension is legal on this target.
900 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
901 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
904 /// Return true if the specified load with extension is legal or custom
906 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
907 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
908 getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
911 /// Return how this store with truncation should be treated: either it is
912 /// legal, needs to be promoted to a larger size, needs to be expanded to some
913 /// other code sequence, or the target has a custom expander for it.
914 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
915 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
916 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
917 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
918 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
919 "Table isn't big enough!");
920 return TruncStoreActions[ValI][MemI];
923 /// Return true if the specified store with truncation is legal on this
925 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
926 return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
929 /// Return true if the specified store with truncation has solution on this
931 bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
932 return isTypeLegal(ValVT) &&
933 (getTruncStoreAction(ValVT, MemVT) == Legal ||
934 getTruncStoreAction(ValVT, MemVT) == Custom);
937 /// Return how the indexed load should be treated: either it is legal, needs
938 /// to be promoted to a larger size, needs to be expanded to some other code
939 /// sequence, or the target has a custom expander for it.
941 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
942 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
943 "Table isn't big enough!");
944 unsigned Ty = (unsigned)VT.SimpleTy;
945 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
948 /// Return true if the specified indexed load is legal on this target.
949 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
950 return VT.isSimple() &&
951 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
952 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
955 /// Return how the indexed store should be treated: either it is legal, needs
956 /// to be promoted to a larger size, needs to be expanded to some other code
957 /// sequence, or the target has a custom expander for it.
959 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
960 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
961 "Table isn't big enough!");
962 unsigned Ty = (unsigned)VT.SimpleTy;
963 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
966 /// Return true if the specified indexed load is legal on this target.
967 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
968 return VT.isSimple() &&
969 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
970 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
973 /// Return how the condition code should be treated: either it is legal, needs
974 /// to be expanded to some other code sequence, or the target has a custom
977 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
978 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
979 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
980 "Table isn't big enough!");
981 // See setCondCodeAction for how this is encoded.
982 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
983 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
984 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
985 assert(Action != Promote && "Can't promote condition code!");
989 /// Return true if the specified condition code is legal on this target.
990 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
991 return getCondCodeAction(CC, VT) == Legal;
994 /// Return true if the specified condition code is legal or custom on this
996 bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
997 return getCondCodeAction(CC, VT) == Legal ||
998 getCondCodeAction(CC, VT) == Custom;
1001 /// If the action for this operation is to promote, this method returns the
1002 /// ValueType to promote to.
1003 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1004 assert(getOperationAction(Op, VT) == Promote &&
1005 "This operation isn't promoted!");
1007 // See if this has an explicit type specified.
1008 std::map<std::pair<unsigned, MVT::SimpleValueType>,
1009 MVT::SimpleValueType>::const_iterator PTTI =
1010 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1011 if (PTTI != PromoteToType.end()) return PTTI->second;
1013 assert((VT.isInteger() || VT.isFloatingPoint()) &&
1014 "Cannot autopromote this type, add it with AddPromotedToType.");
1018 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1019 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1020 "Didn't find type to promote to!");
1021 } while (!isTypeLegal(NVT) ||
1022 getOperationAction(Op, NVT) == Promote);
1026 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1027 /// operations except for the pointer size. If AllowUnknown is true, this
1028 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1029 /// otherwise it will assert.
1030 EVT getValueType(const DataLayout &DL, Type *Ty,
1031 bool AllowUnknown = false) const {
1032 // Lower scalar pointers to native pointer types.
1033 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1034 return getPointerTy(DL, PTy->getAddressSpace());
1036 if (Ty->isVectorTy()) {
1037 VectorType *VTy = cast<VectorType>(Ty);
1038 Type *Elm = VTy->getElementType();
1039 // Lower vectors of pointers to native pointer types.
1040 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1041 EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1042 Elm = PointerTy.getTypeForEVT(Ty->getContext());
1045 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1046 VTy->getNumElements());
1048 return EVT::getEVT(Ty, AllowUnknown);
1051 /// Return the MVT corresponding to this LLVM type. See getValueType.
1052 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1053 bool AllowUnknown = false) const {
1054 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1057 /// Return the desired alignment for ByVal or InAlloca aggregate function
1058 /// arguments in the caller parameter area. This is the actual alignment, not
1060 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1062 /// Return the type of registers that this ValueType will eventually require.
1063 MVT getRegisterType(MVT VT) const {
1064 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1065 return RegisterTypeForVT[VT.SimpleTy];
1068 /// Return the type of registers that this ValueType will eventually require.
1069 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1070 if (VT.isSimple()) {
1071 assert((unsigned)VT.getSimpleVT().SimpleTy <
1072 array_lengthof(RegisterTypeForVT));
1073 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1075 if (VT.isVector()) {
1078 unsigned NumIntermediates;
1079 (void)getVectorTypeBreakdown(Context, VT, VT1,
1080 NumIntermediates, RegisterVT);
1083 if (VT.isInteger()) {
1084 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1086 llvm_unreachable("Unsupported extended type!");
1089 /// Return the number of registers that this ValueType will eventually
1092 /// This is one for any types promoted to live in larger registers, but may be
1093 /// more than one for types (like i64) that are split into pieces. For types
1094 /// like i140, which are first promoted then expanded, it is the number of
1095 /// registers needed to hold all the bits of the original type. For an i140
1096 /// on a 32 bit machine this means 5 registers.
1097 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1098 if (VT.isSimple()) {
1099 assert((unsigned)VT.getSimpleVT().SimpleTy <
1100 array_lengthof(NumRegistersForVT));
1101 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1103 if (VT.isVector()) {
1106 unsigned NumIntermediates;
1107 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1109 if (VT.isInteger()) {
1110 unsigned BitWidth = VT.getSizeInBits();
1111 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1112 return (BitWidth + RegWidth - 1) / RegWidth;
1114 llvm_unreachable("Unsupported extended type!");
1117 /// Certain combinations of ABIs, Targets and features require that types
1118 /// are legal for some operations and not for other operations.
1119 /// For MIPS all vector types must be passed through the integer register set.
1120 virtual MVT getRegisterTypeForCallingConv(MVT VT) const {
1121 return getRegisterType(VT);
1124 virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1126 return getRegisterType(Context, VT);
1129 /// Certain targets require unusual breakdowns of certain types. For MIPS,
1130 /// this occurs when a vector type is used, as vector are passed through the
1131 /// integer register set.
1132 virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1134 return getNumRegisters(Context, VT);
1137 /// Certain targets have context senstive alignment requirements, where one
1138 /// type has the alignment requirement of another type.
1139 virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1140 DataLayout DL) const {
1141 return DL.getABITypeAlignment(ArgTy);
1144 /// If true, then instruction selection should seek to shrink the FP constant
1145 /// of the specified type to a smaller type in order to save space and / or
1147 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1149 // Return true if it is profitable to reduce the given load node to a smaller
1152 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1153 virtual bool shouldReduceLoadWidth(SDNode *Load,
1154 ISD::LoadExtType ExtTy,
1159 /// When splitting a value of the specified type into parts, does the Lo
1160 /// or Hi part come first? This usually follows the endianness, except
1161 /// for ppcf128, where the Hi part always comes first.
1162 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1163 return DL.isBigEndian() || VT == MVT::ppcf128;
1166 /// If true, the target has custom DAG combine transformations that it can
1167 /// perform for the specified node.
1168 bool hasTargetDAGCombine(ISD::NodeType NT) const {
1169 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1170 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1173 unsigned getGatherAllAliasesMaxDepth() const {
1174 return GatherAllAliasesMaxDepth;
1177 /// Returns the size of the platform's va_list object.
1178 virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1179 return getPointerTy(DL).getSizeInBits();
1182 /// \brief Get maximum # of store operations permitted for llvm.memset
1184 /// This function returns the maximum number of store operations permitted
1185 /// to replace a call to llvm.memset. The value is set by the target at the
1186 /// performance threshold for such a replacement. If OptSize is true,
1187 /// return the limit for functions that have OptSize attribute.
1188 unsigned getMaxStoresPerMemset(bool OptSize) const {
1189 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1192 /// \brief Get maximum # of store operations permitted for llvm.memcpy
1194 /// This function returns the maximum number of store operations permitted
1195 /// to replace a call to llvm.memcpy. The value is set by the target at the
1196 /// performance threshold for such a replacement. If OptSize is true,
1197 /// return the limit for functions that have OptSize attribute.
1198 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1199 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1202 /// Get maximum # of load operations permitted for memcmp
1204 /// This function returns the maximum number of load operations permitted
1205 /// to replace a call to memcmp. The value is set by the target at the
1206 /// performance threshold for such a replacement. If OptSize is true,
1207 /// return the limit for functions that have OptSize attribute.
1208 unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1209 return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1212 /// For memcmp expansion when the memcmp result is only compared equal or
1213 /// not-equal to 0, allow up to this number of load pairs per block. As an
1214 /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1215 /// a0 = load2bytes &a[0]
1216 /// b0 = load2bytes &b[0]
1217 /// a2 = load1byte &a[2]
1218 /// b2 = load1byte &b[2]
1219 /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1220 virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1224 /// \brief Get maximum # of store operations permitted for llvm.memmove
1226 /// This function returns the maximum number of store operations permitted
1227 /// to replace a call to llvm.memmove. The value is set by the target at the
1228 /// performance threshold for such a replacement. If OptSize is true,
1229 /// return the limit for functions that have OptSize attribute.
1230 unsigned getMaxStoresPerMemmove(bool OptSize) const {
1231 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1234 /// \brief Determine if the target supports unaligned memory accesses.
1236 /// This function returns true if the target allows unaligned memory accesses
1237 /// of the specified type in the given address space. If true, it also returns
1238 /// whether the unaligned memory access is "fast" in the last argument by
1239 /// reference. This is used, for example, in situations where an array
1240 /// copy/move/set is converted to a sequence of store operations. Its use
1241 /// helps to ensure that such replacements don't generate code that causes an
1242 /// alignment error (trap) on the target machine.
1243 virtual bool allowsMisalignedMemoryAccesses(EVT,
1244 unsigned AddrSpace = 0,
1246 bool * /*Fast*/ = nullptr) const {
1250 /// Return true if the target supports a memory access of this type for the
1251 /// given address space and alignment. If the access is allowed, the optional
1252 /// final parameter returns if the access is also fast (as defined by the
1254 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1255 unsigned AddrSpace = 0, unsigned Alignment = 1,
1256 bool *Fast = nullptr) const;
1258 /// Returns the target specific optimal type for load and store operations as
1259 /// a result of memset, memcpy, and memmove lowering.
1261 /// If DstAlign is zero that means it's safe to destination alignment can
1262 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1263 /// a need to check it against alignment requirement, probably because the
1264 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1265 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1266 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1267 /// does not need to be loaded. It returns EVT::Other if the type should be
1268 /// determined using generic target-independent logic.
1269 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1270 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1272 bool /*ZeroMemset*/,
1273 bool /*MemcpyStrSrc*/,
1274 MachineFunction &/*MF*/) const {
1278 /// Returns true if it's safe to use load / store of the specified type to
1279 /// expand memcpy / memset inline.
1281 /// This is mostly true for all types except for some special cases. For
1282 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1283 /// fstpl which also does type conversion. Note the specified type doesn't
1284 /// have to be legal as the hook is used before type legalization.
1285 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1287 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1288 bool usesUnderscoreSetJmp() const {
1289 return UseUnderscoreSetJmp;
1292 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1293 bool usesUnderscoreLongJmp() const {
1294 return UseUnderscoreLongJmp;
1297 /// Return lower limit for number of blocks in a jump table.
1298 virtual unsigned getMinimumJumpTableEntries() const;
1300 /// Return lower limit of the density in a jump table.
1301 unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1303 /// Return upper limit for number of entries in a jump table.
1304 /// Zero if no limit.
1305 unsigned getMaximumJumpTableSize() const;
1307 virtual bool isJumpTableRelative() const {
1308 return TM.isPositionIndependent();
1311 /// If a physical register, this specifies the register that
1312 /// llvm.savestack/llvm.restorestack should save and restore.
1313 unsigned getStackPointerRegisterToSaveRestore() const {
1314 return StackPointerRegisterToSaveRestore;
1317 /// If a physical register, this returns the register that receives the
1318 /// exception address on entry to an EH pad.
1320 getExceptionPointerRegister(const Constant *PersonalityFn) const {
1321 // 0 is guaranteed to be the NoRegister value on all targets
1325 /// If a physical register, this returns the register that receives the
1326 /// exception typeid on entry to a landing pad.
1328 getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1329 // 0 is guaranteed to be the NoRegister value on all targets
1333 virtual bool needsFixedCatchObjects() const {
1334 report_fatal_error("Funclet EH is not implemented for this target");
1337 /// Returns the target's jmp_buf size in bytes (if never set, the default is
1339 unsigned getJumpBufSize() const {
1343 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1345 unsigned getJumpBufAlignment() const {
1346 return JumpBufAlignment;
1349 /// Return the minimum stack alignment of an argument.
1350 unsigned getMinStackArgumentAlignment() const {
1351 return MinStackArgumentAlignment;
1354 /// Return the minimum function alignment.
1355 unsigned getMinFunctionAlignment() const {
1356 return MinFunctionAlignment;
1359 /// Return the preferred function alignment.
1360 unsigned getPrefFunctionAlignment() const {
1361 return PrefFunctionAlignment;
1364 /// Return the preferred loop alignment.
1365 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1366 return PrefLoopAlignment;
1369 /// If the target has a standard location for the stack protector guard,
1370 /// returns the address of that location. Otherwise, returns nullptr.
1371 /// DEPRECATED: please override useLoadStackGuardNode and customize
1372 /// LOAD_STACK_GUARD, or customize @llvm.stackguard().
1373 virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1375 /// Inserts necessary declarations for SSP (stack protection) purpose.
1376 /// Should be used only when getIRStackGuard returns nullptr.
1377 virtual void insertSSPDeclarations(Module &M) const;
1379 /// Return the variable that's previously inserted by insertSSPDeclarations,
1380 /// if any, otherwise return nullptr. Should be used only when
1381 /// getIRStackGuard returns nullptr.
1382 virtual Value *getSDagStackGuard(const Module &M) const;
1384 /// If this function returns true, stack protection checks should XOR the
1385 /// frame pointer (or whichever pointer is used to address locals) into the
1386 /// stack guard value before checking it. getIRStackGuard must return nullptr
1387 /// if this returns true.
1388 virtual bool useStackGuardXorFP() const { return false; }
1390 /// If the target has a standard stack protection check function that
1391 /// performs validation and error handling, returns the function. Otherwise,
1392 /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1393 /// Should be used only when getIRStackGuard returns nullptr.
1394 virtual Value *getSSPStackGuardCheck(const Module &M) const;
1397 Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1401 /// Returns the target-specific address of the unsafe stack pointer.
1402 virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1404 /// Returns the name of the symbol used to emit stack probes or the empty
1405 /// string if not applicable.
1406 virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1410 /// Returns true if a cast between SrcAS and DestAS is a noop.
1411 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1415 /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1416 /// are happy to sink it into basic blocks.
1417 virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1418 return isNoopAddrSpaceCast(SrcAS, DestAS);
1421 /// Return true if the pointer arguments to CI should be aligned by aligning
1422 /// the object whose address is being passed. If so then MinSize is set to the
1423 /// minimum size the object must be to be aligned and PrefAlign is set to the
1424 /// preferred alignment.
1425 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1426 unsigned & /*PrefAlign*/) const {
1430 //===--------------------------------------------------------------------===//
1431 /// \name Helpers for TargetTransformInfo implementations
1434 /// Get the ISD node that corresponds to the Instruction class opcode.
1435 int InstructionOpcodeToISD(unsigned Opcode) const;
1437 /// Estimate the cost of type-legalization and the legalized type.
1438 std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1443 //===--------------------------------------------------------------------===//
1444 /// \name Helpers for atomic expansion.
1447 /// Returns the maximum atomic operation size (in bits) supported by
1448 /// the backend. Atomic operations greater than this size (as well
1449 /// as ones that are not naturally aligned), will be expanded by
1450 /// AtomicExpandPass into an __atomic_* library call.
1451 unsigned getMaxAtomicSizeInBitsSupported() const {
1452 return MaxAtomicSizeInBitsSupported;
1455 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1456 /// the backend supports. Any smaller operations are widened in
1457 /// AtomicExpandPass.
1459 /// Note that *unlike* operations above the maximum size, atomic ops
1460 /// are still natively supported below the minimum; they just
1461 /// require a more complex expansion.
1462 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1464 /// Whether the target supports unaligned atomic operations.
1465 bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1467 /// Whether AtomicExpandPass should automatically insert fences and reduce
1468 /// ordering for this atomic. This should be true for most architectures with
1469 /// weak memory ordering. Defaults to false.
1470 virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1474 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1475 /// corresponding pointee type. This may entail some non-trivial operations to
1476 /// truncate or reconstruct types that will be illegal in the backend. See
1477 /// ARMISelLowering for an example implementation.
1478 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1479 AtomicOrdering Ord) const {
1480 llvm_unreachable("Load linked unimplemented on this target");
1483 /// Perform a store-conditional operation to Addr. Return the status of the
1484 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1485 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1486 Value *Addr, AtomicOrdering Ord) const {
1487 llvm_unreachable("Store conditional unimplemented on this target");
1490 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1491 /// It is called by AtomicExpandPass before expanding an
1492 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1493 /// if shouldInsertFencesForAtomic returns true.
1495 /// Inst is the original atomic instruction, prior to other expansions that
1496 /// may be performed.
1498 /// This function should either return a nullptr, or a pointer to an IR-level
1499 /// Instruction*. Even complex fence sequences can be represented by a
1500 /// single Instruction* through an intrinsic to be lowered later.
1501 /// Backends should override this method to produce target-specific intrinsic
1502 /// for their fences.
1503 /// FIXME: Please note that the default implementation here in terms of
1504 /// IR-level fences exists for historical/compatibility reasons and is
1505 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1506 /// consistency. For example, consider the following example:
1507 /// atomic<int> x = y = 0;
1508 /// int r1, r2, r3, r4;
1519 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1520 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1521 /// IR-level fences can prevent it.
1523 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1524 AtomicOrdering Ord) const {
1525 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1526 return Builder.CreateFence(Ord);
1531 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1533 AtomicOrdering Ord) const {
1534 if (isAcquireOrStronger(Ord))
1535 return Builder.CreateFence(Ord);
1541 // Emits code that executes when the comparison result in the ll/sc
1542 // expansion of a cmpxchg instruction is such that the store-conditional will
1543 // not execute. This makes it possible to balance out the load-linked with
1544 // a dedicated instruction, if desired.
1545 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1546 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1547 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1549 /// Returns true if the given (atomic) store should be expanded by the
1550 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1551 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1555 /// Returns true if arguments should be sign-extended in lib calls.
1556 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1560 /// Returns how the given (atomic) load should be expanded by the
1561 /// IR-level AtomicExpand pass.
1562 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1563 return AtomicExpansionKind::None;
1566 /// Returns true if the given atomic cmpxchg should be expanded by the
1567 /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1568 /// (through emitLoadLinked() and emitStoreConditional()).
1569 virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1573 /// Returns how the IR-level AtomicExpand pass should expand the given
1574 /// AtomicRMW, if at all. Default is to never expand.
1575 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1576 return AtomicExpansionKind::None;
1579 /// On some platforms, an AtomicRMW that never actually modifies the value
1580 /// (such as fetch_add of 0) can be turned into a fence followed by an
1581 /// atomic load. This may sound useless, but it makes it possible for the
1582 /// processor to keep the cacheline shared, dramatically improving
1583 /// performance. And such idempotent RMWs are useful for implementing some
1584 /// kinds of locks, see for example (justification + benchmarks):
1585 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1586 /// This method tries doing that transformation, returning the atomic load if
1587 /// it succeeds, and nullptr otherwise.
1588 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1589 /// another round of expansion.
1591 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1595 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1596 /// SIGN_EXTEND, or ANY_EXTEND).
1597 virtual ISD::NodeType getExtendForAtomicOps() const {
1598 return ISD::ZERO_EXTEND;
1603 /// Returns true if we should normalize
1604 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1605 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1606 /// that it saves us from materializing N0 and N1 in an integer register.
1607 /// Targets that are able to perform and/or on flags should return false here.
1608 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1610 // If a target has multiple condition registers, then it likely has logical
1611 // operations on those registers.
1612 if (hasMultipleConditionRegisters())
1614 // Only do the transform if the value won't be split into multiple
1616 LegalizeTypeAction Action = getTypeAction(Context, VT);
1617 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1618 Action != TypeSplitVector;
1621 /// Return true if a select of constants (select Cond, C1, C2) should be
1622 /// transformed into simple math ops with the condition value. For example:
1623 /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1624 virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1628 //===--------------------------------------------------------------------===//
1629 // TargetLowering Configuration Methods - These methods should be invoked by
1630 // the derived class constructor to configure this object for the target.
1633 /// Specify how the target extends the result of integer and floating point
1634 /// boolean values from i1 to a wider type. See getBooleanContents.
1635 void setBooleanContents(BooleanContent Ty) {
1636 BooleanContents = Ty;
1637 BooleanFloatContents = Ty;
1640 /// Specify how the target extends the result of integer and floating point
1641 /// boolean values from i1 to a wider type. See getBooleanContents.
1642 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1643 BooleanContents = IntTy;
1644 BooleanFloatContents = FloatTy;
1647 /// Specify how the target extends the result of a vector boolean value from a
1648 /// vector of i1 to a wider type. See getBooleanContents.
1649 void setBooleanVectorContents(BooleanContent Ty) {
1650 BooleanVectorContents = Ty;
1653 /// Specify the target scheduling preference.
1654 void setSchedulingPreference(Sched::Preference Pref) {
1655 SchedPreferenceInfo = Pref;
1658 /// Indicate whether this target prefers to use _setjmp to implement
1659 /// llvm.setjmp or the version without _. Defaults to false.
1660 void setUseUnderscoreSetJmp(bool Val) {
1661 UseUnderscoreSetJmp = Val;
1664 /// Indicate whether this target prefers to use _longjmp to implement
1665 /// llvm.longjmp or the version without _. Defaults to false.
1666 void setUseUnderscoreLongJmp(bool Val) {
1667 UseUnderscoreLongJmp = Val;
1670 /// Indicate the minimum number of blocks to generate jump tables.
1671 void setMinimumJumpTableEntries(unsigned Val);
1673 /// Indicate the maximum number of entries in jump tables.
1674 /// Set to zero to generate unlimited jump tables.
1675 void setMaximumJumpTableSize(unsigned);
1677 /// If set to a physical register, this specifies the register that
1678 /// llvm.savestack/llvm.restorestack should save and restore.
1679 void setStackPointerRegisterToSaveRestore(unsigned R) {
1680 StackPointerRegisterToSaveRestore = R;
1683 /// Tells the code generator that the target has multiple (allocatable)
1684 /// condition registers that can be used to store the results of comparisons
1685 /// for use by selects and conditional branches. With multiple condition
1686 /// registers, the code generator will not aggressively sink comparisons into
1687 /// the blocks of their users.
1688 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1689 HasMultipleConditionRegisters = hasManyRegs;
1692 /// Tells the code generator that the target has BitExtract instructions.
1693 /// The code generator will aggressively sink "shift"s into the blocks of
1694 /// their users if the users will generate "and" instructions which can be
1695 /// combined with "shift" to BitExtract instructions.
1696 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1697 HasExtractBitsInsn = hasExtractInsn;
1700 /// Tells the code generator not to expand logic operations on comparison
1701 /// predicates into separate sequences that increase the amount of flow
1703 void setJumpIsExpensive(bool isExpensive = true);
1705 /// Tells the code generator that this target supports floating point
1706 /// exceptions and cares about preserving floating point exception behavior.
1707 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1708 HasFloatingPointExceptions = FPExceptions;
1711 /// Tells the code generator which bitwidths to bypass.
1712 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1713 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1716 /// Add the specified register class as an available regclass for the
1717 /// specified value type. This indicates the selector can handle values of
1718 /// that class natively.
1719 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1720 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1721 RegClassForVT[VT.SimpleTy] = RC;
1724 /// Return the largest legal super-reg register class of the register class
1725 /// for the specified type and its associated "cost".
1726 virtual std::pair<const TargetRegisterClass *, uint8_t>
1727 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1729 /// Once all of the register classes are added, this allows us to compute
1730 /// derived properties we expose.
1731 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1733 /// Indicate that the specified operation does not work with the specified
1734 /// type and indicate what to do about it. Note that VT may refer to either
1735 /// the type of a result or that of an operand of Op.
1736 void setOperationAction(unsigned Op, MVT VT,
1737 LegalizeAction Action) {
1738 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1739 OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1742 /// Indicate that the specified load with extension does not work with the
1743 /// specified type and indicate what to do about it.
1744 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1745 LegalizeAction Action) {
1746 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1747 MemVT.isValid() && "Table isn't big enough!");
1748 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1749 unsigned Shift = 4 * ExtType;
1750 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1751 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1754 /// Indicate that the specified truncating store does not work with the
1755 /// specified type and indicate what to do about it.
1756 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1757 LegalizeAction Action) {
1758 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1759 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1762 /// Indicate that the specified indexed load does or does not work with the
1763 /// specified type and indicate what to do abort it.
1765 /// NOTE: All indexed mode loads are initialized to Expand in
1766 /// TargetLowering.cpp
1767 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1768 LegalizeAction Action) {
1769 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1770 (unsigned)Action < 0xf && "Table isn't big enough!");
1771 // Load action are kept in the upper half.
1772 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1773 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1776 /// Indicate that the specified indexed store does or does not work with the
1777 /// specified type and indicate what to do about it.
1779 /// NOTE: All indexed mode stores are initialized to Expand in
1780 /// TargetLowering.cpp
1781 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1782 LegalizeAction Action) {
1783 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1784 (unsigned)Action < 0xf && "Table isn't big enough!");
1785 // Store action are kept in the lower half.
1786 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1787 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1790 /// Indicate that the specified condition code is or isn't supported on the
1791 /// target and indicate what to do about it.
1792 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1793 LegalizeAction Action) {
1794 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1795 "Table isn't big enough!");
1796 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1797 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1798 /// value and the upper 29 bits index into the second dimension of the array
1799 /// to select what 32-bit value to use.
1800 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1801 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1802 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1805 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1806 /// to trying a larger integer/fp until it can find one that works. If that
1807 /// default is insufficient, this method can be used by the target to override
1809 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1810 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1813 /// Convenience method to set an operation to Promote and specify the type
1814 /// in a single call.
1815 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1816 setOperationAction(Opc, OrigVT, Promote);
1817 AddPromotedToType(Opc, OrigVT, DestVT);
1820 /// Targets should invoke this method for each target independent node that
1821 /// they want to provide a custom DAG combiner for by implementing the
1822 /// PerformDAGCombine virtual method.
1823 void setTargetDAGCombine(ISD::NodeType NT) {
1824 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1825 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1828 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1829 void setJumpBufSize(unsigned Size) {
1833 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1835 void setJumpBufAlignment(unsigned Align) {
1836 JumpBufAlignment = Align;
1839 /// Set the target's minimum function alignment (in log2(bytes))
1840 void setMinFunctionAlignment(unsigned Align) {
1841 MinFunctionAlignment = Align;
1844 /// Set the target's preferred function alignment. This should be set if
1845 /// there is a performance benefit to higher-than-minimum alignment (in
1847 void setPrefFunctionAlignment(unsigned Align) {
1848 PrefFunctionAlignment = Align;
1851 /// Set the target's preferred loop alignment. Default alignment is zero, it
1852 /// means the target does not care about loop alignment. The alignment is
1853 /// specified in log2(bytes). The target may also override
1854 /// getPrefLoopAlignment to provide per-loop values.
1855 void setPrefLoopAlignment(unsigned Align) {
1856 PrefLoopAlignment = Align;
1859 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1860 void setMinStackArgumentAlignment(unsigned Align) {
1861 MinStackArgumentAlignment = Align;
1864 /// Set the maximum atomic operation size supported by the
1865 /// backend. Atomic operations greater than this size (as well as
1866 /// ones that are not naturally aligned), will be expanded by
1867 /// AtomicExpandPass into an __atomic_* library call.
1868 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1869 MaxAtomicSizeInBitsSupported = SizeInBits;
1872 /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1873 void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1874 MinCmpXchgSizeInBits = SizeInBits;
1877 /// Sets whether unaligned atomic operations are supported.
1878 void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1879 SupportsUnalignedAtomics = UnalignedSupported;
1883 //===--------------------------------------------------------------------===//
1884 // Addressing mode description hooks (used by LSR etc).
1887 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1888 /// instructions reading the address. This allows as much computation as
1889 /// possible to be done in the address mode for that operand. This hook lets
1890 /// targets also pass back when this should be done on intrinsics which
1892 virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1893 SmallVectorImpl<Value*> &/*Ops*/,
1894 Type *&/*AccessTy*/) const {
1898 /// This represents an addressing mode of:
1899 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1900 /// If BaseGV is null, there is no BaseGV.
1901 /// If BaseOffs is zero, there is no base offset.
1902 /// If HasBaseReg is false, there is no base register.
1903 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1906 GlobalValue *BaseGV = nullptr;
1907 int64_t BaseOffs = 0;
1908 bool HasBaseReg = false;
1910 AddrMode() = default;
1913 /// Return true if the addressing mode represented by AM is legal for this
1914 /// target, for a load/store of the specified type.
1916 /// The type may be VoidTy, in which case only return true if the addressing
1917 /// mode is legal for a load/store of any legal type. TODO: Handle
1918 /// pre/postinc as well.
1920 /// If the address space cannot be determined, it will be -1.
1922 /// TODO: Remove default argument
1923 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1924 Type *Ty, unsigned AddrSpace,
1925 Instruction *I = nullptr) const;
1927 /// \brief Return the cost of the scaling factor used in the addressing mode
1928 /// represented by AM for this target, for a load/store of the specified type.
1930 /// If the AM is supported, the return value must be >= 0.
1931 /// If the AM is not supported, it returns a negative value.
1932 /// TODO: Handle pre/postinc as well.
1933 /// TODO: Remove default argument
1934 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1935 Type *Ty, unsigned AS = 0) const {
1936 // Default: assume that any scaling factor used in a legal AM is free.
1937 if (isLegalAddressingMode(DL, AM, Ty, AS))
1942 /// Return true if the specified immediate is legal icmp immediate, that is
1943 /// the target has icmp instructions which can compare a register against the
1944 /// immediate without having to materialize the immediate into a register.
1945 virtual bool isLegalICmpImmediate(int64_t) const {
1949 /// Return true if the specified immediate is legal add immediate, that is the
1950 /// target has add instructions which can add a register with the immediate
1951 /// without having to materialize the immediate into a register.
1952 virtual bool isLegalAddImmediate(int64_t) const {
1956 /// Return true if it's significantly cheaper to shift a vector by a uniform
1957 /// scalar than by an amount which will vary across each lane. On x86, for
1958 /// example, there is a "psllw" instruction for the former case, but no simple
1959 /// instruction for a general "a << b" operation on vectors.
1960 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1964 /// Returns true if the opcode is a commutative binary operation.
1965 virtual bool isCommutativeBinOp(unsigned Opcode) const {
1966 // FIXME: This should get its info from the td file.
1976 case ISD::SMUL_LOHI:
1977 case ISD::UMUL_LOHI:
1992 default: return false;
1996 /// Return true if it's free to truncate a value of type FromTy to type
1997 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1998 /// by referencing its sub-register AX.
1999 /// Targets must return false when FromTy <= ToTy.
2000 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2004 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2005 /// whether a call is in tail position. Typically this means that both results
2006 /// would be assigned to the same register or stack slot, but it could mean
2007 /// the target performs adequate checks of its own before proceeding with the
2008 /// tail call. Targets must return false when FromTy <= ToTy.
2009 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2013 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2017 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2019 /// Return true if the extension represented by \p I is free.
2020 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2021 /// this method can use the context provided by \p I to decide
2022 /// whether or not \p I is free.
2023 /// This method extends the behavior of the is[Z|FP]ExtFree family.
2024 /// In other words, if is[Z|FP]Free returns true, then this method
2025 /// returns true as well. The converse is not true.
2026 /// The target can perform the adequate checks by overriding isExtFreeImpl.
2027 /// \pre \p I must be a sign, zero, or fp extension.
2028 bool isExtFree(const Instruction *I) const {
2029 switch (I->getOpcode()) {
2030 case Instruction::FPExt:
2031 if (isFPExtFree(EVT::getEVT(I->getType()),
2032 EVT::getEVT(I->getOperand(0)->getType())))
2035 case Instruction::ZExt:
2036 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2039 case Instruction::SExt:
2042 llvm_unreachable("Instruction is not an extension");
2044 return isExtFreeImpl(I);
2047 /// Return true if \p Load and \p Ext can form an ExtLoad.
2048 /// For example, in AArch64
2049 /// %L = load i8, i8* %ptr
2050 /// %E = zext i8 %L to i32
2051 /// can be lowered into one load instruction
2053 bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2054 const DataLayout &DL) const {
2055 EVT VT = getValueType(DL, Ext->getType());
2056 EVT LoadVT = getValueType(DL, Load->getType());
2058 // If the load has other users and the truncate is not free, the ext
2059 // probably isn't free.
2060 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2061 !isTruncateFree(Ext->getType(), Load->getType()))
2064 // Check whether the target supports casts folded into loads.
2066 if (isa<ZExtInst>(Ext))
2067 LType = ISD::ZEXTLOAD;
2069 assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2070 LType = ISD::SEXTLOAD;
2073 return isLoadExtLegal(LType, VT, LoadVT);
2076 /// Return true if any actual instruction that defines a value of type FromTy
2077 /// implicitly zero-extends the value to ToTy in the result register.
2079 /// The function should return true when it is likely that the truncate can
2080 /// be freely folded with an instruction defining a value of FromTy. If
2081 /// the defining instruction is unknown (because you're looking at a
2082 /// function argument, PHI, etc.) then the target may require an
2083 /// explicit truncate, which is not necessarily free, but this function
2084 /// does not deal with those cases.
2085 /// Targets must return false when FromTy >= ToTy.
2086 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2090 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2094 /// Return true if the target supplies and combines to a paired load
2095 /// two loaded values of type LoadedType next to each other in memory.
2096 /// RequiredAlignment gives the minimal alignment constraints that must be met
2097 /// to be able to select this paired load.
2099 /// This information is *not* used to generate actual paired loads, but it is
2100 /// used to generate a sequence of loads that is easier to combine into a
2102 /// For instance, something like this:
2103 /// a = load i64* addr
2104 /// b = trunc i64 a to i32
2105 /// c = lshr i64 a, 32
2106 /// d = trunc i64 c to i32
2107 /// will be optimized into:
2108 /// b = load i32* addr1
2109 /// d = load i32* addr2
2110 /// Where addr1 = addr2 +/- sizeof(i32).
2112 /// In other words, unless the target performs a post-isel load combining,
2113 /// this information should not be provided because it will generate more
2115 virtual bool hasPairedLoad(EVT /*LoadedType*/,
2116 unsigned & /*RequiredAlignment*/) const {
2120 /// Return true if the target has a vector blend instruction.
2121 virtual bool hasVectorBlend() const { return false; }
2123 /// \brief Get the maximum supported factor for interleaved memory accesses.
2124 /// Default to be the minimum interleave factor: 2.
2125 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2127 /// \brief Lower an interleaved load to target specific intrinsics. Return
2128 /// true on success.
2130 /// \p LI is the vector load instruction.
2131 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2132 /// \p Indices is the corresponding indices for each shufflevector.
2133 /// \p Factor is the interleave factor.
2134 virtual bool lowerInterleavedLoad(LoadInst *LI,
2135 ArrayRef<ShuffleVectorInst *> Shuffles,
2136 ArrayRef<unsigned> Indices,
2137 unsigned Factor) const {
2141 /// \brief Lower an interleaved store to target specific intrinsics. Return
2142 /// true on success.
2144 /// \p SI is the vector store instruction.
2145 /// \p SVI is the shufflevector to RE-interleave the stored vector.
2146 /// \p Factor is the interleave factor.
2147 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2148 unsigned Factor) const {
2152 /// Return true if zero-extending the specific node Val to type VT2 is free
2153 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2154 /// because it's folded such as X86 zero-extending loads).
2155 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2156 return isZExtFree(Val.getValueType(), VT2);
2159 /// Return true if an fpext operation is free (for instance, because
2160 /// single-precision floating-point numbers are implicitly extended to
2161 /// double-precision).
2162 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2163 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2164 "invalid fpext types");
2168 /// Return true if an fpext operation input to an \p Opcode operation is free
2169 /// (for instance, because half-precision floating-point numbers are
2170 /// implicitly extended to float-precision) for an FMA instruction.
2171 virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2172 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2173 "invalid fpext types");
2174 return isFPExtFree(DestVT, SrcVT);
2177 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2178 /// extend node) is profitable.
2179 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2181 /// Return true if an fneg operation is free to the point where it is never
2182 /// worthwhile to replace it with a bitwise operation.
2183 virtual bool isFNegFree(EVT VT) const {
2184 assert(VT.isFloatingPoint());
2188 /// Return true if an fabs operation is free to the point where it is never
2189 /// worthwhile to replace it with a bitwise operation.
2190 virtual bool isFAbsFree(EVT VT) const {
2191 assert(VT.isFloatingPoint());
2195 /// Return true if an FMA operation is faster than a pair of fmul and fadd
2196 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2197 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2199 /// NOTE: This may be called before legalization on types for which FMAs are
2200 /// not legal, but should return true if those types will eventually legalize
2201 /// to types that support FMAs. After legalization, it will only be called on
2202 /// types that support FMAs (via Legal or Custom actions)
2203 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2207 /// Return true if it's profitable to narrow operations of type VT1 to
2208 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2210 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2214 /// \brief Return true if it is beneficial to convert a load of a constant to
2215 /// just the constant itself.
2216 /// On some targets it might be more efficient to use a combination of
2217 /// arithmetic instructions to materialize the constant instead of loading it
2218 /// from a constant pool.
2219 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2224 /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2225 /// from this source type with this index. This is needed because
2226 /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2227 /// the first element, and only the target knows which lowering is cheap.
2228 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2229 unsigned Index) const {
2233 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2234 // even if the vector itself has multiple uses.
2235 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2239 //===--------------------------------------------------------------------===//
2240 // Runtime Library hooks
2243 /// Rename the default libcall routine name for the specified libcall.
2244 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2245 LibcallRoutineNames[Call] = Name;
2248 /// Get the libcall routine name for the specified libcall.
2249 const char *getLibcallName(RTLIB::Libcall Call) const {
2250 return LibcallRoutineNames[Call];
2253 /// Override the default CondCode to be used to test the result of the
2254 /// comparison libcall against zero.
2255 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2256 CmpLibcallCCs[Call] = CC;
2259 /// Get the CondCode that's to be used to test the result of the comparison
2260 /// libcall against zero.
2261 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2262 return CmpLibcallCCs[Call];
2265 /// Set the CallingConv that should be used for the specified libcall.
2266 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2267 LibcallCallingConvs[Call] = CC;
2270 /// Get the CallingConv that should be used for the specified libcall.
2271 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2272 return LibcallCallingConvs[Call];
2275 /// Execute target specific actions to finalize target lowering.
2276 /// This is used to set extra flags in MachineFrameInformation and freezing
2277 /// the set of reserved registers.
2278 /// The default implementation just freezes the set of reserved registers.
2279 virtual void finalizeLowering(MachineFunction &MF) const;
2282 const TargetMachine &TM;
2284 /// Tells the code generator that the target has multiple (allocatable)
2285 /// condition registers that can be used to store the results of comparisons
2286 /// for use by selects and conditional branches. With multiple condition
2287 /// registers, the code generator will not aggressively sink comparisons into
2288 /// the blocks of their users.
2289 bool HasMultipleConditionRegisters;
2291 /// Tells the code generator that the target has BitExtract instructions.
2292 /// The code generator will aggressively sink "shift"s into the blocks of
2293 /// their users if the users will generate "and" instructions which can be
2294 /// combined with "shift" to BitExtract instructions.
2295 bool HasExtractBitsInsn;
2297 /// Tells the code generator to bypass slow divide or remainder
2298 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2299 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2300 /// div/rem when the operands are positive and less than 256.
2301 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2303 /// Tells the code generator that it shouldn't generate extra flow control
2304 /// instructions and should attempt to combine flow control instructions via
2306 bool JumpIsExpensive;
2308 /// Whether the target supports or cares about preserving floating point
2309 /// exception behavior.
2310 bool HasFloatingPointExceptions;
2312 /// This target prefers to use _setjmp to implement llvm.setjmp.
2314 /// Defaults to false.
2315 bool UseUnderscoreSetJmp;
2317 /// This target prefers to use _longjmp to implement llvm.longjmp.
2319 /// Defaults to false.
2320 bool UseUnderscoreLongJmp;
2322 /// Information about the contents of the high-bits in boolean values held in
2323 /// a type wider than i1. See getBooleanContents.
2324 BooleanContent BooleanContents;
2326 /// Information about the contents of the high-bits in boolean values held in
2327 /// a type wider than i1. See getBooleanContents.
2328 BooleanContent BooleanFloatContents;
2330 /// Information about the contents of the high-bits in boolean vector values
2331 /// when the element type is wider than i1. See getBooleanContents.
2332 BooleanContent BooleanVectorContents;
2334 /// The target scheduling preference: shortest possible total cycles or lowest
2336 Sched::Preference SchedPreferenceInfo;
2338 /// The size, in bytes, of the target's jmp_buf buffers
2339 unsigned JumpBufSize;
2341 /// The alignment, in bytes, of the target's jmp_buf buffers
2342 unsigned JumpBufAlignment;
2344 /// The minimum alignment that any argument on the stack needs to have.
2345 unsigned MinStackArgumentAlignment;
2347 /// The minimum function alignment (used when optimizing for size, and to
2348 /// prevent explicitly provided alignment from leading to incorrect code).
2349 unsigned MinFunctionAlignment;
2351 /// The preferred function alignment (used when alignment unspecified and
2352 /// optimizing for speed).
2353 unsigned PrefFunctionAlignment;
2355 /// The preferred loop alignment.
2356 unsigned PrefLoopAlignment;
2358 /// Size in bits of the maximum atomics size the backend supports.
2359 /// Accesses larger than this will be expanded by AtomicExpandPass.
2360 unsigned MaxAtomicSizeInBitsSupported;
2362 /// Size in bits of the minimum cmpxchg or ll/sc operation the
2363 /// backend supports.
2364 unsigned MinCmpXchgSizeInBits;
2366 /// This indicates if the target supports unaligned atomic operations.
2367 bool SupportsUnalignedAtomics;
2369 /// If set to a physical register, this specifies the register that
2370 /// llvm.savestack/llvm.restorestack should save and restore.
2371 unsigned StackPointerRegisterToSaveRestore;
2373 /// This indicates the default register class to use for each ValueType the
2374 /// target supports natively.
2375 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2376 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2377 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2379 /// This indicates the "representative" register class to use for each
2380 /// ValueType the target supports natively. This information is used by the
2381 /// scheduler to track register pressure. By default, the representative
2382 /// register class is the largest legal super-reg register class of the
2383 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2384 /// representative class would be GR32.
2385 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2387 /// This indicates the "cost" of the "representative" register class for each
2388 /// ValueType. The cost is used by the scheduler to approximate register
2390 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2392 /// For any value types we are promoting or expanding, this contains the value
2393 /// type that we are changing to. For Expanded types, this contains one step
2394 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2395 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2396 /// the same type (e.g. i32 -> i32).
2397 MVT TransformToType[MVT::LAST_VALUETYPE];
2399 /// For each operation and each value type, keep a LegalizeAction that
2400 /// indicates how instruction selection should deal with the operation. Most
2401 /// operations are Legal (aka, supported natively by the target), but
2402 /// operations that are not should be described. Note that operations on
2403 /// non-legal value types are not described here.
2404 LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2406 /// For each load extension type and each value type, keep a LegalizeAction
2407 /// that indicates how instruction selection should deal with a load of a
2408 /// specific value type and extension type. Uses 4-bits to store the action
2409 /// for each of the 4 load ext types.
2410 uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2412 /// For each value type pair keep a LegalizeAction that indicates whether a
2413 /// truncating store of a specific value type and truncating type is legal.
2414 LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2416 /// For each indexed mode and each value type, keep a pair of LegalizeAction
2417 /// that indicates how instruction selection should deal with the load /
2420 /// The first dimension is the value_type for the reference. The second
2421 /// dimension represents the various modes for load store.
2422 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2424 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2425 /// indicates how instruction selection should deal with the condition code.
2427 /// Because each CC action takes up 4 bits, we need to have the array size be
2428 /// large enough to fit all of the value types. This can be done by rounding
2429 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2430 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2433 ValueTypeActionImpl ValueTypeActions;
2436 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2438 /// Targets can specify ISD nodes that they would like PerformDAGCombine
2439 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2442 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2444 /// For operations that must be promoted to a specific type, this holds the
2445 /// destination type. This map should be sparse, so don't hold it as an
2448 /// Targets add entries to this map with AddPromotedToType(..), clients access
2449 /// this with getTypeToPromoteTo(..).
2450 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2453 /// Stores the name each libcall.
2454 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2456 /// The ISD::CondCode that should be used to test the result of each of the
2457 /// comparison libcall against zero.
2458 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2460 /// Stores the CallingConv that should be used for each libcall.
2461 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2463 /// Set default libcall names and calling conventions.
2464 void InitLibcalls(const Triple &TT);
2467 /// Return true if the extension represented by \p I is free.
2468 /// \pre \p I is a sign, zero, or fp extension and
2469 /// is[Z|FP]ExtFree of the related types is not true.
2470 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2472 /// Depth that GatherAllAliases should should continue looking for chain
2473 /// dependencies when trying to find a more preferable chain. As an
2474 /// approximation, this should be more than the number of consecutive stores
2475 /// expected to be merged.
2476 unsigned GatherAllAliasesMaxDepth;
2478 /// \brief Specify maximum number of store instructions per memset call.
2480 /// When lowering \@llvm.memset this field specifies the maximum number of
2481 /// store operations that may be substituted for the call to memset. Targets
2482 /// must set this value based on the cost threshold for that target. Targets
2483 /// should assume that the memset will be done using as many of the largest
2484 /// store operations first, followed by smaller ones, if necessary, per
2485 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2486 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2487 /// store. This only applies to setting a constant array of a constant size.
2488 unsigned MaxStoresPerMemset;
2490 /// Maximum number of stores operations that may be substituted for the call
2491 /// to memset, used for functions with OptSize attribute.
2492 unsigned MaxStoresPerMemsetOptSize;
2494 /// \brief Specify maximum bytes of store instructions per memcpy call.
2496 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2497 /// store operations that may be substituted for a call to memcpy. Targets
2498 /// must set this value based on the cost threshold for that target. Targets
2499 /// should assume that the memcpy will be done using as many of the largest
2500 /// store operations first, followed by smaller ones, if necessary, per
2501 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2502 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2503 /// and one 1-byte store. This only applies to copying a constant array of
2505 unsigned MaxStoresPerMemcpy;
2507 /// Maximum number of store operations that may be substituted for a call to
2508 /// memcpy, used for functions with OptSize attribute.
2509 unsigned MaxStoresPerMemcpyOptSize;
2510 unsigned MaxLoadsPerMemcmp;
2511 unsigned MaxLoadsPerMemcmpOptSize;
2513 /// \brief Specify maximum bytes of store instructions per memmove call.
2515 /// When lowering \@llvm.memmove this field specifies the maximum number of
2516 /// store instructions that may be substituted for a call to memmove. Targets
2517 /// must set this value based on the cost threshold for that target. Targets
2518 /// should assume that the memmove will be done using as many of the largest
2519 /// store operations first, followed by smaller ones, if necessary, per
2520 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2521 /// with 8-bit alignment would result in nine 1-byte stores. This only
2522 /// applies to copying a constant array of constant size.
2523 unsigned MaxStoresPerMemmove;
2525 /// Maximum number of store instructions that may be substituted for a call to
2526 /// memmove, used for functions with OptSize attribute.
2527 unsigned MaxStoresPerMemmoveOptSize;
2529 /// Tells the code generator that select is more expensive than a branch if
2530 /// the branch is usually predicted right.
2531 bool PredictableSelectIsExpensive;
2533 /// \see enableExtLdPromotion.
2534 bool EnableExtLdPromotion;
2536 /// Return true if the value types that can be represented by the specified
2537 /// register class are all legal.
2538 bool isLegalRC(const TargetRegisterInfo &TRI,
2539 const TargetRegisterClass &RC) const;
2541 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2542 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2543 MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2544 MachineBasicBlock *MBB) const;
2546 /// Replace/modify the XRay custom event operands with target-dependent
2548 MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2549 MachineBasicBlock *MBB) const;
2552 /// This class defines information used to lower LLVM code to legal SelectionDAG
2553 /// operators that the target instruction selector can accept natively.
2555 /// This class also defines callbacks that targets must implement to lower
2556 /// target-specific constructs to SelectionDAG operators.
2557 class TargetLowering : public TargetLoweringBase {
2559 struct DAGCombinerInfo;
2561 TargetLowering(const TargetLowering &) = delete;
2562 TargetLowering &operator=(const TargetLowering &) = delete;
2564 /// NOTE: The TargetMachine owns TLOF.
2565 explicit TargetLowering(const TargetMachine &TM);
2567 bool isPositionIndependent() const;
2569 virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2570 FunctionLoweringInfo *FLI,
2571 DivergenceAnalysis *DA) const {
2575 virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2579 /// Returns true by value, base pointer and offset pointer and addressing mode
2580 /// by reference if the node's address can be legally represented as
2581 /// pre-indexed load / store address.
2582 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2583 SDValue &/*Offset*/,
2584 ISD::MemIndexedMode &/*AM*/,
2585 SelectionDAG &/*DAG*/) const {
2589 /// Returns true by value, base pointer and offset pointer and addressing mode
2590 /// by reference if this node can be combined with a load / store to form a
2591 /// post-indexed load / store.
2592 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2594 SDValue &/*Offset*/,
2595 ISD::MemIndexedMode &/*AM*/,
2596 SelectionDAG &/*DAG*/) const {
2600 /// Return the entry encoding for a jump table in the current function. The
2601 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2602 virtual unsigned getJumpTableEncoding() const;
2604 virtual const MCExpr *
2605 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2606 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2607 MCContext &/*Ctx*/) const {
2608 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2611 /// Returns relocation base for the given PIC jumptable.
2612 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2613 SelectionDAG &DAG) const;
2615 /// This returns the relocation base for the given PIC jumptable, the same as
2616 /// getPICJumpTableRelocBase, but as an MCExpr.
2617 virtual const MCExpr *
2618 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2619 unsigned JTI, MCContext &Ctx) const;
2621 /// Return true if folding a constant offset with the given GlobalAddress is
2622 /// legal. It is frequently not legal in PIC relocation models.
2623 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2625 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2626 SDValue &Chain) const;
2628 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2629 SDValue &NewRHS, ISD::CondCode &CCCode,
2630 const SDLoc &DL) const;
2632 /// Returns a pair of (return value, chain).
2633 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2634 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2635 EVT RetVT, ArrayRef<SDValue> Ops,
2636 bool isSigned, const SDLoc &dl,
2637 bool doesNotReturn = false,
2638 bool isReturnValueUsed = true) const;
2640 /// Check whether parameters to a call that are passed in callee saved
2641 /// registers are the same as from the calling function. This needs to be
2642 /// checked for tail call eligibility.
2643 bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2644 const uint32_t *CallerPreservedMask,
2645 const SmallVectorImpl<CCValAssign> &ArgLocs,
2646 const SmallVectorImpl<SDValue> &OutVals) const;
2648 //===--------------------------------------------------------------------===//
2649 // TargetLowering Optimization Methods
2652 /// A convenience struct that encapsulates a DAG, and two SDValues for
2653 /// returning information from TargetLowering to its clients that want to
2655 struct TargetLoweringOpt {
2662 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2664 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2666 bool LegalTypes() const { return LegalTys; }
2667 bool LegalOperations() const { return LegalOps; }
2669 bool CombineTo(SDValue O, SDValue N) {
2676 /// Check to see if the specified operand of the specified instruction is a
2677 /// constant integer. If so, check to see if there are any bits set in the
2678 /// constant that are not demanded. If so, shrink the constant and return
2680 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2681 TargetLoweringOpt &TLO) const;
2683 // Target hook to do target-specific const optimization, which is called by
2684 // ShrinkDemandedConstant. This function should return true if the target
2685 // doesn't want ShrinkDemandedConstant to further optimize the constant.
2686 virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2687 TargetLoweringOpt &TLO) const {
2691 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2692 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2693 /// generalized for targets with other types of implicit widening casts.
2694 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2695 TargetLoweringOpt &TLO) const;
2697 /// Helper for SimplifyDemandedBits that can simplify an operation with
2698 /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2699 /// then updates \p User with the simplified version. No other uses of
2700 /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2701 /// function behaves exactly like function SimplifyDemandedBits declared
2702 /// below except that it also updates the DAG by calling
2703 /// DCI.CommitTargetLoweringOpt.
2704 bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2705 DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2707 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2708 /// result of Op are ever used downstream. If we can use this information to
2709 /// simplify Op, create a new simplified DAG node and return true, returning
2710 /// the original and new nodes in Old and New. Otherwise, analyze the
2711 /// expression and return a mask of KnownOne and KnownZero bits for the
2712 /// expression (used to simplify the caller). The KnownZero/One bits may only
2713 /// be accurate for those bits in the DemandedMask.
2714 /// \p AssumeSingleUse When this parameter is true, this function will
2715 /// attempt to simplify \p Op even if there are multiple uses.
2716 /// Callers are responsible for correctly updating the DAG based on the
2717 /// results of this function, because simply replacing replacing TLO.Old
2718 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2719 /// has multiple uses.
2720 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2722 TargetLoweringOpt &TLO,
2724 bool AssumeSingleUse = false) const;
2726 /// Helper wrapper around SimplifyDemandedBits
2727 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2728 DAGCombinerInfo &DCI) const;
2730 /// Look at Vector Op. At this point, we know that only the DemandedElts
2731 /// elements of the result of Op are ever used downstream. If we can use
2732 /// this information to simplify Op, create a new simplified DAG node and
2733 /// return true, storing the original and new nodes in TLO.
2734 /// Otherwise, analyze the expression and return a mask of KnownUndef and
2735 /// KnownZero elements for the expression (used to simplify the caller).
2736 /// The KnownUndef/Zero elements may only be accurate for those bits
2737 /// in the DemandedMask.
2738 /// \p AssumeSingleUse When this parameter is true, this function will
2739 /// attempt to simplify \p Op even if there are multiple uses.
2740 /// Callers are responsible for correctly updating the DAG based on the
2741 /// results of this function, because simply replacing replacing TLO.Old
2742 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2743 /// has multiple uses.
2744 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2745 APInt &KnownUndef, APInt &KnownZero,
2746 TargetLoweringOpt &TLO, unsigned Depth = 0,
2747 bool AssumeSingleUse = false) const;
2749 /// Helper wrapper around SimplifyDemandedVectorElts
2750 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2751 APInt &KnownUndef, APInt &KnownZero,
2752 DAGCombinerInfo &DCI) const;
2754 /// Determine which of the bits specified in Mask are known to be either zero
2755 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2756 /// argument allows us to only collect the known bits that are shared by the
2757 /// requested vector elements.
2758 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2760 const APInt &DemandedElts,
2761 const SelectionDAG &DAG,
2762 unsigned Depth = 0) const;
2764 /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2765 /// Default implementation computes low bits based on alignment
2766 /// information. This should preserve known bits passed into it.
2767 virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2769 const APInt &DemandedElts,
2770 const SelectionDAG &DAG,
2771 unsigned Depth = 0) const;
2773 /// This method can be implemented by targets that want to expose additional
2774 /// information about sign bits to the DAG Combiner. The DemandedElts
2775 /// argument allows us to only collect the minimum sign bits that are shared
2776 /// by the requested vector elements.
2777 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2778 const APInt &DemandedElts,
2779 const SelectionDAG &DAG,
2780 unsigned Depth = 0) const;
2782 /// Attempt to simplify any target nodes based on the demanded vector
2783 /// elements, returning true on success. Otherwise, analyze the expression and
2784 /// return a mask of KnownUndef and KnownZero elements for the expression
2785 /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2786 /// accurate for those bits in the DemandedMask
2787 virtual bool SimplifyDemandedVectorEltsForTargetNode(
2788 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2789 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2791 struct DAGCombinerInfo {
2792 void *DC; // The DAG Combiner object.
2794 bool CalledByLegalizer;
2799 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2800 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2802 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2803 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2804 bool isAfterLegalizeDAG() const {
2805 return Level == AfterLegalizeDAG;
2807 CombineLevel getDAGCombineLevel() { return Level; }
2808 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2810 void AddToWorklist(SDNode *N);
2811 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2812 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2813 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2815 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2818 /// Return if the N is a constant or constant vector equal to the true value
2819 /// from getBooleanContents().
2820 bool isConstTrueVal(const SDNode *N) const;
2822 /// Return if the N is a constant or constant vector equal to the false value
2823 /// from getBooleanContents().
2824 bool isConstFalseVal(const SDNode *N) const;
2826 /// Return if \p N is a True value when extended to \p VT.
2827 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2829 /// Try to simplify a setcc built with the specified operands and cc. If it is
2830 /// unable to simplify it, return a null SDValue.
2831 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2832 bool foldBooleans, DAGCombinerInfo &DCI,
2833 const SDLoc &dl) const;
2835 // For targets which wrap address, unwrap for analysis.
2836 virtual SDValue unwrapAddress(SDValue N) const { return N; }
2838 /// Returns true (and the GlobalValue and the offset) if the node is a
2839 /// GlobalAddress + offset.
2841 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2843 /// This method will be invoked for all target nodes and for any
2844 /// target-independent nodes that the target has registered with invoke it
2847 /// The semantics are as follows:
2849 /// SDValue.Val == 0 - No change was made
2850 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2851 /// otherwise - N should be replaced by the returned Operand.
2853 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2854 /// more complex transformations.
2856 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2858 /// Return true if it is profitable to move a following shift through this
2859 // node, adjusting any immediate operands as necessary to preserve semantics.
2860 // This transformation may not be desirable if it disrupts a particularly
2861 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2862 // By default, it returns true.
2863 virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
2867 // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2868 // to a shuffle and a truncate.
2869 // Example of such a combine:
2870 // v4i32 build_vector((extract_elt V, 1),
2871 // (extract_elt V, 3),
2872 // (extract_elt V, 5),
2873 // (extract_elt V, 7))
2875 // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2876 virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
2877 ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2881 /// Return true if the target has native support for the specified value type
2882 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2883 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2884 /// and some i16 instructions are slow.
2885 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2886 // By default, assume all legal types are desirable.
2887 return isTypeLegal(VT);
2890 /// Return true if it is profitable for dag combiner to transform a floating
2891 /// point op of specified opcode to a equivalent op of an integer
2892 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2893 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2898 /// This method query the target whether it is beneficial for dag combiner to
2899 /// promote the specified node. If true, it should return the desired
2900 /// promotion type by reference.
2901 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2905 /// Return true if the target supports swifterror attribute. It optimizes
2906 /// loads and stores to reading and writing a specific register.
2907 virtual bool supportSwiftError() const {
2911 /// Return true if the target supports that a subset of CSRs for the given
2912 /// machine function is handled explicitly via copies.
2913 virtual bool supportSplitCSR(MachineFunction *MF) const {
2917 /// Perform necessary initialization to handle a subset of CSRs explicitly
2918 /// via copies. This function is called at the beginning of instruction
2920 virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
2921 llvm_unreachable("Not Implemented");
2924 /// Insert explicit copies in entry and exit blocks. We copy a subset of
2925 /// CSRs to virtual registers in the entry block, and copy them back to
2926 /// physical registers in the exit blocks. This function is called at the end
2927 /// of instruction selection.
2928 virtual void insertCopiesSplitCSR(
2929 MachineBasicBlock *Entry,
2930 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2931 llvm_unreachable("Not Implemented");
2934 //===--------------------------------------------------------------------===//
2935 // Lowering methods - These methods must be implemented by targets so that
2936 // the SelectionDAGBuilder code knows how to lower these.
2939 /// This hook must be implemented to lower the incoming (formal) arguments,
2940 /// described by the Ins array, into the specified DAG. The implementation
2941 /// should fill in the InVals array with legal-type argument values, and
2942 /// return the resulting token chain value.
2943 virtual SDValue LowerFormalArguments(
2944 SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
2945 const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
2946 SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
2947 llvm_unreachable("Not Implemented");
2950 /// This structure contains all information that is necessary for lowering
2951 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2952 /// needs to lower a call, and targets will see this struct in their LowerCall
2954 struct CallLoweringInfo {
2956 Type *RetTy = nullptr;
2961 bool DoesNotReturn : 1;
2962 bool IsReturnValueUsed : 1;
2963 bool IsConvergent : 1;
2964 bool IsPatchPoint : 1;
2966 // IsTailCall should be modified by implementations of
2967 // TargetLowering::LowerCall that perform tail call conversions.
2968 bool IsTailCall = false;
2970 // Is Call lowering done post SelectionDAG type legalization.
2971 bool IsPostTypeLegalization = false;
2973 unsigned NumFixedArgs = -1;
2974 CallingConv::ID CallConv = CallingConv::C;
2979 ImmutableCallSite CS;
2980 SmallVector<ISD::OutputArg, 32> Outs;
2981 SmallVector<SDValue, 32> OutVals;
2982 SmallVector<ISD::InputArg, 32> Ins;
2983 SmallVector<SDValue, 4> InVals;
2985 CallLoweringInfo(SelectionDAG &DAG)
2986 : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
2987 DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
2988 IsPatchPoint(false), DAG(DAG) {}
2990 CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
2995 CallLoweringInfo &setChain(SDValue InChain) {
3000 // setCallee with target/module-specific attributes
3001 CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
3002 SDValue Target, ArgListTy &&ArgsList) {
3006 NumFixedArgs = ArgsList.size();
3007 Args = std::move(ArgsList);
3009 DAG.getTargetLoweringInfo().markLibCallAttributes(
3010 &(DAG.getMachineFunction()), CC, Args);
3014 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
3015 SDValue Target, ArgListTy &&ArgsList) {
3019 NumFixedArgs = ArgsList.size();
3020 Args = std::move(ArgsList);
3024 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
3025 SDValue Target, ArgListTy &&ArgsList,
3026 ImmutableCallSite Call) {
3029 IsInReg = Call.hasRetAttr(Attribute::InReg);
3031 Call.doesNotReturn() ||
3032 (!Call.isInvoke() &&
3033 isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3034 IsVarArg = FTy->isVarArg();
3035 IsReturnValueUsed = !Call.getInstruction()->use_empty();
3036 RetSExt = Call.hasRetAttr(Attribute::SExt);
3037 RetZExt = Call.hasRetAttr(Attribute::ZExt);
3041 CallConv = Call.getCallingConv();
3042 NumFixedArgs = FTy->getNumParams();
3043 Args = std::move(ArgsList);
3050 CallLoweringInfo &setInRegister(bool Value = true) {
3055 CallLoweringInfo &setNoReturn(bool Value = true) {
3056 DoesNotReturn = Value;
3060 CallLoweringInfo &setVarArg(bool Value = true) {
3065 CallLoweringInfo &setTailCall(bool Value = true) {
3070 CallLoweringInfo &setDiscardResult(bool Value = true) {
3071 IsReturnValueUsed = !Value;
3075 CallLoweringInfo &setConvergent(bool Value = true) {
3076 IsConvergent = Value;
3080 CallLoweringInfo &setSExtResult(bool Value = true) {
3085 CallLoweringInfo &setZExtResult(bool Value = true) {
3090 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
3091 IsPatchPoint = Value;
3095 CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
3096 IsPostTypeLegalization = Value;
3100 ArgListTy &getArgs() {
3105 /// This function lowers an abstract call to a function into an actual call.
3106 /// This returns a pair of operands. The first element is the return value
3107 /// for the function (if RetTy is not VoidTy). The second element is the
3108 /// outgoing token chain. It calls LowerCall to do the actual lowering.
3109 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3111 /// This hook must be implemented to lower calls into the specified
3112 /// DAG. The outgoing arguments to the call are described by the Outs array,
3113 /// and the values to be returned by the call are described by the Ins
3114 /// array. The implementation should fill in the InVals array with legal-type
3115 /// return values from the call, and return the resulting token chain value.
3117 LowerCall(CallLoweringInfo &/*CLI*/,
3118 SmallVectorImpl<SDValue> &/*InVals*/) const {
3119 llvm_unreachable("Not Implemented");
3122 /// Target-specific cleanup for formal ByVal parameters.
3123 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3125 /// This hook should be implemented to check whether the return values
3126 /// described by the Outs array can fit into the return registers. If false
3127 /// is returned, an sret-demotion is performed.
3128 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3129 MachineFunction &/*MF*/, bool /*isVarArg*/,
3130 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3131 LLVMContext &/*Context*/) const
3133 // Return true by default to get preexisting behavior.
3137 /// This hook must be implemented to lower outgoing return values, described
3138 /// by the Outs array, into the specified DAG. The implementation should
3139 /// return the resulting token chain value.
3140 virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3142 const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3143 const SmallVectorImpl<SDValue> & /*OutVals*/,
3144 const SDLoc & /*dl*/,
3145 SelectionDAG & /*DAG*/) const {
3146 llvm_unreachable("Not Implemented");
3149 /// Return true if result of the specified node is used by a return node
3150 /// only. It also compute and return the input chain for the tail call.
3152 /// This is used to determine whether it is possible to codegen a libcall as
3153 /// tail call at legalization time.
3154 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3158 /// Return true if the target may be able emit the call instruction as a tail
3159 /// call. This is used by optimization passes to determine if it's profitable
3160 /// to duplicate return instructions to enable tailcall optimization.
3161 virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3165 /// Return the builtin name for the __builtin___clear_cache intrinsic
3166 /// Default is to invoke the clear cache library call
3167 virtual const char * getClearCacheBuiltinName() const {
3168 return "__clear_cache";
3171 /// Return the register ID of the name passed in. Used by named register
3172 /// global variables extension. There is no target-independent behaviour
3173 /// so the default action is to bail.
3174 virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3175 SelectionDAG &DAG) const {
3176 report_fatal_error("Named registers not implemented for this target");
3179 /// Return the type that should be used to zero or sign extend a
3180 /// zeroext/signext integer return value. FIXME: Some C calling conventions
3181 /// require the return type to be promoted, but this is not true all the time,
3182 /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3183 /// conventions. The frontend should handle this and include all of the
3184 /// necessary information.
3185 virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3186 ISD::NodeType /*ExtendKind*/) const {
3187 EVT MinVT = getRegisterType(Context, MVT::i32);
3188 return VT.bitsLT(MinVT) ? MinVT : VT;
3191 /// For some targets, an LLVM struct type must be broken down into multiple
3192 /// simple types, but the calling convention specifies that the entire struct
3193 /// must be passed in a block of consecutive registers.
3195 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3196 bool isVarArg) const {
3200 /// Returns a 0 terminated array of registers that can be safely used as
3201 /// scratch registers.
3202 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3206 /// This callback is used to prepare for a volatile or atomic load.
3207 /// It takes a chain node as input and returns the chain for the load itself.
3209 /// Having a callback like this is necessary for targets like SystemZ,
3210 /// which allows a CPU to reuse the result of a previous load indefinitely,
3211 /// even if a cache-coherent store is performed by another CPU. The default
3212 /// implementation does nothing.
3213 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3214 SelectionDAG &DAG) const {
3218 /// This callback is used to inspect load/store instructions and add
3219 /// target-specific MachineMemOperand flags to them. The default
3220 /// implementation does nothing.
3221 virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3222 return MachineMemOperand::MONone;
3225 /// This callback is invoked by the type legalizer to legalize nodes with an
3226 /// illegal operand type but legal result types. It replaces the
3227 /// LowerOperation callback in the type Legalizer. The reason we can not do
3228 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3229 /// use this callback.
3231 /// TODO: Consider merging with ReplaceNodeResults.
3233 /// The target places new result values for the node in Results (their number
3234 /// and types must exactly match those of the original return values of
3235 /// the node), or leaves Results empty, which indicates that the node is not
3236 /// to be custom lowered after all.
3237 /// The default implementation calls LowerOperation.
3238 virtual void LowerOperationWrapper(SDNode *N,
3239 SmallVectorImpl<SDValue> &Results,
3240 SelectionDAG &DAG) const;
3242 /// This callback is invoked for operations that are unsupported by the
3243 /// target, which are registered to use 'custom' lowering, and whose defined
3244 /// values are all legal. If the target has no operations that require custom
3245 /// lowering, it need not implement this. The default implementation of this
3247 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3249 /// This callback is invoked when a node result type is illegal for the
3250 /// target, and the operation was registered to use 'custom' lowering for that
3251 /// result type. The target places new result values for the node in Results
3252 /// (their number and types must exactly match those of the original return
3253 /// values of the node), or leaves Results empty, which indicates that the
3254 /// node is not to be custom lowered after all.
3256 /// If the target has no operations that require custom lowering, it need not
3257 /// implement this. The default implementation aborts.
3258 virtual void ReplaceNodeResults(SDNode * /*N*/,
3259 SmallVectorImpl<SDValue> &/*Results*/,
3260 SelectionDAG &/*DAG*/) const {
3261 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3264 /// This method returns the name of a target specific DAG node.
3265 virtual const char *getTargetNodeName(unsigned Opcode) const;
3267 /// This method returns a target specific FastISel object, or null if the
3268 /// target does not support "fast" ISel.
3269 virtual FastISel *createFastISel(FunctionLoweringInfo &,
3270 const TargetLibraryInfo *) const {
3274 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3275 SelectionDAG &DAG) const;
3277 //===--------------------------------------------------------------------===//
3278 // Inline Asm Support hooks
3281 /// This hook allows the target to expand an inline asm call to be explicit
3282 /// llvm code if it wants to. This is useful for turning simple inline asms
3283 /// into LLVM intrinsics, which gives the compiler more information about the
3284 /// behavior of the code.
3285 virtual bool ExpandInlineAsm(CallInst *) const {
3289 enum ConstraintType {
3290 C_Register, // Constraint represents specific register(s).
3291 C_RegisterClass, // Constraint represents any of register(s) in class.
3292 C_Memory, // Memory constraint.
3293 C_Other, // Something else.
3294 C_Unknown // Unsupported constraint.
3297 enum ConstraintWeight {
3299 CW_Invalid = -1, // No match.
3300 CW_Okay = 0, // Acceptable.
3301 CW_Good = 1, // Good weight.
3302 CW_Better = 2, // Better weight.
3303 CW_Best = 3, // Best weight.
3305 // Well-known weights.
3306 CW_SpecificReg = CW_Okay, // Specific register operands.
3307 CW_Register = CW_Good, // Register operands.
3308 CW_Memory = CW_Better, // Memory operands.
3309 CW_Constant = CW_Best, // Constant operand.
3310 CW_Default = CW_Okay // Default or don't know type.
3313 /// This contains information for each constraint that we are lowering.
3314 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3315 /// This contains the actual string for the code, like "m". TargetLowering
3316 /// picks the 'best' code from ConstraintInfo::Codes that most closely
3317 /// matches the operand.
3318 std::string ConstraintCode;
3320 /// Information about the constraint code, e.g. Register, RegisterClass,
3321 /// Memory, Other, Unknown.
3322 TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3324 /// If this is the result output operand or a clobber, this is null,
3325 /// otherwise it is the incoming operand to the CallInst. This gets
3326 /// modified as the asm is processed.
3327 Value *CallOperandVal = nullptr;
3329 /// The ValueType for the operand value.
3330 MVT ConstraintVT = MVT::Other;
3332 /// Copy constructor for copying from a ConstraintInfo.
3333 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3334 : InlineAsm::ConstraintInfo(std::move(Info)) {}
3336 /// Return true of this is an input operand that is a matching constraint
3338 bool isMatchingInputConstraint() const;
3340 /// If this is an input matching constraint, this method returns the output
3341 /// operand it matches.
3342 unsigned getMatchedOperand() const;
3345 using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3347 /// Split up the constraint string from the inline assembly value into the
3348 /// specific constraints and their prefixes, and also tie in the associated
3349 /// operand values. If this returns an empty vector, and if the constraint
3350 /// string itself isn't empty, there was an error parsing.
3351 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3352 const TargetRegisterInfo *TRI,
3353 ImmutableCallSite CS) const;
3355 /// Examine constraint type and operand type and determine a weight value.
3356 /// The operand object must already have been set up with the operand type.
3357 virtual ConstraintWeight getMultipleConstraintMatchWeight(
3358 AsmOperandInfo &info, int maIndex) const;
3360 /// Examine constraint string and operand type and determine a weight value.
3361 /// The operand object must already have been set up with the operand type.
3362 virtual ConstraintWeight getSingleConstraintMatchWeight(
3363 AsmOperandInfo &info, const char *constraint) const;
3365 /// Determines the constraint code and constraint type to use for the specific
3366 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3367 /// If the actual operand being passed in is available, it can be passed in as
3368 /// Op, otherwise an empty SDValue can be passed.
3369 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3371 SelectionDAG *DAG = nullptr) const;
3373 /// Given a constraint, return the type of constraint it is for this target.
3374 virtual ConstraintType getConstraintType(StringRef Constraint) const;
3376 /// Given a physical register constraint (e.g. {edx}), return the register
3377 /// number and the register class for the register.
3379 /// Given a register class constraint, like 'r', if this corresponds directly
3380 /// to an LLVM register class, return a register of 0 and the register class
3383 /// This should only be used for C_Register constraints. On error, this
3384 /// returns a register number of 0 and a null register class pointer.
3385 virtual std::pair<unsigned, const TargetRegisterClass *>
3386 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3387 StringRef Constraint, MVT VT) const;
3389 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3390 if (ConstraintCode == "i")
3391 return InlineAsm::Constraint_i;
3392 else if (ConstraintCode == "m")
3393 return InlineAsm::Constraint_m;
3394 return InlineAsm::Constraint_Unknown;
3397 /// Try to replace an X constraint, which matches anything, with another that
3398 /// has more specific requirements based on the type of the corresponding
3399 /// operand. This returns null if there is no replacement to make.
3400 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3402 /// Lower the specified operand into the Ops vector. If it is invalid, don't
3403 /// add anything to Ops.
3404 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3405 std::vector<SDValue> &Ops,
3406 SelectionDAG &DAG) const;
3408 //===--------------------------------------------------------------------===//
3409 // Div utility functions
3411 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3412 bool IsAfterLegalization,
3413 std::vector<SDNode *> *Created) const;
3414 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3415 bool IsAfterLegalization,
3416 std::vector<SDNode *> *Created) const;
3418 /// Targets may override this function to provide custom SDIV lowering for
3419 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3420 /// assumes SDIV is expensive and replaces it with a series of other integer
3422 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3424 std::vector<SDNode *> *Created) const;
3426 /// Indicate whether this target prefers to combine FDIVs with the same
3427 /// divisor. If the transform should never be done, return zero. If the
3428 /// transform should be done, return the minimum number of divisor uses
3429 /// that must exist.
3430 virtual unsigned combineRepeatedFPDivisors() const {
3434 /// Hooks for building estimates in place of slower divisions and square
3437 /// Return either a square root or its reciprocal estimate value for the input
3439 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3440 /// 'Enabled' as set by a potential default override attribute.
3441 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3442 /// refinement iterations required to generate a sufficient (though not
3443 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3444 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3445 /// algorithm implementation that uses either one or two constants.
3446 /// The boolean Reciprocal is used to select whether the estimate is for the
3447 /// square root of the input operand or the reciprocal of its square root.
3448 /// A target may choose to implement its own refinement within this function.
3449 /// If that's true, then return '0' as the number of RefinementSteps to avoid
3450 /// any further refinement of the estimate.
3451 /// An empty SDValue return means no estimate sequence can be created.
3452 virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
3453 int Enabled, int &RefinementSteps,
3454 bool &UseOneConstNR, bool Reciprocal) const {
3458 /// Return a reciprocal estimate value for the input operand.
3459 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3460 /// 'Enabled' as set by a potential default override attribute.
3461 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3462 /// refinement iterations required to generate a sufficient (though not
3463 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3464 /// A target may choose to implement its own refinement within this function.
3465 /// If that's true, then return '0' as the number of RefinementSteps to avoid
3466 /// any further refinement of the estimate.
3467 /// An empty SDValue return means no estimate sequence can be created.
3468 virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
3469 int Enabled, int &RefinementSteps) const {
3473 //===--------------------------------------------------------------------===//
3474 // Legalization utility functions
3477 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3478 /// respectively, each computing an n/2-bit part of the result.
3479 /// \param Result A vector that will be filled with the parts of the result
3480 /// in little-endian order.
3481 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3482 /// if you want to control how low bits are extracted from the LHS.
3483 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3484 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3485 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3486 /// \returns true if the node has been expanded, false if it has not
3487 bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3488 SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3489 SelectionDAG &DAG, MulExpansionKind Kind,
3490 SDValue LL = SDValue(), SDValue LH = SDValue(),
3491 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3493 /// Expand a MUL into two nodes. One that computes the high bits of
3494 /// the result and one that computes the low bits.
3495 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3496 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3497 /// if you want to control how low bits are extracted from the LHS.
3498 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3499 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3500 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3501 /// \returns true if the node has been expanded. false if it has not
3502 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3503 SelectionDAG &DAG, MulExpansionKind Kind,
3504 SDValue LL = SDValue(), SDValue LH = SDValue(),
3505 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3507 /// Expand float(f32) to SINT(i64) conversion
3508 /// \param N Node to expand
3509 /// \param Result output after conversion
3510 /// \returns True, if the expansion was successful, false otherwise
3511 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3513 /// Turn load of vector type into a load of the individual elements.
3514 /// \param LD load to expand
3515 /// \returns MERGE_VALUEs of the scalar loads with their chains.
3516 SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3518 // Turn a store of a vector type into stores of the individual elements.
3519 /// \param ST Store with a vector value type
3520 /// \returns MERGE_VALUs of the individual store chains.
3521 SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3523 /// Expands an unaligned load to 2 half-size loads for an integer, and
3524 /// possibly more for vectors.
3525 std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3526 SelectionDAG &DAG) const;
3528 /// Expands an unaligned store to 2 half-size stores for integer values, and
3529 /// possibly more for vectors.
3530 SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3532 /// Increments memory address \p Addr according to the type of the value
3533 /// \p DataVT that should be stored. If the data is stored in compressed
3534 /// form, the memory address should be incremented according to the number of
3535 /// the stored elements. This number is equal to the number of '1's bits
3537 /// \p DataVT is a vector type. \p Mask is a vector value.
3538 /// \p DataVT and \p Mask have the same number of vector elements.
3539 SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3540 EVT DataVT, SelectionDAG &DAG,
3541 bool IsCompressedMemory) const;
3543 /// Get a pointer to vector element \p Idx located in memory for a vector of
3544 /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3545 /// bounds the returned pointer is unspecified, but will be within the vector
3547 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3550 //===--------------------------------------------------------------------===//
3551 // Instruction Emitting Hooks
3554 /// This method should be implemented by targets that mark instructions with
3555 /// the 'usesCustomInserter' flag. These instructions are special in various
3556 /// ways, which require special support to insert. The specified MachineInstr
3557 /// is created but not inserted into any basic blocks, and this method is
3558 /// called to expand it into a sequence of instructions, potentially also
3559 /// creating new basic blocks and control flow.
3560 /// As long as the returned basic block is different (i.e., we created a new
3561 /// one), the custom inserter is free to modify the rest of \p MBB.
3562 virtual MachineBasicBlock *
3563 EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3565 /// This method should be implemented by targets that mark instructions with
3566 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3567 /// instruction selection by target hooks. e.g. To fill in optional defs for
3568 /// ARM 's' setting instructions.
3569 virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3570 SDNode *Node) const;
3572 /// If this function returns true, SelectionDAGBuilder emits a
3573 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3574 virtual bool useLoadStackGuardNode() const {
3578 virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
3579 const SDLoc &DL) const {
3580 llvm_unreachable("not implemented for this target");
3583 /// Lower TLS global address SDNode for target independent emulated TLS model.
3584 virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3585 SelectionDAG &DAG) const;
3587 /// Expands target specific indirect branch for the case of JumpTable
3589 virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
3590 SelectionDAG &DAG) const {
3591 return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3594 // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3595 // If we're comparing for equality to zero and isCtlzFast is true, expose the
3596 // fact that this can be implemented as a ctlz/srl pair, so that the dag
3597 // combiner can fold the new nodes.
3598 SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3601 SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3602 ISD::CondCode Cond, DAGCombinerInfo &DCI,
3603 const SDLoc &DL) const;
3606 /// Given an LLVM IR type and return type attributes, compute the return value
3607 /// EVTs and flags, and optionally also the offsets, if the return value is
3608 /// being lowered to memory.
3609 void GetReturnInfo(Type *ReturnType, AttributeList attr,
3610 SmallVectorImpl<ISD::OutputArg> &Outs,
3611 const TargetLowering &TLI, const DataLayout &DL);
3613 } // end namespace llvm
3615 #endif // LLVM_CODEGEN_TARGETLOWERING_H