1 2009-09-21 Ben Elliston <bje@au.ibm.com>
3 * ppc.h (PPC_OPCODE_PPCA2): New.
5 2009-09-05 Martin Thuresson <martin@mtme.org>
7 * ia64.h (struct ia64_operand): Renamed member class to op_class.
9 2009-08-29 Martin Thuresson <martin@mtme.org>
11 * tic30.h (template): Rename type template to
12 insn_template. Updated code to use new name.
13 * tic54x.h (template): Rename type template to
16 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
18 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
20 2009-06-11 Anthony Green <green@moxielogic.com>
22 * moxie.h (MOXIE_F3_PCREL): Define.
23 (moxie_form3_opc_info): Grow.
25 2009-06-06 Anthony Green <green@moxielogic.com>
27 * moxie.h (MOXIE_F1_M): Define.
29 2009-04-15 Anthony Green <green@moxielogic.com>
33 2009-04-06 DJ Delorie <dj@redhat.com>
35 * h8300.h: Add relaxation attributes to MOVA opcodes.
37 2009-03-10 Alan Modra <amodra@bigpond.net.au>
39 * ppc.h (ppc_parse_cpu): Declare.
41 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
43 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
44 and _IMM11 for mbitclr and mbitset.
45 * score-datadep.h: Update dependency information.
47 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
49 * ppc.h (PPC_OPCODE_POWER7): New.
51 2009-02-06 Doug Evans <dje@google.com>
53 * i386.h: Add comment regarding sse* insns and prefixes.
55 2009-02-03 Sandip Matte <sandip@rmicorp.com>
57 * mips.h (INSN_XLR): Define.
58 (INSN_CHIP_MASK): Update.
60 (OPCODE_IS_MEMBER): Update.
61 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
63 2009-01-28 Doug Evans <dje@google.com>
65 * opcode/i386.h: Add multiple inclusion protection.
66 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
67 (EDI_REG_NUM): New macros.
68 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
69 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
70 (REX_PREFIX_P): New macro.
72 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
74 * ppc.h (struct powerpc_opcode): New field "deprecated".
75 (PPC_OPCODE_NOPOWER4): Delete.
77 2008-11-28 Joshua Kinard <kumba@gentoo.org>
79 * mips.h: Define CPU_R14000, CPU_R16000.
80 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
82 2008-11-18 Catherine Moore <clm@codesourcery.com>
84 * arm.h (FPU_NEON_FP16): New.
85 (FPU_ARCH_NEON_FP16): New.
87 2008-11-06 Chao-ying Fu <fu@mips.com>
89 * mips.h: Doucument '1' for 5-bit sync type.
91 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
93 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
96 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
98 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
100 2008-07-30 Michael J. Eager <eager@eagercon.com>
102 * ppc.h (PPC_OPCODE_405): Define.
103 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
105 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
107 * ppc.h (ppc_cpu_t): New typedef.
108 (struct powerpc_opcode <flags>): Use it.
109 (struct powerpc_operand <insert, extract>): Likewise.
110 (struct powerpc_macro <flags>): Likewise.
112 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
114 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
115 Update comment before MIPS16 field descriptors to mention MIPS16.
116 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
118 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
119 New bit masks and shift counts for cins and exts.
121 * mips.h: Document new field descriptors +Q.
122 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
124 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
126 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
127 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
129 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
131 * ppc.h: (PPC_OPCODE_E500MC): New.
133 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
135 * i386.h (MAX_OPERANDS): Set to 5.
136 (MAX_MNEM_SIZE): Changed to 20.
138 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
140 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
142 2008-03-09 Paul Brook <paul@codesourcery.com>
144 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
146 2008-03-04 Paul Brook <paul@codesourcery.com>
148 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
149 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
150 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
152 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
153 Nick Clifton <nickc@redhat.com>
156 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
157 with a 32-bit displacement but without the top bit of the 4th byte
160 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
162 * cr16.h (cr16_num_optab): Declared.
164 2008-02-14 Hakan Ardo <hakan@debian.org>
167 * avr.h (AVR_ISA_2xxe): Define.
169 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
171 * mips.h: Update copyright.
172 (INSN_CHIP_MASK): New macro.
173 (INSN_OCTEON): New macro.
174 (CPU_OCTEON): New macro.
175 (OPCODE_IS_MEMBER): Handle Octeon instructions.
177 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
179 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
181 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
183 * avr.h (AVR_ISA_USB162): Add new opcode set.
184 (AVR_ISA_AVR3): Likewise.
186 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
188 * mips.h (INSN_LOONGSON_2E): New.
189 (INSN_LOONGSON_2F): New.
190 (CPU_LOONGSON_2E): New.
191 (CPU_LOONGSON_2F): New.
192 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
194 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
196 * mips.h (INSN_ISA*): Redefine certain values as an
197 enumeration. Update comments.
198 (mips_isa_table): New.
199 (ISA_MIPS*): Redefine to match enumeration.
200 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
203 2007-08-08 Ben Elliston <bje@au.ibm.com>
205 * ppc.h (PPC_OPCODE_PPCPS): New.
207 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
209 * m68k.h: Document j K & E.
211 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
213 * cr16.h: New file for CR16 target.
215 2007-05-02 Alan Modra <amodra@bigpond.net.au>
217 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
219 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
221 * m68k.h (mcfisa_c): New.
222 (mcfusp, mcf_mask): Adjust.
224 2007-04-20 Alan Modra <amodra@bigpond.net.au>
226 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
227 (num_powerpc_operands): Declare.
228 (PPC_OPERAND_SIGNED et al): Redefine as hex.
229 (PPC_OPERAND_PLUS1): Define.
231 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
233 * i386.h (REX_MODE64): Renamed to ...
235 (REX_EXTX): Renamed to ...
237 (REX_EXTY): Renamed to ...
239 (REX_EXTZ): Renamed to ...
242 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
244 * i386.h: Add entries from config/tc-i386.h and move tables
245 to opcodes/i386-opc.h.
247 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
249 * i386.h (FloatDR): Removed.
250 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
252 2007-03-01 Alan Modra <amodra@bigpond.net.au>
254 * spu-insns.h: Add soma double-float insns.
256 2007-02-20 Thiemo Seufer <ths@mips.com>
257 Chao-Ying Fu <fu@mips.com>
259 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
260 (INSN_DSPR2): Add flag for DSP R2 instructions.
261 (M_BALIGN): New macro.
263 2007-02-14 Alan Modra <amodra@bigpond.net.au>
265 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
266 and Seg3ShortFrom with Shortform.
268 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
271 * i386.h (i386_optab): Put the real "test" before the pseudo
274 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
276 * m68k.h (m68010up): OR fido_a.
278 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
280 * m68k.h (fido_a): New.
282 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
284 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
285 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
288 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
290 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
292 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
294 * score-inst.h (enum score_insn_type): Add Insn_internal.
296 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
297 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
298 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
299 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
300 Alan Modra <amodra@bigpond.net.au>
302 * spu-insns.h: New file.
305 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
307 * ppc.h (PPC_OPCODE_CELL): Define.
309 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
311 * i386.h : Modify opcode to support for the change in POPCNT opcode
312 in amdfam10 architecture.
314 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
316 * i386.h: Replace CpuMNI with CpuSSSE3.
318 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
319 Joseph Myers <joseph@codesourcery.com>
320 Ian Lance Taylor <ian@wasabisystems.com>
321 Ben Elliston <bje@wasabisystems.com>
323 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
325 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
327 * score-datadep.h: New file.
328 * score-inst.h: New file.
330 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
332 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
333 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
336 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
337 Michael Meissner <michael.meissner@amd.com>
339 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
341 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
343 * i386.h (i386_optab): Add "nop" with memory reference.
345 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
347 * i386.h (i386_optab): Update comment for 64bit NOP.
349 2006-06-06 Ben Elliston <bje@au.ibm.com>
350 Anton Blanchard <anton@samba.org>
352 * ppc.h (PPC_OPCODE_POWER6): Define.
355 2006-06-05 Thiemo Seufer <ths@mips.com>
357 * mips.h: Improve description of MT flags.
359 2006-05-25 Richard Sandiford <richard@codesourcery.com>
361 * m68k.h (mcf_mask): Define.
363 2006-05-05 Thiemo Seufer <ths@mips.com>
364 David Ung <davidu@mips.com>
366 * mips.h (enum): Add macro M_CACHE_AB.
368 2006-05-04 Thiemo Seufer <ths@mips.com>
369 Nigel Stephens <nigel@mips.com>
370 David Ung <davidu@mips.com>
372 * mips.h: Add INSN_SMARTMIPS define.
374 2006-04-30 Thiemo Seufer <ths@mips.com>
375 David Ung <davidu@mips.com>
377 * mips.h: Defines udi bits and masks. Add description of
378 characters which may appear in the args field of udi
381 2006-04-26 Thiemo Seufer <ths@networkno.de>
383 * mips.h: Improve comments describing the bitfield instruction
386 2006-04-26 Julian Brown <julian@codesourcery.com>
388 * arm.h (FPU_VFP_EXT_V3): Define constant.
389 (FPU_NEON_EXT_V1): Likewise.
390 (FPU_VFP_HARD): Update.
391 (FPU_VFP_V3): Define macro.
392 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
394 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
396 * avr.h (AVR_ISA_PWMx): New.
398 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
400 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
401 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
402 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
403 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
404 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
406 2006-03-10 Paul Brook <paul@codesourcery.com>
408 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
410 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
412 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
413 first. Correct mask of bb "B" opcode.
415 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
417 * i386.h (i386_optab): Support Intel Merom New Instructions.
419 2006-02-24 Paul Brook <paul@codesourcery.com>
421 * arm.h: Add V7 feature bits.
423 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
425 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
427 2006-01-31 Paul Brook <paul@codesourcery.com>
428 Richard Earnshaw <rearnsha@arm.com>
430 * arm.h: Use ARM_CPU_FEATURE.
431 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
432 (arm_feature_set): Change to a structure.
433 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
434 ARM_FEATURE): New macros.
436 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
438 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
439 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
440 (ADD_PC_INCR_OPCODE): Don't define.
442 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
445 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
447 2005-11-14 David Ung <davidu@mips.com>
449 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
450 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
451 save/restore encoding of the args field.
453 2005-10-28 Dave Brolley <brolley@redhat.com>
455 Contribute the following changes:
456 2005-02-16 Dave Brolley <brolley@redhat.com>
458 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
459 cgen_isa_mask_* to cgen_bitset_*.
462 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
464 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
465 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
466 (CGEN_CPU_TABLE): Make isas a ponter.
468 2003-09-29 Dave Brolley <brolley@redhat.com>
470 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
471 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
472 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
474 2002-12-13 Dave Brolley <brolley@redhat.com>
476 * cgen.h (symcat.h): #include it.
477 (cgen-bitset.h): #include it.
478 (CGEN_ATTR_VALUE_TYPE): Now a union.
479 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
480 (CGEN_ATTR_ENTRY): 'value' now unsigned.
481 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
482 * cgen-bitset.h: New file.
484 2005-09-30 Catherine Moore <clm@cm00re.com>
488 2005-10-24 Jan Beulich <jbeulich@novell.com>
490 * ia64.h (enum ia64_opnd): Move memory operand out of set of
493 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
495 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
496 Add FLAG_STRICT to pa10 ftest opcode.
498 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
500 * hppa.h (pa_opcodes): Remove lha entries.
502 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
504 * hppa.h (FLAG_STRICT): Revise comment.
505 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
506 before corresponding pa11 opcodes. Add strict pa10 register-immediate
509 2005-09-30 Catherine Moore <clm@cm00re.com>
513 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
515 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
517 2005-09-06 Chao-ying Fu <fu@mips.com>
519 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
520 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
522 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
523 (INSN_ASE_MASK): Update to include INSN_MT.
524 (INSN_MT): New define for MT ASE.
526 2005-08-25 Chao-ying Fu <fu@mips.com>
528 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
529 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
530 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
531 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
532 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
533 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
535 (INSN_DSP): New define for DSP ASE.
537 2005-08-18 Alan Modra <amodra@bigpond.net.au>
541 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
543 * ppc.h (PPC_OPCODE_E300): Define.
545 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
547 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
549 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
552 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
555 2005-07-27 Jan Beulich <jbeulich@novell.com>
557 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
558 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
559 Add movq-s as 64-bit variants of movd-s.
561 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
563 * hppa.h: Fix punctuation in comment.
565 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
566 implicit space-register addressing. Set space-register bits on opcodes
567 using implicit space-register addressing. Add various missing pa20
568 long-immediate opcodes. Remove various opcodes using implicit 3-bit
569 space-register addressing. Use "fE" instead of "fe" in various
572 2005-07-18 Jan Beulich <jbeulich@novell.com>
574 * i386.h (i386_optab): Operands of aam and aad are unsigned.
576 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
578 * i386.h (i386_optab): Support Intel VMX Instructions.
580 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
582 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
584 2005-07-05 Jan Beulich <jbeulich@novell.com>
586 * i386.h (i386_optab): Add new insns.
588 2005-07-01 Nick Clifton <nickc@redhat.com>
590 * sparc.h: Add typedefs to structure declarations.
592 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
595 * i386.h (i386_optab): Update comments for 64bit addressing on
596 mov. Allow 64bit addressing for mov and movq.
598 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
600 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
601 respectively, in various floating-point load and store patterns.
603 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
605 * hppa.h (FLAG_STRICT): Correct comment.
606 (pa_opcodes): Update load and store entries to allow both PA 1.X and
607 PA 2.0 mneumonics when equivalent. Entries with cache control
608 completers now require PA 1.1. Adjust whitespace.
610 2005-05-19 Anton Blanchard <anton@samba.org>
612 * ppc.h (PPC_OPCODE_POWER5): Define.
614 2005-05-10 Nick Clifton <nickc@redhat.com>
616 * Update the address and phone number of the FSF organization in
617 the GPL notices in the following files:
618 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
619 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
620 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
621 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
622 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
623 tic54x.h, tic80.h, v850.h, vax.h
625 2005-05-09 Jan Beulich <jbeulich@novell.com>
627 * i386.h (i386_optab): Add ht and hnt.
629 2005-04-18 Mark Kettenis <kettenis@gnu.org>
631 * i386.h: Insert hyphens into selected VIA PadLock extensions.
632 Add xcrypt-ctr. Provide aliases without hyphens.
634 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
636 Moved from ../ChangeLog
638 2005-04-12 Paul Brook <paul@codesourcery.com>
639 * m88k.h: Rename psr macros to avoid conflicts.
641 2005-03-12 Zack Weinberg <zack@codesourcery.com>
642 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
643 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
646 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
647 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
648 Remove redundant instruction types.
649 (struct argument): X_op - new field.
650 (struct cst4_entry): Remove.
651 (no_op_insn): Declare.
653 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
654 * crx.h (enum argtype): Rename types, remove unused types.
656 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
657 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
658 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
659 (enum operand_type): Rearrange operands, edit comments.
660 replace us<N> with ui<N> for unsigned immediate.
661 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
662 displacements (respectively).
663 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
664 (instruction type): Add NO_TYPE_INS.
665 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
666 (operand_entry): New field - 'flags'.
667 (operand flags): New.
669 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
670 * crx.h (operand_type): Remove redundant types i3, i4,
672 Add new unsigned immediate types us3, us4, us5, us16.
674 2005-04-12 Mark Kettenis <kettenis@gnu.org>
676 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
677 adjust them accordingly.
679 2005-04-01 Jan Beulich <jbeulich@novell.com>
681 * i386.h (i386_optab): Add rdtscp.
683 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
685 * i386.h (i386_optab): Don't allow the `l' suffix for moving
686 between memory and segment register. Allow movq for moving between
687 general-purpose register and segment register.
689 2005-02-09 Jan Beulich <jbeulich@novell.com>
692 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
693 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
696 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
698 * m68k.h (m68008, m68ec030, m68882): Remove.
700 (cpu_m68k, cpu_cf): New.
701 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
702 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
704 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
706 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
707 * cgen.h (enum cgen_parse_operand_type): Add
708 CGEN_PARSE_OPERAND_SYMBOLIC.
710 2005-01-21 Fred Fish <fnf@specifixinc.com>
712 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
713 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
714 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
716 2005-01-19 Fred Fish <fnf@specifixinc.com>
718 * mips.h (struct mips_opcode): Add new pinfo2 member.
719 (INSN_ALIAS): New define for opcode table entries that are
720 specific instances of another entry, such as 'move' for an 'or'
722 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
723 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
725 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
727 * mips.h (CPU_RM9000): Define.
728 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
730 2004-11-25 Jan Beulich <jbeulich@novell.com>
732 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
733 to/from test registers are illegal in 64-bit mode. Add missing
734 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
735 (previously one had to explicitly encode a rex64 prefix). Re-enable
736 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
737 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
739 2004-11-23 Jan Beulich <jbeulich@novell.com>
741 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
742 available only with SSE2. Change the MMX additions introduced by SSE
743 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
744 instructions by their now designated identifier (since combining i686
745 and 3DNow! does not really imply 3DNow!A).
747 2004-11-19 Alan Modra <amodra@bigpond.net.au>
749 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
750 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
752 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
753 Vineet Sharma <vineets@noida.hcltech.com>
755 * maxq.h: New file: Disassembly information for the maxq port.
757 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
759 * i386.h (i386_optab): Put back "movzb".
761 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
763 * cris.h (enum cris_insn_version_usage): Tweak formatting and
764 comments. Remove member cris_ver_sim. Add members
765 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
766 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
767 (struct cris_support_reg, struct cris_cond15): New types.
768 (cris_conds15): Declare.
769 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
770 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
771 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
772 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
773 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
776 2004-11-04 Jan Beulich <jbeulich@novell.com>
778 * i386.h (sldx_Suf): Remove.
779 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
780 (q_FP): Define, implying no REX64.
781 (x_FP, sl_FP): Imply FloatMF.
782 (i386_optab): Split reg and mem forms of moving from segment registers
783 so that the memory forms can ignore the 16-/32-bit operand size
784 distinction. Adjust a few others for Intel mode. Remove *FP uses from
785 all non-floating-point instructions. Unite 32- and 64-bit forms of
786 movsx, movzx, and movd. Adjust floating point operations for the above
787 changes to the *FP macros. Add DefaultSize to floating point control
788 insns operating on larger memory ranges. Remove left over comments
789 hinting at certain insns being Intel-syntax ones where the ones
790 actually meant are already gone.
792 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
794 * crx.h: Add COPS_REG_INS - Coprocessor Special register
797 2004-09-30 Paul Brook <paul@codesourcery.com>
799 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
800 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
802 2004-09-11 Theodore A. Roth <troth@openavr.org>
804 * avr.h: Add support for
805 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
807 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
809 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
811 2004-08-24 Dmitry Diky <diwil@spec.ru>
813 * msp430.h (msp430_opc): Add new instructions.
814 (msp430_rcodes): Declare new instructions.
815 (msp430_hcodes): Likewise..
817 2004-08-13 Nick Clifton <nickc@redhat.com>
820 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
823 2004-08-30 Michal Ludvig <mludvig@suse.cz>
825 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
827 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
829 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
831 2004-07-21 Jan Beulich <jbeulich@novell.com>
833 * i386.h: Adjust instruction descriptions to better match the
836 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
838 * arm.h: Remove all old content. Replace with architecture defines
839 from gas/config/tc-arm.c.
841 2004-07-09 Andreas Schwab <schwab@suse.de>
843 * m68k.h: Fix comment.
845 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
849 2004-06-24 Alan Modra <amodra@bigpond.net.au>
851 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
853 2004-05-24 Peter Barada <peter@the-baradas.com>
855 * m68k.h: Add 'size' to m68k_opcode.
857 2004-05-05 Peter Barada <peter@the-baradas.com>
859 * m68k.h: Switch from ColdFire chip name to core variant.
861 2004-04-22 Peter Barada <peter@the-baradas.com>
863 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
864 descriptions for new EMAC cases.
865 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
866 handle Motorola MAC syntax.
867 Allow disassembly of ColdFire V4e object files.
869 2004-03-16 Alan Modra <amodra@bigpond.net.au>
871 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
873 2004-03-12 Jakub Jelinek <jakub@redhat.com>
875 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
877 2004-03-12 Michal Ludvig <mludvig@suse.cz>
879 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
881 2004-03-12 Michal Ludvig <mludvig@suse.cz>
883 * i386.h (i386_optab): Added xstore/xcrypt insns.
885 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
887 * h8300.h (32bit ldc/stc): Add relaxing support.
889 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
891 * h8300.h (BITOP): Pass MEMRELAX flag.
893 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
895 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
898 For older changes see ChangeLog-9103
904 version-control: never