1 2008-07-30 Michael J. Eager <eager@eagercon.com>
3 * ppc.h (PPC_OPCODE_405): Define.
4 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
6 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
8 * ppc.h (ppc_cpu_t): New typedef.
9 (struct powerpc_opcode <flags>): Use it.
10 (struct powerpc_operand <insert, extract>): Likewise.
11 (struct powerpc_macro <flags>): Likewise.
13 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
15 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
16 Update comment before MIPS16 field descriptors to mention MIPS16.
17 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
19 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
20 New bit masks and shift counts for cins and exts.
22 * mips.h: Document new field descriptors +Q.
23 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
25 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
27 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
28 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
30 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
32 * ppc.h: (PPC_OPCODE_E500MC): New.
34 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
36 * i386.h (MAX_OPERANDS): Set to 5.
37 (MAX_MNEM_SIZE): Changed to 20.
39 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
41 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
43 2008-03-09 Paul Brook <paul@codesourcery.com>
45 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
47 2008-03-04 Paul Brook <paul@codesourcery.com>
49 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
50 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
51 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
53 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
54 Nick Clifton <nickc@redhat.com>
57 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
58 with a 32-bit displacement but without the top bit of the 4th byte
61 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
63 * cr16.h (cr16_num_optab): Declared.
65 2008-02-14 Hakan Ardo <hakan@debian.org>
68 * avr.h (AVR_ISA_2xxe): Define.
70 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
72 * mips.h: Update copyright.
73 (INSN_CHIP_MASK): New macro.
74 (INSN_OCTEON): New macro.
75 (CPU_OCTEON): New macro.
76 (OPCODE_IS_MEMBER): Handle Octeon instructions.
78 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
80 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
82 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
84 * avr.h (AVR_ISA_USB162): Add new opcode set.
85 (AVR_ISA_AVR3): Likewise.
87 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
89 * mips.h (INSN_LOONGSON_2E): New.
90 (INSN_LOONGSON_2F): New.
91 (CPU_LOONGSON_2E): New.
92 (CPU_LOONGSON_2F): New.
93 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
95 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
97 * mips.h (INSN_ISA*): Redefine certain values as an
98 enumeration. Update comments.
99 (mips_isa_table): New.
100 (ISA_MIPS*): Redefine to match enumeration.
101 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
104 2007-08-08 Ben Elliston <bje@au.ibm.com>
106 * ppc.h (PPC_OPCODE_PPCPS): New.
108 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
110 * m68k.h: Document j K & E.
112 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
114 * cr16.h: New file for CR16 target.
116 2007-05-02 Alan Modra <amodra@bigpond.net.au>
118 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
120 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
122 * m68k.h (mcfisa_c): New.
123 (mcfusp, mcf_mask): Adjust.
125 2007-04-20 Alan Modra <amodra@bigpond.net.au>
127 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
128 (num_powerpc_operands): Declare.
129 (PPC_OPERAND_SIGNED et al): Redefine as hex.
130 (PPC_OPERAND_PLUS1): Define.
132 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
134 * i386.h (REX_MODE64): Renamed to ...
136 (REX_EXTX): Renamed to ...
138 (REX_EXTY): Renamed to ...
140 (REX_EXTZ): Renamed to ...
143 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
145 * i386.h: Add entries from config/tc-i386.h and move tables
146 to opcodes/i386-opc.h.
148 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
150 * i386.h (FloatDR): Removed.
151 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
153 2007-03-01 Alan Modra <amodra@bigpond.net.au>
155 * spu-insns.h: Add soma double-float insns.
157 2007-02-20 Thiemo Seufer <ths@mips.com>
158 Chao-Ying Fu <fu@mips.com>
160 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
161 (INSN_DSPR2): Add flag for DSP R2 instructions.
162 (M_BALIGN): New macro.
164 2007-02-14 Alan Modra <amodra@bigpond.net.au>
166 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
167 and Seg3ShortFrom with Shortform.
169 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
172 * i386.h (i386_optab): Put the real "test" before the pseudo
175 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
177 * m68k.h (m68010up): OR fido_a.
179 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
181 * m68k.h (fido_a): New.
183 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
185 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
186 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
189 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
191 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
193 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
195 * score-inst.h (enum score_insn_type): Add Insn_internal.
197 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
198 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
199 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
200 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
201 Alan Modra <amodra@bigpond.net.au>
203 * spu-insns.h: New file.
206 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
208 * ppc.h (PPC_OPCODE_CELL): Define.
210 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
212 * i386.h : Modify opcode to support for the change in POPCNT opcode
213 in amdfam10 architecture.
215 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
217 * i386.h: Replace CpuMNI with CpuSSSE3.
219 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
220 Joseph Myers <joseph@codesourcery.com>
221 Ian Lance Taylor <ian@wasabisystems.com>
222 Ben Elliston <bje@wasabisystems.com>
224 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
226 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
228 * score-datadep.h: New file.
229 * score-inst.h: New file.
231 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
233 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
234 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
237 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
238 Michael Meissner <michael.meissner@amd.com>
240 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
242 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
244 * i386.h (i386_optab): Add "nop" with memory reference.
246 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
248 * i386.h (i386_optab): Update comment for 64bit NOP.
250 2006-06-06 Ben Elliston <bje@au.ibm.com>
251 Anton Blanchard <anton@samba.org>
253 * ppc.h (PPC_OPCODE_POWER6): Define.
256 2006-06-05 Thiemo Seufer <ths@mips.com>
258 * mips.h: Improve description of MT flags.
260 2006-05-25 Richard Sandiford <richard@codesourcery.com>
262 * m68k.h (mcf_mask): Define.
264 2006-05-05 Thiemo Seufer <ths@mips.com>
265 David Ung <davidu@mips.com>
267 * mips.h (enum): Add macro M_CACHE_AB.
269 2006-05-04 Thiemo Seufer <ths@mips.com>
270 Nigel Stephens <nigel@mips.com>
271 David Ung <davidu@mips.com>
273 * mips.h: Add INSN_SMARTMIPS define.
275 2006-04-30 Thiemo Seufer <ths@mips.com>
276 David Ung <davidu@mips.com>
278 * mips.h: Defines udi bits and masks. Add description of
279 characters which may appear in the args field of udi
282 2006-04-26 Thiemo Seufer <ths@networkno.de>
284 * mips.h: Improve comments describing the bitfield instruction
287 2006-04-26 Julian Brown <julian@codesourcery.com>
289 * arm.h (FPU_VFP_EXT_V3): Define constant.
290 (FPU_NEON_EXT_V1): Likewise.
291 (FPU_VFP_HARD): Update.
292 (FPU_VFP_V3): Define macro.
293 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
295 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
297 * avr.h (AVR_ISA_PWMx): New.
299 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
301 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
302 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
303 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
304 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
305 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
307 2006-03-10 Paul Brook <paul@codesourcery.com>
309 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
311 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
313 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
314 first. Correct mask of bb "B" opcode.
316 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
318 * i386.h (i386_optab): Support Intel Merom New Instructions.
320 2006-02-24 Paul Brook <paul@codesourcery.com>
322 * arm.h: Add V7 feature bits.
324 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
326 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
328 2006-01-31 Paul Brook <paul@codesourcery.com>
329 Richard Earnshaw <rearnsha@arm.com>
331 * arm.h: Use ARM_CPU_FEATURE.
332 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
333 (arm_feature_set): Change to a structure.
334 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
335 ARM_FEATURE): New macros.
337 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
339 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
340 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
341 (ADD_PC_INCR_OPCODE): Don't define.
343 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
346 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
348 2005-11-14 David Ung <davidu@mips.com>
350 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
351 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
352 save/restore encoding of the args field.
354 2005-10-28 Dave Brolley <brolley@redhat.com>
356 Contribute the following changes:
357 2005-02-16 Dave Brolley <brolley@redhat.com>
359 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
360 cgen_isa_mask_* to cgen_bitset_*.
363 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
365 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
366 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
367 (CGEN_CPU_TABLE): Make isas a ponter.
369 2003-09-29 Dave Brolley <brolley@redhat.com>
371 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
372 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
373 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
375 2002-12-13 Dave Brolley <brolley@redhat.com>
377 * cgen.h (symcat.h): #include it.
378 (cgen-bitset.h): #include it.
379 (CGEN_ATTR_VALUE_TYPE): Now a union.
380 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
381 (CGEN_ATTR_ENTRY): 'value' now unsigned.
382 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
383 * cgen-bitset.h: New file.
385 2005-09-30 Catherine Moore <clm@cm00re.com>
389 2005-10-24 Jan Beulich <jbeulich@novell.com>
391 * ia64.h (enum ia64_opnd): Move memory operand out of set of
394 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
396 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
397 Add FLAG_STRICT to pa10 ftest opcode.
399 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
401 * hppa.h (pa_opcodes): Remove lha entries.
403 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
405 * hppa.h (FLAG_STRICT): Revise comment.
406 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
407 before corresponding pa11 opcodes. Add strict pa10 register-immediate
410 2005-09-30 Catherine Moore <clm@cm00re.com>
414 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
416 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
418 2005-09-06 Chao-ying Fu <fu@mips.com>
420 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
421 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
423 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
424 (INSN_ASE_MASK): Update to include INSN_MT.
425 (INSN_MT): New define for MT ASE.
427 2005-08-25 Chao-ying Fu <fu@mips.com>
429 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
430 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
431 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
432 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
433 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
434 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
436 (INSN_DSP): New define for DSP ASE.
438 2005-08-18 Alan Modra <amodra@bigpond.net.au>
442 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
444 * ppc.h (PPC_OPCODE_E300): Define.
446 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
448 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
450 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
453 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
456 2005-07-27 Jan Beulich <jbeulich@novell.com>
458 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
459 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
460 Add movq-s as 64-bit variants of movd-s.
462 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
464 * hppa.h: Fix punctuation in comment.
466 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
467 implicit space-register addressing. Set space-register bits on opcodes
468 using implicit space-register addressing. Add various missing pa20
469 long-immediate opcodes. Remove various opcodes using implicit 3-bit
470 space-register addressing. Use "fE" instead of "fe" in various
473 2005-07-18 Jan Beulich <jbeulich@novell.com>
475 * i386.h (i386_optab): Operands of aam and aad are unsigned.
477 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
479 * i386.h (i386_optab): Support Intel VMX Instructions.
481 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
483 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
485 2005-07-05 Jan Beulich <jbeulich@novell.com>
487 * i386.h (i386_optab): Add new insns.
489 2005-07-01 Nick Clifton <nickc@redhat.com>
491 * sparc.h: Add typedefs to structure declarations.
493 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
496 * i386.h (i386_optab): Update comments for 64bit addressing on
497 mov. Allow 64bit addressing for mov and movq.
499 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
501 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
502 respectively, in various floating-point load and store patterns.
504 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
506 * hppa.h (FLAG_STRICT): Correct comment.
507 (pa_opcodes): Update load and store entries to allow both PA 1.X and
508 PA 2.0 mneumonics when equivalent. Entries with cache control
509 completers now require PA 1.1. Adjust whitespace.
511 2005-05-19 Anton Blanchard <anton@samba.org>
513 * ppc.h (PPC_OPCODE_POWER5): Define.
515 2005-05-10 Nick Clifton <nickc@redhat.com>
517 * Update the address and phone number of the FSF organization in
518 the GPL notices in the following files:
519 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
520 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
521 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
522 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
523 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
524 tic54x.h, tic80.h, v850.h, vax.h
526 2005-05-09 Jan Beulich <jbeulich@novell.com>
528 * i386.h (i386_optab): Add ht and hnt.
530 2005-04-18 Mark Kettenis <kettenis@gnu.org>
532 * i386.h: Insert hyphens into selected VIA PadLock extensions.
533 Add xcrypt-ctr. Provide aliases without hyphens.
535 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
537 Moved from ../ChangeLog
539 2005-04-12 Paul Brook <paul@codesourcery.com>
540 * m88k.h: Rename psr macros to avoid conflicts.
542 2005-03-12 Zack Weinberg <zack@codesourcery.com>
543 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
544 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
547 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
548 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
549 Remove redundant instruction types.
550 (struct argument): X_op - new field.
551 (struct cst4_entry): Remove.
552 (no_op_insn): Declare.
554 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
555 * crx.h (enum argtype): Rename types, remove unused types.
557 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
558 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
559 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
560 (enum operand_type): Rearrange operands, edit comments.
561 replace us<N> with ui<N> for unsigned immediate.
562 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
563 displacements (respectively).
564 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
565 (instruction type): Add NO_TYPE_INS.
566 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
567 (operand_entry): New field - 'flags'.
568 (operand flags): New.
570 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
571 * crx.h (operand_type): Remove redundant types i3, i4,
573 Add new unsigned immediate types us3, us4, us5, us16.
575 2005-04-12 Mark Kettenis <kettenis@gnu.org>
577 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
578 adjust them accordingly.
580 2005-04-01 Jan Beulich <jbeulich@novell.com>
582 * i386.h (i386_optab): Add rdtscp.
584 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
586 * i386.h (i386_optab): Don't allow the `l' suffix for moving
587 between memory and segment register. Allow movq for moving between
588 general-purpose register and segment register.
590 2005-02-09 Jan Beulich <jbeulich@novell.com>
593 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
594 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
597 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
599 * m68k.h (m68008, m68ec030, m68882): Remove.
601 (cpu_m68k, cpu_cf): New.
602 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
603 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
605 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
607 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
608 * cgen.h (enum cgen_parse_operand_type): Add
609 CGEN_PARSE_OPERAND_SYMBOLIC.
611 2005-01-21 Fred Fish <fnf@specifixinc.com>
613 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
614 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
615 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
617 2005-01-19 Fred Fish <fnf@specifixinc.com>
619 * mips.h (struct mips_opcode): Add new pinfo2 member.
620 (INSN_ALIAS): New define for opcode table entries that are
621 specific instances of another entry, such as 'move' for an 'or'
623 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
624 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
626 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
628 * mips.h (CPU_RM9000): Define.
629 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
631 2004-11-25 Jan Beulich <jbeulich@novell.com>
633 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
634 to/from test registers are illegal in 64-bit mode. Add missing
635 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
636 (previously one had to explicitly encode a rex64 prefix). Re-enable
637 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
638 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
640 2004-11-23 Jan Beulich <jbeulich@novell.com>
642 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
643 available only with SSE2. Change the MMX additions introduced by SSE
644 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
645 instructions by their now designated identifier (since combining i686
646 and 3DNow! does not really imply 3DNow!A).
648 2004-11-19 Alan Modra <amodra@bigpond.net.au>
650 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
651 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
653 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
654 Vineet Sharma <vineets@noida.hcltech.com>
656 * maxq.h: New file: Disassembly information for the maxq port.
658 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
660 * i386.h (i386_optab): Put back "movzb".
662 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
664 * cris.h (enum cris_insn_version_usage): Tweak formatting and
665 comments. Remove member cris_ver_sim. Add members
666 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
667 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
668 (struct cris_support_reg, struct cris_cond15): New types.
669 (cris_conds15): Declare.
670 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
671 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
672 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
673 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
674 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
677 2004-11-04 Jan Beulich <jbeulich@novell.com>
679 * i386.h (sldx_Suf): Remove.
680 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
681 (q_FP): Define, implying no REX64.
682 (x_FP, sl_FP): Imply FloatMF.
683 (i386_optab): Split reg and mem forms of moving from segment registers
684 so that the memory forms can ignore the 16-/32-bit operand size
685 distinction. Adjust a few others for Intel mode. Remove *FP uses from
686 all non-floating-point instructions. Unite 32- and 64-bit forms of
687 movsx, movzx, and movd. Adjust floating point operations for the above
688 changes to the *FP macros. Add DefaultSize to floating point control
689 insns operating on larger memory ranges. Remove left over comments
690 hinting at certain insns being Intel-syntax ones where the ones
691 actually meant are already gone.
693 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
695 * crx.h: Add COPS_REG_INS - Coprocessor Special register
698 2004-09-30 Paul Brook <paul@codesourcery.com>
700 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
701 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
703 2004-09-11 Theodore A. Roth <troth@openavr.org>
705 * avr.h: Add support for
706 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
708 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
710 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
712 2004-08-24 Dmitry Diky <diwil@spec.ru>
714 * msp430.h (msp430_opc): Add new instructions.
715 (msp430_rcodes): Declare new instructions.
716 (msp430_hcodes): Likewise..
718 2004-08-13 Nick Clifton <nickc@redhat.com>
721 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
724 2004-08-30 Michal Ludvig <mludvig@suse.cz>
726 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
728 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
730 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
732 2004-07-21 Jan Beulich <jbeulich@novell.com>
734 * i386.h: Adjust instruction descriptions to better match the
737 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
739 * arm.h: Remove all old content. Replace with architecture defines
740 from gas/config/tc-arm.c.
742 2004-07-09 Andreas Schwab <schwab@suse.de>
744 * m68k.h: Fix comment.
746 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
750 2004-06-24 Alan Modra <amodra@bigpond.net.au>
752 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
754 2004-05-24 Peter Barada <peter@the-baradas.com>
756 * m68k.h: Add 'size' to m68k_opcode.
758 2004-05-05 Peter Barada <peter@the-baradas.com>
760 * m68k.h: Switch from ColdFire chip name to core variant.
762 2004-04-22 Peter Barada <peter@the-baradas.com>
764 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
765 descriptions for new EMAC cases.
766 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
767 handle Motorola MAC syntax.
768 Allow disassembly of ColdFire V4e object files.
770 2004-03-16 Alan Modra <amodra@bigpond.net.au>
772 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
774 2004-03-12 Jakub Jelinek <jakub@redhat.com>
776 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
778 2004-03-12 Michal Ludvig <mludvig@suse.cz>
780 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
782 2004-03-12 Michal Ludvig <mludvig@suse.cz>
784 * i386.h (i386_optab): Added xstore/xcrypt insns.
786 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
788 * h8300.h (32bit ldc/stc): Add relaxing support.
790 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
792 * h8300.h (BITOP): Pass MEMRELAX flag.
794 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
796 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
799 For older changes see ChangeLog-9103
805 version-control: never