1 2009-04-06 DJ Delorie <dj@redhat.com>
3 * h8300.h: Add relaxation attributes to MOVA opcodes.
5 2009-03-10 Alan Modra <amodra@bigpond.net.au>
7 * ppc.h (ppc_parse_cpu): Declare.
9 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
11 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
12 and _IMM11 for mbitclr and mbitset.
13 * score-datadep.h: Update dependency information.
15 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
17 * ppc.h (PPC_OPCODE_POWER7): New.
19 2009-02-06 Doug Evans <dje@google.com>
21 * i386.h: Add comment regarding sse* insns and prefixes.
23 2009-02-03 Sandip Matte <sandip@rmicorp.com>
25 * mips.h (INSN_XLR): Define.
26 (INSN_CHIP_MASK): Update.
28 (OPCODE_IS_MEMBER): Update.
29 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
31 2009-01-28 Doug Evans <dje@google.com>
33 * opcode/i386.h: Add multiple inclusion protection.
34 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
35 (EDI_REG_NUM): New macros.
36 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
37 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
38 (REX_PREFIX_P): New macro.
40 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
42 * ppc.h (struct powerpc_opcode): New field "deprecated".
43 (PPC_OPCODE_NOPOWER4): Delete.
45 2008-11-28 Joshua Kinard <kumba@gentoo.org>
47 * mips.h: Define CPU_R14000, CPU_R16000.
48 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
50 2008-11-18 Catherine Moore <clm@codesourcery.com>
52 * arm.h (FPU_NEON_FP16): New.
53 (FPU_ARCH_NEON_FP16): New.
55 2008-11-06 Chao-ying Fu <fu@mips.com>
57 * mips.h: Doucument '1' for 5-bit sync type.
59 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
61 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
64 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
66 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
68 2008-07-30 Michael J. Eager <eager@eagercon.com>
70 * ppc.h (PPC_OPCODE_405): Define.
71 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
73 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
75 * ppc.h (ppc_cpu_t): New typedef.
76 (struct powerpc_opcode <flags>): Use it.
77 (struct powerpc_operand <insert, extract>): Likewise.
78 (struct powerpc_macro <flags>): Likewise.
80 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
82 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
83 Update comment before MIPS16 field descriptors to mention MIPS16.
84 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
86 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
87 New bit masks and shift counts for cins and exts.
89 * mips.h: Document new field descriptors +Q.
90 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
92 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
94 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
95 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
97 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
99 * ppc.h: (PPC_OPCODE_E500MC): New.
101 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
103 * i386.h (MAX_OPERANDS): Set to 5.
104 (MAX_MNEM_SIZE): Changed to 20.
106 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
108 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
110 2008-03-09 Paul Brook <paul@codesourcery.com>
112 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
114 2008-03-04 Paul Brook <paul@codesourcery.com>
116 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
117 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
118 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
120 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
121 Nick Clifton <nickc@redhat.com>
124 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
125 with a 32-bit displacement but without the top bit of the 4th byte
128 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
130 * cr16.h (cr16_num_optab): Declared.
132 2008-02-14 Hakan Ardo <hakan@debian.org>
135 * avr.h (AVR_ISA_2xxe): Define.
137 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
139 * mips.h: Update copyright.
140 (INSN_CHIP_MASK): New macro.
141 (INSN_OCTEON): New macro.
142 (CPU_OCTEON): New macro.
143 (OPCODE_IS_MEMBER): Handle Octeon instructions.
145 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
147 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
149 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
151 * avr.h (AVR_ISA_USB162): Add new opcode set.
152 (AVR_ISA_AVR3): Likewise.
154 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
156 * mips.h (INSN_LOONGSON_2E): New.
157 (INSN_LOONGSON_2F): New.
158 (CPU_LOONGSON_2E): New.
159 (CPU_LOONGSON_2F): New.
160 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
162 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
164 * mips.h (INSN_ISA*): Redefine certain values as an
165 enumeration. Update comments.
166 (mips_isa_table): New.
167 (ISA_MIPS*): Redefine to match enumeration.
168 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
171 2007-08-08 Ben Elliston <bje@au.ibm.com>
173 * ppc.h (PPC_OPCODE_PPCPS): New.
175 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
177 * m68k.h: Document j K & E.
179 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
181 * cr16.h: New file for CR16 target.
183 2007-05-02 Alan Modra <amodra@bigpond.net.au>
185 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
187 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
189 * m68k.h (mcfisa_c): New.
190 (mcfusp, mcf_mask): Adjust.
192 2007-04-20 Alan Modra <amodra@bigpond.net.au>
194 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
195 (num_powerpc_operands): Declare.
196 (PPC_OPERAND_SIGNED et al): Redefine as hex.
197 (PPC_OPERAND_PLUS1): Define.
199 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
201 * i386.h (REX_MODE64): Renamed to ...
203 (REX_EXTX): Renamed to ...
205 (REX_EXTY): Renamed to ...
207 (REX_EXTZ): Renamed to ...
210 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
212 * i386.h: Add entries from config/tc-i386.h and move tables
213 to opcodes/i386-opc.h.
215 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
217 * i386.h (FloatDR): Removed.
218 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
220 2007-03-01 Alan Modra <amodra@bigpond.net.au>
222 * spu-insns.h: Add soma double-float insns.
224 2007-02-20 Thiemo Seufer <ths@mips.com>
225 Chao-Ying Fu <fu@mips.com>
227 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
228 (INSN_DSPR2): Add flag for DSP R2 instructions.
229 (M_BALIGN): New macro.
231 2007-02-14 Alan Modra <amodra@bigpond.net.au>
233 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
234 and Seg3ShortFrom with Shortform.
236 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
239 * i386.h (i386_optab): Put the real "test" before the pseudo
242 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
244 * m68k.h (m68010up): OR fido_a.
246 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
248 * m68k.h (fido_a): New.
250 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
252 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
253 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
256 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
258 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
260 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
262 * score-inst.h (enum score_insn_type): Add Insn_internal.
264 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
265 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
266 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
267 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
268 Alan Modra <amodra@bigpond.net.au>
270 * spu-insns.h: New file.
273 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
275 * ppc.h (PPC_OPCODE_CELL): Define.
277 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
279 * i386.h : Modify opcode to support for the change in POPCNT opcode
280 in amdfam10 architecture.
282 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
284 * i386.h: Replace CpuMNI with CpuSSSE3.
286 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
287 Joseph Myers <joseph@codesourcery.com>
288 Ian Lance Taylor <ian@wasabisystems.com>
289 Ben Elliston <bje@wasabisystems.com>
291 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
293 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
295 * score-datadep.h: New file.
296 * score-inst.h: New file.
298 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
300 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
301 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
304 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
305 Michael Meissner <michael.meissner@amd.com>
307 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
309 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
311 * i386.h (i386_optab): Add "nop" with memory reference.
313 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
315 * i386.h (i386_optab): Update comment for 64bit NOP.
317 2006-06-06 Ben Elliston <bje@au.ibm.com>
318 Anton Blanchard <anton@samba.org>
320 * ppc.h (PPC_OPCODE_POWER6): Define.
323 2006-06-05 Thiemo Seufer <ths@mips.com>
325 * mips.h: Improve description of MT flags.
327 2006-05-25 Richard Sandiford <richard@codesourcery.com>
329 * m68k.h (mcf_mask): Define.
331 2006-05-05 Thiemo Seufer <ths@mips.com>
332 David Ung <davidu@mips.com>
334 * mips.h (enum): Add macro M_CACHE_AB.
336 2006-05-04 Thiemo Seufer <ths@mips.com>
337 Nigel Stephens <nigel@mips.com>
338 David Ung <davidu@mips.com>
340 * mips.h: Add INSN_SMARTMIPS define.
342 2006-04-30 Thiemo Seufer <ths@mips.com>
343 David Ung <davidu@mips.com>
345 * mips.h: Defines udi bits and masks. Add description of
346 characters which may appear in the args field of udi
349 2006-04-26 Thiemo Seufer <ths@networkno.de>
351 * mips.h: Improve comments describing the bitfield instruction
354 2006-04-26 Julian Brown <julian@codesourcery.com>
356 * arm.h (FPU_VFP_EXT_V3): Define constant.
357 (FPU_NEON_EXT_V1): Likewise.
358 (FPU_VFP_HARD): Update.
359 (FPU_VFP_V3): Define macro.
360 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
362 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
364 * avr.h (AVR_ISA_PWMx): New.
366 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
368 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
369 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
370 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
371 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
372 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
374 2006-03-10 Paul Brook <paul@codesourcery.com>
376 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
378 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
380 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
381 first. Correct mask of bb "B" opcode.
383 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
385 * i386.h (i386_optab): Support Intel Merom New Instructions.
387 2006-02-24 Paul Brook <paul@codesourcery.com>
389 * arm.h: Add V7 feature bits.
391 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
393 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
395 2006-01-31 Paul Brook <paul@codesourcery.com>
396 Richard Earnshaw <rearnsha@arm.com>
398 * arm.h: Use ARM_CPU_FEATURE.
399 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
400 (arm_feature_set): Change to a structure.
401 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
402 ARM_FEATURE): New macros.
404 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
406 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
407 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
408 (ADD_PC_INCR_OPCODE): Don't define.
410 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
413 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
415 2005-11-14 David Ung <davidu@mips.com>
417 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
418 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
419 save/restore encoding of the args field.
421 2005-10-28 Dave Brolley <brolley@redhat.com>
423 Contribute the following changes:
424 2005-02-16 Dave Brolley <brolley@redhat.com>
426 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
427 cgen_isa_mask_* to cgen_bitset_*.
430 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
432 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
433 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
434 (CGEN_CPU_TABLE): Make isas a ponter.
436 2003-09-29 Dave Brolley <brolley@redhat.com>
438 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
439 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
440 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
442 2002-12-13 Dave Brolley <brolley@redhat.com>
444 * cgen.h (symcat.h): #include it.
445 (cgen-bitset.h): #include it.
446 (CGEN_ATTR_VALUE_TYPE): Now a union.
447 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
448 (CGEN_ATTR_ENTRY): 'value' now unsigned.
449 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
450 * cgen-bitset.h: New file.
452 2005-09-30 Catherine Moore <clm@cm00re.com>
456 2005-10-24 Jan Beulich <jbeulich@novell.com>
458 * ia64.h (enum ia64_opnd): Move memory operand out of set of
461 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
463 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
464 Add FLAG_STRICT to pa10 ftest opcode.
466 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
468 * hppa.h (pa_opcodes): Remove lha entries.
470 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
472 * hppa.h (FLAG_STRICT): Revise comment.
473 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
474 before corresponding pa11 opcodes. Add strict pa10 register-immediate
477 2005-09-30 Catherine Moore <clm@cm00re.com>
481 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
483 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
485 2005-09-06 Chao-ying Fu <fu@mips.com>
487 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
488 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
490 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
491 (INSN_ASE_MASK): Update to include INSN_MT.
492 (INSN_MT): New define for MT ASE.
494 2005-08-25 Chao-ying Fu <fu@mips.com>
496 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
497 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
498 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
499 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
500 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
501 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
503 (INSN_DSP): New define for DSP ASE.
505 2005-08-18 Alan Modra <amodra@bigpond.net.au>
509 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
511 * ppc.h (PPC_OPCODE_E300): Define.
513 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
515 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
517 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
520 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
523 2005-07-27 Jan Beulich <jbeulich@novell.com>
525 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
526 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
527 Add movq-s as 64-bit variants of movd-s.
529 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
531 * hppa.h: Fix punctuation in comment.
533 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
534 implicit space-register addressing. Set space-register bits on opcodes
535 using implicit space-register addressing. Add various missing pa20
536 long-immediate opcodes. Remove various opcodes using implicit 3-bit
537 space-register addressing. Use "fE" instead of "fe" in various
540 2005-07-18 Jan Beulich <jbeulich@novell.com>
542 * i386.h (i386_optab): Operands of aam and aad are unsigned.
544 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
546 * i386.h (i386_optab): Support Intel VMX Instructions.
548 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
550 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
552 2005-07-05 Jan Beulich <jbeulich@novell.com>
554 * i386.h (i386_optab): Add new insns.
556 2005-07-01 Nick Clifton <nickc@redhat.com>
558 * sparc.h: Add typedefs to structure declarations.
560 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
563 * i386.h (i386_optab): Update comments for 64bit addressing on
564 mov. Allow 64bit addressing for mov and movq.
566 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
568 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
569 respectively, in various floating-point load and store patterns.
571 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
573 * hppa.h (FLAG_STRICT): Correct comment.
574 (pa_opcodes): Update load and store entries to allow both PA 1.X and
575 PA 2.0 mneumonics when equivalent. Entries with cache control
576 completers now require PA 1.1. Adjust whitespace.
578 2005-05-19 Anton Blanchard <anton@samba.org>
580 * ppc.h (PPC_OPCODE_POWER5): Define.
582 2005-05-10 Nick Clifton <nickc@redhat.com>
584 * Update the address and phone number of the FSF organization in
585 the GPL notices in the following files:
586 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
587 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
588 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
589 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
590 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
591 tic54x.h, tic80.h, v850.h, vax.h
593 2005-05-09 Jan Beulich <jbeulich@novell.com>
595 * i386.h (i386_optab): Add ht and hnt.
597 2005-04-18 Mark Kettenis <kettenis@gnu.org>
599 * i386.h: Insert hyphens into selected VIA PadLock extensions.
600 Add xcrypt-ctr. Provide aliases without hyphens.
602 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
604 Moved from ../ChangeLog
606 2005-04-12 Paul Brook <paul@codesourcery.com>
607 * m88k.h: Rename psr macros to avoid conflicts.
609 2005-03-12 Zack Weinberg <zack@codesourcery.com>
610 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
611 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
614 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
615 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
616 Remove redundant instruction types.
617 (struct argument): X_op - new field.
618 (struct cst4_entry): Remove.
619 (no_op_insn): Declare.
621 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
622 * crx.h (enum argtype): Rename types, remove unused types.
624 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
625 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
626 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
627 (enum operand_type): Rearrange operands, edit comments.
628 replace us<N> with ui<N> for unsigned immediate.
629 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
630 displacements (respectively).
631 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
632 (instruction type): Add NO_TYPE_INS.
633 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
634 (operand_entry): New field - 'flags'.
635 (operand flags): New.
637 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
638 * crx.h (operand_type): Remove redundant types i3, i4,
640 Add new unsigned immediate types us3, us4, us5, us16.
642 2005-04-12 Mark Kettenis <kettenis@gnu.org>
644 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
645 adjust them accordingly.
647 2005-04-01 Jan Beulich <jbeulich@novell.com>
649 * i386.h (i386_optab): Add rdtscp.
651 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
653 * i386.h (i386_optab): Don't allow the `l' suffix for moving
654 between memory and segment register. Allow movq for moving between
655 general-purpose register and segment register.
657 2005-02-09 Jan Beulich <jbeulich@novell.com>
660 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
661 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
664 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
666 * m68k.h (m68008, m68ec030, m68882): Remove.
668 (cpu_m68k, cpu_cf): New.
669 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
670 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
672 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
674 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
675 * cgen.h (enum cgen_parse_operand_type): Add
676 CGEN_PARSE_OPERAND_SYMBOLIC.
678 2005-01-21 Fred Fish <fnf@specifixinc.com>
680 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
681 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
682 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
684 2005-01-19 Fred Fish <fnf@specifixinc.com>
686 * mips.h (struct mips_opcode): Add new pinfo2 member.
687 (INSN_ALIAS): New define for opcode table entries that are
688 specific instances of another entry, such as 'move' for an 'or'
690 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
691 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
693 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
695 * mips.h (CPU_RM9000): Define.
696 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
698 2004-11-25 Jan Beulich <jbeulich@novell.com>
700 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
701 to/from test registers are illegal in 64-bit mode. Add missing
702 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
703 (previously one had to explicitly encode a rex64 prefix). Re-enable
704 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
705 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
707 2004-11-23 Jan Beulich <jbeulich@novell.com>
709 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
710 available only with SSE2. Change the MMX additions introduced by SSE
711 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
712 instructions by their now designated identifier (since combining i686
713 and 3DNow! does not really imply 3DNow!A).
715 2004-11-19 Alan Modra <amodra@bigpond.net.au>
717 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
718 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
720 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
721 Vineet Sharma <vineets@noida.hcltech.com>
723 * maxq.h: New file: Disassembly information for the maxq port.
725 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
727 * i386.h (i386_optab): Put back "movzb".
729 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
731 * cris.h (enum cris_insn_version_usage): Tweak formatting and
732 comments. Remove member cris_ver_sim. Add members
733 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
734 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
735 (struct cris_support_reg, struct cris_cond15): New types.
736 (cris_conds15): Declare.
737 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
738 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
739 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
740 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
741 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
744 2004-11-04 Jan Beulich <jbeulich@novell.com>
746 * i386.h (sldx_Suf): Remove.
747 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
748 (q_FP): Define, implying no REX64.
749 (x_FP, sl_FP): Imply FloatMF.
750 (i386_optab): Split reg and mem forms of moving from segment registers
751 so that the memory forms can ignore the 16-/32-bit operand size
752 distinction. Adjust a few others for Intel mode. Remove *FP uses from
753 all non-floating-point instructions. Unite 32- and 64-bit forms of
754 movsx, movzx, and movd. Adjust floating point operations for the above
755 changes to the *FP macros. Add DefaultSize to floating point control
756 insns operating on larger memory ranges. Remove left over comments
757 hinting at certain insns being Intel-syntax ones where the ones
758 actually meant are already gone.
760 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
762 * crx.h: Add COPS_REG_INS - Coprocessor Special register
765 2004-09-30 Paul Brook <paul@codesourcery.com>
767 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
768 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
770 2004-09-11 Theodore A. Roth <troth@openavr.org>
772 * avr.h: Add support for
773 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
775 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
777 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
779 2004-08-24 Dmitry Diky <diwil@spec.ru>
781 * msp430.h (msp430_opc): Add new instructions.
782 (msp430_rcodes): Declare new instructions.
783 (msp430_hcodes): Likewise..
785 2004-08-13 Nick Clifton <nickc@redhat.com>
788 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
791 2004-08-30 Michal Ludvig <mludvig@suse.cz>
793 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
795 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
797 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
799 2004-07-21 Jan Beulich <jbeulich@novell.com>
801 * i386.h: Adjust instruction descriptions to better match the
804 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
806 * arm.h: Remove all old content. Replace with architecture defines
807 from gas/config/tc-arm.c.
809 2004-07-09 Andreas Schwab <schwab@suse.de>
811 * m68k.h: Fix comment.
813 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
817 2004-06-24 Alan Modra <amodra@bigpond.net.au>
819 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
821 2004-05-24 Peter Barada <peter@the-baradas.com>
823 * m68k.h: Add 'size' to m68k_opcode.
825 2004-05-05 Peter Barada <peter@the-baradas.com>
827 * m68k.h: Switch from ColdFire chip name to core variant.
829 2004-04-22 Peter Barada <peter@the-baradas.com>
831 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
832 descriptions for new EMAC cases.
833 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
834 handle Motorola MAC syntax.
835 Allow disassembly of ColdFire V4e object files.
837 2004-03-16 Alan Modra <amodra@bigpond.net.au>
839 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
841 2004-03-12 Jakub Jelinek <jakub@redhat.com>
843 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
845 2004-03-12 Michal Ludvig <mludvig@suse.cz>
847 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
849 2004-03-12 Michal Ludvig <mludvig@suse.cz>
851 * i386.h (i386_optab): Added xstore/xcrypt insns.
853 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
855 * h8300.h (32bit ldc/stc): Add relaxing support.
857 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
859 * h8300.h (BITOP): Pass MEMRELAX flag.
861 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
863 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
866 For older changes see ChangeLog-9103
872 version-control: never