1 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
3 * i386.h (i386_optab): Support Intel VMX Instructions.
5 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
7 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
9 2005-07-05 Jan Beulich <jbeulich@novell.com>
11 * i386.h (i386_optab): Add new insns.
13 2005-07-01 Nick Clifton <nickc@redhat.com>
15 * sparc.h: Add typedefs to structure declarations.
17 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
20 * i386.h (i386_optab): Update comments for 64bit addressing on
21 mov. Allow 64bit addressing for mov and movq.
23 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
25 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
26 respectively, in various floating-point load and store patterns.
28 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
30 * hppa.h (FLAG_STRICT): Correct comment.
31 (pa_opcodes): Update load and store entries to allow both PA 1.X and
32 PA 2.0 mneumonics when equivalent. Entries with cache control
33 completers now require PA 1.1. Adjust whitespace.
35 2005-05-19 Anton Blanchard <anton@samba.org>
37 * ppc.h (PPC_OPCODE_POWER5): Define.
39 2005-05-10 Nick Clifton <nickc@redhat.com>
41 * Update the address and phone number of the FSF organization in
42 the GPL notices in the following files:
43 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
44 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
45 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
46 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
47 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
48 tic54x.h, tic80.h, v850.h, vax.h
50 2005-05-09 Jan Beulich <jbeulich@novell.com>
52 * i386.h (i386_optab): Add ht and hnt.
54 2005-04-18 Mark Kettenis <kettenis@gnu.org>
56 * i386.h: Insert hyphens into selected VIA PadLock extensions.
57 Add xcrypt-ctr. Provide aliases without hyphens.
59 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
61 Moved from ../ChangeLog
63 2005-04-12 Paul Brook <paul@codesourcery.com>
64 * m88k.h: Rename psr macros to avoid conflicts.
66 2005-03-12 Zack Weinberg <zack@codesourcery.com>
67 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
68 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
71 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
72 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
73 Remove redundant instruction types.
74 (struct argument): X_op - new field.
75 (struct cst4_entry): Remove.
76 (no_op_insn): Declare.
78 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
79 * crx.h (enum argtype): Rename types, remove unused types.
81 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
82 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
83 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
84 (enum operand_type): Rearrange operands, edit comments.
85 replace us<N> with ui<N> for unsigned immediate.
86 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
87 displacements (respectively).
88 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
89 (instruction type): Add NO_TYPE_INS.
90 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
91 (operand_entry): New field - 'flags'.
94 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
95 * crx.h (operand_type): Remove redundant types i3, i4,
97 Add new unsigned immediate types us3, us4, us5, us16.
99 2005-04-12 Mark Kettenis <kettenis@gnu.org>
101 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
102 adjust them accordingly.
104 2005-04-01 Jan Beulich <jbeulich@novell.com>
106 * i386.h (i386_optab): Add rdtscp.
108 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
110 * i386.h (i386_optab): Don't allow the `l' suffix for moving
111 between memory and segment register. Allow movq for moving between
112 general-purpose register and segment register.
114 2005-02-09 Jan Beulich <jbeulich@novell.com>
117 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
118 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
121 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
123 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
124 * cgen.h (enum cgen_parse_operand_type): Add
125 CGEN_PARSE_OPERAND_SYMBOLIC.
127 2005-01-21 Fred Fish <fnf@specifixinc.com>
129 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
130 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
131 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
133 2005-01-19 Fred Fish <fnf@specifixinc.com>
135 * mips.h (struct mips_opcode): Add new pinfo2 member.
136 (INSN_ALIAS): New define for opcode table entries that are
137 specific instances of another entry, such as 'move' for an 'or'
139 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
140 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
142 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
144 * mips.h (CPU_RM9000): Define.
145 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
147 2004-11-25 Jan Beulich <jbeulich@novell.com>
149 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
150 to/from test registers are illegal in 64-bit mode. Add missing
151 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
152 (previously one had to explicitly encode a rex64 prefix). Re-enable
153 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
154 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
156 2004-11-23 Jan Beulich <jbeulich@novell.com>
158 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
159 available only with SSE2. Change the MMX additions introduced by SSE
160 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
161 instructions by their now designated identifier (since combining i686
162 and 3DNow! does not really imply 3DNow!A).
164 2004-11-19 Alan Modra <amodra@bigpond.net.au>
166 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
167 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
169 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
170 Vineet Sharma <vineets@noida.hcltech.com>
172 * maxq.h: New file: Disassembly information for the maxq port.
174 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
176 * i386.h (i386_optab): Put back "movzb".
178 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
180 * cris.h (enum cris_insn_version_usage): Tweak formatting and
181 comments. Remove member cris_ver_sim. Add members
182 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
183 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
184 (struct cris_support_reg, struct cris_cond15): New types.
185 (cris_conds15): Declare.
186 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
187 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
188 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
189 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
190 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
193 2004-11-04 Jan Beulich <jbeulich@novell.com>
195 * i386.h (sldx_Suf): Remove.
196 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
197 (q_FP): Define, implying no REX64.
198 (x_FP, sl_FP): Imply FloatMF.
199 (i386_optab): Split reg and mem forms of moving from segment registers
200 so that the memory forms can ignore the 16-/32-bit operand size
201 distinction. Adjust a few others for Intel mode. Remove *FP uses from
202 all non-floating-point instructions. Unite 32- and 64-bit forms of
203 movsx, movzx, and movd. Adjust floating point operations for the above
204 changes to the *FP macros. Add DefaultSize to floating point control
205 insns operating on larger memory ranges. Remove left over comments
206 hinting at certain insns being Intel-syntax ones where the ones
207 actually meant are already gone.
209 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
211 * crx.h: Add COPS_REG_INS - Coprocessor Special register
214 2004-09-30 Paul Brook <paul@codesourcery.com>
216 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
217 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
219 2004-09-11 Theodore A. Roth <troth@openavr.org>
221 * avr.h: Add support for
222 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
224 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
226 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
228 2004-08-24 Dmitry Diky <diwil@spec.ru>
230 * msp430.h (msp430_opc): Add new instructions.
231 (msp430_rcodes): Declare new instructions.
232 (msp430_hcodes): Likewise..
234 2004-08-13 Nick Clifton <nickc@redhat.com>
237 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
240 2004-08-30 Michal Ludvig <mludvig@suse.cz>
242 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
244 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
246 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
248 2004-07-21 Jan Beulich <jbeulich@novell.com>
250 * i386.h: Adjust instruction descriptions to better match the
253 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
255 * arm.h: Remove all old content. Replace with architecture defines
256 from gas/config/tc-arm.c.
258 2004-07-09 Andreas Schwab <schwab@suse.de>
260 * m68k.h: Fix comment.
262 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
266 2004-06-24 Alan Modra <amodra@bigpond.net.au>
268 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
270 2004-05-24 Peter Barada <peter@the-baradas.com>
272 * m68k.h: Add 'size' to m68k_opcode.
274 2004-05-05 Peter Barada <peter@the-baradas.com>
276 * m68k.h: Switch from ColdFire chip name to core variant.
278 2004-04-22 Peter Barada <peter@the-baradas.com>
280 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
281 descriptions for new EMAC cases.
282 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
283 handle Motorola MAC syntax.
284 Allow disassembly of ColdFire V4e object files.
286 2004-03-16 Alan Modra <amodra@bigpond.net.au>
288 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
290 2004-03-12 Jakub Jelinek <jakub@redhat.com>
292 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
294 2004-03-12 Michal Ludvig <mludvig@suse.cz>
296 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
298 2004-03-12 Michal Ludvig <mludvig@suse.cz>
300 * i386.h (i386_optab): Added xstore/xcrypt insns.
302 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
304 * h8300.h (32bit ldc/stc): Add relaxing support.
306 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
308 * h8300.h (BITOP): Pass MEMRELAX flag.
310 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
312 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
315 For older changes see ChangeLog-9103
321 version-control: never