1 /* Header file for targets using CGEN: Cpu tools GENerator.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009
4 Free Software Foundation, Inc.
6 This file is part of GDB, the GNU debugger, and the GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License along
19 with this program; if not, write to the Free Software Foundation, Inc.,
20 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
26 #include "cgen/bitset.h"
28 /* ??? This file requires bfd.h but only to get bfd_vma.
29 Seems like an awful lot to require just to get such a fundamental type.
30 Perhaps the definition of bfd_vma can be moved outside of bfd.h.
31 Or perhaps one could duplicate its definition in another file.
32 Until such time, this file conditionally compiles definitions that require
33 bfd_vma using __BFD_H_SEEN__. */
35 /* Enums must be defined before they can be used.
36 Allow them to be used in struct definitions, even though the enum must
38 If CGEN_ARCH isn't defined, this file is being included by something other
39 than <arch>-desc.h. */
41 /* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S.
42 The lack of spaces in the arg list is important for non-stdc systems.
43 This file is included by <arch>-desc.h.
44 It can be included independently of <arch>-desc.h, in which case the arch
45 dependent portions will be declared as "unknown_cgen_foo". */
48 #define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s)
51 /* This file contains the static (unchanging) pieces and as much other stuff
52 as we can reasonably put here. It's generally cleaner to put stuff here
53 rather than having it machine generated if possible. */
55 /* The assembler syntax is made up of expressions (duh...).
56 At the lowest level the values are mnemonics, register names, numbers, etc.
57 Above that are subexpressions, if any (an example might be the
58 "effective address" in m68k cpus). Subexpressions are wip.
59 At the second highest level are the insns themselves. Above that are
60 pseudo-insns, synthetic insns, and macros, if any. */
62 /* Lots of cpu's have a fixed insn size, or one which rarely changes,
63 and it's generally easier to handle these by treating the insn as an
64 integer type, rather than an array of characters. So we allow targets
65 to control this. When an integer type the value is in host byte order,
66 when an array of characters the value is in target byte order. */
68 typedef unsigned int CGEN_INSN_INT;
70 typedef CGEN_INSN_INT CGEN_INSN_BYTES;
71 typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR;
73 typedef unsigned char *CGEN_INSN_BYTES;
74 typedef unsigned char *CGEN_INSN_BYTES_PTR;
78 #define CGEN_INLINE __inline__
92 typedef struct cgen_insn CGEN_INSN;
94 /* Opaque pointer version for use by external world. */
96 typedef struct cgen_cpu_desc *CGEN_CPU_DESC;
99 Attributes are used to describe various random things associated with
100 an object (ifield, hardware, operand, insn, whatever) and are specified
102 Integer attributes computed at compile time are currently all that's
103 supported, though adding string attributes and run-time computation is
104 straightforward. Integer attribute values are always host int's
105 (signed or unsigned). For portability, this means 32 bits.
106 Integer attributes are further categorized as boolean, bitset, integer,
107 and enum types. Boolean attributes appear frequently enough that they're
108 recorded in one host int. This limits the maximum number of boolean
109 attributes to 32, though that's a *lot* of attributes. */
111 /* Type of attribute values. */
113 typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE;
114 typedef int CGEN_ATTR_VALUE_ENUM_TYPE;
117 CGEN_ATTR_VALUE_BITSET_TYPE bitset;
118 CGEN_ATTR_VALUE_ENUM_TYPE nonbitset;
119 } CGEN_ATTR_VALUE_TYPE;
121 /* Struct to record attribute information. */
125 /* Boolean attributes. */
127 /* Non-boolean integer attributes. */
128 CGEN_ATTR_VALUE_TYPE nonbool[1];
131 /* Define a structure member for attributes with N non-boolean entries.
132 There is no maximum number of non-boolean attributes.
133 There is a maximum of 32 boolean attributes (since they are all recorded
136 #define CGEN_ATTR_TYPE(n) \
137 struct { unsigned int bool; \
138 CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }
140 /* Return the boolean attributes. */
142 #define CGEN_ATTR_BOOLS(a) ((a)->bool)
144 /* Non-boolean attribute numbers are offset by this much. */
146 #define CGEN_ATTR_NBOOL_OFFSET 32
148 /* Given a boolean attribute number, return its mask. */
150 #define CGEN_ATTR_MASK(attr) (1 << (attr))
152 /* Return the value of boolean attribute ATTR in ATTRS. */
154 #define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
156 /* Return value of attribute ATTR in ATTR_TABLE for OBJ.
157 OBJ is a pointer to the entity that has the attributes
158 (??? not used at present but is reserved for future purposes - eventually
159 the goal is to allow recording attributes in source form and computing
160 them lazily at runtime, not sure of the details yet). */
162 #define CGEN_ATTR_VALUE(obj, attr_table, attr) \
163 ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
164 ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
165 : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
166 #define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
167 ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
169 /* Attribute name/value tables.
170 These are used to assist parsing of descriptions at run-time. */
178 /* For each domain (ifld,hw,operand,insn), list of attributes. */
183 const CGEN_ATTR_ENTRY * dfault;
184 const CGEN_ATTR_ENTRY * vals;
187 /* Instruction set variants. */
192 /* Default instruction size (in bits).
193 This is used by the assembler when it encounters an unknown insn. */
194 unsigned int default_insn_bitsize;
196 /* Base instruction size (in bits).
197 For non-LIW cpus this is generally the length of the smallest insn.
198 For LIW cpus its wip (work-in-progress). For the m32r its 32. */
199 unsigned int base_insn_bitsize;
201 /* Minimum/maximum instruction size (in bits). */
202 unsigned int min_insn_bitsize;
203 unsigned int max_insn_bitsize;
206 /* Machine variants. */
210 /* The argument to bfd_arch_info->scan. */
211 const char *bfd_name;
212 /* one of enum mach_attr */
214 /* parameter from mach->cpu */
215 unsigned int insn_chunk_bitsize;
218 /* Parse result (also extraction result).
220 The result of parsing an insn is stored here.
221 To generate the actual insn, this is passed to the insert handler.
222 When printing an insn, the result of extraction is stored here.
223 To print the insn, this is passed to the print handler.
225 It is machine generated so we don't define it here,
226 but we do need a forward decl for the handler fns.
228 There is one member for each possible field in the insn.
229 The type depends on the field.
230 Also recorded here is the computed length of the insn for architectures
234 typedef struct cgen_fields CGEN_FIELDS;
236 /* Total length of the insn, as recorded in the `fields' struct. */
237 /* ??? The field insert handler has lots of opportunities for optimization
238 if it ever gets inlined. On architectures where insns all have the same
239 size, may wish to detect that and make this macro a constant - to allow
240 further optimizations. */
242 #define CGEN_FIELDS_BITSIZE(fields) ((fields)->length)
244 /* Extraction support for variable length insn sets. */
246 /* When disassembling we don't know the number of bytes to read at the start.
247 So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest
248 are read when needed. This struct controls this. It is basically the
249 disassemble_info stuff, except that we provide a cache for values already
250 read (since bytes can typically be read several times to fetch multiple
251 operands that may be in them), and that extraction of fields is needed
252 in contexts other than disassembly. */
255 /* A pointer to the disassemble_info struct.
256 We don't require dis-asm.h so we use void * for the type here.
257 If NULL, BYTES is full of valid data (VALID == -1). */
259 /* Points to a working buffer of sufficient size. */
260 unsigned char *insn_bytes;
261 /* Mask of bytes that are valid in INSN_BYTES. */
265 /* Associated with each insn or expression is a set of "handlers" for
266 performing operations like parsing, printing, etc. These require a bfd_vma
267 value to be passed around but we don't want all applications to need bfd.h.
268 So this stuff is only provided if bfd.h has been included. */
271 CD is a cpu table descriptor.
272 INSN is a pointer to a struct describing the insn being parsed.
273 STRP is a pointer to a pointer to the text being parsed.
274 FIELDS is a pointer to a cgen_fields struct in which the results are placed.
275 If the expression is successfully parsed, *STRP is updated.
276 If not it is left alone.
277 The result is NULL if success or an error message. */
278 typedef const char * (cgen_parse_fn)
279 (CGEN_CPU_DESC, const CGEN_INSN *insn_,
280 const char **strp_, CGEN_FIELDS *fields_);
283 CD is a cpu table descriptor.
284 INSN is a pointer to a struct describing the insn being parsed.
285 FIELDS is a pointer to a cgen_fields struct from which the values
287 INSNP is a pointer to a buffer in which to place the insn.
288 PC is the pc value of the insn.
289 The result is an error message or NULL if success. */
291 #ifdef __BFD_H_SEEN__
292 typedef const char * (cgen_insert_fn)
293 (CGEN_CPU_DESC, const CGEN_INSN *insn_,
294 CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_,
297 typedef const char * (cgen_insert_fn) ();
301 CD is a cpu table descriptor.
302 INSN is a pointer to a struct describing the insn being parsed.
303 The second argument is a pointer to a struct controlling extraction
304 (only used for variable length insns).
305 EX_INFO is a pointer to a struct for controlling reading of further
307 BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order).
308 FIELDS is a pointer to a cgen_fields struct in which the results are placed.
309 PC is the pc value of the insn.
310 The result is the length of the insn in bits or zero if not recognized. */
312 #ifdef __BFD_H_SEEN__
313 typedef int (cgen_extract_fn)
314 (CGEN_CPU_DESC, const CGEN_INSN *insn_,
315 CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_,
316 CGEN_FIELDS *fields_, bfd_vma pc_);
318 typedef int (cgen_extract_fn) ();
322 CD is a cpu table descriptor.
323 INFO is a pointer to the disassembly info.
324 Eg: disassemble_info. It's defined as `PTR' so this file can be included
326 INSN is a pointer to a struct describing the insn being printed.
327 FIELDS is a pointer to a cgen_fields struct.
328 PC is the pc value of the insn.
329 LEN is the length of the insn, in bits. */
331 #ifdef __BFD_H_SEEN__
332 typedef void (cgen_print_fn)
333 (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_,
334 CGEN_FIELDS *fields_, bfd_vma pc_, int len_);
336 typedef void (cgen_print_fn) ();
339 /* Parse/insert/extract/print handlers.
341 Indices into the handler tables.
342 We could use pointers here instead, but 90% of them are generally identical
343 and that's a lot of redundant data. Making these unsigned char indices
344 into tables of pointers saves a bit of space.
345 Using indices also keeps assembler code out of the disassembler and
348 struct cgen_opcode_handler
350 unsigned char parse, insert, extract, print;
353 /* Assembler interface.
355 The interface to the assembler is intended to be clean in the sense that
356 libopcodes.a is a standalone entity and could be used with any assembler.
357 Not that one would necessarily want to do that but rather that it helps
358 keep a clean interface. The interface will obviously be slanted towards
359 GAS, but at least it's a start.
360 ??? Note that one possible user of the assembler besides GAS is GDB.
362 Parsing is controlled by the assembler which calls
363 CGEN_SYM (assemble_insn). If it can parse and build the entire insn
364 it doesn't call back to the assembler. If it needs/wants to call back
365 to the assembler, cgen_parse_operand_fn is called which can either
367 - return a number to be inserted in the insn
368 - return a "register" value to be inserted
369 (the register might not be a register per pe)
370 - queue the argument and return a marker saying the expression has been
371 queued (eg: a fix-up)
372 - return an error message indicating the expression wasn't recognizable
374 The result is an error message or NULL for success.
375 The parsed value is stored in the bfd_vma *. */
377 /* Values for indicating what the caller wants. */
379 enum cgen_parse_operand_type
381 CGEN_PARSE_OPERAND_INIT,
382 CGEN_PARSE_OPERAND_INTEGER,
383 CGEN_PARSE_OPERAND_ADDRESS,
384 CGEN_PARSE_OPERAND_SYMBOLIC
387 /* Values for indicating what was parsed. */
389 enum cgen_parse_operand_result
391 CGEN_PARSE_OPERAND_RESULT_NUMBER,
392 CGEN_PARSE_OPERAND_RESULT_REGISTER,
393 CGEN_PARSE_OPERAND_RESULT_QUEUED,
394 CGEN_PARSE_OPERAND_RESULT_ERROR
397 #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */
398 typedef const char * (cgen_parse_operand_fn)
400 enum cgen_parse_operand_type, const char **, int, int,
401 enum cgen_parse_operand_result *, bfd_vma *);
403 typedef const char * (cgen_parse_operand_fn) ();
406 /* Set the cgen_parse_operand_fn callback. */
408 extern void cgen_set_parse_operand_fn
409 (CGEN_CPU_DESC, cgen_parse_operand_fn);
411 /* Called before trying to match a table entry with the insn. */
413 extern void cgen_init_parse_operand (CGEN_CPU_DESC);
415 /* Operand values (keywords, integers, symbols, etc.) */
417 /* Types of assembler elements. */
421 CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX
425 enum cgen_hw_type { CGEN_HW_MAX };
428 /* List of hardware elements. */
433 enum cgen_hw_type type;
434 /* There is currently no example where both index specs and value specs
435 are required, so for now both are clumped under "asm_data". */
436 enum cgen_asm_type asm_type;
438 #ifndef CGEN_HW_NBOOL_ATTRS
439 #define CGEN_HW_NBOOL_ATTRS 1
441 CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs;
442 #define CGEN_HW_ATTRS(hw) (&(hw)->attrs)
445 /* Return value of attribute ATTR in HW. */
447 #define CGEN_HW_ATTR_VALUE(hw, attr) \
448 CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))
450 /* Table of hardware elements for selected mach, computed at runtime.
451 enum cgen_hw_type is an index into this table (specifically `entries'). */
454 /* Pointer to null terminated table of all compiled in entries. */
455 const CGEN_HW_ENTRY *init_entries;
456 unsigned int entry_size; /* since the attribute member is variable sized */
457 /* Array of all entries, initial and run-time added. */
458 const CGEN_HW_ENTRY **entries;
459 /* Number of elements in `entries'. */
460 unsigned int num_entries;
461 /* For now, xrealloc is called each time a new entry is added at runtime.
462 ??? May wish to keep track of some slop to reduce the number of calls to
463 xrealloc, except that there's unlikely to be many and not expected to be
464 in speed critical code. */
467 extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name
468 (CGEN_CPU_DESC, const char *);
469 extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num
470 (CGEN_CPU_DESC, unsigned int);
472 /* This struct is used to describe things like register names, etc. */
474 typedef struct cgen_keyword_entry
476 /* Name (as in register name). */
479 /* Value (as in register number).
480 The value cannot be -1 as that is used to indicate "not found".
481 IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */
485 This should, but technically needn't, appear last. It is a variable sized
486 array in that one architecture may have 1 nonbool attribute and another
487 may have more. Having this last means the non-architecture specific code
488 needn't care. The goal is to eventually record
489 attributes in their raw form, evaluate them at run-time, and cache the
490 values, so this worry will go away anyway. */
491 /* ??? Moving this last should be done by treating keywords like insn lists
492 and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */
493 /* FIXME: Not used yet. */
494 #ifndef CGEN_KEYWORD_NBOOL_ATTRS
495 #define CGEN_KEYWORD_NBOOL_ATTRS 1
497 CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs;
499 /* ??? Putting these here means compiled in entries can't be const.
500 Not a really big deal, but something to consider. */
501 /* Next name hash table entry. */
502 struct cgen_keyword_entry *next_name;
503 /* Next value hash table entry. */
504 struct cgen_keyword_entry *next_value;
505 } CGEN_KEYWORD_ENTRY;
507 /* Top level struct for describing a set of related keywords
508 (e.g. register names).
510 This struct supports run-time entry of new values, and hashed lookups. */
512 typedef struct cgen_keyword
514 /* Pointer to initial [compiled in] values. */
515 CGEN_KEYWORD_ENTRY *init_entries;
517 /* Number of entries in `init_entries'. */
518 unsigned int num_init_entries;
520 /* Hash table used for name lookup. */
521 CGEN_KEYWORD_ENTRY **name_hash_table;
523 /* Hash table used for value lookup. */
524 CGEN_KEYWORD_ENTRY **value_hash_table;
526 /* Number of entries in the hash_tables. */
527 unsigned int hash_table_size;
529 /* Pointer to null keyword "" entry if present. */
530 const CGEN_KEYWORD_ENTRY *null_entry;
532 /* String containing non-alphanumeric characters used
534 At present, the highest number of entries used is 1. */
535 char nonalpha_chars[8];
538 /* Structure used for searching. */
542 /* Table being searched. */
543 const CGEN_KEYWORD *table;
545 /* Specification of what is being searched for. */
548 /* Current index in hash table. */
549 unsigned int current_hash;
551 /* Current element in current hash chain. */
552 CGEN_KEYWORD_ENTRY *current_entry;
553 } CGEN_KEYWORD_SEARCH;
555 /* Lookup a keyword from its name. */
557 const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name
558 (CGEN_KEYWORD *, const char *);
560 /* Lookup a keyword from its value. */
562 const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value
563 (CGEN_KEYWORD *, int);
567 void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *);
569 /* Keyword searching.
570 This can be used to retrieve every keyword, or a subset. */
572 CGEN_KEYWORD_SEARCH cgen_keyword_search_init
573 (CGEN_KEYWORD *, const char *);
574 const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next
575 (CGEN_KEYWORD_SEARCH *);
577 /* Operand value support routines. */
579 extern const char *cgen_parse_keyword
580 (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
581 #ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */
582 extern const char *cgen_parse_signed_integer
583 (CGEN_CPU_DESC, const char **, int, long *);
584 extern const char *cgen_parse_unsigned_integer
585 (CGEN_CPU_DESC, const char **, int, unsigned long *);
586 extern const char *cgen_parse_address
587 (CGEN_CPU_DESC, const char **, int, int,
588 enum cgen_parse_operand_result *, bfd_vma *);
589 extern const char *cgen_validate_signed_integer
591 extern const char *cgen_validate_unsigned_integer
592 (unsigned long, unsigned long, unsigned long);
597 /* ??? This duplicates the values in arch.h. Revisit.
598 These however need the CGEN_ prefix [as does everything in this file]. */
599 /* ??? Targets may need to add their own modes so we may wish to move this
600 to <arch>-opc.h, or add a hook. */
603 CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */
604 CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI,
605 CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI,
606 CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF,
607 CGEN_MODE_TARGET_MAX,
608 CGEN_MODE_INT, CGEN_MODE_UINT,
612 /* FIXME: Until simulator is updated. */
614 #define CGEN_MODE_VM CGEN_MODE_VOID
619 enum cgen_operand_type { CGEN_OPERAND_MAX };
622 /* "nil" indicator for the operand instance table */
623 #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
625 /* A tree of these structs represents the multi-ifield
626 structure of an operand's hw-index value, if it exists. */
630 typedef struct cgen_maybe_multi_ifield
632 int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
633 n: indexed by array of more cgen_maybe_multi_ifields. */
637 const struct cgen_maybe_multi_ifield * multi;
638 const struct cgen_ifld * leaf;
641 CGEN_MAYBE_MULTI_IFLD;
643 /* This struct defines each entry in the operand table. */
647 /* Name as it appears in the syntax string. */
651 enum cgen_operand_type type;
653 /* The hardware element associated with this operand. */
654 enum cgen_hw_type hw_type;
656 /* FIXME: We don't yet record ifield definitions, which we should.
657 When we do it might make sense to delete start/length (since they will
658 be duplicated in the ifield's definition) and replace them with a
659 pointer to the ifield entry. */
662 This is just a hint, and may be unused in more complex operands.
663 May be unused for a modifier. */
666 /* The number of bits in the operand.
667 This is just a hint, and may be unused in more complex operands.
668 May be unused for a modifier. */
669 unsigned char length;
671 /* The (possibly-multi) ifield used as an index for this operand, if it
672 is indexed by a field at all. This substitutes / extends the start and
673 length fields above, but unsure at this time whether they are used
675 CGEN_MAYBE_MULTI_IFLD index_fields;
676 #if 0 /* ??? Interesting idea but relocs tend to get too complicated,
677 and ABI dependent, for simple table lookups to work. */
678 /* Ideally this would be the internal (external?) reloc type. */
683 This should, but technically needn't, appear last. It is a variable sized
684 array in that one architecture may have 1 nonbool attribute and another
685 may have more. Having this last means the non-architecture specific code
686 needn't care, now or tomorrow. The goal is to eventually record
687 attributes in their raw form, evaluate them at run-time, and cache the
688 values, so this worry will go away anyway. */
689 #ifndef CGEN_OPERAND_NBOOL_ATTRS
690 #define CGEN_OPERAND_NBOOL_ATTRS 1
692 CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs;
693 #define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
696 /* Return value of attribute ATTR in OPERAND. */
698 #define CGEN_OPERAND_ATTR_VALUE(operand, attr) \
699 CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))
701 /* Table of operands for selected mach/isa, computed at runtime.
702 enum cgen_operand_type is an index into this table (specifically
706 /* Pointer to null terminated table of all compiled in entries. */
707 const CGEN_OPERAND *init_entries;
708 unsigned int entry_size; /* since the attribute member is variable sized */
709 /* Array of all entries, initial and run-time added. */
710 const CGEN_OPERAND **entries;
711 /* Number of elements in `entries'. */
712 unsigned int num_entries;
713 /* For now, xrealloc is called each time a new entry is added at runtime.
714 ??? May wish to keep track of some slop to reduce the number of calls to
715 xrealloc, except that there's unlikely to be many and not expected to be
716 in speed critical code. */
717 } CGEN_OPERAND_TABLE;
719 extern const CGEN_OPERAND * cgen_operand_lookup_by_name
720 (CGEN_CPU_DESC, const char *);
721 extern const CGEN_OPERAND * cgen_operand_lookup_by_num
722 (CGEN_CPU_DESC, int);
724 /* Instruction operand instances.
726 For each instruction, a list of the hardware elements that are read and
727 written are recorded. */
729 /* The type of the instance. */
731 enum cgen_opinst_type {
732 /* End of table marker. */
734 CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT
739 /* Input or output indicator. */
740 enum cgen_opinst_type type;
742 /* Name of operand. */
745 /* The hardware element referenced. */
746 enum cgen_hw_type hw_type;
748 /* The mode in which the operand is being used. */
751 /* The operand table entry CGEN_OPERAND_NIL if there is none
752 (i.e. an explicit hardware reference). */
753 enum cgen_operand_type op_type;
755 /* If `operand' is "nil", the index (e.g. into array of registers). */
759 ??? This perhaps should be a real attribute struct but there's
760 no current need, so we save a bit of space and just have a set of
761 flags. The interface is such that this can easily be made attributes
762 should it prove useful. */
764 #define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs)
765 /* Return value of attribute ATTR in OPINST. */
766 #define CGEN_OPINST_ATTR(opinst, attr) \
767 ((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
768 /* Operand is conditionally referenced (read/written). */
769 #define CGEN_OPINST_COND_REF 1
774 Each insn format and subexpression has one of these.
776 The syntax "string" consists of characters (n > 0 && n < 128), and operand
777 values (n >= 128), and is terminated by 0. Operand values are 128 + index
778 into the operand table. The operand table doesn't exist in C, per se, as
779 the data is recorded in the parse/insert/extract/print switch statements. */
781 /* This should be at least as large as necessary for any target. */
782 #define CGEN_MAX_SYNTAX_ELEMENTS 48
784 /* A target may know its own precise maximum. Assert that it falls below
786 #ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS
787 #if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS
788 #error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS"
792 typedef unsigned short CGEN_SYNTAX_CHAR_TYPE;
796 CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS];
799 #define CGEN_SYNTAX_STRING(syn) (syn->syntax)
800 #define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
801 #define CGEN_SYNTAX_CHAR(c) ((unsigned char)c)
802 #define CGEN_SYNTAX_FIELD(c) ((c) - 128)
803 #define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
805 /* ??? I can't currently think of any case where the mnemonic doesn't come
806 first [and if one ever doesn't building the hash tables will be tricky].
807 However, we treat mnemonics as just another operand of the instruction.
808 A value of 1 means "this is where the mnemonic appears". 1 isn't
809 special other than it's a non-printable ASCII char. */
811 #define CGEN_SYNTAX_MNEMONIC 1
812 #define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC)
814 /* Instruction fields.
816 ??? We currently don't allow adding fields at run-time.
817 Easy to fix when needed. */
819 typedef struct cgen_ifld {
820 /* Enum of ifield. */
822 #define CGEN_IFLD_NUM(f) ((f)->num)
824 /* Name of the field, distinguishes it from all other fields. */
826 #define CGEN_IFLD_NAME(f) ((f)->name)
828 /* Default offset, in bits, from the start of the insn to the word
829 containing the field. */
831 #define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset)
833 /* Default length of the word containing the field. */
835 #define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size)
837 /* Default starting bit number.
838 Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */
840 #define CGEN_IFLD_START(f) ((f)->start)
842 /* Length of the field, in bits. */
844 #define CGEN_IFLD_LENGTH(f) ((f)->length)
846 #ifndef CGEN_IFLD_NBOOL_ATTRS
847 #define CGEN_IFLD_NBOOL_ATTRS 1
849 CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs;
850 #define CGEN_IFLD_ATTRS(f) (&(f)->attrs)
853 /* Return value of attribute ATTR in IFLD. */
854 #define CGEN_IFLD_ATTR_VALUE(ifld, attr) \
855 CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))
857 /* Instruction data. */
859 /* Instruction formats.
861 Instructions are grouped by format. Associated with an instruction is its
862 format. Each insn's opcode table entry contains a format table entry.
863 ??? There is usually very few formats compared with the number of insns,
864 so one can reduce the size of the opcode table by recording the format table
865 as a separate entity. Given that we currently don't, format table entries
866 are also distinguished by their operands. This increases the size of the
867 table, but reduces the number of tables. It's all minutiae anyway so it
868 doesn't really matter [at this point in time].
870 ??? Support for variable length ISA's is wip. */
872 /* Accompanying each iformat description is a list of its fields. */
875 const CGEN_IFLD *ifld;
876 #define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld)
879 /* This should be at least as large as necessary for any target. */
880 #define CGEN_MAX_IFMT_OPERANDS 16
882 /* A target may know its own precise maximum. Assert that it falls below
884 #ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS
885 #if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS
886 #error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS"
893 /* Length that MASK and VALUE have been calculated to
894 [VALUE is recorded elsewhere].
895 Normally it is base_insn_bitsize. On [V]LIW architectures where the base
896 insn size may be larger than the size of an insn, this field is less than
897 base_insn_bitsize. */
898 unsigned char mask_length;
899 #define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length)
901 /* Total length of instruction, in bits. */
902 unsigned char length;
903 #define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length)
905 /* Mask to apply to the first MASK_LENGTH bits.
906 Each insn's value is stored with the insn.
907 The first step in recognizing an insn for disassembly is
908 (opcode & mask) == value. */
910 #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
912 /* Instruction fields.
913 +1 for trailing NULL. */
914 CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1];
915 #define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds)
918 /* Instruction values. */
922 /* The opcode portion of the base insn. */
923 CGEN_INSN_INT base_value;
925 #ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS
926 /* Extra opcode values beyond base_value. */
927 unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS];
931 /* Instruction opcode table.
932 This contains the syntax and format data of an instruction. */
934 /* ??? Some ports already have an opcode table yet still need to use the rest
935 of what cgen_insn has. Plus keeping the opcode data with the operand
936 instance data can create a pretty big file. So we keep them separately.
937 Not sure this is a good idea in the long run. */
941 /* Indices into parse/insert/extract/print handler tables. */
942 struct cgen_opcode_handler handlers;
943 #define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers)
947 #define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax)
950 const CGEN_IFMT *format;
951 #define CGEN_OPCODE_FORMAT(opc) ((opc)->format)
952 #define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc))
953 #define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc))
954 #define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc))
956 /* Instruction opcode value. */
958 #define CGEN_OPCODE_VALUE(opc) (& (opc)->value)
959 #define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value)
960 #define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc))
963 /* Instruction attributes.
964 This is made a published type as applications can cache a pointer to
965 the attributes for speed. */
967 #ifndef CGEN_INSN_NBOOL_ATTRS
968 #define CGEN_INSN_NBOOL_ATTRS 1
970 typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
972 /* Enum of architecture independent attributes. */
975 /* ??? Numbers here are recorded in two places. */
976 typedef enum cgen_insn_attr {
979 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
982 /* This struct defines each entry in the instruction table. */
986 /* Each real instruction is enumerated. */
987 /* ??? This may go away in time. */
989 #define CGEN_INSN_NUM(insn) ((insn)->base->num)
991 /* Name of entry (that distinguishes it from all other entries). */
992 /* ??? If mnemonics have operands, try to print full mnemonic. */
994 #define CGEN_INSN_NAME(insn) ((insn)->base->name)
996 /* Mnemonic. This is used when parsing and printing the insn.
997 In the case of insns that have operands on the mnemonics, this is
998 only the constant part. E.g. for conditional execution of an `add' insn,
999 where the full mnemonic is addeq, addne, etc., and the condition is
1000 treated as an operand, this is only "add". */
1001 const char *mnemonic;
1002 #define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic)
1004 /* Total length of instruction, in bits. */
1006 #define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize)
1008 #if 0 /* ??? Disabled for now as there is a problem with embedded newlines
1009 and the table is already pretty big. Should perhaps be moved
1010 to a file of its own. */
1011 /* Semantics, as RTL. */
1012 /* ??? Plain text or bytecodes? */
1013 /* ??? Note that the operand instance table could be computed at run-time
1014 if we parse this and cache the results. Something to eventually do. */
1016 #define CGEN_INSN_RTX(insn) ((insn)->base->rtx)
1020 This must appear last. It is a variable sized array in that one
1021 architecture may have 1 nonbool attribute and another may have more.
1022 Having this last means the non-architecture specific code needn't
1023 care. The goal is to eventually record attributes in their raw form,
1024 evaluate them at run-time, and cache the values, so this worry will go
1026 CGEN_INSN_ATTR_TYPE attrs;
1027 #define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs)
1028 /* Return value of attribute ATTR in INSN. */
1029 #define CGEN_INSN_ATTR_VALUE(insn, attr) \
1030 CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
1031 #define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
1032 CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
1035 /* Return non-zero if INSN is the "invalid" insn marker. */
1037 #define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0)
1039 /* Main struct contain instruction information.
1040 BASE is always present, the rest is present only if asked for. */
1044 /* ??? May be of use to put a type indicator here.
1045 Then this struct could different info for different classes of insns. */
1046 /* ??? A speedup can be had by moving `base' into this struct.
1048 const CGEN_IBASE *base;
1049 const CGEN_OPCODE *opcode;
1050 const CGEN_OPINST *opinst;
1052 /* Regex to disambiguate overloaded opcodes */
1054 #define CGEN_INSN_RX(insn) ((insn)->rx)
1055 #define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5)
1058 /* Instruction lists.
1059 This is used for adding new entries and for creating the hash lists. */
1061 typedef struct cgen_insn_list
1063 struct cgen_insn_list *next;
1064 const CGEN_INSN *insn;
1067 /* Table of instructions. */
1071 const CGEN_INSN *init_entries;
1072 unsigned int entry_size; /* since the attribute member is variable sized */
1073 unsigned int num_init_entries;
1074 CGEN_INSN_LIST *new_entries;
1077 /* Return number of instructions. This includes any added at run-time. */
1079 extern int cgen_insn_count (CGEN_CPU_DESC);
1080 extern int cgen_macro_insn_count (CGEN_CPU_DESC);
1082 /* Macros to access the other insn elements not recorded in CGEN_IBASE. */
1084 /* Fetch INSN's operand instance table. */
1085 /* ??? Doesn't handle insns added at runtime. */
1086 #define CGEN_INSN_OPERANDS(insn) ((insn)->opinst)
1088 /* Return INSN's opcode table entry. */
1089 #define CGEN_INSN_OPCODE(insn) ((insn)->opcode)
1091 /* Return INSN's handler data. */
1092 #define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn))
1094 /* Return INSN's syntax. */
1095 #define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn))
1097 /* Return size of base mask in bits. */
1098 #define CGEN_INSN_MASK_BITSIZE(insn) \
1099 CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn))
1101 /* Return mask of base part of INSN. */
1102 #define CGEN_INSN_BASE_MASK(insn) \
1103 CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn))
1105 /* Return value of base part of INSN. */
1106 #define CGEN_INSN_BASE_VALUE(insn) \
1107 CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn))
1109 /* Standard way to test whether INSN is supported by MACH.
1110 MACH is one of enum mach_attr.
1111 The "|1" is because the base mach is always selected. */
1112 #define CGEN_INSN_MACH_HAS_P(insn, mach) \
1113 ((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)
1115 /* Macro instructions.
1116 Macro insns aren't real insns, they map to one or more real insns.
1117 E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or
1120 Macro insns can expand to nothing (e.g. a nop that is optimized away).
1121 This is useful in multi-insn macros that build a constant in a register.
1122 Of course this isn't the default behaviour and must be explicitly enabled.
1124 Assembly of macro-insns is relatively straightforward. Disassembly isn't.
1125 However, disassembly of at least some kinds of macro insns is important
1126 in order that the disassembled code preserve the readability of the original
1127 insn. What is attempted here is to disassemble all "simple" macro-insns,
1128 where "simple" is currently defined to mean "expands to one real insn".
1130 Simple macro-insns are handled specially. They are emitted as ALIAS's
1131 of real insns. This simplifies their handling since there's usually more
1132 of them than any other kind of macro-insn, and proper disassembly of them
1133 falls out for free. */
1135 /* For each macro-insn there may be multiple expansion possibilities,
1136 depending on the arguments. This structure is accessed via the `data'
1137 member of CGEN_INSN. */
1139 typedef struct cgen_minsn_expansion {
1140 /* Function to do the expansion.
1141 If the expansion fails (e.g. "no match") NULL is returned.
1142 Space for the expansion is obtained with malloc.
1143 It is up to the caller to free it. */
1145 (const struct cgen_minsn_expansion *,
1146 const char *, const char **, int *,
1148 #define CGEN_MIEXPN_FN(ex) ((ex)->fn)
1150 /* Instruction(s) the macro expands to.
1151 The format of STR is defined by FN.
1152 It is typically the assembly code of the real insn, but it could also be
1153 the original Scheme expression or a tokenized form of it (with FN being
1154 an appropriate interpreter). */
1156 #define CGEN_MIEXPN_STR(ex) ((ex)->str)
1157 } CGEN_MINSN_EXPANSION;
1160 When supported, this function will convert the input string to another
1161 string and the parser will be invoked recursively. The output string
1162 may contain further macro invocations. */
1164 extern const char * cgen_expand_macro_insn
1165 (CGEN_CPU_DESC, const struct cgen_minsn_expansion *,
1166 const char *, const char **, int *, CGEN_OPERAND **);
1168 /* The assembler insn table is hashed based on some function of the mnemonic
1169 (the actually hashing done is up to the target, but we provide a few
1170 examples like the first letter or a function of the entire mnemonic). */
1172 extern CGEN_INSN_LIST * cgen_asm_lookup_insn
1173 (CGEN_CPU_DESC, const char *);
1174 #define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string))
1175 #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next)
1177 /* The disassembler insn table is hashed based on some function of machine
1178 instruction (the actually hashing done is up to the target). */
1180 extern CGEN_INSN_LIST * cgen_dis_lookup_insn
1181 (CGEN_CPU_DESC, const char *, CGEN_INSN_INT);
1182 /* FIXME: delete these two */
1183 #define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value))
1184 #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next)
1186 /* The CPU description.
1187 A copy of this is created when the cpu table is "opened".
1188 All global state information is recorded here.
1189 Access macros are provided for "public" members. */
1191 typedef struct cgen_cpu_desc
1193 /* Bitmap of selected machine(s) (a la BFD machine number). */
1196 /* Bitmap of selected isa(s). */
1198 #define CGEN_CPU_ISAS(cd) ((cd)->isas)
1200 /* Current endian. */
1201 enum cgen_endian endian;
1202 #define CGEN_CPU_ENDIAN(cd) ((cd)->endian)
1204 /* Current insn endian. */
1205 enum cgen_endian insn_endian;
1206 #define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian)
1208 /* Word size (in bits). */
1209 /* ??? Or maybe maximum word size - might we ever need to allow a cpu table
1210 to be opened for both sparc32/sparc64?
1211 ??? Another alternative is to create a table of selected machs and
1212 lazily fetch the data from there. */
1213 unsigned int word_bitsize;
1215 /* Instruction chunk size (in bits), for purposes of endianness
1217 unsigned int insn_chunk_bitsize;
1219 /* Indicator if sizes are unknown.
1220 This is used by default_insn_bitsize,base_insn_bitsize if there is a
1221 difference between the selected isa's. */
1222 #define CGEN_SIZE_UNKNOWN 65535
1224 /* Default instruction size (in bits).
1225 This is used by the assembler when it encounters an unknown insn. */
1226 unsigned int default_insn_bitsize;
1228 /* Base instruction size (in bits).
1229 For non-LIW cpus this is generally the length of the smallest insn.
1230 For LIW cpus its wip (work-in-progress). For the m32r its 32. */
1231 unsigned int base_insn_bitsize;
1233 /* Minimum/maximum instruction size (in bits). */
1234 unsigned int min_insn_bitsize;
1235 unsigned int max_insn_bitsize;
1237 /* Instruction set variants. */
1238 const CGEN_ISA *isa_table;
1240 /* Machine variants. */
1241 const CGEN_MACH *mach_table;
1243 /* Hardware elements. */
1244 CGEN_HW_TABLE hw_table;
1246 /* Instruction fields. */
1247 const CGEN_IFLD *ifld_table;
1250 CGEN_OPERAND_TABLE operand_table;
1252 /* Main instruction table. */
1253 CGEN_INSN_TABLE insn_table;
1254 #define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table)
1256 /* Macro instructions are defined separately and are combined with real
1257 insns during hash table computation. */
1258 CGEN_INSN_TABLE macro_insn_table;
1260 /* Copy of CGEN_INT_INSN_P. */
1263 /* Called to rebuild the tables after something has changed. */
1264 void (*rebuild_tables) (CGEN_CPU_DESC);
1266 /* Operand parser callback. */
1267 cgen_parse_operand_fn * parse_operand_fn;
1269 /* Parse/insert/extract/print cover fns for operands. */
1270 const char * (*parse_operand)
1271 (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_);
1272 #ifdef __BFD_H_SEEN__
1273 const char * (*insert_operand)
1274 (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_,
1275 CGEN_INSN_BYTES_PTR, bfd_vma pc_);
1276 int (*extract_operand)
1277 (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
1278 CGEN_FIELDS *fields_, bfd_vma pc_);
1279 void (*print_operand)
1280 (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_,
1281 void const *attrs_, bfd_vma pc_, int length_);
1283 const char * (*insert_operand) ();
1284 int (*extract_operand) ();
1285 void (*print_operand) ();
1287 #define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand)
1288 #define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand)
1289 #define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand)
1290 #define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand)
1292 /* Size of CGEN_FIELDS struct. */
1293 unsigned int sizeof_fields;
1294 #define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields)
1296 /* Set the bitsize field. */
1297 void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_);
1298 #define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize)
1300 /* CGEN_FIELDS accessors. */
1301 int (*get_int_operand)
1302 (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
1303 void (*set_int_operand)
1304 (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_);
1305 #ifdef __BFD_H_SEEN__
1306 bfd_vma (*get_vma_operand)
1307 (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
1308 void (*set_vma_operand)
1309 (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_);
1311 long (*get_vma_operand) ();
1312 void (*set_vma_operand) ();
1314 #define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand)
1315 #define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand)
1316 #define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand)
1317 #define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand)
1319 /* Instruction parse/insert/extract/print handlers. */
1320 /* FIXME: make these types uppercase. */
1321 cgen_parse_fn * const *parse_handlers;
1322 cgen_insert_fn * const *insert_handlers;
1323 cgen_extract_fn * const *extract_handlers;
1324 cgen_print_fn * const *print_handlers;
1325 #define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse])
1326 #define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert])
1327 #define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract])
1328 #define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print])
1330 /* Return non-zero if insn should be added to hash table. */
1331 int (* asm_hash_p) (const CGEN_INSN *);
1333 /* Assembler hash function. */
1334 unsigned int (* asm_hash) (const char *);
1336 /* Number of entries in assembler hash table. */
1337 unsigned int asm_hash_size;
1339 /* Return non-zero if insn should be added to hash table. */
1340 int (* dis_hash_p) (const CGEN_INSN *);
1342 /* Disassembler hash function. */
1343 unsigned int (* dis_hash) (const char *, CGEN_INSN_INT);
1345 /* Number of entries in disassembler hash table. */
1346 unsigned int dis_hash_size;
1348 /* Assembler instruction hash table. */
1349 CGEN_INSN_LIST **asm_hash_table;
1350 CGEN_INSN_LIST *asm_hash_table_entries;
1352 /* Disassembler instruction hash table. */
1353 CGEN_INSN_LIST **dis_hash_table;
1354 CGEN_INSN_LIST *dis_hash_table_entries;
1356 /* This field could be turned into a bitfield if room for other flags is needed. */
1357 unsigned int signed_overflow_ok_p;
1362 #ifndef CGEN_WORD_ENDIAN
1363 #define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd)
1365 #ifndef CGEN_INSN_WORD_ENDIAN
1366 #define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd)
1369 /* Prototypes of major functions. */
1370 /* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC.
1371 Not the init fns though, as that would drag in things that mightn't be
1372 used and might not even exist. */
1374 /* Argument types to cpu_open. */
1376 enum cgen_cpu_open_arg {
1378 /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */
1380 /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */
1381 CGEN_CPU_OPEN_MACHS,
1382 /* Select machine, arg is mach's bfd name.
1383 Multiple machines can be specified by repeated use. */
1384 CGEN_CPU_OPEN_BFDMACH,
1385 /* Select endian, arg is CGEN_ENDIAN_*. */
1386 CGEN_CPU_OPEN_ENDIAN
1389 /* Open a cpu descriptor table for use.
1390 ??? We only support ISO C stdargs here, not K&R.
1391 Laziness, plus experiment to see if anything requires K&R - eventually
1392 K&R will no longer be supported - e.g. GDB is currently trying this. */
1394 extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...);
1396 /* Cover fn to handle simple case. */
1398 extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1)
1399 (const char *mach_name_, enum cgen_endian endian_);
1403 extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC);
1405 /* Initialize the opcode table for use.
1406 Called by init_asm/init_dis. */
1408 extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_);
1410 /* build the insn selection regex.
1411 called by init_opcode_table */
1413 extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_);
1415 /* Initialize the ibld table for use.
1416 Called by init_asm/init_dis. */
1418 extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_);
1420 /* Initialize an cpu table for assembler or disassembler use.
1421 These must be called immediately after cpu_open. */
1423 extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC);
1424 extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC);
1426 /* Initialize the operand instance table for use. */
1428 extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_);
1430 /* Assemble an instruction. */
1432 extern const CGEN_INSN * CGEN_SYM (assemble_insn)
1433 (CGEN_CPU_DESC, const char *, CGEN_FIELDS *,
1434 CGEN_INSN_BYTES_PTR, char **);
1436 extern const CGEN_KEYWORD CGEN_SYM (operand_mach);
1437 extern int CGEN_SYM (get_mach) (const char *);
1439 /* Operand index computation. */
1440 extern const CGEN_INSN * cgen_lookup_insn
1441 (CGEN_CPU_DESC, const CGEN_INSN * insn_,
1442 CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
1443 int length_, CGEN_FIELDS *fields_, int alias_p_);
1444 extern void cgen_get_insn_operands
1445 (CGEN_CPU_DESC, const CGEN_INSN * insn_,
1446 const CGEN_FIELDS *fields_, int *indices_);
1447 extern const CGEN_INSN * cgen_lookup_get_insn_operands
1448 (CGEN_CPU_DESC, const CGEN_INSN *insn_,
1449 CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
1450 int length_, int *indices_, CGEN_FIELDS *fields_);
1452 /* Cover fns to bfd_get/set. */
1454 extern CGEN_INSN_INT cgen_get_insn_value
1455 (CGEN_CPU_DESC, unsigned char *, int);
1456 extern void cgen_put_insn_value
1457 (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT);
1459 /* Read in a cpu description file.
1460 ??? For future concerns, including adding instructions to the assembler/
1461 disassembler at run-time. */
1463 extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_);
1465 /* Allow signed overflow of instruction fields. */
1466 extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC);
1468 /* Generate an error message if a signed field in an instruction overflows. */
1469 extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC);
1471 /* Will an error message be generated if a signed field in an instruction overflows ? */
1472 extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC);
1474 #endif /* OPCODE_CGEN_H */