1 /* score-inst.h -- Score Instructions Table
2 Copyright 2006 Free Software Foundation, Inc.
4 Mei Ligang (ligang@sunnorth.com.cn)
5 Pei-Lin Tsai (pltsai@sunplus.com)
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
27 #define LDST_UNALIGN_MASK 0x0000007f
28 #define UA_LCB 0x00000060
29 #define UA_LCW 0x00000062
30 #define UA_LCE 0x00000066
31 #define UA_SCB 0x00000068
32 #define UA_SCW 0x0000006a
33 #define UA_SCE 0x0000006e
34 #define UA_LL 0x0000000c
35 #define UA_SC 0x0000000e
36 #define LDST16_RR_MASK 0x0000000f
45 #define LDST16_RI_MASK 0x7007
46 #define N16_LWP 0x7000
47 #define N16_LHP 0x7001
48 #define N16_LBUP 0x7003
49 #define N16_SWP 0x7004
50 #define N16_SHP 0x7005
51 #define N16_SBP 0x7007
52 #define N16_LIU 0x5000
54 #define OPC_PSEUDOLDST_MASK 0x00000007
68 /* Sub opcdoe opcode. */
102 Rd_rvalueRs_postSI12,
104 Rd_lvalueRs_postSI12,
169 _VALUE_LDST_LO16 = 23,
178 _SIMM16_pic = 42, /* Index in score_df_range. */
179 _IMM16_LO16_pic = 43,
185 #define OP_REG_TYPE (1 << 6)
186 #define OP_IMM_TYPE (1 << 7)
187 #define OP_SH_REGD (OP_REG_TYPE |20)
188 #define OP_SH_REGS1 (OP_REG_TYPE |15)
189 #define OP_SH_REGS2 (OP_REG_TYPE |10)
190 #define OP_SH_I (OP_IMM_TYPE | 1)
191 #define OP_SH_RI15 (OP_IMM_TYPE | 0)
192 #define OP_SH_I12 (OP_IMM_TYPE | 3)
193 #define OP_SH_DISP24 (OP_IMM_TYPE | 1)
194 #define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
195 #define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
196 #define OP_SH_I5 (OP_IMM_TYPE |10)
197 #define OP_SH_I10 (OP_IMM_TYPE | 5)
198 #define OP_SH_COPID (OP_IMM_TYPE | 5)
199 #define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
200 #define OP_SH_I15 (OP_IMM_TYPE |10)
202 #define OP16_SH_REGD (OP_REG_TYPE | 8)
203 #define OP16_SH_REGS1 (OP_REG_TYPE | 4)
204 #define OP16_SH_I45 (OP_IMM_TYPE | 3)
205 #define OP16_SH_I8 (OP_IMM_TYPE | 0)
206 #define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
207 #define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
209 struct datafield_range
216 struct datafield_range score_df_range[] =
218 {_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
219 {_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
220 {_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
221 {_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
222 {_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
223 {_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
224 {_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
225 {_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
226 {_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
227 {_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
228 {_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
229 {_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
230 {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
231 {_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
232 {_IMM20, 20, {0, (1 << 20) - 1}},
233 {_IMM25, 25, {0, (1 << 25) - 1}},
234 {_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
235 {_DISP11div2, 11, {0, 0}},
236 {_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
237 {_DISP24div2, 24, {0, 0}},
238 {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
239 {_VALUE_HI16, 16, {0, (1 << 16) - 1}},
240 {_VALUE_LO16, 16, {0, (1 << 16) - 1}},
241 {_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
242 {_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
243 {_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
244 {_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
245 {_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
246 {_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
247 {_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
248 {_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
249 {_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
250 {_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
251 {_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
252 {_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
253 {_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
254 {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
255 {_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
256 {_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
257 {_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
258 {_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
259 {_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
260 {_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
261 {_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
262 {_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
269 struct datafield_range *df_range;
274 struct shift_bitmask score_sh_bits_map[] =
277 Rd_I4, 2, &score_df_range[_IMM4],
278 {OP16_SH_REGD, OP16_SH_I45, 0, 0},
282 Rd_I5, 2, &score_df_range[_IMM5],
283 {OP16_SH_REGD, OP16_SH_I45, 0, 0},
287 Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
288 {OP16_SH_REGD, OP16_SH_I45, 0, 0},
292 Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
293 {OP16_SH_REGD, OP16_SH_I45, 0, 0},
297 Rd_Rs_I5, 3, &score_df_range[_IMM5],
298 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
299 {0x1f, 0x1f, 0x1f, 0},
302 x_Rs_I5, 2, &score_df_range[_IMM5],
303 {OP_SH_REGS1, OP_SH_I5, 0, 0},
307 x_I5_x, 1, &score_df_range[_IMM5],
308 {OP_SH_TRAPI5, 0, 0, 0},
312 Rd_I8, 2, &score_df_range[_IMM8],
313 {OP16_SH_REGD, OP16_SH_I8, 0, 0},
317 Rd_Rs_I14, 3, &score_df_range[_IMM14],
318 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
319 {0x1f, 0x1f, 0x3fff, 0},
322 I15, 1, &score_df_range[_IMM15],
323 {OP_SH_I15, 0, 0, 0},
327 Rd_I16, 2, &score_df_range[_IMM16],
328 {OP_SH_REGD, OP_SH_I, 0, 0},
329 {0x1f, 0xffff, 0, 0},
332 Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
333 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
334 {0x1f, 0x1f, 0x3ff, 0},
337 Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
338 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
339 {0x1f, 0x1f, 0x3ff, 0},
342 Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
343 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
344 {0xf, 0xf, 0xfff, 0},
347 Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
348 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
349 {0xf, 0xf, 0xfff, 0},
352 Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
353 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
354 {0xf, 0xf, 0xfff, 0},
357 Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
358 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
359 {0xf, 0xf, 0xfff, 0},
362 Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
363 {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
364 {0x1f, 0x1f, 0x3fff, 0},
367 Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
368 {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
369 {0x1f, 0x1f, 0x7fff, 0},
372 Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
373 {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
374 {0x1f, 0x1f, 0x7fff, 0},
377 Rd_SI16, 2, &score_df_range[_SIMM16],
378 {OP_SH_REGD, OP_SH_I, 0, 0},
379 {0x1f, 0xffff, 0, 0},
382 PC_DISP8div2, 1, &score_df_range[_DISP8div2],
383 {OP16_SH_DISP8, 0, 0, 0},
387 PC_DISP11div2, 1, &score_df_range[_DISP11div2],
388 {OP16_SH_DISP11, 0, 0, 0},
392 PC_DISP19div2, 2, &score_df_range[_DISP19div2],
393 {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
394 {0x3ff, 0x1ff, 0, 0},
397 PC_DISP24div2, 1, &score_df_range[_DISP24div2],
398 {OP_SH_DISP24, 0, 0, 0},
403 {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
404 {0x1f, 0x1f, 0x1f, 0}
408 {OP_SH_REGD, OP_SH_REGS1, 0, 0},
413 {OP_SH_REGD, OP_SH_REGS2, 0, 0},
418 {OP_SH_REGD, 0, 0, 0},
423 {OP_SH_REGS1, OP_SH_REGS2, 0, 0},
428 {OP_SH_REGS1, 0, 0, 0},
433 {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
438 {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
442 Rd_rvalueRs, 2, NULL,
443 {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
447 Rd_lvalueRs, 2, NULL,
448 {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
452 Rd_lvalue32Rs, 2, NULL,
453 {OP_SH_REGD, OP_SH_REGS1, 0, 0},
457 Rd_rvalue32Rs, 2, NULL,
458 {OP_SH_REGD, OP_SH_REGS1, 0, 0},
463 {OP16_SH_REGS1, 0, 0, 0},
480 /* Instruction name. */
481 const char *template;
483 /* Instruction Opcode. */
486 /* Instruction bit mask. */
487 unsigned long bitmask;
489 /* Relax instruction opcode. 0x8000 imply no relaxation. */
490 unsigned long relax_value;
492 /* Instruction type. */
493 enum score_insn_type type;
495 /* Function to call to parse args. */
496 void (*parms) (char *);