1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 /* Port Group IDs (PGID) are masks of destination ports.
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55 * of the switch port net devices, towards the CPU port module.
56 * PGID_UC: the flooding destinations for unknown unicast traffic.
57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
65 #define PGID_MCIPV4 62
66 #define PGID_MCIPV6 63
68 /* Aggregation PGIDs, one per Link Aggregation Code */
71 /* Source PGIDs, one per physical port */
74 #define IFH_INJ_BYPASS BIT(31)
75 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
77 #define IFH_TAG_TYPE_C 0
78 #define IFH_TAG_TYPE_S 1
80 #define IFH_REW_OP_NOOP 0x0
81 #define IFH_REW_OP_DSCP 0x1
82 #define IFH_REW_OP_ONE_STEP_PTP 0x2
83 #define IFH_REW_OP_TWO_STEP_PTP 0x3
84 #define IFH_REW_OP_ORIGIN_PTP 0x5
86 #define OCELOT_TAG_LEN 16
87 #define OCELOT_SHORT_PREFIX_LEN 4
88 #define OCELOT_LONG_PREFIX_LEN 16
90 #define OCELOT_SPEED_2500 0
91 #define OCELOT_SPEED_1000 1
92 #define OCELOT_SPEED_100 2
93 #define OCELOT_SPEED_10 3
95 #define TARGET_OFFSET 24
96 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
97 #define REG(reg, offset) [reg & REG_MASK] = offset
99 #define REG_RESERVED_ADDR 0xffffffff
100 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
116 ANA_ADVLEARN = ANA << TARGET_OFFSET,
121 ANA_STORMLIMIT_BURST,
140 ANA_TABLES_STREAMDATA,
141 ANA_TABLES_MACACCESS,
143 ANA_TABLES_VLANACCESS,
145 ANA_TABLES_ISDXACCESS,
148 ANA_TABLES_PTP_ID_HIGH,
149 ANA_TABLES_PTP_ID_LOW,
150 ANA_TABLES_STREAMACCESS,
151 ANA_TABLES_STREAMTIDX,
152 ANA_TABLES_SEQ_HISTORY,
154 ANA_TABLES_SFID_MASK,
155 ANA_TABLES_SFIDACCESS,
165 ANA_SG_GCL_GS_CONFIG,
166 ANA_SG_GCL_TI_CONFIG,
174 ANA_PORT_VCAP_S1_KEY_CFG,
175 ANA_PORT_VCAP_S2_CFG,
176 ANA_PORT_PCP_DEI_MAP,
177 ANA_PORT_CPU_FWD_CFG,
178 ANA_PORT_CPU_FWD_BPDU_CFG,
179 ANA_PORT_CPU_FWD_GARP_CFG,
180 ANA_PORT_CPU_FWD_CCM_CFG,
184 ANA_PORT_PTP_DLY1_CFG,
185 ANA_PORT_PTP_DLY2_CFG,
199 ANA_VCAP_RNG_TYPE_CFG,
200 ANA_VCAP_RNG_VAL_CFG,
215 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
227 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
228 QSYS_SWITCH_PORT_MODE,
240 QSYS_TIMED_FRAME_ENTRY,
243 QSYS_TFRM_TIMER_CFG_1,
244 QSYS_TFRM_TIMER_CFG_2,
245 QSYS_TFRM_TIMER_CFG_3,
246 QSYS_TFRM_TIMER_CFG_4,
247 QSYS_TFRM_TIMER_CFG_5,
248 QSYS_TFRM_TIMER_CFG_6,
249 QSYS_TFRM_TIMER_CFG_7,
250 QSYS_TFRM_TIMER_CFG_8,
278 QSYS_TAS_PARAM_CFG_CTRL,
280 QSYS_PARAM_CFG_REG_1,
281 QSYS_PARAM_CFG_REG_2,
282 QSYS_PARAM_CFG_REG_3,
283 QSYS_PARAM_CFG_REG_4,
284 QSYS_PARAM_CFG_REG_5,
287 QSYS_PARAM_STATUS_REG_1,
288 QSYS_PARAM_STATUS_REG_2,
289 QSYS_PARAM_STATUS_REG_3,
290 QSYS_PARAM_STATUS_REG_4,
291 QSYS_PARAM_STATUS_REG_5,
292 QSYS_PARAM_STATUS_REG_6,
293 QSYS_PARAM_STATUS_REG_7,
294 QSYS_PARAM_STATUS_REG_8,
295 QSYS_PARAM_STATUS_REG_9,
296 QSYS_GCL_STATUS_REG_1,
297 QSYS_GCL_STATUS_REG_2,
298 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
302 REW_PCP_DEI_QOS_MAP_CFG,
306 REW_DSCP_REMAP_DP1_CFG,
311 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
312 SYS_COUNT_RX_UNICAST,
313 SYS_COUNT_RX_MULTICAST,
314 SYS_COUNT_RX_BROADCAST,
316 SYS_COUNT_RX_FRAGMENTS,
317 SYS_COUNT_RX_JABBERS,
318 SYS_COUNT_RX_CRC_ALIGN_ERRS,
319 SYS_COUNT_RX_SYM_ERRS,
322 SYS_COUNT_RX_128_255,
323 SYS_COUNT_RX_256_1023,
324 SYS_COUNT_RX_1024_1526,
325 SYS_COUNT_RX_1527_MAX,
327 SYS_COUNT_RX_CONTROL,
329 SYS_COUNT_RX_CLASSIFIED_DROPS,
331 SYS_COUNT_TX_UNICAST,
332 SYS_COUNT_TX_MULTICAST,
333 SYS_COUNT_TX_BROADCAST,
334 SYS_COUNT_TX_COLLISION,
339 SYS_COUNT_TX_128_511,
340 SYS_COUNT_TX_512_1023,
341 SYS_COUNT_TX_1024_1526,
342 SYS_COUNT_TX_1527_MAX,
353 SYS_REW_MAC_HIGH_CFG,
355 SYS_TIMESTAMP_OFFSET,
377 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
384 PTP_PIN_CFG = PTP << TARGET_OFFSET,
390 PTP_CLK_CFG_ADJ_FREQ,
391 GCB_SOFT_RST = GCB << TARGET_OFFSET,
394 enum ocelot_regfield {
395 ANA_ADVLEARN_VLAN_CHK,
396 ANA_ADVLEARN_LEARN_MIRROR,
397 ANA_ANEVENTS_FLOOD_DISCARD,
398 ANA_ANEVENTS_MSTI_DROP,
399 ANA_ANEVENTS_ACLKILL,
400 ANA_ANEVENTS_ACLUSED,
401 ANA_ANEVENTS_AUTOAGE,
402 ANA_ANEVENTS_VS2TTL1,
403 ANA_ANEVENTS_STORM_DROP,
404 ANA_ANEVENTS_LEARN_DROP,
405 ANA_ANEVENTS_AGED_ENTRY,
406 ANA_ANEVENTS_CPU_LEARN_FAILED,
407 ANA_ANEVENTS_AUTO_LEARN_FAILED,
408 ANA_ANEVENTS_LEARN_REMOVE,
409 ANA_ANEVENTS_AUTO_LEARNED,
410 ANA_ANEVENTS_AUTO_MOVED,
411 ANA_ANEVENTS_DROPPED,
412 ANA_ANEVENTS_CLASSIFIED_DROP,
413 ANA_ANEVENTS_CLASSIFIED_COPY,
414 ANA_ANEVENTS_VLAN_DISCARD,
415 ANA_ANEVENTS_FWD_DISCARD,
416 ANA_ANEVENTS_MULTICAST_FLOOD,
417 ANA_ANEVENTS_UNICAST_FLOOD,
418 ANA_ANEVENTS_DEST_KNOWN,
419 ANA_ANEVENTS_BUCKET3_MATCH,
420 ANA_ANEVENTS_BUCKET2_MATCH,
421 ANA_ANEVENTS_BUCKET1_MATCH,
422 ANA_ANEVENTS_BUCKET0_MATCH,
423 ANA_ANEVENTS_CPU_OPERATION,
424 ANA_ANEVENTS_DMAC_LOOKUP,
425 ANA_ANEVENTS_SMAC_LOOKUP,
426 ANA_ANEVENTS_SEQ_GEN_ERR_0,
427 ANA_ANEVENTS_SEQ_GEN_ERR_1,
428 ANA_TABLES_MACACCESS_B_DOM,
429 ANA_TABLES_MACTINDX_BUCKET,
430 ANA_TABLES_MACTINDX_M_INDEX,
431 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
432 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
433 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
434 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
435 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
436 SYS_RESET_CFG_CORE_ENA,
437 SYS_RESET_CFG_MEM_ENA,
438 SYS_RESET_CFG_MEM_INIT,
439 GCB_SOFT_RST_SWC_RST,
443 enum ocelot_clk_pins {
450 struct ocelot_stat_layout {
452 char name[ETH_GSTRING_LEN];
455 enum ocelot_tag_prefix {
456 OCELOT_TAG_PREFIX_DISABLED = 0,
457 OCELOT_TAG_PREFIX_NONE,
458 OCELOT_TAG_PREFIX_SHORT,
459 OCELOT_TAG_PREFIX_LONG,
465 int (*reset)(struct ocelot *ocelot);
468 struct ocelot_acl_block {
469 struct list_head rules;
475 struct ocelot *ocelot;
481 /* Ingress default VLAN (pvid) */
484 /* Egress default VLAN (vid) */
488 struct sk_buff_head tx_skbs;
491 phy_interface_t phy_mode;
497 const struct ocelot_ops *ops;
498 struct regmap *targets[TARGET_MAX];
499 struct regmap_field *regfields[REGFIELD_MAX];
500 const u32 *const *map;
501 const struct ocelot_stat_layout *stats_layout;
502 unsigned int num_stats;
506 struct net_device *hw_bridge_dev;
510 struct ocelot_port **ports;
512 u8 base_mac[ETH_ALEN];
514 /* Keep track of the vlan port masks */
515 u32 vlan_mask[VLAN_N_VID];
517 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
518 * the CPU is located after the physical ports (at the
519 * num_phys_ports index).
525 enum ocelot_tag_prefix inj_prefix;
526 enum ocelot_tag_prefix xtr_prefix;
530 struct list_head multicast;
532 struct ocelot_acl_block acl_block;
534 const struct vcap_field *vcap_is2_keys;
535 const struct vcap_field *vcap_is2_actions;
536 const struct vcap_props *vcap;
538 /* Workqueue to check statistics for overflow with its lock */
539 struct mutex stats_lock;
541 struct delayed_work stats_work;
542 struct workqueue_struct *stats_queue;
545 struct ptp_clock *ptp_clock;
546 struct ptp_clock_info ptp_info;
547 struct hwtstamp_config hwtstamp_config;
548 /* Protects the PTP interface state */
549 struct mutex ptp_lock;
550 /* Protects the PTP clock */
551 spinlock_t ptp_clock_lock;
554 struct ocelot_policer {
555 u32 rate; /* kilobit per second */
556 u32 burst; /* bytes */
559 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
560 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
561 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
562 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
564 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
565 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
566 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
567 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
569 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
570 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
571 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
572 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
575 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
576 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
577 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
578 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
579 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
582 /* Hardware initialization */
583 int ocelot_regfields_init(struct ocelot *ocelot,
584 const struct reg_field *const regfields);
585 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
586 void ocelot_configure_cpu(struct ocelot *ocelot, int npi,
587 enum ocelot_tag_prefix injection,
588 enum ocelot_tag_prefix extraction);
589 int ocelot_init(struct ocelot *ocelot);
590 void ocelot_deinit(struct ocelot *ocelot);
591 void ocelot_init_port(struct ocelot *ocelot, int port);
594 void ocelot_port_enable(struct ocelot *ocelot, int port,
595 struct phy_device *phy);
596 void ocelot_port_disable(struct ocelot *ocelot, int port);
597 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
598 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
599 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
600 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
601 struct ethtool_ts_info *info);
602 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
603 void ocelot_adjust_link(struct ocelot *ocelot, int port,
604 struct phy_device *phydev);
605 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
607 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
608 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
609 struct net_device *bridge);
610 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
611 struct net_device *bridge);
612 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
613 dsa_fdb_dump_cb_t *cb, void *data);
614 int ocelot_fdb_add(struct ocelot *ocelot, int port,
615 const unsigned char *addr, u16 vid);
616 int ocelot_fdb_del(struct ocelot *ocelot, int port,
617 const unsigned char *addr, u16 vid);
618 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
620 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
621 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
622 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
623 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
624 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
625 struct sk_buff *skb);
626 void ocelot_get_txtstamp(struct ocelot *ocelot);
627 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
628 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
629 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
630 struct ocelot_policer *pol);
631 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
632 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
633 struct flow_cls_offload *f, bool ingress);
634 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
635 struct flow_cls_offload *f, bool ingress);
636 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
637 struct flow_cls_offload *f, bool ingress);