include/sound/apr_audio.h

   1 /*
   2  *
   3  * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #ifndef _APR_AUDIO_H_
  17 #define _APR_AUDIO_H_
  18
  19 /* ASM opcodes without APR payloads*/
  20 #include <linux/qdsp6v2/apr.h>
  21
  22 /*
  23  * Audio Front End (AFE)
  24  */
  25
  26 /* Port ID. Update afe_get_port_index when a new port is added here. */
  27 #define PRIMARY_I2S_RX 0                /* index = 0 */
  28 #define PRIMARY_I2S_TX 1                /* index = 1 */
  29 #define PCM_RX 2                        /* index = 2 */
  30 #define PCM_TX 3                        /* index = 3 */
  31 #define SECONDARY_I2S_RX 4              /* index = 4 */
  32 #define SECONDARY_I2S_TX 5              /* index = 5 */
  33 #define MI2S_RX 6                       /* index = 6 */
  34 #define MI2S_TX 7                       /* index = 7 */
  35 #define HDMI_RX 8                       /* index = 8 */
  36 #define RSVD_2 9                        /* index = 9 */
  37 #define RSVD_3 10                       /* index = 10 */
  38 #define DIGI_MIC_TX 11                  /* index = 11 */
  39 #define VOICE_RECORD_RX 0x8003          /* index = 12 */
  40 #define VOICE_RECORD_TX 0x8004          /* index = 13 */
  41 #define VOICE_PLAYBACK_TX 0x8005        /* index = 14 */
  42
  43 /* Slimbus Multi channel port id pool  */
  44 #define SLIMBUS_0_RX            0x4000          /* index = 15 */
  45 #define SLIMBUS_0_TX            0x4001          /* index = 16 */
  46 #define SLIMBUS_1_RX            0x4002          /* index = 17 */
  47 #define SLIMBUS_1_TX            0x4003          /* index = 18 */
  48 #define SLIMBUS_2_RX            0x4004
  49 #define SLIMBUS_2_TX            0x4005
  50 #define SLIMBUS_3_RX            0x4006
  51 #define SLIMBUS_3_TX            0x4007
  52 #define SLIMBUS_4_RX            0x4008
  53 #define SLIMBUS_4_TX            0x4009          /* index = 24 */
  54
  55 #define INT_BT_SCO_RX 0x3000            /* index = 25 */
  56 #define INT_BT_SCO_TX 0x3001            /* index = 26 */
  57 #define INT_BT_A2DP_RX 0x3002           /* index = 27 */
  58 #define INT_FM_RX 0x3004                /* index = 28 */
  59 #define INT_FM_TX 0x3005                /* index = 29 */
  60 #define RT_PROXY_PORT_001_RX    0x2000    /* index = 30 */
  61 #define RT_PROXY_PORT_001_TX    0x2001    /* index = 31 */
  62 #define SECONDARY_PCM_RX 12                     /* index = 32 */
  63 #define SECONDARY_PCM_TX 13                     /* index = 33 */
  64 #define PSEUDOPORT_01           0x8001    /* index =34 */
  65
  66 #define AFE_PORT_INVALID 0xFFFF
  67 #define SLIMBUS_EXTPROC_RX AFE_PORT_INVALID
  68
  69 #define AFE_PORT_CMD_START 0x000100ca
  70
  71 #define AFE_EVENT_RTPORT_START 0
  72 #define AFE_EVENT_RTPORT_STOP 1
  73 #define AFE_EVENT_RTPORT_LOW_WM 2
  74 #define AFE_EVENT_RTPORT_HI_WM 3
  75
  76 struct afe_port_start_command {
  77         struct apr_hdr hdr;
  78         u16 port_id;
  79         u16 gain;               /* Q13 */
  80         u32 sample_rate;        /* 8 , 16, 48khz */
  81 } __attribute__ ((packed));
  82
  83 #define AFE_PORT_CMD_STOP 0x000100cb
  84 struct afe_port_stop_command {
  85         struct apr_hdr hdr;
  86         u16 port_id;
  87         u16 reserved;
  88 } __attribute__ ((packed));
  89
  90 #define AFE_PORT_CMD_APPLY_GAIN 0x000100cc
  91 struct afe_port_gain_command {
  92         struct apr_hdr hdr;
  93         u16 port_id;
  94         u16     gain;/* Q13 */
  95 } __attribute__ ((packed));
  96
  97 #define AFE_PORT_CMD_SIDETONE_CTL 0x000100cd
  98 struct afe_port_sidetone_command {
  99         struct apr_hdr hdr;
 100         u16 rx_port_id;         /* Primary i2s tx = 1 */
 101                                 /* PCM tx = 3 */
 102                                 /* Secondary i2s tx = 5 */
 103                                 /* Mi2s tx = 7 */
 104                                 /* Digital mic tx = 11 */
 105         u16 tx_port_id;         /* Primary i2s rx = 0 */
 106                                 /* PCM rx = 2 */
 107                                 /* Secondary i2s rx = 4 */
 108                                 /* Mi2S rx = 6 */
 109                                 /* HDMI rx = 8 */
 110         u16 gain;               /* Q13 */
 111         u16 enable;             /* 1 = enable, 0 = disable */
 112 } __attribute__ ((packed));
 113
 114 #define AFE_PORT_CMD_LOOPBACK 0x000100ce
 115 struct afe_loopback_command {
 116         struct apr_hdr hdr;
 117         u16 tx_port_id;         /* Primary i2s rx = 0 */
 118                                 /* PCM rx = 2 */
 119                                 /* Secondary i2s rx = 4 */
 120                                 /* Mi2S rx = 6 */
 121                                 /* HDMI rx = 8 */
 122         u16 rx_port_id;         /* Primary i2s tx = 1 */
 123                                 /* PCM tx = 3 */
 124                                 /* Secondary i2s tx = 5 */
 125                                 /* Mi2s tx = 7 */
 126                                 /* Digital mic tx = 11 */
 127         u16 mode;               /* Default -1, DSP will conver
 128                                         the tx to rx format */
 129         u16 enable;             /* 1 = enable, 0 = disable */
 130 } __attribute__ ((packed));
 131
 132 #define AFE_PSEUDOPORT_CMD_START 0x000100cf
 133 struct afe_pseudoport_start_command {
 134         struct apr_hdr hdr;
 135         u16 port_id;            /* Pseudo Port 1 = 0x8000 */
 136                                 /* Pseudo Port 2 = 0x8001 */
 137                                 /* Pseudo Port 3 = 0x8002 */
 138         u16 timing;             /* FTRT = 0 , AVTimer = 1, */
 139 } __attribute__ ((packed));
 140
 141 #define AFE_PSEUDOPORT_CMD_STOP 0x000100d0
 142 struct afe_pseudoport_stop_command {
 143         struct apr_hdr hdr;
 144         u16 port_id;            /* Pseudo Port 1 = 0x8000 */
 145                                 /* Pseudo Port 2 = 0x8001 */
 146                                 /* Pseudo Port 3 = 0x8002 */
 147         u16 reserved;
 148 } __attribute__ ((packed));
 149
 150 #define AFE_CMD_GET_ACTIVE_PORTS 0x000100d1
 151
 152
 153 #define AFE_CMD_GET_ACTIVE_HANDLES_FOR_PORT 0x000100d2
 154 struct afe_get_active_handles_command {
 155         struct apr_hdr hdr;
 156         u16 port_id;
 157         u16 reserved;
 158 } __attribute__ ((packed));
 159
 160 /*
 161  * Opcode for AFE to start DTMF.
 162  */
 163 #define AFE_PORTS_CMD_DTMF_CTL  0x00010102
 164
 165 /** DTMF payload.*/
 166 struct afe_dtmf_generation_command {
 167         struct apr_hdr hdr;
 168
 169         /*
 170          * Duration of the DTMF tone in ms.
 171          * -1      -> continuous,
 172          *  0      -> disable
 173          */
 174         int64_t                   duration_in_ms;
 175
 176         /*
 177          * The DTMF high tone frequency.
 178          */
 179         uint16_t                  high_freq;
 180
 181         /*
 182          * The DTMF low tone frequency.
 183          */
 184         uint16_t                  low_freq;
 185
 186         /*
 187          * The DTMF volume setting
 188          */
 189         uint16_t                  gain;
 190
 191         /*
 192          * The number of ports to enable/disable on.
 193          */
 194         uint16_t                  num_ports;
 195
 196         /*
 197          * The Destination ports - array  .
 198          * For DTMF on multiple ports, portIds needs to
 199          * be populated numPorts times.
 200          */
 201         uint16_t                  port_ids;
 202
 203         /*
 204          * variable for 32 bit alignment of APR packet.
 205          */
 206         uint16_t                  reserved;
 207 } __packed;
 208
 209 #define AFE_PCM_CFG_MODE_PCM                    0x0
 210 #define AFE_PCM_CFG_MODE_AUX                    0x1
 211 #define AFE_PCM_CFG_SYNC_EXT                    0x0
 212 #define AFE_PCM_CFG_SYNC_INT                    0x1
 213 #define AFE_PCM_CFG_FRM_8BPF                    0x0
 214 #define AFE_PCM_CFG_FRM_16BPF                   0x1
 215 #define AFE_PCM_CFG_FRM_32BPF                   0x2
 216 #define AFE_PCM_CFG_FRM_64BPF                   0x3
 217 #define AFE_PCM_CFG_FRM_128BPF                  0x4
 218 #define AFE_PCM_CFG_FRM_256BPF                  0x5
 219 #define AFE_PCM_CFG_QUANT_ALAW_NOPAD            0x0
 220 #define AFE_PCM_CFG_QUANT_MULAW_NOPAD           0x1
 221 #define AFE_PCM_CFG_QUANT_LINEAR_NOPAD          0x2
 222 #define AFE_PCM_CFG_QUANT_ALAW_PAD              0x3
 223 #define AFE_PCM_CFG_QUANT_MULAW_PAD             0x4
 224 #define AFE_PCM_CFG_QUANT_LINEAR_PAD            0x5
 225 #define AFE_PCM_CFG_CDATAOE_MASTER              0x0
 226 #define AFE_PCM_CFG_CDATAOE_SHARE               0x1
 227
 228 struct afe_port_pcm_cfg {
 229         u16     mode;   /* PCM (short sync) = 0, AUXPCM (long sync) = 1 */
 230         u16     sync;   /* external = 0 , internal = 1 */
 231         u16     frame;  /* 8 bpf = 0 */
 232                         /* 16 bpf = 1 */
 233                         /* 32 bpf = 2 */
 234                         /* 64 bpf = 3 */
 235                         /* 128 bpf = 4 */
 236                         /* 256 bpf = 5 */
 237         u16     quant;
 238         u16     slot;   /* Slot for PCM stream , 0 - 31 */
 239         u16     data;   /* 0, PCM block is the only master */
 240                         /* 1, PCM block is shares to driver data out signal */
 241                         /*    other master                                  */
 242         u16     reserved;
 243 } __attribute__ ((packed));
 244
 245 enum {
 246         AFE_I2S_SD0 = 1,
 247         AFE_I2S_SD1,
 248         AFE_I2S_SD2,
 249         AFE_I2S_SD3,
 250         AFE_I2S_QUAD01,
 251         AFE_I2S_QUAD23,
 252         AFE_I2S_6CHS,
 253         AFE_I2S_8CHS,
 254 };
 255
 256 #define AFE_MI2S_MONO 0
 257 #define AFE_MI2S_STEREO 3
 258 #define AFE_MI2S_4CHANNELS 4
 259 #define AFE_MI2S_6CHANNELS 6
 260 #define AFE_MI2S_8CHANNELS 8
 261
 262 struct afe_port_mi2s_cfg {
 263         u16     bitwidth;       /* 16,24,32 */
 264         u16     line;           /* Called ChannelMode in documentation */
 265                                 /* i2s_sd0 = 1 */
 266                                 /* i2s_sd1 = 2 */
 267                                 /* i2s_sd2 = 3 */
 268                                 /* i2s_sd3 = 4 */
 269                                 /* i2s_quad01 = 5 */
 270                                 /* i2s_quad23 = 6 */
 271                                 /* i2s_6chs = 7 */
 272                                 /* i2s_8chs = 8 */
 273         u16     channel;        /* Called MonoStereo in documentation */
 274                                 /* i2s mono = 0 */
 275                                 /* i2s mono right = 1 */
 276                                 /* i2s mono left = 2 */
 277                                 /* i2s stereo = 3 */
 278         u16     ws;             /* 0, word select signal from external source */
 279                                 /* 1, word select signal from internal source */
 280         u16     format; /* don't touch this field if it is not for */
 281                                 /* AFE_PORT_CMD_I2S_CONFIG opcode */
 282 } __attribute__ ((packed));
 283
 284 struct afe_port_hdmi_cfg {
 285         u16     bitwidth;       /* 16,24,32 */
 286         u16     channel_mode;   /* HDMI Stereo = 0 */
 287                                 /* HDMI_3Point1 (4-ch) = 1 */
 288                                 /* HDMI_5Point1 (6-ch) = 2 */
 289                                 /* HDMI_6Point1 (8-ch) = 3 */
 290         u16     data_type;      /* HDMI_Linear = 0 */
 291                                 /* HDMI_non_Linear = 1 */
 292 } __attribute__ ((packed));
 293
 294
 295 struct afe_port_hdmi_multi_ch_cfg {
 296         u16     data_type;              /* HDMI_Linear = 0 */
 297                                         /* HDMI_non_Linear = 1 */
 298         u16     channel_allocation;     /* The default is 0 (Stereo) */
 299         u16     reserved;               /* must be set to 0 */
 300 } __packed;
 301
 302
 303 /* Slimbus Device Ids */
 304 #define AFE_SLIMBUS_DEVICE_1            0x0
 305 #define AFE_SLIMBUS_DEVICE_2            0x1
 306 #define AFE_PORT_MAX_AUDIO_CHAN_CNT     16
 307
 308 struct afe_port_slimbus_cfg {
 309         u16     slimbus_dev_id;         /* SLIMBUS Device id.*/
 310
 311         u16     slave_dev_pgd_la;       /* Slave ported generic device
 312                                         * logical address.
 313                                         */
 314         u16     slave_dev_intfdev_la;   /* Slave interface device logical
 315                                         * address.
 316                                         */
 317         u16     bit_width;              /**  bit width of the samples, 16, 24.*/
 318
 319         u16     data_format;            /** data format.*/
 320
 321         u16     num_channels;           /** Number of channels.*/
 322
 323         /** Slave port mapping for respective channels.*/
 324         u16     slave_port_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT];
 325
 326         u16     reserved;
 327 } __packed;
 328
 329 struct afe_port_slimbus_sch_cfg {
 330         u16     slimbus_dev_id;         /* SLIMBUS Device id.*/
 331         u16     bit_width;              /**  bit width of the samples, 16, 24.*/
 332         u16     data_format;            /** data format.*/
 333         u16     num_channels;           /** Number of channels.*/
 334         u16     reserved;
 335         /** Slave channel  mapping for respective channels.*/
 336         u8      slave_ch_mapping[8];
 337 } __packed;
 338
 339 struct afe_port_rtproxy_cfg {
 340         u16     bitwidth;       /* 16,24,32 */
 341         u16     interleaved;    /* interleaved = 1 */
 342                                 /* Noninterleaved = 0 */
 343         u16     frame_sz;       /* 5ms buffers = 160bytes */
 344         u16     jitter;         /* 10ms of jitter = 320 */
 345         u16     lw_mark;        /* Low watermark in bytes for triggering event*/
 346         u16     hw_mark;        /* High watermark bytes for triggering event*/
 347         u16     rsvd;
 348         int     num_ch;         /* 1 to 8 */
 349 } __packed;
 350
 351 struct afe_port_pseudo_cfg {
 352         u16 bit_width;
 353         u16 num_channels;
 354         u16 data_format;
 355         u16 timing_mode;
 356         u16 reserved;
 357 } __packed;
 358
 359 #define AFE_PORT_AUDIO_IF_CONFIG 0x000100d3
 360 #define AFE_PORT_AUDIO_SLIM_SCH_CONFIG 0x000100e4
 361 #define AFE_PORT_MULTI_CHAN_HDMI_AUDIO_IF_CONFIG        0x000100D9
 362 #define AFE_PORT_CMD_I2S_CONFIG 0x000100E7
 363
 364 union afe_port_config {
 365         struct afe_port_pcm_cfg           pcm;
 366         struct afe_port_mi2s_cfg          mi2s;
 367         struct afe_port_hdmi_cfg          hdmi;
 368         struct afe_port_hdmi_multi_ch_cfg hdmi_multi_ch;
 369         struct afe_port_slimbus_cfg       slimbus;
 370         struct afe_port_slimbus_sch_cfg   slim_sch;
 371         struct afe_port_rtproxy_cfg       rtproxy;
 372         struct afe_port_pseudo_cfg        pseudo;
 373 } __attribute__((packed));
 374
 375 struct afe_audioif_config_command {
 376         struct apr_hdr hdr;
 377         u16 port_id;
 378         union afe_port_config port;
 379 } __attribute__ ((packed));
 380
 381 #define AFE_TEST_CODEC_LOOPBACK_CTL 0x000100d5
 382 struct afe_codec_loopback_command {
 383         u16     port_inf;       /* Primary i2s = 0 */
 384                                 /* PCM = 2 */
 385                                 /* Secondary i2s = 4 */
 386                                 /* Mi2s = 6 */
 387         u16     enable;         /* 0, disable. 1, enable */
 388 } __attribute__ ((packed));
 389
 390
 391 #define AFE_PARAM_ID_SIDETONE_GAIN      0x00010300
 392 struct afe_param_sidetone_gain {
 393         u16 gain;
 394         u16 reserved;
 395 } __attribute__ ((packed));
 396
 397 #define AFE_PARAM_ID_SAMPLING_RATE      0x00010301
 398 struct afe_param_sampling_rate {
 399         u32 sampling_rate;
 400 } __attribute__ ((packed));
 401
 402
 403 #define AFE_PARAM_ID_CHANNELS           0x00010302
 404 struct afe_param_channels {
 405         u16 channels;
 406         u16 reserved;
 407 } __attribute__ ((packed));
 408
 409
 410 #define AFE_PARAM_ID_LOOPBACK_GAIN      0x00010303
 411 struct afe_param_loopback_gain {
 412         u16 gain;
 413         u16 reserved;
 414 } __attribute__ ((packed));
 415
 416 /* Parameter ID used to configure and enable/disable the loopback path. The
 417  * difference with respect to the existing API, AFE_PORT_CMD_LOOPBACK, is that
 418  * it allows Rx port to be configured as source port in loopback path. Port-id
 419  * in AFE_PORT_CMD_SET_PARAM cmd is the source port whcih can be Tx or Rx port.
 420  * In addition, we can configure the type of routing mode to handle different
 421  * use cases.
 422 */
 423 enum {
 424         /* Regular loopback from source to destination port */
 425         LB_MODE_DEFAULT = 1,
 426         /* Sidetone feed from Tx source to Rx destination port */
 427         LB_MODE_SIDETONE,
 428         /* Echo canceller reference, voice + audio + DTMF */
 429         LB_MODE_EC_REF_VOICE_AUDIO,
 430         /* Echo canceller reference, voice alone */
 431         LB_MODE_EC_REF_VOICE
 432 };
 433
 434 #define AFE_PARAM_ID_LOOPBACK_CONFIG 0x0001020B
 435 #define AFE_API_VERSION_LOOPBACK_CONFIG 0x1
 436 struct afe_param_loopback_cfg {
 437         /* Minor version used for tracking the version of the configuration
 438          * interface.
 439          */
 440         uint32_t loopback_cfg_minor_version;
 441
 442         /* Destination Port Id. */
 443         uint16_t dst_port_id;
 444
 445         /* Specifies data path type from src to dest port. Supported values:
 446          * LB_MODE_DEFAULT
 447          * LB_MODE_SIDETONE
 448          * LB_MODE_EC_REF_VOICE_AUDIO
 449          * LB_MODE_EC_REF_VOICE
 450          */
 451         uint16_t routing_mode;
 452
 453         /* Specifies whether to enable (1) or disable (0) an AFE loopback. */
 454         uint16_t enable;
 455
 456         /* Reserved for 32-bit alignment. This field must be set to 0. */
 457         uint16_t reserved;
 458 } __packed;
 459
 460 #define AFE_MODULE_ID_PORT_INFO         0x00010200
 461 /* Module ID for the loopback-related parameters. */
 462 #define AFE_MODULE_LOOPBACK           0x00010205
 463 struct afe_param_payload_base {
 464         u32 module_id;
 465         u32 param_id;
 466         u16 param_size;
 467         u16 reserved;
 468 } __packed;
 469
 470 struct afe_param_payload {
 471         struct afe_param_payload_base base;
 472         union {
 473                 struct afe_param_sidetone_gain sidetone_gain;
 474                 struct afe_param_sampling_rate sampling_rate;
 475                 struct afe_param_channels      channels;
 476                 struct afe_param_loopback_gain loopback_gain;
 477                 struct afe_param_loopback_cfg loopback_cfg;
 478         } __attribute__((packed)) param;
 479 } __attribute__ ((packed));
 480
 481 #define AFE_PORT_CMD_SET_PARAM          0x000100dc
 482
 483 struct afe_port_cmd_set_param {
 484         struct apr_hdr hdr;
 485         u16 port_id;
 486         u16 payload_size;
 487         u32 payload_address;
 488         struct afe_param_payload payload;
 489 } __attribute__ ((packed));
 490
 491 struct afe_port_cmd_set_param_no_payload {
 492         struct apr_hdr hdr;
 493         u16 port_id;
 494         u16 payload_size;
 495         u32 payload_address;
 496 } __packed;
 497
 498 #define AFE_EVENT_GET_ACTIVE_PORTS 0x00010100
 499 struct afe_get_active_ports_rsp {
 500         u16     num_ports;
 501         u16     port_id;
 502 } __attribute__ ((packed));
 503
 504
 505 #define AFE_EVENT_GET_ACTIVE_HANDLES 0x00010102
 506 struct afe_get_active_handles_rsp {
 507         u16     port_id;
 508         u16     num_handles;
 509         u16     mode;           /* 0, voice rx */
 510                                 /* 1, voice tx */
 511                                 /* 2, audio rx */
 512                                 /* 3, audio tx */
 513         u16     handle;
 514 } __attribute__ ((packed));
 515
 516 #define AFE_SERVICE_CMD_MEMORY_MAP 0x000100DE
 517 struct afe_cmd_memory_map {
 518         struct apr_hdr hdr;
 519         u32 phy_addr;
 520         u32 mem_sz;
 521         u16 mem_id;
 522         u16 rsvd;
 523 } __packed;
 524
 525 #define AFE_SERVICE_CMD_MEMORY_UNMAP 0x000100DF
 526 struct afe_cmd_memory_unmap {
 527         struct apr_hdr hdr;
 528         u32 phy_addr;
 529 } __packed;
 530
 531 #define AFE_SERVICE_CMD_REG_RTPORT 0x000100E0
 532 struct afe_cmd_reg_rtport {
 533         struct apr_hdr hdr;
 534         u16 port_id;
 535         u16 rsvd;
 536 } __packed;
 537
 538 #define AFE_SERVICE_CMD_UNREG_RTPORT 0x000100E1
 539 struct afe_cmd_unreg_rtport {
 540         struct apr_hdr hdr;
 541         u16 port_id;
 542         u16 rsvd;
 543 } __packed;
 544
 545 #define AFE_SERVICE_CMD_RTPORT_WR 0x000100E2
 546 struct afe_cmd_rtport_wr {
 547         struct apr_hdr hdr;
 548         u16 port_id;
 549         u16 rsvd;
 550         u32 buf_addr;
 551         u32 bytes_avail;
 552 } __packed;
 553
 554 #define AFE_SERVICE_CMD_RTPORT_RD 0x000100E3
 555 struct afe_cmd_rtport_rd {
 556         struct apr_hdr hdr;
 557         u16 port_id;
 558         u16 rsvd;
 559         u32 buf_addr;
 560         u32 bytes_avail;
 561 } __packed;
 562
 563 #define AFE_EVENT_RT_PROXY_PORT_STATUS 0x00010105
 564
 565 #define ADM_MAX_COPPS 5
 566
 567 #define ADM_SERVICE_CMD_GET_COPP_HANDLES                 0x00010300
 568 struct adm_get_copp_handles_command {
 569         struct apr_hdr hdr;
 570 } __attribute__ ((packed));
 571
 572 #define ADM_CMD_MATRIX_MAP_ROUTINGS                      0x00010301
 573 struct adm_routings_session {
 574         u16 id;
 575         u16 num_copps;
 576         u16 copp_id[ADM_MAX_COPPS+1]; /*Padding if numCopps is odd */
 577 } __packed;
 578
 579 struct adm_routings_command {
 580         struct apr_hdr hdr;
 581         u32 path; /* 0 = Rx, 1 Tx */
 582         u32 num_sessions;
 583         struct adm_routings_session session[8];
 584 } __attribute__ ((packed));
 585
 586
 587 #define ADM_CMD_MATRIX_RAMP_GAINS                        0x00010302
 588 struct adm_ramp_gain {
 589         struct apr_hdr hdr;
 590         u16 session_id;
 591         u16 copp_id;
 592         u16 initial_gain;
 593         u16 gain_increment;
 594         u16 ramp_duration;
 595         u16 reserved;
 596 } __attribute__ ((packed));
 597
 598 struct adm_ramp_gains_command {
 599         struct apr_hdr hdr;
 600         u32 id;
 601         u32 num_gains;
 602         struct adm_ramp_gain gains[ADM_MAX_COPPS];
 603 } __attribute__ ((packed));
 604
 605
 606 #define ADM_CMD_COPP_OPEN                                0x00010304
 607 struct adm_copp_open_command {
 608         struct apr_hdr hdr;
 609         u16 flags;
 610         u16 mode; /* 1-RX, 2-Live TX, 3-Non Live TX */
 611         u16 endpoint_id1;
 612         u16 endpoint_id2;
 613         u32 topology_id;
 614         u16 channel_config;
 615         u16 reserved;
 616         u32 rate;
 617 } __attribute__ ((packed));
 618
 619 #define ADM_CMD_COPP_CLOSE                               0x00010305
 620
 621 #define ADM_CMD_MULTI_CHANNEL_COPP_OPEN                  0x00010310
 622 #define ADM_CMD_MULTI_CHANNEL_COPP_OPEN_V3               0x00010333
 623 struct adm_multi_ch_copp_open_command {
 624         struct apr_hdr hdr;
 625         u16 flags;
 626         u16 mode; /* 1-RX, 2-Live TX, 3-Non Live TX */
 627         u16 endpoint_id1;
 628         u16 endpoint_id2;
 629         u32 topology_id;
 630         u16 channel_config;
 631         u16 reserved;
 632         u32 rate;
 633         u8 dev_channel_mapping[8];
 634 } __packed;
 635
 636 struct adm_multi_channel_copp_open_v3 {
 637         struct apr_hdr hdr;
 638         u16 flags;
 639         u16 mode;
 640         u16 endpoint_id1;
 641         u16 endpoint_id2;
 642         u32 topology_id;
 643         u16 channel_config;
 644         u16 bit_width;
 645         u32 rate;
 646         u8  dev_channel_mapping[8];
 647 };
 648 #define ADM_CMD_MEMORY_MAP                              0x00010C30
 649 struct adm_cmd_memory_map{
 650         struct apr_hdr  hdr;
 651         u32             buf_add;
 652         u32             buf_size;
 653         u16             mempool_id;
 654         u16             reserved;
 655 } __attribute__((packed));
 656
 657 #define ADM_CMD_MEMORY_UNMAP                            0x00010C31
 658 struct adm_cmd_memory_unmap{
 659         struct apr_hdr  hdr;
 660         u32             buf_add;
 661 } __attribute__((packed));
 662
 663 #define ADM_CMD_MEMORY_MAP_REGIONS                      0x00010C47
 664 struct adm_memory_map_regions{
 665         u32             phys;
 666         u32             buf_size;
 667 } __attribute__((packed));
 668
 669 struct adm_cmd_memory_map_regions{
 670         struct apr_hdr  hdr;
 671         u16             mempool_id;
 672         u16             nregions;
 673 } __attribute__((packed));
 674
 675 #define ADM_CMD_MEMORY_UNMAP_REGIONS                    0x00010C48
 676 struct adm_memory_unmap_regions{
 677         u32             phys;
 678 } __attribute__((packed));
 679
 680 struct adm_cmd_memory_unmap_regions{
 681         struct apr_hdr  hdr;
 682         u16             nregions;
 683         u16             reserved;
 684 } __attribute__((packed));
 685
 686 #define DEFAULT_COPP_TOPOLOGY                           0x00010be3
 687 #define DEFAULT_POPP_TOPOLOGY                           0x00010be4
 688 #define VPM_TX_SM_ECNS_COPP_TOPOLOGY                    0x00010F71
 689 #define VPM_TX_DM_FLUENCE_COPP_TOPOLOGY                 0x00010F72
 690 #define VPM_TX_QMIC_FLUENCE_COPP_TOPOLOGY               0x00010F75
 691
 692 #define LOWLATENCY_POPP_TOPOLOGY                        0x00010C68
 693 #define LOWLATENCY_COPP_TOPOLOGY                        0x00010312
 694 #define PCM_BITS_PER_SAMPLE                             16
 695
 696 #define ASM_OPEN_WRITE_PERF_MODE_BIT                    (1<<28)
 697 #define ASM_OPEN_READ_PERF_MODE_BIT                     (1<<29)
 698 #define ADM_MULTI_CH_COPP_OPEN_PERF_MODE_BIT            (1<<13)
 699
 700
 701 #define ASM_MAX_EQ_BANDS 12
 702
 703 struct asm_eq_band {
 704         u32 band_idx; /* The band index, 0 .. 11 */
 705         u32 filter_type; /* Filter band type */
 706         u32 center_freq_hz; /* Filter band center frequency */
 707         u32 filter_gain; /* Filter band initial gain (dB) */
 708                         /* Range is +12 dB to -12 dB with 1dB increments. */
 709         u32 q_factor;
 710 } __attribute__ ((packed));
 711
 712 struct asm_equalizer_params {
 713         u32 enable;
 714         u32 num_bands;
 715         struct asm_eq_band eq_bands[ASM_MAX_EQ_BANDS];
 716 } __attribute__ ((packed));
 717
 718 struct asm_master_gain_params {
 719         u16 master_gain;
 720         u16 padding;
 721 } __attribute__ ((packed));
 722
 723 struct asm_lrchannel_gain_params {
 724         u16 left_gain;
 725         u16 right_gain;
 726 } __attribute__ ((packed));
 727
 728 struct asm_mute_params {
 729         u32 muteflag;
 730 } __attribute__ ((packed));
 731
 732 struct asm_softvolume_params {
 733         u32 period;
 734         u32 step;
 735         u32 rampingcurve;
 736 } __attribute__ ((packed));
 737
 738 struct asm_softpause_params {
 739         u32 enable;
 740         u32 period;
 741         u32 step;
 742         u32 rampingcurve;
 743 } __packed;
 744
 745 struct asm_pp_param_data_hdr {
 746         u32 module_id;
 747         u32 param_id;
 748         u16 param_size;
 749         u16 reserved;
 750 } __attribute__ ((packed));
 751
 752 struct asm_pp_params_command {
 753         struct apr_hdr  hdr;
 754         u32    *payload;
 755         u32     payload_size;
 756         struct  asm_pp_param_data_hdr params;
 757 } __attribute__ ((packed));
 758
 759 #define EQUALIZER_MODULE_ID             0x00010c27
 760 #define EQUALIZER_PARAM_ID              0x00010c28
 761
 762 #define VOLUME_CONTROL_MODULE_ID        0x00010bfe
 763 #define MASTER_GAIN_PARAM_ID            0x00010bff
 764 #define L_R_CHANNEL_GAIN_PARAM_ID       0x00010c00
 765 #define MUTE_CONFIG_PARAM_ID 0x00010c01
 766 #define SOFT_PAUSE_PARAM_ID 0x00010D6A
 767 #define SOFT_VOLUME_PARAM_ID 0x00010C29
 768
 769 #define IIR_FILTER_ENABLE_PARAM_ID 0x00010c03
 770 #define IIR_FILTER_PREGAIN_PARAM_ID 0x00010c04
 771 #define IIR_FILTER_CONFIG_PARAM_ID 0x00010c05
 772
 773 #define MBADRC_MODULE_ID 0x00010c06
 774 #define MBADRC_ENABLE_PARAM_ID 0x00010c07
 775 #define MBADRC_CONFIG_PARAM_ID 0x00010c08
 776
 777
 778 #define ADM_CMD_SET_PARAMS                               0x00010306
 779 #define ADM_CMD_GET_PARAMS                               0x0001030B
 780 #define ADM_CMDRSP_GET_PARAMS                            0x0001030C
 781 struct adm_set_params_command {
 782         struct apr_hdr          hdr;
 783         u32                     payload;
 784         u32                     payload_size;
 785 } __attribute__ ((packed));
 786
 787
 788 #define ADM_CMD_TAP_COPP_PCM                             0x00010307
 789 struct adm_tap_copp_pcm_command {
 790         struct apr_hdr hdr;
 791 } __attribute__ ((packed));
 792
 793
 794 /* QDSP6 to Client messages
 795 */
 796 #define ADM_SERVICE_CMDRSP_GET_COPP_HANDLES              0x00010308
 797 struct adm_get_copp_handles_respond {
 798         struct apr_hdr hdr;
 799         u32 handles;
 800         u32 copp_id;
 801 } __attribute__ ((packed));
 802
 803 #define ADM_CMDRSP_COPP_OPEN                             0x0001030A
 804 struct adm_copp_open_respond {
 805         u32 status;
 806         u16 copp_id;
 807         u16 reserved;
 808 } __attribute__ ((packed));
 809
 810 #define ADM_CMDRSP_MULTI_CHANNEL_COPP_OPEN               0x00010311
 811 #define ADM_CMDRSP_MULTI_CHANNEL_COPP_OPEN_V3            0x00010334
 812
 813
 814 #define ASM_STREAM_PRIORITY_NORMAL      0
 815 #define ASM_STREAM_PRIORITY_LOW         1
 816 #define ASM_STREAM_PRIORITY_HIGH        2
 817 #define ASM_STREAM_PRIORITY_RESERVED    3
 818
 819 #define ASM_END_POINT_DEVICE_MATRIX     0
 820 #define ASM_END_POINT_STREAM            1
 821
 822 #define AAC_ENC_MODE_AAC_LC            0x02
 823 #define AAC_ENC_MODE_AAC_P             0x05
 824 #define AAC_ENC_MODE_EAAC_P            0x1D
 825
 826 #define ASM_STREAM_CMD_CLOSE                             0x00010BCD
 827 #define ASM_STREAM_CMD_FLUSH                             0x00010BCE
 828 #define ASM_STREAM_CMD_SET_PP_PARAMS                     0x00010BCF
 829 #define ASM_STREAM_CMD_GET_PP_PARAMS                     0x00010BD0
 830 #define ASM_STREAM_CMDRSP_GET_PP_PARAMS                  0x00010BD1
 831 #define ASM_SESSION_CMD_PAUSE                            0x00010BD3
 832 #define ASM_SESSION_CMD_GET_SESSION_TIME                 0x00010BD4
 833 #define ASM_DATA_CMD_EOS                                 0x00010BDB
 834 #define ASM_DATA_EVENT_EOS                               0x00010BDD
 835
 836 #define ASM_SERVICE_CMD_GET_STREAM_HANDLES               0x00010C0B
 837 #define ASM_STREAM_CMD_FLUSH_READBUFS                    0x00010C09
 838
 839 #define ASM_SESSION_EVENT_RX_UNDERFLOW                   0x00010C17
 840 #define ASM_SESSION_EVENT_TX_OVERFLOW                    0x00010C18
 841 #define ASM_SERVICE_CMD_GET_WALLCLOCK_TIME               0x00010C19
 842 #define ASM_DATA_CMDRSP_EOS                              0x00010C1C
 843
 844 /* ASM Data structures */
 845
 846 /* common declarations */
 847 struct asm_pcm_cfg {
 848         u16 ch_cfg;
 849         u16 bits_per_sample;
 850         u32 sample_rate;
 851         u16 is_signed;
 852         u16 interleaved;
 853 };
 854
 855 #define PCM_CHANNEL_NULL 0
 856
 857 /* Front left channel. */
 858 #define PCM_CHANNEL_FL    1
 859
 860 /* Front right channel. */
 861 #define PCM_CHANNEL_FR    2
 862
 863 /* Front center channel. */
 864 #define PCM_CHANNEL_FC    3
 865
 866 /* Left surround channel.*/
 867 #define PCM_CHANNEL_LS   4
 868
 869 /* Right surround channel.*/
 870 #define PCM_CHANNEL_RS   5
 871
 872 /* Low frequency effect channel. */
 873 #define PCM_CHANNEL_LFE  6
 874
 875 /* Center surround channel; Rear center channel. */
 876 #define PCM_CHANNEL_CS   7
 877
 878 /* Left back channel; Rear left channel. */
 879 #define PCM_CHANNEL_LB   8
 880
 881 /* Right back channel; Rear right channel. */
 882 #define PCM_CHANNEL_RB   9
 883
 884 /* Top surround channel. */
 885 #define PCM_CHANNEL_TS   10
 886
 887 /* Center vertical height channel.*/
 888 #define PCM_CHANNEL_CVH  11
 889
 890 /* Mono surround channel.*/
 891 #define PCM_CHANNEL_MS   12
 892
 893 /* Front left of center. */
 894 #define PCM_CHANNEL_FLC  13
 895
 896 /* Front right of center. */
 897 #define PCM_CHANNEL_FRC  14
 898
 899 /* Rear left of center. */
 900 #define PCM_CHANNEL_RLC  15
 901
 902 /* Rear right of center. */
 903 #define PCM_CHANNEL_RRC  16
 904
 905 #define PCM_FORMAT_MAX_NUM_CHANNEL  8
 906
 907 /* Maximum number of channels supported
 908  * in ASM_ENCDEC_DEC_CHAN_MAP command
 909  */
 910 #define MAX_CHAN_MAP_CHANNELS 16
 911 /*
 912  *  Multiple-channel PCM decoder format block structure used in the
 913  *  #ASM_STREAM_CMD_OPEN_WRITE command.
 914  *  The data must be in little-endian format.
 915  */
 916 struct asm_multi_channel_pcm_fmt_blk {
 917
 918         u16 num_channels;       /*
 919                                  * Number of channels.
 920                                  * Supported values:1 to 8
 921                                  */
 922
 923         u16 bits_per_sample;    /*
 924                                  * Number of bits per sample per channel.
 925                                  * Supported values: 16, 24 When used for
 926                                  * playback, the client must send 24-bit
 927                                  * samples packed in 32-bit words. The
 928                                  * 24-bit samples must be placed in the most
 929                                  * significant 24 bits of the 32-bit word. When
 930                                  * used for recording, the aDSP sends 24-bit
 931                                  * samples packed in 32-bit words. The 24-bit
 932                                  * samples are placed in the most significant
 933                                  * 24 bits of the 32-bit word.
 934                                  */
 935
 936         u32 sample_rate;        /*
 937                                  * Number of samples per second
 938                                  * (in Hertz). Supported values:
 939                                  * 2000 to 48000
 940                                  */
 941
 942         u16 is_signed;          /*
 943                                  * Flag that indicates the samples
 944                                  * are signed (1).
 945                                  */
 946
 947         u16 is_interleaved;     /*
 948                                  * Flag that indicates whether the channels are
 949                                  * de-interleaved (0) or interleaved (1).
 950                                  * Interleaved format means corresponding
 951                                  * samples from the left and right channels are
 952                                  * interleaved within the buffer.
 953                                  * De-interleaved format means samples from
 954                                  * each channel are contiguous in the buffer.
 955                                  * The samples from one channel immediately
 956                                  * follow those of the previous channel.
 957                                  */
 958
 959         u8 channel_mapping[8];  /*
 960                                  * Supported values:
 961                                  * PCM_CHANNEL_NULL, PCM_CHANNEL_FL,
 962                                  * PCM_CHANNEL_FR, PCM_CHANNEL_FC,
 963                                  * PCM_CHANNEL_LS, PCM_CHANNEL_RS,
 964                                  * PCM_CHANNEL_LFE, PCM_CHANNEL_CS,
 965                                  * PCM_CHANNEL_LB, PCM_CHANNEL_RB,
 966                                  * PCM_CHANNEL_TS, PCM_CHANNEL_CVH,
 967                                  * PCM_CHANNEL_MS, PCM_CHANNEL_FLC,
 968                                  * PCM_CHANNEL_FRC, PCM_CHANNEL_RLC,
 969                                  * PCM_CHANNEL_RRC.
 970                                  * Channel[i] mapping describes channel I. Each
 971                                  * element i of the array describes channel I
 972                                  * inside the buffer where  I < num_channels.
 973                                  * An unused channel is set to zero.
 974                                  */
 975 };
 976 struct asm_dts_enc_cfg {
 977         uint32_t        sample_rate;
 978         /*
 979         * Samples at which input is to be encoded.
 980         * Supported values:
 981         * 44100 -- encode at 44.1 Khz
 982         * 48000 -- encode at 48 Khz
 983         */
 984
 985         uint32_t        num_channels;
 986         /*
 987         * Number of channels for multi-channel encoding.
 988         * Supported values: 1 to 6
 989         */
 990
 991         uint8_t         channel_mapping[6];
 992         /*
 993         * Channel array of size 16. Channel[i] mapping describes channel I.
 994         * Each element i of the array describes channel I inside the buffer
 995         * where num_channels. An unused channel is set to zero. Only first
 996         * num_channels elements are valid
 997
 998         * Supported values:
 999         * - # PCM_CHANNEL_L
1000         * - # PCM_CHANNEL_R
1001         * - # PCM_CHANNEL_C
1002         * - # PCM_CHANNEL_LS
1003         * - # PCM_CHANNEL_RS
1004         * - # PCM_CHANNEL_LFE
1005         */
1006
1007 };
1008 struct asm_adpcm_cfg {
1009         u16 ch_cfg;
1010         u16 bits_per_sample;
1011         u32 sample_rate;
1012         u32 block_size;
1013 };
1014
1015 struct asm_yadpcm_cfg {
1016         u16 ch_cfg;
1017         u16 bits_per_sample;
1018         u32 sample_rate;
1019 };
1020
1021 struct asm_midi_cfg {
1022         u32 nMode;
1023 };
1024
1025 struct asm_wma_cfg {
1026         u16 format_tag;
1027         u16 ch_cfg;
1028         u32 sample_rate;
1029         u32 avg_bytes_per_sec;
1030         u16 block_align;
1031         u16 valid_bits_per_sample;
1032         u32 ch_mask;
1033         u16 encode_opt;
1034         u16 adv_encode_opt;
1035         u32 adv_encode_opt2;
1036         u32 drc_peak_ref;
1037         u32 drc_peak_target;
1038         u32 drc_ave_ref;
1039         u32 drc_ave_target;
1040 };
1041
1042 struct asm_wmapro_cfg {
1043         u16 format_tag;
1044         u16 ch_cfg;
1045         u32 sample_rate;
1046         u32 avg_bytes_per_sec;
1047         u16 block_align;
1048         u16 valid_bits_per_sample;
1049         u32 ch_mask;
1050         u16 encode_opt;
1051         u16 adv_encode_opt;
1052         u32 adv_encode_opt2;
1053         u32 drc_peak_ref;
1054         u32 drc_peak_target;
1055         u32 drc_ave_ref;
1056         u32 drc_ave_target;
1057 };
1058
1059 struct asm_aac_cfg {
1060         u16 format;
1061         u16 aot;
1062         u16 ep_config;
1063         u16 section_data_resilience;
1064         u16 scalefactor_data_resilience;
1065         u16 spectral_data_resilience;
1066         u16 ch_cfg;
1067         u16 reserved;
1068         u32 sample_rate;
1069 };
1070
1071 struct asm_amrwbplus_cfg {
1072         u32  size_bytes;
1073         u32  version;
1074         u32  num_channels;
1075         u32  amr_band_mode;
1076         u32  amr_dtx_mode;
1077         u32  amr_frame_fmt;
1078         u32  amr_lsf_idx;
1079 };
1080
1081 struct asm_flac_cfg {
1082         u16 stream_info_present;
1083         u16 min_blk_size;
1084         u16 max_blk_size;
1085         u16 ch_cfg;
1086         u16 sample_size;
1087         u16 sample_rate;
1088         u16 md5_sum;
1089         u32 ext_sample_rate;
1090         u32 min_frame_size;
1091         u32 max_frame_size;
1092 };
1093
1094 struct asm_vorbis_cfg {
1095         u32 ch_cfg;
1096         u32 bit_rate;
1097         u32 min_bit_rate;
1098         u32 max_bit_rate;
1099         u16 bit_depth_pcm_sample;
1100         u16 bit_stream_format;
1101 };
1102
1103 struct asm_aac_read_cfg {
1104         u32 bitrate;
1105         u32 enc_mode;
1106         u16 format;
1107         u16 ch_cfg;
1108         u32 sample_rate;
1109 };
1110
1111 struct asm_amrnb_read_cfg {
1112         u16 mode;
1113         u16 dtx_mode;
1114 };
1115
1116 struct asm_amrwb_read_cfg {
1117         u16 mode;
1118         u16 dtx_mode;
1119 };
1120
1121 struct asm_evrc_read_cfg {
1122         u16 max_rate;
1123         u16 min_rate;
1124         u16 rate_modulation_cmd;
1125         u16 reserved;
1126 };
1127
1128 struct asm_qcelp13_read_cfg {
1129         u16 max_rate;
1130         u16 min_rate;
1131         u16 reduced_rate_level;
1132         u16 rate_modulation_cmd;
1133 };
1134
1135 struct asm_sbc_read_cfg {
1136         u32 subband;
1137         u32 block_len;
1138         u32 ch_mode;
1139         u32 alloc_method;
1140         u32 bit_rate;
1141         u32 sample_rate;
1142 };
1143
1144 struct asm_sbc_bitrate {
1145         u32 bitrate;
1146 };
1147
1148 struct asm_immed_decode {
1149         u32 mode;
1150 };
1151
1152 struct asm_sbr_ps {
1153         u32 enable;
1154 };
1155
1156 struct asm_dual_mono {
1157         u16 sce_left;
1158         u16 sce_right;
1159 };
1160
1161 struct asm_dec_chan_map {
1162         u32 num_channels;                         /* Number of decoder output
1163                                                    * channels. A value of 0
1164                                                    * indicates native channel
1165                                                    * mapping, which is valid
1166                                                    * only for NT mode. This
1167                                                    * means the output of the
1168                                                    * decoder is to be preserved
1169                                                    * as is.
1170                                                    */
1171
1172         u8 channel_mapping[MAX_CHAN_MAP_CHANNELS];/* Channel array of size
1173                                                    * num_channels. It can grow
1174                                                    * till MAX_CHAN_MAP_CHANNELS.
1175                                                    * Channel[i] mapping
1176                                                    * describes channel I inside
1177                                                    * the decoder output buffer.
1178                                                    * Valid channel mapping
1179                                                    * values are to be present at
1180                                                    * the beginning of the array.
1181                                                    * All remaining elements of
1182                                                    * the array are to be filled
1183                                                    * with PCM_CHANNEL_NULL.
1184                                                    */
1185 };
1186
1187 struct asm_encode_cfg_blk {
1188         u32 frames_per_buf;
1189         u32 format_id;
1190         u32 cfg_size;
1191         union {
1192                 struct asm_pcm_cfg          pcm;
1193                 struct asm_aac_read_cfg     aac;
1194                 struct asm_amrnb_read_cfg   amrnb;
1195                 struct asm_evrc_read_cfg    evrc;
1196                 struct asm_qcelp13_read_cfg qcelp13;
1197                 struct asm_sbc_read_cfg     sbc;
1198                 struct asm_amrwb_read_cfg   amrwb;
1199                 struct asm_multi_channel_pcm_fmt_blk      mpcm;
1200                 struct asm_dts_enc_cfg      dts;
1201         } __attribute__((packed)) cfg;
1202 };
1203
1204 struct asm_frame_meta_info {
1205         u32 offset_to_frame;
1206         u32 frame_size;
1207         u32 encoded_pcm_samples;
1208         u32 msw_ts;
1209         u32 lsw_ts;
1210         u32 nflags;
1211 };
1212
1213 /* Stream level commands */
1214 #define ASM_STREAM_CMD_OPEN_READ                         0x00010BCB
1215 #define ASM_STREAM_CMD_OPEN_READ_V2_1                    0x00010DB2
1216 struct asm_stream_cmd_open_read {
1217         struct apr_hdr hdr;
1218         u32            uMode;
1219         u32            src_endpoint;
1220         u32            pre_proc_top;
1221         u32            format;
1222 } __attribute__((packed));
1223
1224 struct asm_stream_cmd_open_read_v2_1 {
1225         struct apr_hdr hdr;
1226         u32            uMode;
1227         u32            src_endpoint;
1228         u32            pre_proc_top;
1229         u32            format;
1230         u16            bits_per_sample;
1231         u16            reserved;
1232 } __packed;
1233
1234 /* Supported formats */
1235 #define LINEAR_PCM   0x00010BE5
1236 #define DTMF         0x00010BE6
1237 #define ADPCM        0x00010BE7
1238 #define YADPCM       0x00010BE8
1239 #define MP3          0x00010BE9
1240 #define MPEG4_AAC    0x00010BEA
1241 #define AMRNB_FS     0x00010BEB
1242 #define AMRWB_FS     0x00010BEC
1243 #define V13K_FS      0x00010BED
1244 #define EVRC_FS      0x00010BEE
1245 #define EVRCB_FS     0x00010BEF
1246 #define EVRCWB_FS    0x00010BF0
1247 #define MIDI         0x00010BF1
1248 #define SBC          0x00010BF2
1249 #define WMA_V10PRO   0x00010BF3
1250 #define WMA_V9       0x00010BF4
1251 #define AMR_WB_PLUS  0x00010BF5
1252 #define AC3_DECODER  0x00010BF6
1253 #define EAC3_DECODER 0x00010C3C
1254 #define DTS     0x00010D88
1255 #define DTS_LBR 0x00010DBB
1256 #define MP2          0x00010DBE
1257 #define ATRAC   0x00010D89
1258 #define MAT     0x00010D8A
1259 #define G711_ALAW_FS 0x00010BF7
1260 #define G711_MLAW_FS 0x00010BF8
1261 #define G711_PCM_FS  0x00010BF9
1262 #define MPEG4_MULTI_AAC 0x00010D86
1263 #define US_POINT_EPOS_FORMAT 0x00012310
1264 #define US_RAW_FORMAT        0x0001127C
1265 #define US_PROX_FORMAT       0x0001272B
1266 #define MULTI_CHANNEL_PCM    0x00010C66
1267
1268 #define ASM_ENCDEC_SBCRATE         0x00010C13
1269 #define ASM_ENCDEC_IMMDIATE_DECODE 0x00010C14
1270 #define ASM_ENCDEC_CFG_BLK         0x00010C2C
1271
1272 #define ASM_ENCDEC_SBCRATE         0x00010C13
1273 #define ASM_ENCDEC_IMMDIATE_DECODE 0x00010C14
1274 #define ASM_ENCDEC_CFG_BLK         0x00010C2C
1275
1276 #define ASM_STREAM_CMD_OPEN_READ_COMPRESSED               0x00010D95
1277 struct asm_stream_cmd_open_read_compressed {
1278         struct apr_hdr hdr;
1279         u32            uMode;
1280         u32            frame_per_buf;
1281 } __packed;
1282
1283 #define ASM_STREAM_CMD_OPEN_WRITE                        0x00010BCA
1284 #define ASM_STREAM_CMD_OPEN_WRITE_V2_1                   0x00010DB1
1285 struct asm_stream_cmd_open_write {
1286         struct apr_hdr hdr;
1287         u32            uMode;
1288         u16            sink_endpoint;
1289         u16            stream_handle;
1290         u32            post_proc_top;
1291         u32            format;
1292 } __attribute__((packed));
1293
1294 #define IEC_61937_MASK  0x00000001
1295 #define IEC_60958_MASK  0x00000002
1296
1297 #define ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED    0x00010D84
1298 struct asm_stream_cmd_open_write_compressed {
1299         struct apr_hdr hdr;
1300         u32     flags;
1301         u32     format;
1302 } __packed;
1303 #define ASM_STREAM_CMD_OPEN_TRANSCODE_LOOPBACK     0x00010DBA
1304 struct asm_stream_cmd_open_transcode_loopback {
1305         struct apr_hdr hdr;
1306         uint32_t        mode_flags;
1307         /*
1308         * All bits are reserved. Clients must set them to zero.
1309         */
1310
1311         uint32_t        src_format_id;
1312         /*
1313         * Specifies the media format of the input audio stream.
1314
1315         * Supported values:
1316         * - #ASM_MEDIA_FMT_LINEAR_PCM
1317         * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM
1318         */
1319
1320         uint32_t        sink_format_id;
1321         /*
1322         * Specifies the media format of the output stream.
1323
1324         * Supported values:
1325         * - #ASM_MEDIA_FMT_LINEAR_PCM
1326         * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM
1327         * - #ASM_MEDIA_FMT_DTS
1328         */
1329
1330         uint32_t        audproc_topo_id;
1331         /*
1332         * Postprocessing topology ID, which specifies the topology (order of
1333         * processing) of postprocessing algorithms.
1334
1335         * Supported values:
1336         * - #ASM_STREAM_POSTPROC_TOPO_ID_DEFAULT
1337         * - #ASM_STREAM_POSTPROC_TOPO_ID_PEAKMETER
1338         * - #ASM_STREAM_POSTPROC_TOPO_ID_NONE
1339         * - #ASM_STREAM_POSTPROC_TOPO_ID_MCH_PEAK_VOL
1340         */
1341
1342         uint16_t        src_endpoint_type;
1343         /*
1344         * Specifies the source endpoint that provides the input samples.
1345
1346         * Supported values:
1347         * - 0 -- Tx device matrix or stream router
1348         * (gateway to the hardware ports)
1349         * - All other values are reserved
1350
1351         * Clients must set this field to zero. Otherwise, an error is returned.
1352         */
1353
1354         uint16_t        sink_endpoint_type;
1355         /*
1356         * Specifies the sink endpoint type.
1357
1358         * Supported values:
1359         * - 0 -- Rx device matrix or stream router
1360         * (gateway to the hardware ports)
1361         * - All other values are reserved
1362
1363         * Clients must set this field to zero. Otherwise, an error is returned.
1364         */
1365
1366         uint16_t        bits_per_sample;
1367         /*
1368         * Number of bits per sample processed by the ASM modules.
1369         * Supported values: 16, 24
1370         */
1371
1372         uint16_t        reserved;
1373         /*
1374         * This field must be set to zero.
1375         */
1376 } __packed;
1377
1378 /*
1379 * ID of the DTS mix LFE channel to front channels parameter in the
1380 * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
1381 * asm_dts_generic_param_t
1382 * ASM_PARAM_ID_DTS_MIX_LFE_TO_FRONT
1383 */
1384 #define ASM_PARAM_ID_DTS_MIX_LFE_TO_FRONT                          0x00010DB6
1385
1386 /*
1387 * ID of the DTS DRC ratio parameter in the
1388 * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
1389 * asm_dts_generic_param_t
1390 * ASM_PARAM_ID_DTS_DRC_RATIO
1391 */
1392 #define ASM_PARAM_ID_DTS_DRC_RATIO                                   0x00010DB7
1393
1394 /*
1395 * ID of the DTS enable dialog normalization parameter in the
1396 * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
1397
1398 * asm_dts_generic_param_t
1399 * ASM_PARAM_ID_DTS_ENABLE_DIALNORM
1400 */
1401 #define ASM_PARAM_ID_DTS_ENABLE_DIALNORM                             0x00010DB8
1402
1403 /*
1404 * ID of the DTS enable parse REV2AUX parameter in the
1405 * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command.
1406 * asm_dts_generic_param_t
1407 * ASM_PARAM_ID_DTS_ENABLE_PARSE_REV2AUX
1408 */
1409 #define ASM_PARAM_ID_DTS_ENABLE_PARSE_REV2AUX                         0x00010DB9
1410
1411 struct asm_dts_generic_param {
1412         int32_t         generic_parameter;
1413         /*
1414         * #ASM_PARAM_ID_DTS_MIX_LFE_TO_FRONT:
1415         * - if enabled, mixes LFE channel to front
1416         * while downmixing (if necessary)
1417         * - Supported values: 1-> enable, 0-> disable
1418         * - Default: disabled
1419
1420         * #ASM_PARAM_ID_DTS_DRC_RATIO:
1421         * - percentage of DRC ratio.
1422         * - Supported values: 0-100
1423         * - Default: 0, DRC is disabled.
1424
1425         * #ASM_PARAM_ID_DTS_ENABLE_DIALNORM:
1426         * - flag to enable dialog normalization post processing.
1427         * - Supported values: 1-> enable, 0-> disable.
1428         * - Default: enabled.
1429
1430         * #ASM_PARAM_ID_DTS_ENABLE_PARSE_REV2AUX:
1431         * - flag to enable parsing of rev2aux chunk in the bitstream.
1432         * This chunk contains broadcast metadata.
1433         * - Supported values: 1-> enable, 0-> disable.
1434         * - Default: disabled.
1435         */
1436 };
1437
1438 struct asm_stream_cmd_dts_dec_param {
1439         struct apr_hdr hdr;
1440         u32            param_id;
1441         u32            param_size;
1442         struct asm_dts_generic_param generic_param;
1443 } __packed;
1444
1445
1446 #define ASM_STREAM_CMD_OPEN_READWRITE                    0x00010BCC
1447
1448 struct asm_stream_cmd_open_read_write {
1449         struct apr_hdr     hdr;
1450         u32                uMode;
1451         u32                post_proc_top;
1452         u32                write_format;
1453         u32                read_format;
1454 } __attribute__((packed));
1455
1456 #define ASM_STREAM_CMD_OPEN_LOOPBACK    0x00010D6E
1457 struct asm_stream_cmd_open_loopback {
1458         struct apr_hdr         hdr;
1459         u32                    mode_flags;
1460 /* Mode flags.
1461  * Bit 0-31: reserved; client should set these bits to 0
1462  */
1463         u16                    src_endpointype;
1464         /* Endpoint type. 0 = Tx Matrix */
1465         u16                    sink_endpointype;
1466         /* Endpoint type. 0 = Rx Matrix */
1467         u32                    postprocopo_id;
1468 /* Postprocessor topology ID. Specifies the topology of
1469  * postprocessing algorithms.
1470  */
1471 } __packed;
1472
1473 #define ADM_CMD_CONNECT_AFE_PORT 0x00010320
1474 #define ADM_CMD_DISCONNECT_AFE_PORT 0x00010321
1475
1476 struct adm_cmd_connect_afe_port {
1477         struct apr_hdr     hdr;
1478         u8      mode; /*mode represent the interface is for RX or TX*/
1479         u8      session_id; /*ASM session ID*/
1480         u16     afe_port_id;
1481 } __packed;
1482
1483 #define ADM_CMD_CONNECT_AFE_PORT_V2 0x00010332
1484
1485 struct adm_cmd_connect_afe_port_v2 {
1486         struct apr_hdr     hdr;
1487         u8      mode; /*mode represent the interface is for RX or TX*/
1488         u8      session_id; /*ASM session ID*/
1489         u16     afe_port_id;
1490         u32     num_channels;
1491         u32     sampling_rate;
1492 } __packed;
1493
1494 #define ASM_STREAM_CMD_SET_ENCDEC_PARAM                  0x00010C10
1495 #define ASM_STREAM_CMD_GET_ENCDEC_PARAM                  0x00010C11
1496 #define ASM_ENCDEC_CFG_BLK_ID                            0x00010C2C
1497 #define ASM_ENABLE_SBR_PS                                0x00010C63
1498 #define ASM_CONFIGURE_DUAL_MONO                  0x00010C64
1499 struct asm_stream_cmd_encdec_cfg_blk{
1500         struct apr_hdr              hdr;
1501         u32                         param_id;
1502         u32                         param_size;
1503         struct asm_encode_cfg_blk   enc_blk;
1504 } __attribute__((packed));
1505
1506 struct asm_stream_cmd_encdec_sbc_bitrate{
1507         struct apr_hdr hdr;
1508         u32            param_id;
1509                 struct asm_sbc_bitrate      sbc_bitrate;
1510 } __attribute__((packed));
1511
1512 struct asm_stream_cmd_encdec_immed_decode{
1513         struct apr_hdr hdr;
1514         u32            param_id;
1515         u32            param_size;
1516         struct asm_immed_decode dec;
1517 } __attribute__((packed));
1518
1519 struct asm_stream_cmd_encdec_sbr{
1520         struct apr_hdr hdr;
1521         u32            param_id;
1522         u32            param_size;
1523         struct asm_sbr_ps sbr_ps;
1524 } __attribute__((packed));
1525
1526 struct asm_stream_cmd_encdec_dualmono {
1527         struct apr_hdr hdr;
1528         u32            param_id;
1529         u32            param_size;
1530         struct asm_dual_mono channel_map;
1531 } __packed;
1532
1533 #define ASM_PARAM_ID_AAC_STEREO_MIX_COEFF_SELECTION_FLAG        0x00010DD8
1534
1535 /* Structure for AAC decoder stereo coefficient setting. */
1536
1537 struct asm_aac_stereo_mix_coeff_selection_param {
1538         struct apr_hdr                          hdr;
1539         u32                                     param_id;
1540         u32                                     param_size;
1541         u32                                     aac_stereo_mix_coeff_flag;
1542 } __packed;
1543
1544 #define ASM_ENCDEC_DEC_CHAN_MAP                          0x00010D82
1545 struct asm_stream_cmd_encdec_channelmap {
1546         struct apr_hdr hdr;
1547         u32            param_id;
1548         u32            param_size;
1549         struct asm_dec_chan_map chan_map;
1550 } __packed;
1551
1552 #define ASM_STREAM _CMD_ADJUST_SAMPLES                   0x00010C0A
1553 struct asm_stream_cmd_adjust_samples{
1554         struct apr_hdr hdr;
1555         u16            nsamples;
1556         u16            reserved;
1557 } __attribute__((packed));
1558
1559 #define ASM_STREAM_CMD_TAP_POPP_PCM                      0x00010BF9
1560 struct asm_stream_cmd_tap_popp_pcm{
1561         struct apr_hdr hdr;
1562         u16            enable;
1563         u16            reserved;
1564         u32            module_id;
1565 } __attribute__((packed));
1566
1567 /*  Session Level commands */
1568 #define ASM_SESSION_CMD_MEMORY_MAP                      0x00010C32
1569 struct asm_stream_cmd_memory_map{
1570         struct apr_hdr  hdr;
1571         u32             buf_add;
1572         u32             buf_size;
1573         u16             mempool_id;
1574         u16             reserved;
1575 } __attribute__((packed));
1576
1577 #define ASM_SESSION_CMD_MEMORY_UNMAP                    0x00010C33
1578 struct asm_stream_cmd_memory_unmap{
1579         struct apr_hdr  hdr;
1580         u32             buf_add;
1581 } __attribute__((packed));
1582
1583 #define ASM_SESSION_CMD_MEMORY_MAP_REGIONS              0x00010C45
1584 struct asm_memory_map_regions{
1585         u32             phys;
1586         u32             buf_size;
1587 } __attribute__((packed));
1588
1589 struct asm_stream_cmd_memory_map_regions{
1590         struct apr_hdr  hdr;
1591         u16             mempool_id;
1592         u16             nregions;
1593 } __attribute__((packed));
1594
1595 #define ASM_SESSION_CMD_MEMORY_UNMAP_REGIONS            0x00010C46
1596 struct asm_memory_unmap_regions{
1597         u32             phys;
1598 } __attribute__((packed));
1599
1600 struct asm_stream_cmd_memory_unmap_regions{
1601         struct apr_hdr  hdr;
1602         u16             nregions;
1603         u16             reserved;
1604 } __attribute__((packed));
1605
1606 #define ASM_SESSION_CMD_RUN                              0x00010BD2
1607 struct asm_stream_cmd_run{
1608         struct apr_hdr hdr;
1609         u32            flags;
1610         u32            msw_ts;
1611         u32            lsw_ts;
1612 } __attribute__((packed));
1613
1614 /* Session level events */
1615 #define ASM_SESSION_CMD_REGISTER_FOR_RX_UNDERFLOW_EVENTS 0x00010BD5
1616 struct asm_stream_cmd_reg_rx_underflow_event{
1617         struct apr_hdr hdr;
1618         u16            enable;
1619         u16            reserved;
1620 } __attribute__((packed));
1621
1622 #define ASM_SESSION_CMD_REGISTER_FOR_TX_OVERFLOW_EVENTS  0x00010BD6
1623 struct asm_stream_cmd_reg_tx_overflow_event{
1624         struct apr_hdr hdr;
1625         u16            enable;
1626         u16            reserved;
1627 } __attribute__((packed));
1628
1629 /* Data Path commands */
1630 #define ASM_DATA_CMD_WRITE                               0x00010BD9
1631 struct asm_stream_cmd_write{
1632         struct apr_hdr     hdr;
1633         u32     buf_add;
1634         u32     avail_bytes;
1635         u32     uid;
1636         u32     msw_ts;
1637         u32     lsw_ts;
1638         u32     uflags;
1639 } __attribute__((packed));
1640
1641 #define ASM_DATA_CMD_READ                                0x00010BDA
1642 struct asm_stream_cmd_read{
1643         struct apr_hdr     hdr;
1644         u32     buf_add;
1645         u32     buf_size;
1646         u32     uid;
1647 } __attribute__((packed));
1648
1649 #define ASM_DATA_CMD_READ_COMPRESSED                     0x00010DBF
1650 struct asm_stream_cmd_read_compressed {
1651         struct apr_hdr     hdr;
1652         u32     buf_add;
1653         u32     buf_size;
1654         u32     uid;
1655 } __packed;
1656
1657 #define ASM_DATA_CMD_MEDIA_FORMAT_UPDATE                 0x00010BDC
1658 #define ASM_DATA_EVENT_ENC_SR_CM_NOTIFY                  0x00010BDE
1659 struct asm_stream_media_format_update{
1660         struct apr_hdr hdr;
1661         u32            format;
1662         u32            cfg_size;
1663         union {
1664                 struct asm_pcm_cfg         pcm_cfg;
1665                 struct asm_adpcm_cfg       adpcm_cfg;
1666                 struct asm_yadpcm_cfg      yadpcm_cfg;
1667                 struct asm_midi_cfg        midi_cfg;
1668                 struct asm_wma_cfg         wma_cfg;
1669                 struct asm_wmapro_cfg      wmapro_cfg;
1670                 struct asm_aac_cfg         aac_cfg;
1671                 struct asm_flac_cfg        flac_cfg;
1672                 struct asm_vorbis_cfg      vorbis_cfg;
1673                 struct asm_multi_channel_pcm_fmt_blk multi_ch_pcm_cfg;
1674                 struct asm_amrwbplus_cfg   amrwbplus_cfg;
1675         } __attribute__((packed)) write_cfg;
1676 } __attribute__((packed));
1677
1678
1679 /* Command Responses */
1680 #define ASM_STREAM_CMDRSP_GET_ENCDEC_PARAM               0x00010C12
1681 struct asm_stream_cmdrsp_get_readwrite_param{
1682         struct apr_hdr hdr;
1683         u32            status;
1684         u32            param_id;
1685         u16            param_size;
1686         u16            padding;
1687         union {
1688                 struct asm_sbc_bitrate      sbc_bitrate;
1689                 struct asm_immed_decode aac_dec;
1690         } __attribute__((packed)) read_write_cfg;
1691 } __attribute__((packed));
1692
1693
1694 #define ASM_SESSION_CMDRSP_GET_SESSION_TIME              0x00010BD8
1695 struct asm_stream_cmdrsp_get_session_time{
1696         struct apr_hdr hdr;
1697         u32            status;
1698         u32            msw_ts;
1699         u32            lsw_ts;
1700 } __attribute__((packed));
1701
1702 #define ASM_DATA_EVENT_WRITE_DONE                        0x00010BDF
1703 struct asm_data_event_write_done{
1704         u32     buf_add;
1705         u32            status;
1706 } __attribute__((packed));
1707
1708 #define ASM_DATA_EVENT_READ_DONE                         0x00010BE0
1709 struct asm_data_event_read_done{
1710         u32            status;
1711         u32            buffer_add;
1712         u32            enc_frame_size;
1713         u32            offset;
1714         u32            msw_ts;
1715         u32            lsw_ts;
1716         u32            flags;
1717         u32            num_frames;
1718         u32            id;
1719 } __attribute__((packed));
1720
1721 #define ASM_DATA_EVENT_READ_COMPRESSED_DONE              0x00010DC0
1722 struct asm_data_event_read_compressed_done {
1723         u32            status;
1724         u32            buffer_add;
1725         u32            enc_frame_size;
1726         u32            offset;
1727         u32            msw_ts;
1728         u32            lsw_ts;
1729         u32            flags;
1730         u32            num_frames;
1731         u32            id;
1732 } __packed;
1733
1734 #define ASM_DATA_EVENT_SR_CM_CHANGE_NOTIFY               0x00010C65
1735 struct asm_data_event_sr_cm_change_notify {
1736         u32            sample_rate;
1737         u16                no_of_channels;
1738         u16            reserved;
1739         u8             channel_map[8];
1740 } __packed;
1741
1742 /* service level events */
1743
1744 #define ASM_SERVICE_CMDRSP_GET_STREAM_HANDLES            0x00010C1B
1745 struct asm_svc_cmdrsp_get_strm_handles{
1746         struct apr_hdr hdr;
1747         u32            num_handles;
1748         u32            stream_handles;
1749 } __attribute__((packed));
1750
1751
1752 #define ASM_SERVICE_CMDRSP_GET_WALLCLOCK_TIME            0x00010C1A
1753 struct asm_svc_cmdrsp_get_wallclock_time{
1754         struct apr_hdr hdr;
1755         u32            status;
1756         u32            msw_ts;
1757         u32            lsw_ts;
1758 } __attribute__((packed));
1759
1760 /*
1761  * Error code
1762 */
1763 #define ADSP_EOK          0x00000000 /* Success / completed / no errors. */
1764 #define ADSP_EFAILED      0x00000001 /* General failure. */
1765 #define ADSP_EBADPARAM    0x00000002 /* Bad operation parameter(s). */
1766 #define ADSP_EUNSUPPORTED 0x00000003 /* Unsupported routine/operation. */
1767 #define ADSP_EVERSION     0x00000004 /* Unsupported version. */
1768 #define ADSP_EUNEXPECTED  0x00000005 /* Unexpected problem encountered. */
1769 #define ADSP_EPANIC       0x00000006 /* Unhandled problem occurred. */
1770 #define ADSP_ENORESOURCE  0x00000007 /* Unable to allocate resource(s). */
1771 #define ADSP_EHANDLE      0x00000008 /* Invalid handle. */
1772 #define ADSP_EALREADY     0x00000009 /* Operation is already processed. */
1773 #define ADSP_ENOTREADY    0x0000000A /* Operation not ready to be processed*/
1774 #define ADSP_EPENDING     0x0000000B /* Operation is pending completion*/
1775 #define ADSP_EBUSY        0x0000000C /* Operation could not be accepted or
1776                                          processed. */
1777 #define ADSP_EABORTED     0x0000000D /* Operation aborted due to an error. */
1778 #define ADSP_EPREEMPTED   0x0000000E /* Operation preempted by higher priority*/
1779 #define ADSP_ECONTINUE    0x0000000F /* Operation requests intervention
1780                                         to complete. */
1781 #define ADSP_EIMMEDIATE   0x00000010 /* Operation requests immediate
1782                                         intervention to complete. */
1783 #define ADSP_ENOTIMPL     0x00000011 /* Operation is not implemented. */
1784 #define ADSP_ENEEDMORE    0x00000012 /* Operation needs more data or resources*/
1785
1786 /* SRS TRUMEDIA GUIDS */
1787 #define SRS_TRUMEDIA_TOPOLOGY_ID    0x00010D90
1788 #define SRS_TRUMEDIA_MODULE_ID      0x10005010
1789 #define SRS_TRUMEDIA_PARAMS         0x10005011
1790 #define SRS_TRUMEDIA_PARAMS_WOWHD   0x10005012
1791 #define SRS_TRUMEDIA_PARAMS_CSHP    0x10005013
1792 #define SRS_TRUMEDIA_PARAMS_HPF     0x10005014
1793 #define SRS_TRUMEDIA_PARAMS_PEQ     0x10005015
1794 #define SRS_TRUMEDIA_PARAMS_HL      0x10005016
1795
1796 /* SRS STUDIO SOUND 3D GUIDS */
1797 #define SRS_SS3D_TOPOLOGY_ID        0x00010720
1798 #define SRS_SS3D_MODULE_ID          0x10005020
1799 #define SRS_SS3D_PARAMS             0x10005021
1800 #define SRS_SS3D_PARAMS_CTRL        0x10005022
1801 #define SRS_SS3D_PARAMS_FILTER      0x10005023
1802
1803 /* SRS ALSA CMD MASKS */
1804 #define SRS_CMD_UPLOAD              0x7FFF0000
1805 #define SRS_PARAM_INDEX_MASK        0x80000000
1806 #define SRS_PARAM_OFFSET_MASK       0x3FFF0000
1807 #define SRS_PARAM_VALUE_MASK        0x0000FFFF
1808
1809 /* SRS TRUMEDIA start */
1810 #define SRS_ID_GLOBAL               0x00000001
1811 #define SRS_ID_WOWHD                0x00000002
1812 #define SRS_ID_CSHP                 0x00000003
1813 #define SRS_ID_HPF                  0x00000004
1814 #define SRS_ID_PEQ                  0x00000005
1815 #define SRS_ID_HL                   0x00000006
1816
1817 struct srs_trumedia_params_GLOBAL {
1818         uint8_t                  v1;
1819         uint8_t                  v2;
1820         uint8_t                  v3;
1821         uint8_t                  v4;
1822         uint8_t                  v5;
1823         uint8_t                  v6;
1824         uint8_t                  v7;
1825         uint8_t                  v8;
1826 } __packed;
1827
1828 struct srs_trumedia_params_WOWHD {
1829         uint32_t                                v1;
1830         uint16_t                                v2;
1831         uint16_t                                v3;
1832         uint16_t                                v4;
1833         uint16_t                                v5;
1834         uint16_t                                v6;
1835         uint16_t                                v7;
1836         uint16_t                                v8;
1837         uint16_t                                v____A1;
1838         uint32_t                                v9;
1839         uint16_t                                v10;
1840         uint16_t                                v11;
1841         uint32_t                                v12[16];
1842 } __packed;
1843
1844 struct srs_trumedia_params_CSHP {
1845         uint32_t                                v1;
1846         uint16_t                                v2;
1847         uint16_t                                v3;
1848         uint16_t                                v4;
1849         uint16_t                                v5;
1850         uint16_t                                v6;
1851         uint16_t                                v____A1;
1852         uint32_t                                v7;
1853         uint16_t                                v8;
1854         uint16_t                                v9;
1855         uint32_t                                v10[16];
1856 } __packed;
1857
1858 struct srs_trumedia_params_HPF {
1859         uint32_t                                v1;
1860         uint32_t                                v2[26];
1861 } __packed;
1862
1863 struct srs_trumedia_params_PEQ {
1864         uint32_t                                v1;
1865         uint16_t                                v2;
1866         uint16_t                                v3;
1867         uint16_t                                v4;
1868         uint16_t                                v____A1;
1869         uint32_t                                v5[26];
1870         uint32_t                                v6[26];
1871 } __packed;
1872
1873 struct srs_trumedia_params_HL {
1874         uint16_t                                v1;
1875         uint16_t                                v2;
1876         uint16_t                                v3;
1877         uint16_t                                v____A1;
1878         int32_t                                 v4;
1879         uint32_t                                v5;
1880         uint16_t                                v6;
1881         uint16_t                                v____A2;
1882         uint32_t                                v7;
1883 } __packed;
1884
1885 struct srs_trumedia_params {
1886         struct srs_trumedia_params_GLOBAL       global;
1887         struct srs_trumedia_params_WOWHD        wowhd;
1888         struct srs_trumedia_params_CSHP         cshp;
1889         struct srs_trumedia_params_HPF          hpf;
1890         struct srs_trumedia_params_PEQ          peq;
1891         struct srs_trumedia_params_HL           hl;
1892 } __packed;
1893
1894 int srs_trumedia_open(int port_id, int srs_tech_id, void *srs_params);
1895 /* SRS TruMedia end */
1896
1897 /* SRS Studio Sound 3D start */
1898 #define SRS_ID_SS3D_GLOBAL      0x00000001
1899 #define SRS_ID_SS3D_CTRL        0x00000002
1900 #define SRS_ID_SS3D_FILTER      0x00000003
1901
1902 struct srs_SS3D_params_GLOBAL {
1903         uint8_t                  v1;
1904         uint8_t                  v2;
1905         uint8_t                  v3;
1906         uint8_t                  v4;
1907         uint8_t                  v5;
1908         uint8_t                  v6;
1909         uint8_t                  v7;
1910         uint8_t                  v8;
1911 } __packed;
1912
1913 struct srs_SS3D_ctrl_params {
1914         uint8_t                         v[236];
1915 } __packed;
1916
1917 struct srs_SS3D_filter_params {
1918         uint8_t                         v[28 + 2752];
1919 } __packed;
1920
1921 struct srs_SS3D_params {
1922         struct srs_SS3D_params_GLOBAL   global;
1923         struct srs_SS3D_ctrl_params     ss3d;
1924         struct srs_SS3D_filter_params   ss3d_f;
1925 } __packed;
1926
1927 int srs_ss3d_open(int port_id, int srs_tech_id, void *srs_params);
1928 /* SRS Studio Sound 3D end */
1929 #endif /*_APR_AUDIO_H_*/