1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
37 #if defined(__cplusplus)
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
54 #define DRM_AMDGPU_VM 0x13
55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56 #define DRM_AMDGPU_SCHED 0x15
58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
79 * Memory in this pool could be swapped out to disk if there is pressure.
81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
83 * pages of system memory, allows GPU access system memory in a linezrized
86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
87 * carved out by the BIOS.
89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
90 * across shader threads.
92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
93 * execution of all the waves on a device.
95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
98 #define AMDGPU_GEM_DOMAIN_CPU 0x1
99 #define AMDGPU_GEM_DOMAIN_GTT 0x2
100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
101 #define AMDGPU_GEM_DOMAIN_GDS 0x8
102 #define AMDGPU_GEM_DOMAIN_GWS 0x10
103 #define AMDGPU_GEM_DOMAIN_OA 0x20
104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)
111 /* Flag that CPU access will be required for the case of VRAM domain */
112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
113 /* Flag that CPU access will not work, this VRAM domain is invisible */
114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
115 /* Flag that USWC attributes should be used for GTT */
116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
117 /* Flag that the memory should be in VRAM and cleared */
118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
119 /* Flag that create shadow bo(GTT) while allocating vram bo */
120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
121 /* Flag that allocating the BO should use linear VRAM */
122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
123 /* Flag that BO is always valid in this VM */
124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
125 /* Flag that BO sharing will be explicitly synchronized */
126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
128 * for the second page onward should be set to NC.
130 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
132 struct drm_amdgpu_gem_create_in {
133 /** the requested memory size */
135 /** physical start_addr alignment in bytes for some HW requirements */
137 /** the requested memory domains */
139 /** allocation flags */
143 struct drm_amdgpu_gem_create_out {
144 /** returned GEM object handle */
149 union drm_amdgpu_gem_create {
150 struct drm_amdgpu_gem_create_in in;
151 struct drm_amdgpu_gem_create_out out;
154 /** Opcode to create new residency list. */
155 #define AMDGPU_BO_LIST_OP_CREATE 0
156 /** Opcode to destroy previously created residency list */
157 #define AMDGPU_BO_LIST_OP_DESTROY 1
158 /** Opcode to update resource information in the list */
159 #define AMDGPU_BO_LIST_OP_UPDATE 2
161 struct drm_amdgpu_bo_list_in {
162 /** Type of operation */
164 /** Handle of list or 0 if we want to create one */
166 /** Number of BOs in list */
168 /** Size of each element describing BO */
170 /** Pointer to array describing BOs */
174 struct drm_amdgpu_bo_list_entry {
177 /** New (if specified) BO priority to be used during migration */
181 struct drm_amdgpu_bo_list_out {
182 /** Handle of resource list */
187 union drm_amdgpu_bo_list {
188 struct drm_amdgpu_bo_list_in in;
189 struct drm_amdgpu_bo_list_out out;
192 /* context related */
193 #define AMDGPU_CTX_OP_ALLOC_CTX 1
194 #define AMDGPU_CTX_OP_FREE_CTX 2
195 #define AMDGPU_CTX_OP_QUERY_STATE 3
196 #define AMDGPU_CTX_OP_QUERY_STATE2 4
198 /* GPU reset status */
199 #define AMDGPU_CTX_NO_RESET 0
200 /* this the context caused it */
201 #define AMDGPU_CTX_GUILTY_RESET 1
202 /* some other context caused it */
203 #define AMDGPU_CTX_INNOCENT_RESET 2
205 #define AMDGPU_CTX_UNKNOWN_RESET 3
207 /* indicate gpu reset occured after ctx created */
208 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
209 /* indicate vram lost occured after ctx created */
210 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
211 /* indicate some job from this context once cause gpu hang */
212 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
213 /* indicate some errors are detected by RAS */
214 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
215 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
217 /* Context priority level */
218 #define AMDGPU_CTX_PRIORITY_UNSET -2048
219 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
220 #define AMDGPU_CTX_PRIORITY_LOW -512
221 #define AMDGPU_CTX_PRIORITY_NORMAL 0
222 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
223 #define AMDGPU_CTX_PRIORITY_HIGH 512
224 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
226 struct drm_amdgpu_ctx_in {
227 /** AMDGPU_CTX_OP_* */
229 /** For future use, no flags defined so far */
235 union drm_amdgpu_ctx_out {
242 /** For future use, no flags defined so far */
244 /** Number of resets caused by this context so far. */
246 /** Reset status since the last call of the ioctl. */
251 union drm_amdgpu_ctx {
252 struct drm_amdgpu_ctx_in in;
253 union drm_amdgpu_ctx_out out;
257 #define AMDGPU_VM_OP_RESERVE_VMID 1
258 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
260 struct drm_amdgpu_vm_in {
261 /** AMDGPU_VM_OP_* */
266 struct drm_amdgpu_vm_out {
267 /** For future use, no flags defined so far */
271 union drm_amdgpu_vm {
272 struct drm_amdgpu_vm_in in;
273 struct drm_amdgpu_vm_out out;
277 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
278 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
280 struct drm_amdgpu_sched_in {
281 /* AMDGPU_SCHED_OP_* */
288 union drm_amdgpu_sched {
289 struct drm_amdgpu_sched_in in;
293 * This is not a reliable API and you should expect it to fail for any
294 * number of reasons and have fallback path that do not use userptr to
295 * perform any operation.
297 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
298 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
299 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
300 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
302 struct drm_amdgpu_gem_userptr {
305 /* AMDGPU_GEM_USERPTR_* */
307 /* Resulting GEM handle */
312 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
313 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
314 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
315 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
316 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
317 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
318 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
319 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
320 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
321 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
322 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
323 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
324 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
325 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
326 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
327 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
328 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
330 /* GFX9 and later: */
331 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
332 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
333 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
334 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
335 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
336 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
337 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
338 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
340 /* Set/Get helpers for tiling flags. */
341 #define AMDGPU_TILING_SET(field, value) \
342 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
343 #define AMDGPU_TILING_GET(value, field) \
344 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
346 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
347 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
349 /** The same structure is shared for input/output */
350 struct drm_amdgpu_gem_metadata {
351 /** GEM Object handle */
353 /** Do we want get or set metadata */
356 /** For future use, no flags defined so far */
358 /** family specific tiling info */
360 __u32 data_size_bytes;
365 struct drm_amdgpu_gem_mmap_in {
366 /** the GEM object handle */
371 struct drm_amdgpu_gem_mmap_out {
372 /** mmap offset from the vma offset manager */
376 union drm_amdgpu_gem_mmap {
377 struct drm_amdgpu_gem_mmap_in in;
378 struct drm_amdgpu_gem_mmap_out out;
381 struct drm_amdgpu_gem_wait_idle_in {
382 /** GEM object handle */
384 /** For future use, no flags defined so far */
386 /** Absolute timeout to wait */
390 struct drm_amdgpu_gem_wait_idle_out {
391 /** BO status: 0 - BO is idle, 1 - BO is busy */
393 /** Returned current memory domain */
397 union drm_amdgpu_gem_wait_idle {
398 struct drm_amdgpu_gem_wait_idle_in in;
399 struct drm_amdgpu_gem_wait_idle_out out;
402 struct drm_amdgpu_wait_cs_in {
403 /* Command submission handle
404 * handle equals 0 means none to wait for
405 * handle equals ~0ull means wait for the latest sequence number
408 /** Absolute timeout to wait */
416 struct drm_amdgpu_wait_cs_out {
417 /** CS status: 0 - CS completed, 1 - CS still busy */
421 union drm_amdgpu_wait_cs {
422 struct drm_amdgpu_wait_cs_in in;
423 struct drm_amdgpu_wait_cs_out out;
426 struct drm_amdgpu_fence {
434 struct drm_amdgpu_wait_fences_in {
435 /** This points to uint64_t * which points to fences */
442 struct drm_amdgpu_wait_fences_out {
444 __u32 first_signaled;
447 union drm_amdgpu_wait_fences {
448 struct drm_amdgpu_wait_fences_in in;
449 struct drm_amdgpu_wait_fences_out out;
452 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
453 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
455 /* Sets or returns a value associated with a buffer. */
456 struct drm_amdgpu_gem_op {
457 /** GEM object handle */
459 /** AMDGPU_GEM_OP_* */
461 /** Input or return value */
465 #define AMDGPU_VA_OP_MAP 1
466 #define AMDGPU_VA_OP_UNMAP 2
467 #define AMDGPU_VA_OP_CLEAR 3
468 #define AMDGPU_VA_OP_REPLACE 4
470 /* Delay the page table update till the next CS */
471 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
474 /* readable mapping */
475 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
476 /* writable mapping */
477 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
478 /* executable mapping, new for VI */
479 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
480 /* partially resident texture */
481 #define AMDGPU_VM_PAGE_PRT (1 << 4)
482 /* MTYPE flags use bit 5 to 8 */
483 #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
484 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
485 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
486 /* Use NC MTYPE instead of default MTYPE */
487 #define AMDGPU_VM_MTYPE_NC (1 << 5)
488 /* Use WC MTYPE instead of default MTYPE */
489 #define AMDGPU_VM_MTYPE_WC (2 << 5)
490 /* Use CC MTYPE instead of default MTYPE */
491 #define AMDGPU_VM_MTYPE_CC (3 << 5)
492 /* Use UC MTYPE instead of default MTYPE */
493 #define AMDGPU_VM_MTYPE_UC (4 << 5)
495 struct drm_amdgpu_gem_va {
496 /** GEM object handle */
499 /** AMDGPU_VA_OP_* */
501 /** AMDGPU_VM_PAGE_* */
503 /** va address to assign . Must be correctly aligned.*/
505 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
507 /** Specify mapping size. Must be correctly aligned. */
511 #define AMDGPU_HW_IP_GFX 0
512 #define AMDGPU_HW_IP_COMPUTE 1
513 #define AMDGPU_HW_IP_DMA 2
514 #define AMDGPU_HW_IP_UVD 3
515 #define AMDGPU_HW_IP_VCE 4
516 #define AMDGPU_HW_IP_UVD_ENC 5
517 #define AMDGPU_HW_IP_VCN_DEC 6
518 #define AMDGPU_HW_IP_VCN_ENC 7
519 #define AMDGPU_HW_IP_VCN_JPEG 8
520 #define AMDGPU_HW_IP_NUM 9
522 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
524 #define AMDGPU_CHUNK_ID_IB 0x01
525 #define AMDGPU_CHUNK_ID_FENCE 0x02
526 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
527 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
528 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
529 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
530 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
531 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
532 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
534 struct drm_amdgpu_cs_chunk {
540 struct drm_amdgpu_cs_in {
541 /** Rendering context id */
543 /** Handle of resource list associated with CS */
544 __u32 bo_list_handle;
547 /** this points to __u64 * which point to cs chunks */
551 struct drm_amdgpu_cs_out {
555 union drm_amdgpu_cs {
556 struct drm_amdgpu_cs_in in;
557 struct drm_amdgpu_cs_out out;
560 /* Specify flags to be used for IB */
562 /* This IB should be submitted to CE */
563 #define AMDGPU_IB_FLAG_CE (1<<0)
565 /* Preamble flag, which means the IB could be dropped if no context switch */
566 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
568 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
569 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
571 /* The IB fence should do the L2 writeback but not invalidate any shader
572 * caches (L2/vL1/sL1/I$). */
573 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
575 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
576 * This will reset wave ID counters for the IB.
578 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
580 struct drm_amdgpu_cs_chunk_ib {
582 /** AMDGPU_IB_FLAG_* */
584 /** Virtual address to begin IB execution */
586 /** Size of submission */
588 /** HW IP to submit to */
590 /** HW IP index of the same type to submit to */
592 /** Ring index to submit to */
596 struct drm_amdgpu_cs_chunk_dep {
604 struct drm_amdgpu_cs_chunk_fence {
609 struct drm_amdgpu_cs_chunk_sem {
613 struct drm_amdgpu_cs_chunk_syncobj {
619 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
620 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
621 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
623 union drm_amdgpu_fence_to_handle {
625 struct drm_amdgpu_fence fence;
634 struct drm_amdgpu_cs_chunk_data {
636 struct drm_amdgpu_cs_chunk_ib ib_data;
637 struct drm_amdgpu_cs_chunk_fence fence_data;
642 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
645 #define AMDGPU_IDS_FLAGS_FUSION 0x1
646 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
648 /* indicate if acceleration can be working */
649 #define AMDGPU_INFO_ACCEL_WORKING 0x00
650 /* get the crtc_id from the mode object id? */
651 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
652 /* query hw IP info */
653 #define AMDGPU_INFO_HW_IP_INFO 0x02
654 /* query hw IP instance count for the specified type */
655 #define AMDGPU_INFO_HW_IP_COUNT 0x03
656 /* timestamp for GL_ARB_timer_query */
657 #define AMDGPU_INFO_TIMESTAMP 0x05
658 /* Query the firmware version */
659 #define AMDGPU_INFO_FW_VERSION 0x0e
660 /* Subquery id: Query VCE firmware version */
661 #define AMDGPU_INFO_FW_VCE 0x1
662 /* Subquery id: Query UVD firmware version */
663 #define AMDGPU_INFO_FW_UVD 0x2
664 /* Subquery id: Query GMC firmware version */
665 #define AMDGPU_INFO_FW_GMC 0x03
666 /* Subquery id: Query GFX ME firmware version */
667 #define AMDGPU_INFO_FW_GFX_ME 0x04
668 /* Subquery id: Query GFX PFP firmware version */
669 #define AMDGPU_INFO_FW_GFX_PFP 0x05
670 /* Subquery id: Query GFX CE firmware version */
671 #define AMDGPU_INFO_FW_GFX_CE 0x06
672 /* Subquery id: Query GFX RLC firmware version */
673 #define AMDGPU_INFO_FW_GFX_RLC 0x07
674 /* Subquery id: Query GFX MEC firmware version */
675 #define AMDGPU_INFO_FW_GFX_MEC 0x08
676 /* Subquery id: Query SMC firmware version */
677 #define AMDGPU_INFO_FW_SMC 0x0a
678 /* Subquery id: Query SDMA firmware version */
679 #define AMDGPU_INFO_FW_SDMA 0x0b
680 /* Subquery id: Query PSP SOS firmware version */
681 #define AMDGPU_INFO_FW_SOS 0x0c
682 /* Subquery id: Query PSP ASD firmware version */
683 #define AMDGPU_INFO_FW_ASD 0x0d
684 /* Subquery id: Query VCN firmware version */
685 #define AMDGPU_INFO_FW_VCN 0x0e
686 /* Subquery id: Query GFX RLC SRLC firmware version */
687 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
688 /* Subquery id: Query GFX RLC SRLG firmware version */
689 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
690 /* Subquery id: Query GFX RLC SRLS firmware version */
691 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
692 /* Subquery id: Query DMCU firmware version */
693 #define AMDGPU_INFO_FW_DMCU 0x12
694 #define AMDGPU_INFO_FW_TA 0x13
695 /* number of bytes moved for TTM migration */
696 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
697 /* the used VRAM size */
698 #define AMDGPU_INFO_VRAM_USAGE 0x10
699 /* the used GTT size */
700 #define AMDGPU_INFO_GTT_USAGE 0x11
701 /* Information about GDS, etc. resource configuration */
702 #define AMDGPU_INFO_GDS_CONFIG 0x13
703 /* Query information about VRAM and GTT domains */
704 #define AMDGPU_INFO_VRAM_GTT 0x14
705 /* Query information about register in MMR address space*/
706 #define AMDGPU_INFO_READ_MMR_REG 0x15
707 /* Query information about device: rev id, family, etc. */
708 #define AMDGPU_INFO_DEV_INFO 0x16
709 /* visible vram usage */
710 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
711 /* number of TTM buffer evictions */
712 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
713 /* Query memory about VRAM and GTT domains */
714 #define AMDGPU_INFO_MEMORY 0x19
715 /* Query vce clock table */
716 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
717 /* Query vbios related information */
718 #define AMDGPU_INFO_VBIOS 0x1B
719 /* Subquery id: Query vbios size */
720 #define AMDGPU_INFO_VBIOS_SIZE 0x1
721 /* Subquery id: Query vbios image */
722 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
723 /* Query UVD handles */
724 #define AMDGPU_INFO_NUM_HANDLES 0x1C
725 /* Query sensor related information */
726 #define AMDGPU_INFO_SENSOR 0x1D
727 /* Subquery id: Query GPU shader clock */
728 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
729 /* Subquery id: Query GPU memory clock */
730 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
731 /* Subquery id: Query GPU temperature */
732 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
733 /* Subquery id: Query GPU load */
734 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
735 /* Subquery id: Query average GPU power */
736 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
737 /* Subquery id: Query northbridge voltage */
738 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
739 /* Subquery id: Query graphics voltage */
740 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
741 /* Subquery id: Query GPU stable pstate shader clock */
742 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
743 /* Subquery id: Query GPU stable pstate memory clock */
744 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
745 /* Number of VRAM page faults on CPU access. */
746 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
747 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
748 /* query ras mask of enabled features*/
749 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
751 /* RAS MASK: UMC (VRAM) */
752 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
754 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
756 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
757 /* RAS MASK: MMHUB */
758 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
759 /* RAS MASK: ATHUB */
760 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
762 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
764 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
766 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
768 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
770 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
772 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
774 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
776 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
778 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
780 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
781 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
782 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
783 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
785 struct drm_amdgpu_query_fw {
786 /** AMDGPU_INFO_FW_* */
789 * Index of the IP if there are more IPs of
794 * Index of the engine. Whether this is used depends
795 * on the firmware type. (e.g. MEC, SDMA)
801 /* Input structure for the INFO ioctl */
802 struct drm_amdgpu_info {
803 /* Where the return value will be stored */
804 __u64 return_pointer;
805 /* The size of the return value. Just like "size" in "snprintf",
806 * it limits how many bytes the kernel can write. */
808 /* The query request id. */
818 /** AMDGPU_HW_IP_* */
821 * Index of the IP if there are more IPs of the same
822 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
829 /** number of registers to read */
832 /** For future use, no flags defined so far */
836 struct drm_amdgpu_query_fw query_fw;
849 struct drm_amdgpu_info_gds {
850 /** GDS GFX partition size */
851 __u32 gds_gfx_partition_size;
852 /** GDS compute partition size */
853 __u32 compute_partition_size;
854 /** total GDS memory size */
855 __u32 gds_total_size;
856 /** GWS size per GFX partition */
857 __u32 gws_per_gfx_partition;
858 /** GSW size per compute partition */
859 __u32 gws_per_compute_partition;
860 /** OA size per GFX partition */
861 __u32 oa_per_gfx_partition;
862 /** OA size per compute partition */
863 __u32 oa_per_compute_partition;
867 struct drm_amdgpu_info_vram_gtt {
869 __u64 vram_cpu_accessible_size;
873 struct drm_amdgpu_heap_info {
874 /** max. physical memory */
875 __u64 total_heap_size;
877 /** Theoretical max. available memory in the given heap */
878 __u64 usable_heap_size;
881 * Number of bytes allocated in the heap. This includes all processes
882 * and private allocations in the kernel. It changes when new buffers
883 * are allocated, freed, and moved. It cannot be larger than
889 * Theoretical possible max. size of buffer which
890 * could be allocated in the given heap
892 __u64 max_allocation;
895 struct drm_amdgpu_memory_info {
896 struct drm_amdgpu_heap_info vram;
897 struct drm_amdgpu_heap_info cpu_accessible_vram;
898 struct drm_amdgpu_heap_info gtt;
901 struct drm_amdgpu_info_firmware {
906 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
907 #define AMDGPU_VRAM_TYPE_GDDR1 1
908 #define AMDGPU_VRAM_TYPE_DDR2 2
909 #define AMDGPU_VRAM_TYPE_GDDR3 3
910 #define AMDGPU_VRAM_TYPE_GDDR4 4
911 #define AMDGPU_VRAM_TYPE_GDDR5 5
912 #define AMDGPU_VRAM_TYPE_HBM 6
913 #define AMDGPU_VRAM_TYPE_DDR3 7
914 #define AMDGPU_VRAM_TYPE_DDR4 8
916 struct drm_amdgpu_info_device {
919 /** Internal chip revision: A0, A1, etc.) */
922 /** Revision id in PCI Config space */
925 __u32 num_shader_engines;
926 __u32 num_shader_arrays_per_engine;
928 __u32 gpu_counter_freq;
929 __u64 max_engine_clock;
930 __u64 max_memory_clock;
932 __u32 cu_active_number;
933 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
935 __u32 cu_bitmap[4][4];
936 /** Render backend pipe mask. One render backend is CB+DB. */
937 __u32 enabled_rb_pipes_mask;
939 __u32 num_hw_gfx_contexts;
942 /** Starting virtual address for UMDs. */
943 __u64 virtual_address_offset;
944 /** The maximum virtual address */
945 __u64 virtual_address_max;
946 /** Required alignment of virtual addresses. */
947 __u32 virtual_address_alignment;
948 /** Page table entry - fragment size */
949 __u32 pte_fragment_size;
950 __u32 gart_page_size;
951 /** constant engine ram size*/
953 /** video memory type info*/
955 /** video memory bit width*/
956 __u32 vram_bit_width;
957 /* vce harvesting instance */
958 __u32 vce_harvest_config;
959 /* gfx double offchip LDS buffers */
960 __u32 gc_double_offchip_lds_buf;
961 /* NGG Primitive Buffer */
962 __u64 prim_buf_gpu_addr;
963 /* NGG Position Buffer */
964 __u64 pos_buf_gpu_addr;
965 /* NGG Control Sideband */
966 __u64 cntl_sb_buf_gpu_addr;
967 /* NGG Parameter Cache */
968 __u64 param_buf_gpu_addr;
971 __u32 cntl_sb_buf_size;
972 __u32 param_buf_size;
974 __u32 wave_front_size;
975 /* shader visible vgprs*/
976 __u32 num_shader_visible_vgprs;
977 /* CU per shader array*/
979 /* number of tcc blocks*/
980 __u32 num_tcc_blocks;
981 /* gs vgt table depth*/
982 __u32 gs_vgt_table_depth;
983 /* gs primitive buffer depth*/
984 __u32 gs_prim_buffer_depth;
985 /* max gs wavefront per vgt*/
986 __u32 max_gs_waves_per_vgt;
988 /* always on cu bitmap */
989 __u32 cu_ao_bitmap[4][4];
990 /** Starting high virtual address for UMDs. */
991 __u64 high_va_offset;
992 /** The maximum high virtual address */
996 struct drm_amdgpu_info_hw_ip {
997 /** Version of h/w IP */
998 __u32 hw_ip_version_major;
999 __u32 hw_ip_version_minor;
1001 __u64 capabilities_flags;
1002 /** command buffer address start alignment*/
1003 __u32 ib_start_alignment;
1004 /** command buffer size alignment*/
1005 __u32 ib_size_alignment;
1006 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
1007 __u32 available_rings;
1011 struct drm_amdgpu_info_num_handles {
1012 /** Max handles as supported by firmware for UVD */
1013 __u32 uvd_max_handles;
1014 /** Handles currently in use for UVD */
1015 __u32 uvd_used_handles;
1018 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
1020 struct drm_amdgpu_info_vce_clock_table_entry {
1030 struct drm_amdgpu_info_vce_clock_table {
1031 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1032 __u32 num_valid_entries;
1037 * Supported GPU families
1039 #define AMDGPU_FAMILY_UNKNOWN 0
1040 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
1041 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
1042 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
1043 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
1044 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
1045 #define AMDGPU_FAMILY_AI 141 /* Vega10 */
1046 #define AMDGPU_FAMILY_RV 142 /* Raven */
1048 #if defined(__cplusplus)