1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
102 unsigned int has_bsd : 1;
103 unsigned int has_blt : 1;
104 unsigned int has_relaxed_fencing : 1;
105 unsigned int bo_reuse : 1;
107 } drm_intel_bufmgr_gem;
109 #define DRM_INTEL_RELOC_FENCE (1<<0)
111 typedef struct _drm_intel_reloc_target_info {
114 } drm_intel_reloc_target;
116 struct _drm_intel_bo_gem {
124 * Kenel-assigned global name for this object
126 unsigned int global_name;
129 * Index of the buffer within the validation list while preparing a
130 * batchbuffer execution.
135 * Current tiling mode
137 uint32_t tiling_mode;
138 uint32_t swizzle_mode;
139 unsigned long stride;
143 /** Array passed to the DRM containing relocation information. */
144 struct drm_i915_gem_relocation_entry *relocs;
146 * Array of info structs corresponding to relocs[i].target_handle etc
148 drm_intel_reloc_target *reloc_target_info;
149 /** Number of entries in relocs */
151 /** Mapped address for the buffer, saved across map/unmap cycles */
153 /** GTT virtual address for the buffer, saved across map/unmap cycles */
160 * Boolean of whether this BO and its children have been included in
161 * the current drm_intel_bufmgr_check_aperture_space() total.
163 char included_in_check_aperture;
166 * Boolean of whether this buffer has been used as a relocation
167 * target and had its size accounted for, and thus can't have any
168 * further relocations added to it.
170 char used_as_reloc_target;
173 * Boolean of whether we have encountered an error whilst building the relocation tree.
178 * Boolean of whether this buffer can be re-used
183 * Size in bytes of this buffer and its relocation descendents.
185 * Used to avoid costly tree walking in
186 * drm_intel_bufmgr_check_aperture in the common case.
191 * Number of potential fence registers required by this buffer and its
194 int reloc_tree_fences;
198 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
201 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
204 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
205 uint32_t * swizzle_mode);
208 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
209 uint32_t tiling_mode,
212 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
215 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
217 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
220 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
221 uint32_t *tiling_mode)
223 unsigned long min_size, max_size;
226 if (*tiling_mode == I915_TILING_NONE)
229 /* 965+ just need multiples of page size for tiling */
230 if (bufmgr_gem->gen >= 4)
231 return ROUND_UP_TO(size, 4096);
233 /* Older chips need powers of two, of at least 512k or 1M */
234 if (bufmgr_gem->gen == 3) {
235 min_size = 1024*1024;
236 max_size = 128*1024*1024;
239 max_size = 64*1024*1024;
242 if (size > max_size) {
243 *tiling_mode = I915_TILING_NONE;
247 /* Do we need to allocate every page for the fence? */
248 if (bufmgr_gem->has_relaxed_fencing)
249 return ROUND_UP_TO(size, 4096);
251 for (i = min_size; i < size; i <<= 1)
258 * Round a given pitch up to the minimum required for X tiling on a
259 * given chip. We use 512 as the minimum to allow for a later tiling
263 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
264 unsigned long pitch, uint32_t *tiling_mode)
266 unsigned long tile_width;
269 /* If untiled, then just align it so that we can do rendering
270 * to it with the 3D engine.
272 if (*tiling_mode == I915_TILING_NONE)
273 return ALIGN(pitch, 64);
275 if (*tiling_mode == I915_TILING_X)
280 /* 965 is flexible */
281 if (bufmgr_gem->gen >= 4)
282 return ROUND_UP_TO(pitch, tile_width);
284 /* The older hardware has a maximum pitch of 8192 with tiled
285 * surfaces, so fallback to untiled if it's too large.
288 *tiling_mode = I915_TILING_NONE;
289 return ALIGN(pitch, 64);
292 /* Pre-965 needs power of two tile width */
293 for (i = tile_width; i < pitch; i <<= 1)
299 static struct drm_intel_gem_bo_bucket *
300 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
305 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
306 struct drm_intel_gem_bo_bucket *bucket =
307 &bufmgr_gem->cache_bucket[i];
308 if (bucket->size >= size) {
317 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
321 for (i = 0; i < bufmgr_gem->exec_count; i++) {
322 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
323 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
325 if (bo_gem->relocs == NULL) {
326 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
331 for (j = 0; j < bo_gem->reloc_count; j++) {
332 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
333 drm_intel_bo_gem *target_gem =
334 (drm_intel_bo_gem *) target_bo;
336 DBG("%2d: %d (%s)@0x%08llx -> "
337 "%d (%s)@0x%08lx + 0x%08x\n",
339 bo_gem->gem_handle, bo_gem->name,
340 (unsigned long long)bo_gem->relocs[j].offset,
341 target_gem->gem_handle,
344 bo_gem->relocs[j].delta);
350 drm_intel_gem_bo_reference(drm_intel_bo *bo)
352 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
354 atomic_inc(&bo_gem->refcount);
358 * Adds the given buffer to the list of buffers to be validated (moved into the
359 * appropriate memory type) with the next batch submission.
361 * If a buffer is validated multiple times in a batch submission, it ends up
362 * with the intersection of the memory type flags and the union of the
366 drm_intel_add_validate_buffer(drm_intel_bo *bo)
368 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
369 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
372 if (bo_gem->validate_index != -1)
375 /* Extend the array of validation entries as necessary. */
376 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
377 int new_size = bufmgr_gem->exec_size * 2;
382 bufmgr_gem->exec_objects =
383 realloc(bufmgr_gem->exec_objects,
384 sizeof(*bufmgr_gem->exec_objects) * new_size);
385 bufmgr_gem->exec_bos =
386 realloc(bufmgr_gem->exec_bos,
387 sizeof(*bufmgr_gem->exec_bos) * new_size);
388 bufmgr_gem->exec_size = new_size;
391 index = bufmgr_gem->exec_count;
392 bo_gem->validate_index = index;
393 /* Fill in array entry */
394 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
395 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
396 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
397 bufmgr_gem->exec_objects[index].alignment = 0;
398 bufmgr_gem->exec_objects[index].offset = 0;
399 bufmgr_gem->exec_bos[index] = bo;
400 bufmgr_gem->exec_count++;
404 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
406 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
407 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
410 if (bo_gem->validate_index != -1) {
412 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
413 EXEC_OBJECT_NEEDS_FENCE;
417 /* Extend the array of validation entries as necessary. */
418 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
419 int new_size = bufmgr_gem->exec_size * 2;
424 bufmgr_gem->exec2_objects =
425 realloc(bufmgr_gem->exec2_objects,
426 sizeof(*bufmgr_gem->exec2_objects) * new_size);
427 bufmgr_gem->exec_bos =
428 realloc(bufmgr_gem->exec_bos,
429 sizeof(*bufmgr_gem->exec_bos) * new_size);
430 bufmgr_gem->exec_size = new_size;
433 index = bufmgr_gem->exec_count;
434 bo_gem->validate_index = index;
435 /* Fill in array entry */
436 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
437 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
438 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
439 bufmgr_gem->exec2_objects[index].alignment = 0;
440 bufmgr_gem->exec2_objects[index].offset = 0;
441 bufmgr_gem->exec_bos[index] = bo;
442 bufmgr_gem->exec2_objects[index].flags = 0;
443 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
444 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
446 bufmgr_gem->exec2_objects[index].flags |=
447 EXEC_OBJECT_NEEDS_FENCE;
449 bufmgr_gem->exec_count++;
452 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
456 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
457 drm_intel_bo_gem *bo_gem)
461 assert(!bo_gem->used_as_reloc_target);
463 /* The older chipsets are far-less flexible in terms of tiling,
464 * and require tiled buffer to be size aligned in the aperture.
465 * This means that in the worst possible case we will need a hole
466 * twice as large as the object in order for it to fit into the
467 * aperture. Optimal packing is for wimps.
469 size = bo_gem->bo.size;
470 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
473 if (bufmgr_gem->has_relaxed_fencing) {
474 if (bufmgr_gem->gen == 3)
475 min_size = 1024*1024;
479 while (min_size < size)
484 /* Account for worst-case alignment. */
488 bo_gem->reloc_tree_size = size;
492 drm_intel_setup_reloc_list(drm_intel_bo *bo)
494 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
495 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
496 unsigned int max_relocs = bufmgr_gem->max_relocs;
498 if (bo->size / 4 < max_relocs)
499 max_relocs = bo->size / 4;
501 bo_gem->relocs = malloc(max_relocs *
502 sizeof(struct drm_i915_gem_relocation_entry));
503 bo_gem->reloc_target_info = malloc(max_relocs *
504 sizeof(drm_intel_reloc_target));
505 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
506 bo_gem->has_error = 1;
508 free (bo_gem->relocs);
509 bo_gem->relocs = NULL;
511 free (bo_gem->reloc_target_info);
512 bo_gem->reloc_target_info = NULL;
521 drm_intel_gem_bo_busy(drm_intel_bo *bo)
523 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
524 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
525 struct drm_i915_gem_busy busy;
528 memset(&busy, 0, sizeof(busy));
529 busy.handle = bo_gem->gem_handle;
531 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
533 return (ret == 0 && busy.busy);
537 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
538 drm_intel_bo_gem *bo_gem, int state)
540 struct drm_i915_gem_madvise madv;
542 madv.handle = bo_gem->gem_handle;
545 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
547 return madv.retained;
551 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
553 return drm_intel_gem_bo_madvise_internal
554 ((drm_intel_bufmgr_gem *) bo->bufmgr,
555 (drm_intel_bo_gem *) bo,
559 /* drop the oldest entries that have been purged by the kernel */
561 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
562 struct drm_intel_gem_bo_bucket *bucket)
564 while (!DRMLISTEMPTY(&bucket->head)) {
565 drm_intel_bo_gem *bo_gem;
567 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
568 bucket->head.next, head);
569 if (drm_intel_gem_bo_madvise_internal
570 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
573 DRMLISTDEL(&bo_gem->head);
574 drm_intel_gem_bo_free(&bo_gem->bo);
578 static drm_intel_bo *
579 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
583 uint32_t tiling_mode,
584 unsigned long stride)
586 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
587 drm_intel_bo_gem *bo_gem;
588 unsigned int page_size = getpagesize();
590 struct drm_intel_gem_bo_bucket *bucket;
591 int alloc_from_cache;
592 unsigned long bo_size;
595 if (flags & BO_ALLOC_FOR_RENDER)
598 /* Round the allocated size up to a power of two number of pages. */
599 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
601 /* If we don't have caching at this size, don't actually round the
604 if (bucket == NULL) {
606 if (bo_size < page_size)
609 bo_size = bucket->size;
612 pthread_mutex_lock(&bufmgr_gem->lock);
613 /* Get a buffer out of the cache if available */
615 alloc_from_cache = 0;
616 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
618 /* Allocate new render-target BOs from the tail (MRU)
619 * of the list, as it will likely be hot in the GPU
620 * cache and in the aperture for us.
622 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
623 bucket->head.prev, head);
624 DRMLISTDEL(&bo_gem->head);
625 alloc_from_cache = 1;
627 /* For non-render-target BOs (where we're probably
628 * going to map it first thing in order to fill it
629 * with data), check if the last BO in the cache is
630 * unbusy, and only reuse in that case. Otherwise,
631 * allocating a new buffer is probably faster than
632 * waiting for the GPU to finish.
634 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
635 bucket->head.next, head);
636 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
637 alloc_from_cache = 1;
638 DRMLISTDEL(&bo_gem->head);
642 if (alloc_from_cache) {
643 if (!drm_intel_gem_bo_madvise_internal
644 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
645 drm_intel_gem_bo_free(&bo_gem->bo);
646 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
651 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
654 drm_intel_gem_bo_free(&bo_gem->bo);
659 pthread_mutex_unlock(&bufmgr_gem->lock);
661 if (!alloc_from_cache) {
662 struct drm_i915_gem_create create;
664 bo_gem = calloc(1, sizeof(*bo_gem));
668 bo_gem->bo.size = bo_size;
669 memset(&create, 0, sizeof(create));
670 create.size = bo_size;
672 ret = drmIoctl(bufmgr_gem->fd,
673 DRM_IOCTL_I915_GEM_CREATE,
675 bo_gem->gem_handle = create.handle;
676 bo_gem->bo.handle = bo_gem->gem_handle;
681 bo_gem->bo.bufmgr = bufmgr;
683 bo_gem->tiling_mode = I915_TILING_NONE;
684 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
687 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
690 drm_intel_gem_bo_free(&bo_gem->bo);
696 atomic_set(&bo_gem->refcount, 1);
697 bo_gem->validate_index = -1;
698 bo_gem->reloc_tree_fences = 0;
699 bo_gem->used_as_reloc_target = 0;
700 bo_gem->has_error = 0;
701 bo_gem->reusable = 1;
703 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
705 DBG("bo_create: buf %d (%s) %ldb\n",
706 bo_gem->gem_handle, bo_gem->name, size);
711 static drm_intel_bo *
712 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
715 unsigned int alignment)
717 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
719 I915_TILING_NONE, 0);
722 static drm_intel_bo *
723 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
726 unsigned int alignment)
728 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
729 I915_TILING_NONE, 0);
732 static drm_intel_bo *
733 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
734 int x, int y, int cpp, uint32_t *tiling_mode,
735 unsigned long *pitch, unsigned long flags)
737 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
738 unsigned long size, stride;
742 unsigned long aligned_y;
744 tiling = *tiling_mode;
746 /* If we're tiled, our allocations are in 8 or 32-row blocks,
747 * so failure to align our height means that we won't allocate
750 * If we're untiled, we still have to align to 2 rows high
751 * because the data port accesses 2x2 blocks even if the
752 * bottom row isn't to be rendered, so failure to align means
753 * we could walk off the end of the GTT and fault. This is
754 * documented on 965, and may be the case on older chipsets
755 * too so we try to be careful.
758 if (tiling == I915_TILING_NONE)
759 aligned_y = ALIGN(y, 2);
760 else if (tiling == I915_TILING_X)
761 aligned_y = ALIGN(y, 8);
762 else if (tiling == I915_TILING_Y)
763 aligned_y = ALIGN(y, 32);
766 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
767 size = stride * aligned_y;
768 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
769 } while (*tiling_mode != tiling);
772 if (tiling == I915_TILING_NONE)
775 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
780 * Returns a drm_intel_bo wrapping the given buffer object handle.
782 * This can be used when one application needs to pass a buffer object
786 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
790 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
791 drm_intel_bo_gem *bo_gem;
793 struct drm_gem_open open_arg;
794 struct drm_i915_gem_get_tiling get_tiling;
796 bo_gem = calloc(1, sizeof(*bo_gem));
800 memset(&open_arg, 0, sizeof(open_arg));
801 open_arg.name = handle;
802 ret = drmIoctl(bufmgr_gem->fd,
806 DBG("Couldn't reference %s handle 0x%08x: %s\n",
807 name, handle, strerror(errno));
811 bo_gem->bo.size = open_arg.size;
812 bo_gem->bo.offset = 0;
813 bo_gem->bo.virtual = NULL;
814 bo_gem->bo.bufmgr = bufmgr;
816 atomic_set(&bo_gem->refcount, 1);
817 bo_gem->validate_index = -1;
818 bo_gem->gem_handle = open_arg.handle;
819 bo_gem->bo.handle = open_arg.handle;
820 bo_gem->global_name = handle;
821 bo_gem->reusable = 0;
823 memset(&get_tiling, 0, sizeof(get_tiling));
824 get_tiling.handle = bo_gem->gem_handle;
825 ret = drmIoctl(bufmgr_gem->fd,
826 DRM_IOCTL_I915_GEM_GET_TILING,
829 drm_intel_gem_bo_unreference(&bo_gem->bo);
832 bo_gem->tiling_mode = get_tiling.tiling_mode;
833 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
834 /* XXX stride is unknown */
835 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
837 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
843 drm_intel_gem_bo_free(drm_intel_bo *bo)
845 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
846 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
847 struct drm_gem_close close;
850 if (bo_gem->mem_virtual)
851 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
852 if (bo_gem->gtt_virtual)
853 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
855 /* Close this object */
856 memset(&close, 0, sizeof(close));
857 close.handle = bo_gem->gem_handle;
858 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
860 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
861 bo_gem->gem_handle, bo_gem->name, strerror(errno));
866 /** Frees all cached buffers significantly older than @time. */
868 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
872 if (bufmgr_gem->time == time)
875 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
876 struct drm_intel_gem_bo_bucket *bucket =
877 &bufmgr_gem->cache_bucket[i];
879 while (!DRMLISTEMPTY(&bucket->head)) {
880 drm_intel_bo_gem *bo_gem;
882 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
883 bucket->head.next, head);
884 if (time - bo_gem->free_time <= 1)
887 DRMLISTDEL(&bo_gem->head);
889 drm_intel_gem_bo_free(&bo_gem->bo);
893 bufmgr_gem->time = time;
897 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
899 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
900 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
901 struct drm_intel_gem_bo_bucket *bucket;
904 /* Unreference all the target buffers */
905 for (i = 0; i < bo_gem->reloc_count; i++) {
906 if (bo_gem->reloc_target_info[i].bo != bo) {
907 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
908 reloc_target_info[i].bo,
912 bo_gem->reloc_count = 0;
913 bo_gem->used_as_reloc_target = 0;
915 DBG("bo_unreference final: %d (%s)\n",
916 bo_gem->gem_handle, bo_gem->name);
918 /* release memory associated with this object */
919 if (bo_gem->reloc_target_info) {
920 free(bo_gem->reloc_target_info);
921 bo_gem->reloc_target_info = NULL;
923 if (bo_gem->relocs) {
924 free(bo_gem->relocs);
925 bo_gem->relocs = NULL;
928 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
929 /* Put the buffer into our internal cache for reuse if we can. */
930 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
931 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
932 I915_MADV_DONTNEED)) {
933 bo_gem->free_time = time;
936 bo_gem->validate_index = -1;
938 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
940 drm_intel_gem_bo_free(bo);
944 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
947 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
949 assert(atomic_read(&bo_gem->refcount) > 0);
950 if (atomic_dec_and_test(&bo_gem->refcount))
951 drm_intel_gem_bo_unreference_final(bo, time);
954 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
956 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
958 assert(atomic_read(&bo_gem->refcount) > 0);
959 if (atomic_dec_and_test(&bo_gem->refcount)) {
960 drm_intel_bufmgr_gem *bufmgr_gem =
961 (drm_intel_bufmgr_gem *) bo->bufmgr;
962 struct timespec time;
964 clock_gettime(CLOCK_MONOTONIC, &time);
966 pthread_mutex_lock(&bufmgr_gem->lock);
967 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
968 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
969 pthread_mutex_unlock(&bufmgr_gem->lock);
973 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
975 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
976 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
977 struct drm_i915_gem_set_domain set_domain;
980 pthread_mutex_lock(&bufmgr_gem->lock);
982 /* Allow recursive mapping. Mesa may recursively map buffers with
983 * nested display loops.
985 if (!bo_gem->mem_virtual) {
986 struct drm_i915_gem_mmap mmap_arg;
988 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
990 memset(&mmap_arg, 0, sizeof(mmap_arg));
991 mmap_arg.handle = bo_gem->gem_handle;
993 mmap_arg.size = bo->size;
994 ret = drmIoctl(bufmgr_gem->fd,
995 DRM_IOCTL_I915_GEM_MMAP,
999 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1000 __FILE__, __LINE__, bo_gem->gem_handle,
1001 bo_gem->name, strerror(errno));
1002 pthread_mutex_unlock(&bufmgr_gem->lock);
1005 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1007 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1008 bo_gem->mem_virtual);
1009 bo->virtual = bo_gem->mem_virtual;
1011 set_domain.handle = bo_gem->gem_handle;
1012 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1014 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1016 set_domain.write_domain = 0;
1017 ret = drmIoctl(bufmgr_gem->fd,
1018 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1021 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1022 __FILE__, __LINE__, bo_gem->gem_handle,
1026 pthread_mutex_unlock(&bufmgr_gem->lock);
1031 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1033 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1034 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1035 struct drm_i915_gem_set_domain set_domain;
1038 pthread_mutex_lock(&bufmgr_gem->lock);
1040 /* Get a mapping of the buffer if we haven't before. */
1041 if (bo_gem->gtt_virtual == NULL) {
1042 struct drm_i915_gem_mmap_gtt mmap_arg;
1044 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1047 memset(&mmap_arg, 0, sizeof(mmap_arg));
1048 mmap_arg.handle = bo_gem->gem_handle;
1050 /* Get the fake offset back... */
1051 ret = drmIoctl(bufmgr_gem->fd,
1052 DRM_IOCTL_I915_GEM_MMAP_GTT,
1056 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1058 bo_gem->gem_handle, bo_gem->name,
1060 pthread_mutex_unlock(&bufmgr_gem->lock);
1065 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1066 MAP_SHARED, bufmgr_gem->fd,
1068 if (bo_gem->gtt_virtual == MAP_FAILED) {
1069 bo_gem->gtt_virtual = NULL;
1071 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1073 bo_gem->gem_handle, bo_gem->name,
1075 pthread_mutex_unlock(&bufmgr_gem->lock);
1080 bo->virtual = bo_gem->gtt_virtual;
1082 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1083 bo_gem->gtt_virtual);
1085 /* Now move it to the GTT domain so that the CPU caches are flushed */
1086 set_domain.handle = bo_gem->gem_handle;
1087 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1088 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1089 ret = drmIoctl(bufmgr_gem->fd,
1090 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1093 DBG("%s:%d: Error setting domain %d: %s\n",
1094 __FILE__, __LINE__, bo_gem->gem_handle,
1098 pthread_mutex_unlock(&bufmgr_gem->lock);
1103 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1105 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1111 pthread_mutex_lock(&bufmgr_gem->lock);
1113 pthread_mutex_unlock(&bufmgr_gem->lock);
1118 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1120 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1121 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1122 struct drm_i915_gem_sw_finish sw_finish;
1128 pthread_mutex_lock(&bufmgr_gem->lock);
1130 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1131 * results show up in a timely manner.
1133 sw_finish.handle = bo_gem->gem_handle;
1134 ret = drmIoctl(bufmgr_gem->fd,
1135 DRM_IOCTL_I915_GEM_SW_FINISH,
1137 ret = ret == -1 ? -errno : 0;
1140 pthread_mutex_unlock(&bufmgr_gem->lock);
1146 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1147 unsigned long size, const void *data)
1149 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1150 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1151 struct drm_i915_gem_pwrite pwrite;
1154 memset(&pwrite, 0, sizeof(pwrite));
1155 pwrite.handle = bo_gem->gem_handle;
1156 pwrite.offset = offset;
1158 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1159 ret = drmIoctl(bufmgr_gem->fd,
1160 DRM_IOCTL_I915_GEM_PWRITE,
1164 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1165 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1166 (int)size, strerror(errno));
1173 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1175 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1176 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1179 get_pipe_from_crtc_id.crtc_id = crtc_id;
1180 ret = drmIoctl(bufmgr_gem->fd,
1181 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1182 &get_pipe_from_crtc_id);
1184 /* We return -1 here to signal that we don't
1185 * know which pipe is associated with this crtc.
1186 * This lets the caller know that this information
1187 * isn't available; using the wrong pipe for
1188 * vblank waiting can cause the chipset to lock up
1193 return get_pipe_from_crtc_id.pipe;
1197 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1198 unsigned long size, void *data)
1200 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1201 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1202 struct drm_i915_gem_pread pread;
1205 memset(&pread, 0, sizeof(pread));
1206 pread.handle = bo_gem->gem_handle;
1207 pread.offset = offset;
1209 pread.data_ptr = (uint64_t) (uintptr_t) data;
1210 ret = drmIoctl(bufmgr_gem->fd,
1211 DRM_IOCTL_I915_GEM_PREAD,
1215 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1216 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1217 (int)size, strerror(errno));
1223 /** Waits for all GPU rendering with the object to have completed. */
1225 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1227 drm_intel_gem_bo_start_gtt_access(bo, 1);
1231 * Sets the object to the GTT read and possibly write domain, used by the X
1232 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1234 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1235 * can do tiled pixmaps this way.
1238 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1240 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1241 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1242 struct drm_i915_gem_set_domain set_domain;
1245 set_domain.handle = bo_gem->gem_handle;
1246 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1247 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1248 ret = drmIoctl(bufmgr_gem->fd,
1249 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1252 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1253 __FILE__, __LINE__, bo_gem->gem_handle,
1254 set_domain.read_domains, set_domain.write_domain,
1260 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1262 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1265 free(bufmgr_gem->exec2_objects);
1266 free(bufmgr_gem->exec_objects);
1267 free(bufmgr_gem->exec_bos);
1269 pthread_mutex_destroy(&bufmgr_gem->lock);
1271 /* Free any cached buffer objects we were going to reuse */
1272 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1273 struct drm_intel_gem_bo_bucket *bucket =
1274 &bufmgr_gem->cache_bucket[i];
1275 drm_intel_bo_gem *bo_gem;
1277 while (!DRMLISTEMPTY(&bucket->head)) {
1278 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1279 bucket->head.next, head);
1280 DRMLISTDEL(&bo_gem->head);
1282 drm_intel_gem_bo_free(&bo_gem->bo);
1290 * Adds the target buffer to the validation list and adds the relocation
1291 * to the reloc_buffer's relocation list.
1293 * The relocation entry at the given offset must already contain the
1294 * precomputed relocation value, because the kernel will optimize out
1295 * the relocation entry write when the buffer hasn't moved from the
1296 * last known offset in target_bo.
1299 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1300 drm_intel_bo *target_bo, uint32_t target_offset,
1301 uint32_t read_domains, uint32_t write_domain,
1304 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1305 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1306 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1309 if (bo_gem->has_error)
1312 if (target_bo_gem->has_error) {
1313 bo_gem->has_error = 1;
1317 /* We never use HW fences for rendering on 965+ */
1318 if (bufmgr_gem->gen >= 4)
1321 fenced_command = need_fence;
1322 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1325 /* Create a new relocation list if needed */
1326 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1329 /* Check overflow */
1330 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1333 assert(offset <= bo->size - 4);
1334 assert((write_domain & (write_domain - 1)) == 0);
1336 /* Make sure that we're not adding a reloc to something whose size has
1337 * already been accounted for.
1339 assert(!bo_gem->used_as_reloc_target);
1340 if (target_bo_gem != bo_gem) {
1341 target_bo_gem->used_as_reloc_target = 1;
1342 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1344 /* An object needing a fence is a tiled buffer, so it won't have
1345 * relocs to other buffers.
1348 target_bo_gem->reloc_tree_fences = 1;
1349 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1351 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1352 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1353 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1354 target_bo_gem->gem_handle;
1355 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1356 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1357 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1359 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1360 if (target_bo != bo)
1361 drm_intel_gem_bo_reference(target_bo);
1363 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1364 DRM_INTEL_RELOC_FENCE;
1366 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1368 bo_gem->reloc_count++;
1374 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1375 drm_intel_bo *target_bo, uint32_t target_offset,
1376 uint32_t read_domains, uint32_t write_domain)
1378 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1380 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1381 read_domains, write_domain,
1382 !bufmgr_gem->fenced_relocs);
1386 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1387 drm_intel_bo *target_bo,
1388 uint32_t target_offset,
1389 uint32_t read_domains, uint32_t write_domain)
1391 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1392 read_domains, write_domain, 1);
1396 * Walk the tree of relocations rooted at BO and accumulate the list of
1397 * validations to be performed and update the relocation buffers with
1398 * index values into the validation list.
1401 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1403 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1406 if (bo_gem->relocs == NULL)
1409 for (i = 0; i < bo_gem->reloc_count; i++) {
1410 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1412 if (target_bo == bo)
1415 /* Continue walking the tree depth-first. */
1416 drm_intel_gem_bo_process_reloc(target_bo);
1418 /* Add the target to the validate list */
1419 drm_intel_add_validate_buffer(target_bo);
1424 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1426 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1429 if (bo_gem->relocs == NULL)
1432 for (i = 0; i < bo_gem->reloc_count; i++) {
1433 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1436 if (target_bo == bo)
1439 /* Continue walking the tree depth-first. */
1440 drm_intel_gem_bo_process_reloc2(target_bo);
1442 need_fence = (bo_gem->reloc_target_info[i].flags &
1443 DRM_INTEL_RELOC_FENCE);
1445 /* Add the target to the validate list */
1446 drm_intel_add_validate_buffer2(target_bo, need_fence);
1452 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1456 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1457 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1458 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1460 /* Update the buffer offset */
1461 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1462 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1463 bo_gem->gem_handle, bo_gem->name, bo->offset,
1464 (unsigned long long)bufmgr_gem->exec_objects[i].
1466 bo->offset = bufmgr_gem->exec_objects[i].offset;
1472 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1476 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1477 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1478 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1480 /* Update the buffer offset */
1481 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1482 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1483 bo_gem->gem_handle, bo_gem->name, bo->offset,
1484 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1485 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1491 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1492 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1494 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1495 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1496 struct drm_i915_gem_execbuffer execbuf;
1499 if (bo_gem->has_error)
1502 pthread_mutex_lock(&bufmgr_gem->lock);
1503 /* Update indices and set up the validate list. */
1504 drm_intel_gem_bo_process_reloc(bo);
1506 /* Add the batch buffer to the validation list. There are no
1507 * relocations pointing to it.
1509 drm_intel_add_validate_buffer(bo);
1511 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1512 execbuf.buffer_count = bufmgr_gem->exec_count;
1513 execbuf.batch_start_offset = 0;
1514 execbuf.batch_len = used;
1515 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1516 execbuf.num_cliprects = num_cliprects;
1520 ret = drmIoctl(bufmgr_gem->fd,
1521 DRM_IOCTL_I915_GEM_EXECBUFFER,
1525 if (errno == ENOSPC) {
1526 DBG("Execbuffer fails to pin. "
1527 "Estimate: %u. Actual: %u. Available: %u\n",
1528 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1531 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1534 (unsigned int)bufmgr_gem->gtt_size);
1537 drm_intel_update_buffer_offsets(bufmgr_gem);
1539 if (bufmgr_gem->bufmgr.debug)
1540 drm_intel_gem_dump_validation_list(bufmgr_gem);
1542 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1543 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1544 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1546 /* Disconnect the buffer from the validate list */
1547 bo_gem->validate_index = -1;
1548 bufmgr_gem->exec_bos[i] = NULL;
1550 bufmgr_gem->exec_count = 0;
1551 pthread_mutex_unlock(&bufmgr_gem->lock);
1557 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1558 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1561 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1562 struct drm_i915_gem_execbuffer2 execbuf;
1565 switch (flags & 0x7) {
1569 if (!bufmgr_gem->has_blt)
1573 if (!bufmgr_gem->has_bsd)
1576 case I915_EXEC_RENDER:
1577 case I915_EXEC_DEFAULT:
1581 pthread_mutex_lock(&bufmgr_gem->lock);
1582 /* Update indices and set up the validate list. */
1583 drm_intel_gem_bo_process_reloc2(bo);
1585 /* Add the batch buffer to the validation list. There are no relocations
1588 drm_intel_add_validate_buffer2(bo, 0);
1590 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1591 execbuf.buffer_count = bufmgr_gem->exec_count;
1592 execbuf.batch_start_offset = 0;
1593 execbuf.batch_len = used;
1594 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1595 execbuf.num_cliprects = num_cliprects;
1598 execbuf.flags = flags;
1602 ret = drmIoctl(bufmgr_gem->fd,
1603 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1607 if (ret == -ENOSPC) {
1608 DBG("Execbuffer fails to pin. "
1609 "Estimate: %u. Actual: %u. Available: %u\n",
1610 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1611 bufmgr_gem->exec_count),
1612 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1613 bufmgr_gem->exec_count),
1614 (unsigned int) bufmgr_gem->gtt_size);
1617 drm_intel_update_buffer_offsets2(bufmgr_gem);
1619 if (bufmgr_gem->bufmgr.debug)
1620 drm_intel_gem_dump_validation_list(bufmgr_gem);
1622 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1623 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1624 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1626 /* Disconnect the buffer from the validate list */
1627 bo_gem->validate_index = -1;
1628 bufmgr_gem->exec_bos[i] = NULL;
1630 bufmgr_gem->exec_count = 0;
1631 pthread_mutex_unlock(&bufmgr_gem->lock);
1637 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1638 drm_clip_rect_t *cliprects, int num_cliprects,
1641 return drm_intel_gem_bo_mrb_exec2(bo, used,
1642 cliprects, num_cliprects, DR4,
1647 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1649 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1650 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1651 struct drm_i915_gem_pin pin;
1654 memset(&pin, 0, sizeof(pin));
1655 pin.handle = bo_gem->gem_handle;
1656 pin.alignment = alignment;
1658 ret = drmIoctl(bufmgr_gem->fd,
1659 DRM_IOCTL_I915_GEM_PIN,
1664 bo->offset = pin.offset;
1669 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1671 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1672 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1673 struct drm_i915_gem_unpin unpin;
1676 memset(&unpin, 0, sizeof(unpin));
1677 unpin.handle = bo_gem->gem_handle;
1679 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1687 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1688 uint32_t tiling_mode,
1691 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1692 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1693 struct drm_i915_gem_set_tiling set_tiling;
1696 if (bo_gem->global_name == 0 &&
1697 tiling_mode == bo_gem->tiling_mode &&
1698 stride == bo_gem->stride)
1701 memset(&set_tiling, 0, sizeof(set_tiling));
1703 /* set_tiling is slightly broken and overwrites the
1704 * input on the error path, so we have to open code
1707 set_tiling.handle = bo_gem->gem_handle;
1708 set_tiling.tiling_mode = tiling_mode;
1709 set_tiling.stride = stride;
1711 ret = ioctl(bufmgr_gem->fd,
1712 DRM_IOCTL_I915_GEM_SET_TILING,
1714 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1718 bo_gem->tiling_mode = set_tiling.tiling_mode;
1719 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1720 bo_gem->stride = set_tiling.stride;
1725 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1728 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1729 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1732 /* Linear buffers have no stride. By ensuring that we only ever use
1733 * stride 0 with linear buffers, we simplify our code.
1735 if (*tiling_mode == I915_TILING_NONE)
1738 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1740 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1742 *tiling_mode = bo_gem->tiling_mode;
1747 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1748 uint32_t * swizzle_mode)
1750 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1752 *tiling_mode = bo_gem->tiling_mode;
1753 *swizzle_mode = bo_gem->swizzle_mode;
1758 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1760 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1761 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1762 struct drm_gem_flink flink;
1765 if (!bo_gem->global_name) {
1766 memset(&flink, 0, sizeof(flink));
1767 flink.handle = bo_gem->gem_handle;
1769 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1772 bo_gem->global_name = flink.name;
1773 bo_gem->reusable = 0;
1776 *name = bo_gem->global_name;
1781 * Enables unlimited caching of buffer objects for reuse.
1783 * This is potentially very memory expensive, as the cache at each bucket
1784 * size is only bounded by how many buffers of that size we've managed to have
1785 * in flight at once.
1788 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1790 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1792 bufmgr_gem->bo_reuse = 1;
1796 * Enable use of fenced reloc type.
1798 * New code should enable this to avoid unnecessary fence register
1799 * allocation. If this option is not enabled, all relocs will have fence
1800 * register allocated.
1803 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1805 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1807 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1808 bufmgr_gem->fenced_relocs = 1;
1812 * Return the additional aperture space required by the tree of buffer objects
1816 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1818 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1822 if (bo == NULL || bo_gem->included_in_check_aperture)
1826 bo_gem->included_in_check_aperture = 1;
1828 for (i = 0; i < bo_gem->reloc_count; i++)
1830 drm_intel_gem_bo_get_aperture_space(bo_gem->
1831 reloc_target_info[i].bo);
1837 * Count the number of buffers in this list that need a fence reg
1839 * If the count is greater than the number of available regs, we'll have
1840 * to ask the caller to resubmit a batch with fewer tiled buffers.
1842 * This function over-counts if the same buffer is used multiple times.
1845 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1848 unsigned int total = 0;
1850 for (i = 0; i < count; i++) {
1851 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1856 total += bo_gem->reloc_tree_fences;
1862 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1863 * for the next drm_intel_bufmgr_check_aperture_space() call.
1866 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1868 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1871 if (bo == NULL || !bo_gem->included_in_check_aperture)
1874 bo_gem->included_in_check_aperture = 0;
1876 for (i = 0; i < bo_gem->reloc_count; i++)
1877 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1878 reloc_target_info[i].bo);
1882 * Return a conservative estimate for the amount of aperture required
1883 * for a collection of buffers. This may double-count some buffers.
1886 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1889 unsigned int total = 0;
1891 for (i = 0; i < count; i++) {
1892 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1894 total += bo_gem->reloc_tree_size;
1900 * Return the amount of aperture needed for a collection of buffers.
1901 * This avoids double counting any buffers, at the cost of looking
1902 * at every buffer in the set.
1905 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1908 unsigned int total = 0;
1910 for (i = 0; i < count; i++) {
1911 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1912 /* For the first buffer object in the array, we get an
1913 * accurate count back for its reloc_tree size (since nothing
1914 * had been flagged as being counted yet). We can save that
1915 * value out as a more conservative reloc_tree_size that
1916 * avoids double-counting target buffers. Since the first
1917 * buffer happens to usually be the batch buffer in our
1918 * callers, this can pull us back from doing the tree
1919 * walk on every new batch emit.
1922 drm_intel_bo_gem *bo_gem =
1923 (drm_intel_bo_gem *) bo_array[i];
1924 bo_gem->reloc_tree_size = total;
1928 for (i = 0; i < count; i++)
1929 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1934 * Return -1 if the batchbuffer should be flushed before attempting to
1935 * emit rendering referencing the buffers pointed to by bo_array.
1937 * This is required because if we try to emit a batchbuffer with relocations
1938 * to a tree of buffers that won't simultaneously fit in the aperture,
1939 * the rendering will return an error at a point where the software is not
1940 * prepared to recover from it.
1942 * However, we also want to emit the batchbuffer significantly before we reach
1943 * the limit, as a series of batchbuffers each of which references buffers
1944 * covering almost all of the aperture means that at each emit we end up
1945 * waiting to evict a buffer from the last rendering, and we get synchronous
1946 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1947 * get better parallelism.
1950 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1952 drm_intel_bufmgr_gem *bufmgr_gem =
1953 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1954 unsigned int total = 0;
1955 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1958 /* Check for fence reg constraints if necessary */
1959 if (bufmgr_gem->available_fences) {
1960 total_fences = drm_intel_gem_total_fences(bo_array, count);
1961 if (total_fences > bufmgr_gem->available_fences)
1965 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1967 if (total > threshold)
1968 total = drm_intel_gem_compute_batch_space(bo_array, count);
1970 if (total > threshold) {
1971 DBG("check_space: overflowed available aperture, "
1973 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1976 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1977 (int)bufmgr_gem->gtt_size / 1024);
1983 * Disable buffer reuse for objects which are shared with the kernel
1984 * as scanout buffers
1987 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1989 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1991 bo_gem->reusable = 0;
1996 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
1998 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2000 return bo_gem->reusable;
2004 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2006 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2009 for (i = 0; i < bo_gem->reloc_count; i++) {
2010 if (bo_gem->reloc_target_info[i].bo == target_bo)
2012 if (bo == bo_gem->reloc_target_info[i].bo)
2014 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2022 /** Return true if target_bo is referenced by bo's relocation tree. */
2024 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2026 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2028 if (bo == NULL || target_bo == NULL)
2030 if (target_bo_gem->used_as_reloc_target)
2031 return _drm_intel_gem_bo_references(bo, target_bo);
2036 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2038 unsigned int i = bufmgr_gem->num_buckets;
2040 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2042 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2043 bufmgr_gem->cache_bucket[i].size = size;
2044 bufmgr_gem->num_buckets++;
2048 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2050 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2052 /* OK, so power of two buckets was too wasteful of memory.
2053 * Give 3 other sizes between each power of two, to hopefully
2054 * cover things accurately enough. (The alternative is
2055 * probably to just go for exact matching of sizes, and assume
2056 * that for things like composited window resize the tiled
2057 * width/height alignment and rounding of sizes to pages will
2058 * get us useful cache hit rates anyway)
2060 add_bucket(bufmgr_gem, 4096);
2061 add_bucket(bufmgr_gem, 4096 * 2);
2062 add_bucket(bufmgr_gem, 4096 * 3);
2064 /* Initialize the linked lists for BO reuse cache. */
2065 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2066 add_bucket(bufmgr_gem, size);
2068 add_bucket(bufmgr_gem, size + size * 1 / 4);
2069 add_bucket(bufmgr_gem, size + size * 2 / 4);
2070 add_bucket(bufmgr_gem, size + size * 3 / 4);
2075 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2076 * and manage map buffer objections.
2078 * \param fd File descriptor of the opened DRM device.
2081 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2083 drm_intel_bufmgr_gem *bufmgr_gem;
2084 struct drm_i915_gem_get_aperture aperture;
2085 drm_i915_getparam_t gp;
2089 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2090 if (bufmgr_gem == NULL)
2093 bufmgr_gem->fd = fd;
2095 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2100 ret = drmIoctl(bufmgr_gem->fd,
2101 DRM_IOCTL_I915_GEM_GET_APERTURE,
2105 bufmgr_gem->gtt_size = aperture.aper_available_size;
2107 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2109 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2110 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2111 "May lead to reduced performance or incorrect "
2113 (int)bufmgr_gem->gtt_size / 1024);
2116 gp.param = I915_PARAM_CHIPSET_ID;
2117 gp.value = &bufmgr_gem->pci_device;
2118 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2120 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2121 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2124 if (IS_GEN2(bufmgr_gem))
2125 bufmgr_gem->gen = 2;
2126 else if (IS_GEN3(bufmgr_gem))
2127 bufmgr_gem->gen = 3;
2128 else if (IS_GEN4(bufmgr_gem))
2129 bufmgr_gem->gen = 4;
2131 bufmgr_gem->gen = 6;
2133 gp.param = I915_PARAM_HAS_EXECBUF2;
2134 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2138 gp.param = I915_PARAM_HAS_BSD;
2139 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2140 bufmgr_gem->has_bsd = ret == 0;
2142 gp.param = I915_PARAM_HAS_BLT;
2143 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2144 bufmgr_gem->has_blt = ret == 0;
2146 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2147 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2148 bufmgr_gem->has_relaxed_fencing = ret == 0;
2150 if (bufmgr_gem->gen < 4) {
2151 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2152 gp.value = &bufmgr_gem->available_fences;
2153 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2155 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2157 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2159 bufmgr_gem->available_fences = 0;
2161 /* XXX The kernel reports the total number of fences,
2162 * including any that may be pinned.
2164 * We presume that there will be at least one pinned
2165 * fence for the scanout buffer, but there may be more
2166 * than one scanout and the user may be manually
2167 * pinning buffers. Let's move to execbuffer2 and
2168 * thereby forget the insanity of using fences...
2170 bufmgr_gem->available_fences -= 2;
2171 if (bufmgr_gem->available_fences < 0)
2172 bufmgr_gem->available_fences = 0;
2176 /* Let's go with one relocation per every 2 dwords (but round down a bit
2177 * since a power of two will mean an extra page allocation for the reloc
2180 * Every 4 was too few for the blender benchmark.
2182 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2184 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2185 bufmgr_gem->bufmgr.bo_alloc_for_render =
2186 drm_intel_gem_bo_alloc_for_render;
2187 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2188 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2189 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2190 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2191 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2192 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2193 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2194 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2195 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2196 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2197 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2198 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2199 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2200 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2201 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2202 /* Use the new one if available */
2204 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2205 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2207 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2208 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2209 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2210 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2211 bufmgr_gem->bufmgr.debug = 0;
2212 bufmgr_gem->bufmgr.check_aperture_space =
2213 drm_intel_gem_check_aperture_space;
2214 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2215 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2216 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2217 drm_intel_gem_get_pipe_from_crtc_id;
2218 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2220 init_cache_buckets(bufmgr_gem);
2222 return &bufmgr_gem->bufmgr;