1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
111 * Kenel-assigned global name for this object
113 unsigned int global_name;
116 * Index of the buffer within the validation list while preparing a
117 * batchbuffer execution.
122 * Current tiling mode
124 uint32_t tiling_mode;
125 uint32_t swizzle_mode;
129 /** Array passed to the DRM containing relocation information. */
130 struct drm_i915_gem_relocation_entry *relocs;
131 /** Array of bos corresponding to relocs[i].target_handle */
132 drm_intel_bo **reloc_target_bo;
133 /** Number of entries in relocs */
135 /** Mapped address for the buffer, saved across map/unmap cycles */
137 /** GTT virtual address for the buffer, saved across map/unmap cycles */
144 * Boolean of whether this BO and its children have been included in
145 * the current drm_intel_bufmgr_check_aperture_space() total.
147 char included_in_check_aperture;
150 * Boolean of whether this buffer has been used as a relocation
151 * target and had its size accounted for, and thus can't have any
152 * further relocations added to it.
154 char used_as_reloc_target;
157 * Boolean of whether we have encountered an error whilst building the relocation tree.
162 * Boolean of whether this buffer can be re-used
167 * Size in bytes of this buffer and its relocation descendents.
169 * Used to avoid costly tree walking in
170 * drm_intel_bufmgr_check_aperture in the common case.
175 * Number of potential fence registers required by this buffer and its
178 int reloc_tree_fences;
182 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
185 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
188 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
189 uint32_t * swizzle_mode);
192 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
195 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
198 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
200 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
203 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
204 uint32_t *tiling_mode)
206 unsigned long min_size, max_size;
209 if (*tiling_mode == I915_TILING_NONE)
212 /* 965+ just need multiples of page size for tiling */
213 if (IS_I965G(bufmgr_gem))
214 return ROUND_UP_TO(size, 4096);
216 /* Older chips need powers of two, of at least 512k or 1M */
217 if (IS_I9XX(bufmgr_gem)) {
218 min_size = 1024*1024;
219 max_size = 128*1024*1024;
222 max_size = 64*1024*1024;
225 if (size > max_size) {
226 *tiling_mode = I915_TILING_NONE;
230 for (i = min_size; i < size; i <<= 1)
237 * Round a given pitch up to the minimum required for X tiling on a
238 * given chip. We use 512 as the minimum to allow for a later tiling
242 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
243 unsigned long pitch, uint32_t tiling_mode)
245 unsigned long tile_width = 512;
248 if (tiling_mode == I915_TILING_NONE)
249 return ROUND_UP_TO(pitch, tile_width);
251 /* 965 is flexible */
252 if (IS_I965G(bufmgr_gem))
253 return ROUND_UP_TO(pitch, tile_width);
255 /* Pre-965 needs power of two tile width */
256 for (i = tile_width; i < pitch; i <<= 1)
262 static struct drm_intel_gem_bo_bucket *
263 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
268 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
269 struct drm_intel_gem_bo_bucket *bucket =
270 &bufmgr_gem->cache_bucket[i];
271 if (bucket->size >= size) {
280 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
284 for (i = 0; i < bufmgr_gem->exec_count; i++) {
285 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
286 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
288 if (bo_gem->relocs == NULL) {
289 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
294 for (j = 0; j < bo_gem->reloc_count; j++) {
295 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
296 drm_intel_bo_gem *target_gem =
297 (drm_intel_bo_gem *) target_bo;
299 DBG("%2d: %d (%s)@0x%08llx -> "
300 "%d (%s)@0x%08lx + 0x%08x\n",
302 bo_gem->gem_handle, bo_gem->name,
303 (unsigned long long)bo_gem->relocs[j].offset,
304 target_gem->gem_handle,
307 bo_gem->relocs[j].delta);
313 drm_intel_gem_bo_reference(drm_intel_bo *bo)
315 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
317 assert(atomic_read(&bo_gem->refcount) > 0);
318 atomic_inc(&bo_gem->refcount);
322 * Adds the given buffer to the list of buffers to be validated (moved into the
323 * appropriate memory type) with the next batch submission.
325 * If a buffer is validated multiple times in a batch submission, it ends up
326 * with the intersection of the memory type flags and the union of the
330 drm_intel_add_validate_buffer(drm_intel_bo *bo)
332 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
333 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
336 if (bo_gem->validate_index != -1)
339 /* Extend the array of validation entries as necessary. */
340 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
341 int new_size = bufmgr_gem->exec_size * 2;
346 bufmgr_gem->exec_objects =
347 realloc(bufmgr_gem->exec_objects,
348 sizeof(*bufmgr_gem->exec_objects) * new_size);
349 bufmgr_gem->exec_bos =
350 realloc(bufmgr_gem->exec_bos,
351 sizeof(*bufmgr_gem->exec_bos) * new_size);
352 bufmgr_gem->exec_size = new_size;
355 index = bufmgr_gem->exec_count;
356 bo_gem->validate_index = index;
357 /* Fill in array entry */
358 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
359 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
360 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
361 bufmgr_gem->exec_objects[index].alignment = 0;
362 bufmgr_gem->exec_objects[index].offset = 0;
363 bufmgr_gem->exec_bos[index] = bo;
364 bufmgr_gem->exec_count++;
367 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
371 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
372 drm_intel_bo_gem *bo_gem)
376 assert(!bo_gem->used_as_reloc_target);
378 /* The older chipsets are far-less flexible in terms of tiling,
379 * and require tiled buffer to be size aligned in the aperture.
380 * This means that in the worst possible case we will need a hole
381 * twice as large as the object in order for it to fit into the
382 * aperture. Optimal packing is for wimps.
384 size = bo_gem->bo.size;
385 if (!IS_I965G(bufmgr_gem) && bo_gem->tiling_mode != I915_TILING_NONE)
388 bo_gem->reloc_tree_size = size;
392 drm_intel_setup_reloc_list(drm_intel_bo *bo)
394 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
395 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
396 unsigned int max_relocs = bufmgr_gem->max_relocs;
398 if (bo->size / 4 < max_relocs)
399 max_relocs = bo->size / 4;
401 bo_gem->relocs = malloc(max_relocs *
402 sizeof(struct drm_i915_gem_relocation_entry));
403 bo_gem->reloc_target_bo = malloc(max_relocs * sizeof(drm_intel_bo *));
404 if (bo_gem->relocs == NULL || bo_gem->reloc_target_bo == NULL) {
405 bo_gem->has_error = 1;
407 free (bo_gem->relocs);
408 bo_gem->relocs = NULL;
410 free (bo_gem->reloc_target_bo);
411 bo_gem->reloc_target_bo = NULL;
420 drm_intel_gem_bo_busy(drm_intel_bo *bo)
422 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
423 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
424 struct drm_i915_gem_busy busy;
427 memset(&busy, 0, sizeof(busy));
428 busy.handle = bo_gem->gem_handle;
431 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
432 } while (ret == -1 && errno == EINTR);
434 return (ret == 0 && busy.busy);
438 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
439 drm_intel_bo_gem *bo_gem, int state)
441 struct drm_i915_gem_madvise madv;
443 madv.handle = bo_gem->gem_handle;
446 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
448 return madv.retained;
452 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
454 return drm_intel_gem_bo_madvise_internal
455 ((drm_intel_bufmgr_gem *) bo->bufmgr,
456 (drm_intel_bo_gem *) bo,
460 /* drop the oldest entries that have been purged by the kernel */
462 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
463 struct drm_intel_gem_bo_bucket *bucket)
465 while (!DRMLISTEMPTY(&bucket->head)) {
466 drm_intel_bo_gem *bo_gem;
468 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
469 bucket->head.next, head);
470 if (drm_intel_gem_bo_madvise_internal
471 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
474 DRMLISTDEL(&bo_gem->head);
475 drm_intel_gem_bo_free(&bo_gem->bo);
479 static drm_intel_bo *
480 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
485 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
486 drm_intel_bo_gem *bo_gem;
487 unsigned int page_size = getpagesize();
489 struct drm_intel_gem_bo_bucket *bucket;
490 int alloc_from_cache;
491 unsigned long bo_size;
494 if (flags & BO_ALLOC_FOR_RENDER)
497 /* Round the allocated size up to a power of two number of pages. */
498 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
500 /* If we don't have caching at this size, don't actually round the
503 if (bucket == NULL) {
505 if (bo_size < page_size)
508 bo_size = bucket->size;
511 pthread_mutex_lock(&bufmgr_gem->lock);
512 /* Get a buffer out of the cache if available */
514 alloc_from_cache = 0;
515 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
517 /* Allocate new render-target BOs from the tail (MRU)
518 * of the list, as it will likely be hot in the GPU
519 * cache and in the aperture for us.
521 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
522 bucket->head.prev, head);
523 DRMLISTDEL(&bo_gem->head);
524 alloc_from_cache = 1;
526 /* For non-render-target BOs (where we're probably
527 * going to map it first thing in order to fill it
528 * with data), check if the last BO in the cache is
529 * unbusy, and only reuse in that case. Otherwise,
530 * allocating a new buffer is probably faster than
531 * waiting for the GPU to finish.
533 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
534 bucket->head.next, head);
535 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
536 alloc_from_cache = 1;
537 DRMLISTDEL(&bo_gem->head);
541 if (alloc_from_cache) {
542 if (!drm_intel_gem_bo_madvise_internal
543 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
544 drm_intel_gem_bo_free(&bo_gem->bo);
545 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
551 pthread_mutex_unlock(&bufmgr_gem->lock);
553 if (!alloc_from_cache) {
554 struct drm_i915_gem_create create;
556 bo_gem = calloc(1, sizeof(*bo_gem));
560 bo_gem->bo.size = bo_size;
561 memset(&create, 0, sizeof(create));
562 create.size = bo_size;
565 ret = ioctl(bufmgr_gem->fd,
566 DRM_IOCTL_I915_GEM_CREATE,
568 } while (ret == -1 && errno == EINTR);
569 bo_gem->gem_handle = create.handle;
570 bo_gem->bo.handle = bo_gem->gem_handle;
575 bo_gem->bo.bufmgr = bufmgr;
579 atomic_set(&bo_gem->refcount, 1);
580 bo_gem->validate_index = -1;
581 bo_gem->reloc_tree_fences = 0;
582 bo_gem->used_as_reloc_target = 0;
583 bo_gem->has_error = 0;
584 bo_gem->tiling_mode = I915_TILING_NONE;
585 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
586 bo_gem->reusable = 1;
588 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
590 DBG("bo_create: buf %d (%s) %ldb\n",
591 bo_gem->gem_handle, bo_gem->name, size);
596 static drm_intel_bo *
597 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
600 unsigned int alignment)
602 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
603 BO_ALLOC_FOR_RENDER);
606 static drm_intel_bo *
607 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
610 unsigned int alignment)
612 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
615 static drm_intel_bo *
616 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
617 int x, int y, int cpp, uint32_t *tiling_mode,
618 unsigned long *pitch, unsigned long flags)
620 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
622 unsigned long size, stride, aligned_y = y;
625 if (*tiling_mode == I915_TILING_NONE)
626 aligned_y = ALIGN(y, 2);
627 else if (*tiling_mode == I915_TILING_X)
628 aligned_y = ALIGN(y, 8);
629 else if (*tiling_mode == I915_TILING_Y)
630 aligned_y = ALIGN(y, 32);
633 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
634 size = stride * aligned_y;
635 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
637 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
641 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
643 drm_intel_gem_bo_unreference(bo);
653 * Returns a drm_intel_bo wrapping the given buffer object handle.
655 * This can be used when one application needs to pass a buffer object
659 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
663 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
664 drm_intel_bo_gem *bo_gem;
666 struct drm_gem_open open_arg;
667 struct drm_i915_gem_get_tiling get_tiling;
669 bo_gem = calloc(1, sizeof(*bo_gem));
673 memset(&open_arg, 0, sizeof(open_arg));
674 open_arg.name = handle;
676 ret = ioctl(bufmgr_gem->fd,
679 } while (ret == -1 && errno == EINTR);
681 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
682 name, handle, strerror(errno));
686 bo_gem->bo.size = open_arg.size;
687 bo_gem->bo.offset = 0;
688 bo_gem->bo.virtual = NULL;
689 bo_gem->bo.bufmgr = bufmgr;
691 atomic_set(&bo_gem->refcount, 1);
692 bo_gem->validate_index = -1;
693 bo_gem->gem_handle = open_arg.handle;
694 bo_gem->global_name = handle;
695 bo_gem->reusable = 0;
697 memset(&get_tiling, 0, sizeof(get_tiling));
698 get_tiling.handle = bo_gem->gem_handle;
699 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
701 drm_intel_gem_bo_unreference(&bo_gem->bo);
704 bo_gem->tiling_mode = get_tiling.tiling_mode;
705 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
706 if (bo_gem->tiling_mode == I915_TILING_NONE)
707 bo_gem->reloc_tree_fences = 0;
709 bo_gem->reloc_tree_fences = 1;
710 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
712 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
718 drm_intel_gem_bo_free(drm_intel_bo *bo)
720 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
721 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
722 struct drm_gem_close close;
725 if (bo_gem->mem_virtual)
726 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
727 if (bo_gem->gtt_virtual)
728 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
730 /* Close this object */
731 memset(&close, 0, sizeof(close));
732 close.handle = bo_gem->gem_handle;
733 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
736 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
737 bo_gem->gem_handle, bo_gem->name, strerror(errno));
742 /** Frees all cached buffers significantly older than @time. */
744 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
748 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
749 struct drm_intel_gem_bo_bucket *bucket =
750 &bufmgr_gem->cache_bucket[i];
752 while (!DRMLISTEMPTY(&bucket->head)) {
753 drm_intel_bo_gem *bo_gem;
755 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
756 bucket->head.next, head);
757 if (time - bo_gem->free_time <= 1)
760 DRMLISTDEL(&bo_gem->head);
762 drm_intel_gem_bo_free(&bo_gem->bo);
768 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
770 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
771 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
772 struct drm_intel_gem_bo_bucket *bucket;
773 uint32_t tiling_mode;
776 /* Unreference all the target buffers */
777 for (i = 0; i < bo_gem->reloc_count; i++) {
778 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
782 bo_gem->reloc_count = 0;
783 bo_gem->used_as_reloc_target = 0;
785 DBG("bo_unreference final: %d (%s)\n",
786 bo_gem->gem_handle, bo_gem->name);
788 /* release memory associated with this object */
789 if (bo_gem->reloc_target_bo) {
790 free(bo_gem->reloc_target_bo);
791 bo_gem->reloc_target_bo = NULL;
793 if (bo_gem->relocs) {
794 free(bo_gem->relocs);
795 bo_gem->relocs = NULL;
798 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
799 /* Put the buffer into our internal cache for reuse if we can. */
800 tiling_mode = I915_TILING_NONE;
801 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
802 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
803 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
804 I915_MADV_DONTNEED)) {
805 bo_gem->free_time = time;
808 bo_gem->validate_index = -1;
810 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
812 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
814 drm_intel_gem_bo_free(bo);
818 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
821 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
823 assert(atomic_read(&bo_gem->refcount) > 0);
824 if (atomic_dec_and_test(&bo_gem->refcount))
825 drm_intel_gem_bo_unreference_final(bo, time);
828 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
830 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
832 assert(atomic_read(&bo_gem->refcount) > 0);
833 if (atomic_dec_and_test(&bo_gem->refcount)) {
834 drm_intel_bufmgr_gem *bufmgr_gem =
835 (drm_intel_bufmgr_gem *) bo->bufmgr;
836 struct timespec time;
838 clock_gettime(CLOCK_MONOTONIC, &time);
840 pthread_mutex_lock(&bufmgr_gem->lock);
841 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
842 pthread_mutex_unlock(&bufmgr_gem->lock);
846 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
848 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
849 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
850 struct drm_i915_gem_set_domain set_domain;
853 pthread_mutex_lock(&bufmgr_gem->lock);
855 /* Allow recursive mapping. Mesa may recursively map buffers with
856 * nested display loops.
858 if (!bo_gem->mem_virtual) {
859 struct drm_i915_gem_mmap mmap_arg;
861 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
863 memset(&mmap_arg, 0, sizeof(mmap_arg));
864 mmap_arg.handle = bo_gem->gem_handle;
866 mmap_arg.size = bo->size;
868 ret = ioctl(bufmgr_gem->fd,
869 DRM_IOCTL_I915_GEM_MMAP,
871 } while (ret == -1 && errno == EINTR);
875 "%s:%d: Error mapping buffer %d (%s): %s .\n",
876 __FILE__, __LINE__, bo_gem->gem_handle,
877 bo_gem->name, strerror(errno));
878 pthread_mutex_unlock(&bufmgr_gem->lock);
881 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
883 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
884 bo_gem->mem_virtual);
885 bo->virtual = bo_gem->mem_virtual;
887 set_domain.handle = bo_gem->gem_handle;
888 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
890 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
892 set_domain.write_domain = 0;
894 ret = ioctl(bufmgr_gem->fd,
895 DRM_IOCTL_I915_GEM_SET_DOMAIN,
897 } while (ret == -1 && errno == EINTR);
900 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
901 __FILE__, __LINE__, bo_gem->gem_handle,
903 pthread_mutex_unlock(&bufmgr_gem->lock);
907 pthread_mutex_unlock(&bufmgr_gem->lock);
912 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
914 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
915 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
916 struct drm_i915_gem_set_domain set_domain;
919 pthread_mutex_lock(&bufmgr_gem->lock);
921 /* Get a mapping of the buffer if we haven't before. */
922 if (bo_gem->gtt_virtual == NULL) {
923 struct drm_i915_gem_mmap_gtt mmap_arg;
925 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
928 memset(&mmap_arg, 0, sizeof(mmap_arg));
929 mmap_arg.handle = bo_gem->gem_handle;
931 /* Get the fake offset back... */
933 ret = ioctl(bufmgr_gem->fd,
934 DRM_IOCTL_I915_GEM_MMAP_GTT,
936 } while (ret == -1 && errno == EINTR);
940 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
942 bo_gem->gem_handle, bo_gem->name,
944 pthread_mutex_unlock(&bufmgr_gem->lock);
949 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
950 MAP_SHARED, bufmgr_gem->fd,
952 if (bo_gem->gtt_virtual == MAP_FAILED) {
955 "%s:%d: Error mapping buffer %d (%s): %s .\n",
957 bo_gem->gem_handle, bo_gem->name,
959 pthread_mutex_unlock(&bufmgr_gem->lock);
964 bo->virtual = bo_gem->gtt_virtual;
966 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
967 bo_gem->gtt_virtual);
969 /* Now move it to the GTT domain so that the CPU caches are flushed */
970 set_domain.handle = bo_gem->gem_handle;
971 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
972 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
974 ret = ioctl(bufmgr_gem->fd,
975 DRM_IOCTL_I915_GEM_SET_DOMAIN,
977 } while (ret == -1 && errno == EINTR);
981 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
982 __FILE__, __LINE__, bo_gem->gem_handle,
986 pthread_mutex_unlock(&bufmgr_gem->lock);
991 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
993 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
994 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1000 assert(bo_gem->gtt_virtual != NULL);
1002 pthread_mutex_lock(&bufmgr_gem->lock);
1004 pthread_mutex_unlock(&bufmgr_gem->lock);
1009 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1011 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1012 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1013 struct drm_i915_gem_sw_finish sw_finish;
1019 assert(bo_gem->mem_virtual != NULL);
1021 pthread_mutex_lock(&bufmgr_gem->lock);
1023 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1024 * results show up in a timely manner.
1026 sw_finish.handle = bo_gem->gem_handle;
1028 ret = ioctl(bufmgr_gem->fd,
1029 DRM_IOCTL_I915_GEM_SW_FINISH,
1031 } while (ret == -1 && errno == EINTR);
1034 pthread_mutex_unlock(&bufmgr_gem->lock);
1039 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1040 unsigned long size, const void *data)
1042 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1043 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1044 struct drm_i915_gem_pwrite pwrite;
1047 memset(&pwrite, 0, sizeof(pwrite));
1048 pwrite.handle = bo_gem->gem_handle;
1049 pwrite.offset = offset;
1051 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1053 ret = ioctl(bufmgr_gem->fd,
1054 DRM_IOCTL_I915_GEM_PWRITE,
1056 } while (ret == -1 && errno == EINTR);
1059 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1060 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1061 (int)size, strerror(errno));
1067 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1069 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1070 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1073 get_pipe_from_crtc_id.crtc_id = crtc_id;
1074 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1075 &get_pipe_from_crtc_id);
1077 /* We return -1 here to signal that we don't
1078 * know which pipe is associated with this crtc.
1079 * This lets the caller know that this information
1080 * isn't available; using the wrong pipe for
1081 * vblank waiting can cause the chipset to lock up
1086 return get_pipe_from_crtc_id.pipe;
1090 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1091 unsigned long size, void *data)
1093 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1094 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1095 struct drm_i915_gem_pread pread;
1098 memset(&pread, 0, sizeof(pread));
1099 pread.handle = bo_gem->gem_handle;
1100 pread.offset = offset;
1102 pread.data_ptr = (uint64_t) (uintptr_t) data;
1104 ret = ioctl(bufmgr_gem->fd,
1105 DRM_IOCTL_I915_GEM_PREAD,
1107 } while (ret == -1 && errno == EINTR);
1111 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1112 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1113 (int)size, strerror(errno));
1118 /** Waits for all GPU rendering to the object to have completed. */
1120 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1122 drm_intel_gem_bo_start_gtt_access(bo, 0);
1126 * Sets the object to the GTT read and possibly write domain, used by the X
1127 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1129 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1130 * can do tiled pixmaps this way.
1133 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1135 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1136 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1137 struct drm_i915_gem_set_domain set_domain;
1140 set_domain.handle = bo_gem->gem_handle;
1141 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1142 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1144 ret = ioctl(bufmgr_gem->fd,
1145 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1147 } while (ret == -1 && errno == EINTR);
1150 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1151 __FILE__, __LINE__, bo_gem->gem_handle,
1152 set_domain.read_domains, set_domain.write_domain,
1158 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1160 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1163 free(bufmgr_gem->exec_objects);
1164 free(bufmgr_gem->exec_bos);
1166 pthread_mutex_destroy(&bufmgr_gem->lock);
1168 /* Free any cached buffer objects we were going to reuse */
1169 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1170 struct drm_intel_gem_bo_bucket *bucket =
1171 &bufmgr_gem->cache_bucket[i];
1172 drm_intel_bo_gem *bo_gem;
1174 while (!DRMLISTEMPTY(&bucket->head)) {
1175 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1176 bucket->head.next, head);
1177 DRMLISTDEL(&bo_gem->head);
1179 drm_intel_gem_bo_free(&bo_gem->bo);
1187 * Adds the target buffer to the validation list and adds the relocation
1188 * to the reloc_buffer's relocation list.
1190 * The relocation entry at the given offset must already contain the
1191 * precomputed relocation value, because the kernel will optimize out
1192 * the relocation entry write when the buffer hasn't moved from the
1193 * last known offset in target_bo.
1196 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1197 drm_intel_bo *target_bo, uint32_t target_offset,
1198 uint32_t read_domains, uint32_t write_domain)
1200 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1201 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1202 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1204 pthread_mutex_lock(&bufmgr_gem->lock);
1205 if (bo_gem->has_error) {
1206 pthread_mutex_unlock(&bufmgr_gem->lock);
1210 if (target_bo_gem->has_error) {
1211 bo_gem->has_error = 1;
1212 pthread_mutex_unlock(&bufmgr_gem->lock);
1216 /* Create a new relocation list if needed */
1217 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo)) {
1218 pthread_mutex_unlock(&bufmgr_gem->lock);
1222 /* Check overflow */
1223 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1226 assert(offset <= bo->size - 4);
1227 assert((write_domain & (write_domain - 1)) == 0);
1229 /* Make sure that we're not adding a reloc to something whose size has
1230 * already been accounted for.
1232 assert(!bo_gem->used_as_reloc_target);
1233 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1234 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1236 /* Flag the target to disallow further relocations in it. */
1237 target_bo_gem->used_as_reloc_target = 1;
1239 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1240 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1241 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1242 target_bo_gem->gem_handle;
1243 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1244 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1245 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1247 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1248 drm_intel_gem_bo_reference(target_bo);
1250 bo_gem->reloc_count++;
1252 pthread_mutex_unlock(&bufmgr_gem->lock);
1258 * Walk the tree of relocations rooted at BO and accumulate the list of
1259 * validations to be performed and update the relocation buffers with
1260 * index values into the validation list.
1263 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1265 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1268 if (bo_gem->relocs == NULL)
1271 for (i = 0; i < bo_gem->reloc_count; i++) {
1272 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1274 /* Continue walking the tree depth-first. */
1275 drm_intel_gem_bo_process_reloc(target_bo);
1277 /* Add the target to the validate list */
1278 drm_intel_add_validate_buffer(target_bo);
1283 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1287 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1288 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1289 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1291 /* Update the buffer offset */
1292 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1293 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1294 bo_gem->gem_handle, bo_gem->name, bo->offset,
1295 (unsigned long long)bufmgr_gem->exec_objects[i].
1297 bo->offset = bufmgr_gem->exec_objects[i].offset;
1303 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1304 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1306 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1307 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1308 struct drm_i915_gem_execbuffer execbuf;
1311 if (bo_gem->has_error)
1314 pthread_mutex_lock(&bufmgr_gem->lock);
1315 /* Update indices and set up the validate list. */
1316 drm_intel_gem_bo_process_reloc(bo);
1318 /* Add the batch buffer to the validation list. There are no
1319 * relocations pointing to it.
1321 drm_intel_add_validate_buffer(bo);
1323 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1324 execbuf.buffer_count = bufmgr_gem->exec_count;
1325 execbuf.batch_start_offset = 0;
1326 execbuf.batch_len = used;
1327 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1328 execbuf.num_cliprects = num_cliprects;
1333 ret = ioctl(bufmgr_gem->fd,
1334 DRM_IOCTL_I915_GEM_EXECBUFFER,
1336 } while (ret != 0 && errno == EINTR);
1340 if (errno == ENOSPC) {
1342 "Execbuffer fails to pin. "
1343 "Estimate: %u. Actual: %u. Available: %u\n",
1344 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1347 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1350 (unsigned int)bufmgr_gem->gtt_size);
1353 drm_intel_update_buffer_offsets(bufmgr_gem);
1355 if (bufmgr_gem->bufmgr.debug)
1356 drm_intel_gem_dump_validation_list(bufmgr_gem);
1358 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1359 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1360 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1362 /* Disconnect the buffer from the validate list */
1363 bo_gem->validate_index = -1;
1364 bufmgr_gem->exec_bos[i] = NULL;
1366 bufmgr_gem->exec_count = 0;
1367 pthread_mutex_unlock(&bufmgr_gem->lock);
1373 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1375 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1376 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1377 struct drm_i915_gem_pin pin;
1380 memset(&pin, 0, sizeof(pin));
1381 pin.handle = bo_gem->gem_handle;
1382 pin.alignment = alignment;
1385 ret = ioctl(bufmgr_gem->fd,
1386 DRM_IOCTL_I915_GEM_PIN,
1388 } while (ret == -1 && errno == EINTR);
1393 bo->offset = pin.offset;
1398 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1400 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1401 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1402 struct drm_i915_gem_unpin unpin;
1405 memset(&unpin, 0, sizeof(unpin));
1406 unpin.handle = bo_gem->gem_handle;
1408 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1416 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1419 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1420 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1421 struct drm_i915_gem_set_tiling set_tiling;
1424 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1427 /* If we're going from non-tiling to tiling, bump fence count */
1428 if (bo_gem->tiling_mode == I915_TILING_NONE)
1429 bo_gem->reloc_tree_fences++;
1431 memset(&set_tiling, 0, sizeof(set_tiling));
1432 set_tiling.handle = bo_gem->gem_handle;
1433 set_tiling.tiling_mode = *tiling_mode;
1434 set_tiling.stride = stride;
1437 ret = ioctl(bufmgr_gem->fd,
1438 DRM_IOCTL_I915_GEM_SET_TILING,
1440 } while (ret == -1 && errno == EINTR);
1442 *tiling_mode = bo_gem->tiling_mode;
1445 bo_gem->tiling_mode = set_tiling.tiling_mode;
1446 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1448 /* If we're going from tiling to non-tiling, drop fence count */
1449 if (bo_gem->tiling_mode == I915_TILING_NONE)
1450 bo_gem->reloc_tree_fences--;
1452 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1454 *tiling_mode = bo_gem->tiling_mode;
1459 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1460 uint32_t * swizzle_mode)
1462 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1464 *tiling_mode = bo_gem->tiling_mode;
1465 *swizzle_mode = bo_gem->swizzle_mode;
1470 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1472 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1473 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1474 struct drm_gem_flink flink;
1477 if (!bo_gem->global_name) {
1478 memset(&flink, 0, sizeof(flink));
1479 flink.handle = bo_gem->gem_handle;
1481 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1484 bo_gem->global_name = flink.name;
1485 bo_gem->reusable = 0;
1488 *name = bo_gem->global_name;
1493 * Enables unlimited caching of buffer objects for reuse.
1495 * This is potentially very memory expensive, as the cache at each bucket
1496 * size is only bounded by how many buffers of that size we've managed to have
1497 * in flight at once.
1500 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1502 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1504 bufmgr_gem->bo_reuse = 1;
1508 * Return the additional aperture space required by the tree of buffer objects
1512 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1514 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1518 if (bo == NULL || bo_gem->included_in_check_aperture)
1522 bo_gem->included_in_check_aperture = 1;
1524 for (i = 0; i < bo_gem->reloc_count; i++)
1526 drm_intel_gem_bo_get_aperture_space(bo_gem->
1527 reloc_target_bo[i]);
1533 * Count the number of buffers in this list that need a fence reg
1535 * If the count is greater than the number of available regs, we'll have
1536 * to ask the caller to resubmit a batch with fewer tiled buffers.
1538 * This function over-counts if the same buffer is used multiple times.
1541 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1544 unsigned int total = 0;
1546 for (i = 0; i < count; i++) {
1547 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1552 total += bo_gem->reloc_tree_fences;
1558 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1559 * for the next drm_intel_bufmgr_check_aperture_space() call.
1562 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1564 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1567 if (bo == NULL || !bo_gem->included_in_check_aperture)
1570 bo_gem->included_in_check_aperture = 0;
1572 for (i = 0; i < bo_gem->reloc_count; i++)
1573 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1574 reloc_target_bo[i]);
1578 * Return a conservative estimate for the amount of aperture required
1579 * for a collection of buffers. This may double-count some buffers.
1582 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1585 unsigned int total = 0;
1587 for (i = 0; i < count; i++) {
1588 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1590 total += bo_gem->reloc_tree_size;
1596 * Return the amount of aperture needed for a collection of buffers.
1597 * This avoids double counting any buffers, at the cost of looking
1598 * at every buffer in the set.
1601 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1604 unsigned int total = 0;
1606 for (i = 0; i < count; i++) {
1607 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1608 /* For the first buffer object in the array, we get an
1609 * accurate count back for its reloc_tree size (since nothing
1610 * had been flagged as being counted yet). We can save that
1611 * value out as a more conservative reloc_tree_size that
1612 * avoids double-counting target buffers. Since the first
1613 * buffer happens to usually be the batch buffer in our
1614 * callers, this can pull us back from doing the tree
1615 * walk on every new batch emit.
1618 drm_intel_bo_gem *bo_gem =
1619 (drm_intel_bo_gem *) bo_array[i];
1620 bo_gem->reloc_tree_size = total;
1624 for (i = 0; i < count; i++)
1625 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1630 * Return -1 if the batchbuffer should be flushed before attempting to
1631 * emit rendering referencing the buffers pointed to by bo_array.
1633 * This is required because if we try to emit a batchbuffer with relocations
1634 * to a tree of buffers that won't simultaneously fit in the aperture,
1635 * the rendering will return an error at a point where the software is not
1636 * prepared to recover from it.
1638 * However, we also want to emit the batchbuffer significantly before we reach
1639 * the limit, as a series of batchbuffers each of which references buffers
1640 * covering almost all of the aperture means that at each emit we end up
1641 * waiting to evict a buffer from the last rendering, and we get synchronous
1642 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1643 * get better parallelism.
1646 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1648 drm_intel_bufmgr_gem *bufmgr_gem =
1649 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1650 unsigned int total = 0;
1651 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1654 /* Check for fence reg constraints if necessary */
1655 if (bufmgr_gem->available_fences) {
1656 total_fences = drm_intel_gem_total_fences(bo_array, count);
1657 if (total_fences > bufmgr_gem->available_fences)
1661 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1663 if (total > threshold)
1664 total = drm_intel_gem_compute_batch_space(bo_array, count);
1666 if (total > threshold) {
1667 DBG("check_space: overflowed available aperture, "
1669 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1672 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1673 (int)bufmgr_gem->gtt_size / 1024);
1679 * Disable buffer reuse for objects which are shared with the kernel
1680 * as scanout buffers
1683 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1685 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1687 bo_gem->reusable = 0;
1692 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1694 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1697 for (i = 0; i < bo_gem->reloc_count; i++) {
1698 if (bo_gem->reloc_target_bo[i] == target_bo)
1700 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i],
1708 /** Return true if target_bo is referenced by bo's relocation tree. */
1710 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1712 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1714 if (bo == NULL || target_bo == NULL)
1716 if (target_bo_gem->used_as_reloc_target)
1717 return _drm_intel_gem_bo_references(bo, target_bo);
1722 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1723 * and manage map buffer objections.
1725 * \param fd File descriptor of the opened DRM device.
1728 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1730 drm_intel_bufmgr_gem *bufmgr_gem;
1731 struct drm_i915_gem_get_aperture aperture;
1732 drm_i915_getparam_t gp;
1736 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1737 bufmgr_gem->fd = fd;
1739 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1744 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1747 bufmgr_gem->gtt_size = aperture.aper_available_size;
1749 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1751 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1752 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1753 "May lead to reduced performance or incorrect "
1755 (int)bufmgr_gem->gtt_size / 1024);
1758 gp.param = I915_PARAM_CHIPSET_ID;
1759 gp.value = &bufmgr_gem->pci_device;
1760 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1762 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1763 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1766 if (!IS_I965G(bufmgr_gem)) {
1767 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1768 gp.value = &bufmgr_gem->available_fences;
1769 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1771 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1773 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1775 bufmgr_gem->available_fences = 0;
1779 /* Let's go with one relocation per every 2 dwords (but round down a bit
1780 * since a power of two will mean an extra page allocation for the reloc
1783 * Every 4 was too few for the blender benchmark.
1785 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1787 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1788 bufmgr_gem->bufmgr.bo_alloc_for_render =
1789 drm_intel_gem_bo_alloc_for_render;
1790 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
1791 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1792 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1793 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1794 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1795 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1796 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1797 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1798 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1799 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1800 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1801 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1802 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1803 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1804 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1805 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1806 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
1807 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1808 bufmgr_gem->bufmgr.debug = 0;
1809 bufmgr_gem->bufmgr.check_aperture_space =
1810 drm_intel_gem_check_aperture_space;
1811 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1812 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
1813 drm_intel_gem_get_pipe_from_crtc_id;
1814 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1816 /* Initialize the linked lists for BO reuse cache. */
1817 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1818 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1819 bufmgr_gem->cache_bucket[i].size = size;
1822 return &bufmgr_gem->bufmgr;