1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
101 int available_fences;
104 unsigned int has_bsd : 1;
105 unsigned int has_blt : 1;
106 unsigned int has_relaxed_fencing : 1;
107 unsigned int bo_reuse : 1;
109 } drm_intel_bufmgr_gem;
111 #define DRM_INTEL_RELOC_FENCE (1<<0)
113 typedef struct _drm_intel_reloc_target_info {
116 } drm_intel_reloc_target;
118 struct _drm_intel_bo_gem {
126 * Kenel-assigned global name for this object
128 unsigned int global_name;
129 drmMMListHead name_list;
132 * Index of the buffer within the validation list while preparing a
133 * batchbuffer execution.
138 * Current tiling mode
140 uint32_t tiling_mode;
141 uint32_t swizzle_mode;
142 unsigned long stride;
146 /** Array passed to the DRM containing relocation information. */
147 struct drm_i915_gem_relocation_entry *relocs;
149 * Array of info structs corresponding to relocs[i].target_handle etc
151 drm_intel_reloc_target *reloc_target_info;
152 /** Number of entries in relocs */
154 /** Mapped address for the buffer, saved across map/unmap cycles */
156 /** GTT virtual address for the buffer, saved across map/unmap cycles */
163 * Boolean of whether this BO and its children have been included in
164 * the current drm_intel_bufmgr_check_aperture_space() total.
166 char included_in_check_aperture;
169 * Boolean of whether this buffer has been used as a relocation
170 * target and had its size accounted for, and thus can't have any
171 * further relocations added to it.
173 char used_as_reloc_target;
176 * Boolean of whether we have encountered an error whilst building the relocation tree.
181 * Boolean of whether this buffer can be re-used
186 * Size in bytes of this buffer and its relocation descendents.
188 * Used to avoid costly tree walking in
189 * drm_intel_bufmgr_check_aperture in the common case.
194 * Number of potential fence registers required by this buffer and its
197 int reloc_tree_fences;
201 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
204 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
207 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
208 uint32_t * swizzle_mode);
211 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
212 uint32_t tiling_mode,
215 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
218 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
220 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
223 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
224 uint32_t *tiling_mode)
226 unsigned long min_size, max_size;
229 if (*tiling_mode == I915_TILING_NONE)
232 /* 965+ just need multiples of page size for tiling */
233 if (bufmgr_gem->gen >= 4)
234 return ROUND_UP_TO(size, 4096);
236 /* Older chips need powers of two, of at least 512k or 1M */
237 if (bufmgr_gem->gen == 3) {
238 min_size = 1024*1024;
239 max_size = 128*1024*1024;
242 max_size = 64*1024*1024;
245 if (size > max_size) {
246 *tiling_mode = I915_TILING_NONE;
250 /* Do we need to allocate every page for the fence? */
251 if (bufmgr_gem->has_relaxed_fencing)
252 return ROUND_UP_TO(size, 4096);
254 for (i = min_size; i < size; i <<= 1)
261 * Round a given pitch up to the minimum required for X tiling on a
262 * given chip. We use 512 as the minimum to allow for a later tiling
266 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
267 unsigned long pitch, uint32_t *tiling_mode)
269 unsigned long tile_width;
272 /* If untiled, then just align it so that we can do rendering
273 * to it with the 3D engine.
275 if (*tiling_mode == I915_TILING_NONE)
276 return ALIGN(pitch, 64);
278 if (*tiling_mode == I915_TILING_X)
283 /* 965 is flexible */
284 if (bufmgr_gem->gen >= 4)
285 return ROUND_UP_TO(pitch, tile_width);
287 /* The older hardware has a maximum pitch of 8192 with tiled
288 * surfaces, so fallback to untiled if it's too large.
291 *tiling_mode = I915_TILING_NONE;
292 return ALIGN(pitch, 64);
295 /* Pre-965 needs power of two tile width */
296 for (i = tile_width; i < pitch; i <<= 1)
302 static struct drm_intel_gem_bo_bucket *
303 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
308 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
309 struct drm_intel_gem_bo_bucket *bucket =
310 &bufmgr_gem->cache_bucket[i];
311 if (bucket->size >= size) {
320 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
324 for (i = 0; i < bufmgr_gem->exec_count; i++) {
325 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
326 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
328 if (bo_gem->relocs == NULL) {
329 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
334 for (j = 0; j < bo_gem->reloc_count; j++) {
335 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
336 drm_intel_bo_gem *target_gem =
337 (drm_intel_bo_gem *) target_bo;
339 DBG("%2d: %d (%s)@0x%08llx -> "
340 "%d (%s)@0x%08lx + 0x%08x\n",
342 bo_gem->gem_handle, bo_gem->name,
343 (unsigned long long)bo_gem->relocs[j].offset,
344 target_gem->gem_handle,
347 bo_gem->relocs[j].delta);
353 drm_intel_gem_bo_reference(drm_intel_bo *bo)
355 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
357 atomic_inc(&bo_gem->refcount);
361 * Adds the given buffer to the list of buffers to be validated (moved into the
362 * appropriate memory type) with the next batch submission.
364 * If a buffer is validated multiple times in a batch submission, it ends up
365 * with the intersection of the memory type flags and the union of the
369 drm_intel_add_validate_buffer(drm_intel_bo *bo)
371 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
372 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
375 if (bo_gem->validate_index != -1)
378 /* Extend the array of validation entries as necessary. */
379 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
380 int new_size = bufmgr_gem->exec_size * 2;
385 bufmgr_gem->exec_objects =
386 realloc(bufmgr_gem->exec_objects,
387 sizeof(*bufmgr_gem->exec_objects) * new_size);
388 bufmgr_gem->exec_bos =
389 realloc(bufmgr_gem->exec_bos,
390 sizeof(*bufmgr_gem->exec_bos) * new_size);
391 bufmgr_gem->exec_size = new_size;
394 index = bufmgr_gem->exec_count;
395 bo_gem->validate_index = index;
396 /* Fill in array entry */
397 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
398 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
399 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
400 bufmgr_gem->exec_objects[index].alignment = 0;
401 bufmgr_gem->exec_objects[index].offset = 0;
402 bufmgr_gem->exec_bos[index] = bo;
403 bufmgr_gem->exec_count++;
407 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
409 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
410 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
413 if (bo_gem->validate_index != -1) {
415 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
416 EXEC_OBJECT_NEEDS_FENCE;
420 /* Extend the array of validation entries as necessary. */
421 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
422 int new_size = bufmgr_gem->exec_size * 2;
427 bufmgr_gem->exec2_objects =
428 realloc(bufmgr_gem->exec2_objects,
429 sizeof(*bufmgr_gem->exec2_objects) * new_size);
430 bufmgr_gem->exec_bos =
431 realloc(bufmgr_gem->exec_bos,
432 sizeof(*bufmgr_gem->exec_bos) * new_size);
433 bufmgr_gem->exec_size = new_size;
436 index = bufmgr_gem->exec_count;
437 bo_gem->validate_index = index;
438 /* Fill in array entry */
439 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
440 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
441 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
442 bufmgr_gem->exec2_objects[index].alignment = 0;
443 bufmgr_gem->exec2_objects[index].offset = 0;
444 bufmgr_gem->exec_bos[index] = bo;
445 bufmgr_gem->exec2_objects[index].flags = 0;
446 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
447 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
449 bufmgr_gem->exec2_objects[index].flags |=
450 EXEC_OBJECT_NEEDS_FENCE;
452 bufmgr_gem->exec_count++;
455 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
459 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
460 drm_intel_bo_gem *bo_gem)
464 assert(!bo_gem->used_as_reloc_target);
466 /* The older chipsets are far-less flexible in terms of tiling,
467 * and require tiled buffer to be size aligned in the aperture.
468 * This means that in the worst possible case we will need a hole
469 * twice as large as the object in order for it to fit into the
470 * aperture. Optimal packing is for wimps.
472 size = bo_gem->bo.size;
473 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
476 if (bufmgr_gem->has_relaxed_fencing) {
477 if (bufmgr_gem->gen == 3)
478 min_size = 1024*1024;
482 while (min_size < size)
487 /* Account for worst-case alignment. */
491 bo_gem->reloc_tree_size = size;
495 drm_intel_setup_reloc_list(drm_intel_bo *bo)
497 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
498 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
499 unsigned int max_relocs = bufmgr_gem->max_relocs;
501 if (bo->size / 4 < max_relocs)
502 max_relocs = bo->size / 4;
504 bo_gem->relocs = malloc(max_relocs *
505 sizeof(struct drm_i915_gem_relocation_entry));
506 bo_gem->reloc_target_info = malloc(max_relocs *
507 sizeof(drm_intel_reloc_target));
508 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
509 bo_gem->has_error = 1;
511 free (bo_gem->relocs);
512 bo_gem->relocs = NULL;
514 free (bo_gem->reloc_target_info);
515 bo_gem->reloc_target_info = NULL;
524 drm_intel_gem_bo_busy(drm_intel_bo *bo)
526 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
527 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
528 struct drm_i915_gem_busy busy;
531 memset(&busy, 0, sizeof(busy));
532 busy.handle = bo_gem->gem_handle;
534 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
536 return (ret == 0 && busy.busy);
540 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
541 drm_intel_bo_gem *bo_gem, int state)
543 struct drm_i915_gem_madvise madv;
545 madv.handle = bo_gem->gem_handle;
548 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
550 return madv.retained;
554 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
556 return drm_intel_gem_bo_madvise_internal
557 ((drm_intel_bufmgr_gem *) bo->bufmgr,
558 (drm_intel_bo_gem *) bo,
562 /* drop the oldest entries that have been purged by the kernel */
564 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
565 struct drm_intel_gem_bo_bucket *bucket)
567 while (!DRMLISTEMPTY(&bucket->head)) {
568 drm_intel_bo_gem *bo_gem;
570 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
571 bucket->head.next, head);
572 if (drm_intel_gem_bo_madvise_internal
573 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
576 DRMLISTDEL(&bo_gem->head);
577 drm_intel_gem_bo_free(&bo_gem->bo);
581 static drm_intel_bo *
582 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
586 uint32_t tiling_mode,
587 unsigned long stride)
589 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
590 drm_intel_bo_gem *bo_gem;
591 unsigned int page_size = getpagesize();
593 struct drm_intel_gem_bo_bucket *bucket;
594 int alloc_from_cache;
595 unsigned long bo_size;
598 if (flags & BO_ALLOC_FOR_RENDER)
601 /* Round the allocated size up to a power of two number of pages. */
602 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
604 /* If we don't have caching at this size, don't actually round the
607 if (bucket == NULL) {
609 if (bo_size < page_size)
612 bo_size = bucket->size;
615 pthread_mutex_lock(&bufmgr_gem->lock);
616 /* Get a buffer out of the cache if available */
618 alloc_from_cache = 0;
619 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
621 /* Allocate new render-target BOs from the tail (MRU)
622 * of the list, as it will likely be hot in the GPU
623 * cache and in the aperture for us.
625 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
626 bucket->head.prev, head);
627 DRMLISTDEL(&bo_gem->head);
628 alloc_from_cache = 1;
630 /* For non-render-target BOs (where we're probably
631 * going to map it first thing in order to fill it
632 * with data), check if the last BO in the cache is
633 * unbusy, and only reuse in that case. Otherwise,
634 * allocating a new buffer is probably faster than
635 * waiting for the GPU to finish.
637 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
638 bucket->head.next, head);
639 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
640 alloc_from_cache = 1;
641 DRMLISTDEL(&bo_gem->head);
645 if (alloc_from_cache) {
646 if (!drm_intel_gem_bo_madvise_internal
647 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
648 drm_intel_gem_bo_free(&bo_gem->bo);
649 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
654 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
657 drm_intel_gem_bo_free(&bo_gem->bo);
662 pthread_mutex_unlock(&bufmgr_gem->lock);
664 if (!alloc_from_cache) {
665 struct drm_i915_gem_create create;
667 bo_gem = calloc(1, sizeof(*bo_gem));
671 bo_gem->bo.size = bo_size;
672 memset(&create, 0, sizeof(create));
673 create.size = bo_size;
675 ret = drmIoctl(bufmgr_gem->fd,
676 DRM_IOCTL_I915_GEM_CREATE,
678 bo_gem->gem_handle = create.handle;
679 bo_gem->bo.handle = bo_gem->gem_handle;
684 bo_gem->bo.bufmgr = bufmgr;
686 bo_gem->tiling_mode = I915_TILING_NONE;
687 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
690 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
693 drm_intel_gem_bo_free(&bo_gem->bo);
697 DRMINITLISTHEAD(&bo_gem->name_list);
701 atomic_set(&bo_gem->refcount, 1);
702 bo_gem->validate_index = -1;
703 bo_gem->reloc_tree_fences = 0;
704 bo_gem->used_as_reloc_target = 0;
705 bo_gem->has_error = 0;
706 bo_gem->reusable = 1;
708 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
710 DBG("bo_create: buf %d (%s) %ldb\n",
711 bo_gem->gem_handle, bo_gem->name, size);
716 static drm_intel_bo *
717 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
720 unsigned int alignment)
722 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
724 I915_TILING_NONE, 0);
727 static drm_intel_bo *
728 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
731 unsigned int alignment)
733 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
734 I915_TILING_NONE, 0);
737 static drm_intel_bo *
738 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
739 int x, int y, int cpp, uint32_t *tiling_mode,
740 unsigned long *pitch, unsigned long flags)
742 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
743 unsigned long size, stride;
747 unsigned long aligned_y, height_alignment;
749 tiling = *tiling_mode;
751 /* If we're tiled, our allocations are in 8 or 32-row blocks,
752 * so failure to align our height means that we won't allocate
755 * If we're untiled, we still have to align to 2 rows high
756 * because the data port accesses 2x2 blocks even if the
757 * bottom row isn't to be rendered, so failure to align means
758 * we could walk off the end of the GTT and fault. This is
759 * documented on 965, and may be the case on older chipsets
760 * too so we try to be careful.
763 height_alignment = 2;
765 if (tiling == I915_TILING_X)
766 height_alignment = 8;
767 else if (tiling == I915_TILING_Y)
768 height_alignment = 32;
769 /* i8xx has a interleaved 2-row tile layout */
770 if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
771 height_alignment *= 2;
772 aligned_y = ALIGN(y, height_alignment);
775 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
776 size = stride * aligned_y;
777 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
778 } while (*tiling_mode != tiling);
781 if (tiling == I915_TILING_NONE)
784 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
789 * Returns a drm_intel_bo wrapping the given buffer object handle.
791 * This can be used when one application needs to pass a buffer object
795 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
799 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
800 drm_intel_bo_gem *bo_gem;
802 struct drm_gem_open open_arg;
803 struct drm_i915_gem_get_tiling get_tiling;
806 /* At the moment most applications only have a few named bo.
807 * For instance, in a DRI client only the render buffers passed
808 * between X and the client are named. And since X returns the
809 * alternating names for the front/back buffer a linear search
810 * provides a sufficiently fast match.
812 for (list = bufmgr_gem->named.next;
813 list != &bufmgr_gem->named;
815 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
816 if (bo_gem->global_name == handle) {
817 drm_intel_gem_bo_reference(&bo_gem->bo);
822 bo_gem = calloc(1, sizeof(*bo_gem));
826 memset(&open_arg, 0, sizeof(open_arg));
827 open_arg.name = handle;
828 ret = drmIoctl(bufmgr_gem->fd,
832 DBG("Couldn't reference %s handle 0x%08x: %s\n",
833 name, handle, strerror(errno));
837 bo_gem->bo.size = open_arg.size;
838 bo_gem->bo.offset = 0;
839 bo_gem->bo.virtual = NULL;
840 bo_gem->bo.bufmgr = bufmgr;
842 atomic_set(&bo_gem->refcount, 1);
843 bo_gem->validate_index = -1;
844 bo_gem->gem_handle = open_arg.handle;
845 bo_gem->bo.handle = open_arg.handle;
846 bo_gem->global_name = handle;
847 bo_gem->reusable = 0;
849 memset(&get_tiling, 0, sizeof(get_tiling));
850 get_tiling.handle = bo_gem->gem_handle;
851 ret = drmIoctl(bufmgr_gem->fd,
852 DRM_IOCTL_I915_GEM_GET_TILING,
855 drm_intel_gem_bo_unreference(&bo_gem->bo);
858 bo_gem->tiling_mode = get_tiling.tiling_mode;
859 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
860 /* XXX stride is unknown */
861 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
863 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
864 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
870 drm_intel_gem_bo_free(drm_intel_bo *bo)
872 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
873 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
874 struct drm_gem_close close;
877 if (bo_gem->mem_virtual)
878 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
879 if (bo_gem->gtt_virtual)
880 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
882 /* Close this object */
883 memset(&close, 0, sizeof(close));
884 close.handle = bo_gem->gem_handle;
885 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
887 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
888 bo_gem->gem_handle, bo_gem->name, strerror(errno));
893 /** Frees all cached buffers significantly older than @time. */
895 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
899 if (bufmgr_gem->time == time)
902 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
903 struct drm_intel_gem_bo_bucket *bucket =
904 &bufmgr_gem->cache_bucket[i];
906 while (!DRMLISTEMPTY(&bucket->head)) {
907 drm_intel_bo_gem *bo_gem;
909 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
910 bucket->head.next, head);
911 if (time - bo_gem->free_time <= 1)
914 DRMLISTDEL(&bo_gem->head);
916 drm_intel_gem_bo_free(&bo_gem->bo);
920 bufmgr_gem->time = time;
924 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
926 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
927 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
928 struct drm_intel_gem_bo_bucket *bucket;
931 /* Unreference all the target buffers */
932 for (i = 0; i < bo_gem->reloc_count; i++) {
933 if (bo_gem->reloc_target_info[i].bo != bo) {
934 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
935 reloc_target_info[i].bo,
939 bo_gem->reloc_count = 0;
940 bo_gem->used_as_reloc_target = 0;
942 DBG("bo_unreference final: %d (%s)\n",
943 bo_gem->gem_handle, bo_gem->name);
945 /* release memory associated with this object */
946 if (bo_gem->reloc_target_info) {
947 free(bo_gem->reloc_target_info);
948 bo_gem->reloc_target_info = NULL;
950 if (bo_gem->relocs) {
951 free(bo_gem->relocs);
952 bo_gem->relocs = NULL;
955 DRMLISTDEL(&bo_gem->name_list);
957 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
958 /* Put the buffer into our internal cache for reuse if we can. */
959 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
960 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
961 I915_MADV_DONTNEED)) {
962 bo_gem->free_time = time;
965 bo_gem->validate_index = -1;
967 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
969 drm_intel_gem_bo_free(bo);
973 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
976 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
978 assert(atomic_read(&bo_gem->refcount) > 0);
979 if (atomic_dec_and_test(&bo_gem->refcount))
980 drm_intel_gem_bo_unreference_final(bo, time);
983 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
985 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
987 assert(atomic_read(&bo_gem->refcount) > 0);
988 if (atomic_dec_and_test(&bo_gem->refcount)) {
989 drm_intel_bufmgr_gem *bufmgr_gem =
990 (drm_intel_bufmgr_gem *) bo->bufmgr;
991 struct timespec time;
993 clock_gettime(CLOCK_MONOTONIC, &time);
995 pthread_mutex_lock(&bufmgr_gem->lock);
996 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
997 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
998 pthread_mutex_unlock(&bufmgr_gem->lock);
1002 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1004 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1005 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1006 struct drm_i915_gem_set_domain set_domain;
1009 pthread_mutex_lock(&bufmgr_gem->lock);
1011 /* Allow recursive mapping. Mesa may recursively map buffers with
1012 * nested display loops.
1014 if (!bo_gem->mem_virtual) {
1015 struct drm_i915_gem_mmap mmap_arg;
1017 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1019 memset(&mmap_arg, 0, sizeof(mmap_arg));
1020 mmap_arg.handle = bo_gem->gem_handle;
1021 mmap_arg.offset = 0;
1022 mmap_arg.size = bo->size;
1023 ret = drmIoctl(bufmgr_gem->fd,
1024 DRM_IOCTL_I915_GEM_MMAP,
1028 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1029 __FILE__, __LINE__, bo_gem->gem_handle,
1030 bo_gem->name, strerror(errno));
1031 pthread_mutex_unlock(&bufmgr_gem->lock);
1034 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1036 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1037 bo_gem->mem_virtual);
1038 bo->virtual = bo_gem->mem_virtual;
1040 set_domain.handle = bo_gem->gem_handle;
1041 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1043 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1045 set_domain.write_domain = 0;
1046 ret = drmIoctl(bufmgr_gem->fd,
1047 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1050 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1051 __FILE__, __LINE__, bo_gem->gem_handle,
1055 pthread_mutex_unlock(&bufmgr_gem->lock);
1060 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1062 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1063 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1064 struct drm_i915_gem_set_domain set_domain;
1067 pthread_mutex_lock(&bufmgr_gem->lock);
1069 /* Get a mapping of the buffer if we haven't before. */
1070 if (bo_gem->gtt_virtual == NULL) {
1071 struct drm_i915_gem_mmap_gtt mmap_arg;
1073 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1076 memset(&mmap_arg, 0, sizeof(mmap_arg));
1077 mmap_arg.handle = bo_gem->gem_handle;
1079 /* Get the fake offset back... */
1080 ret = drmIoctl(bufmgr_gem->fd,
1081 DRM_IOCTL_I915_GEM_MMAP_GTT,
1085 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1087 bo_gem->gem_handle, bo_gem->name,
1089 pthread_mutex_unlock(&bufmgr_gem->lock);
1094 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1095 MAP_SHARED, bufmgr_gem->fd,
1097 if (bo_gem->gtt_virtual == MAP_FAILED) {
1098 bo_gem->gtt_virtual = NULL;
1100 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1102 bo_gem->gem_handle, bo_gem->name,
1104 pthread_mutex_unlock(&bufmgr_gem->lock);
1109 bo->virtual = bo_gem->gtt_virtual;
1111 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1112 bo_gem->gtt_virtual);
1114 /* Now move it to the GTT domain so that the CPU caches are flushed */
1115 set_domain.handle = bo_gem->gem_handle;
1116 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1117 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1118 ret = drmIoctl(bufmgr_gem->fd,
1119 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1122 DBG("%s:%d: Error setting domain %d: %s\n",
1123 __FILE__, __LINE__, bo_gem->gem_handle,
1127 pthread_mutex_unlock(&bufmgr_gem->lock);
1132 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1134 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1140 pthread_mutex_lock(&bufmgr_gem->lock);
1142 pthread_mutex_unlock(&bufmgr_gem->lock);
1147 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1149 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1150 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1151 struct drm_i915_gem_sw_finish sw_finish;
1157 pthread_mutex_lock(&bufmgr_gem->lock);
1159 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1160 * results show up in a timely manner.
1162 sw_finish.handle = bo_gem->gem_handle;
1163 ret = drmIoctl(bufmgr_gem->fd,
1164 DRM_IOCTL_I915_GEM_SW_FINISH,
1166 ret = ret == -1 ? -errno : 0;
1169 pthread_mutex_unlock(&bufmgr_gem->lock);
1175 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1176 unsigned long size, const void *data)
1178 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1179 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1180 struct drm_i915_gem_pwrite pwrite;
1183 memset(&pwrite, 0, sizeof(pwrite));
1184 pwrite.handle = bo_gem->gem_handle;
1185 pwrite.offset = offset;
1187 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1188 ret = drmIoctl(bufmgr_gem->fd,
1189 DRM_IOCTL_I915_GEM_PWRITE,
1193 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1194 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1195 (int)size, strerror(errno));
1202 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1204 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1205 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1208 get_pipe_from_crtc_id.crtc_id = crtc_id;
1209 ret = drmIoctl(bufmgr_gem->fd,
1210 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1211 &get_pipe_from_crtc_id);
1213 /* We return -1 here to signal that we don't
1214 * know which pipe is associated with this crtc.
1215 * This lets the caller know that this information
1216 * isn't available; using the wrong pipe for
1217 * vblank waiting can cause the chipset to lock up
1222 return get_pipe_from_crtc_id.pipe;
1226 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1227 unsigned long size, void *data)
1229 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1230 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1231 struct drm_i915_gem_pread pread;
1234 memset(&pread, 0, sizeof(pread));
1235 pread.handle = bo_gem->gem_handle;
1236 pread.offset = offset;
1238 pread.data_ptr = (uint64_t) (uintptr_t) data;
1239 ret = drmIoctl(bufmgr_gem->fd,
1240 DRM_IOCTL_I915_GEM_PREAD,
1244 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1245 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1246 (int)size, strerror(errno));
1252 /** Waits for all GPU rendering with the object to have completed. */
1254 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1256 drm_intel_gem_bo_start_gtt_access(bo, 1);
1260 * Sets the object to the GTT read and possibly write domain, used by the X
1261 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1263 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1264 * can do tiled pixmaps this way.
1267 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1269 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1270 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1271 struct drm_i915_gem_set_domain set_domain;
1274 set_domain.handle = bo_gem->gem_handle;
1275 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1276 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1277 ret = drmIoctl(bufmgr_gem->fd,
1278 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1281 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1282 __FILE__, __LINE__, bo_gem->gem_handle,
1283 set_domain.read_domains, set_domain.write_domain,
1289 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1291 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1294 free(bufmgr_gem->exec2_objects);
1295 free(bufmgr_gem->exec_objects);
1296 free(bufmgr_gem->exec_bos);
1298 pthread_mutex_destroy(&bufmgr_gem->lock);
1300 /* Free any cached buffer objects we were going to reuse */
1301 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1302 struct drm_intel_gem_bo_bucket *bucket =
1303 &bufmgr_gem->cache_bucket[i];
1304 drm_intel_bo_gem *bo_gem;
1306 while (!DRMLISTEMPTY(&bucket->head)) {
1307 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1308 bucket->head.next, head);
1309 DRMLISTDEL(&bo_gem->head);
1311 drm_intel_gem_bo_free(&bo_gem->bo);
1319 * Adds the target buffer to the validation list and adds the relocation
1320 * to the reloc_buffer's relocation list.
1322 * The relocation entry at the given offset must already contain the
1323 * precomputed relocation value, because the kernel will optimize out
1324 * the relocation entry write when the buffer hasn't moved from the
1325 * last known offset in target_bo.
1328 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1329 drm_intel_bo *target_bo, uint32_t target_offset,
1330 uint32_t read_domains, uint32_t write_domain,
1333 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1334 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1335 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1338 if (bo_gem->has_error)
1341 if (target_bo_gem->has_error) {
1342 bo_gem->has_error = 1;
1346 /* We never use HW fences for rendering on 965+ */
1347 if (bufmgr_gem->gen >= 4)
1350 fenced_command = need_fence;
1351 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1354 /* Create a new relocation list if needed */
1355 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1358 /* Check overflow */
1359 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1362 assert(offset <= bo->size - 4);
1363 assert((write_domain & (write_domain - 1)) == 0);
1365 /* Make sure that we're not adding a reloc to something whose size has
1366 * already been accounted for.
1368 assert(!bo_gem->used_as_reloc_target);
1369 if (target_bo_gem != bo_gem) {
1370 target_bo_gem->used_as_reloc_target = 1;
1371 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1373 /* An object needing a fence is a tiled buffer, so it won't have
1374 * relocs to other buffers.
1377 target_bo_gem->reloc_tree_fences = 1;
1378 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1380 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1381 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1382 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1383 target_bo_gem->gem_handle;
1384 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1385 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1386 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1388 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1389 if (target_bo != bo)
1390 drm_intel_gem_bo_reference(target_bo);
1392 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1393 DRM_INTEL_RELOC_FENCE;
1395 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1397 bo_gem->reloc_count++;
1403 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1404 drm_intel_bo *target_bo, uint32_t target_offset,
1405 uint32_t read_domains, uint32_t write_domain)
1407 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1409 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1410 read_domains, write_domain,
1411 !bufmgr_gem->fenced_relocs);
1415 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1416 drm_intel_bo *target_bo,
1417 uint32_t target_offset,
1418 uint32_t read_domains, uint32_t write_domain)
1420 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1421 read_domains, write_domain, 1);
1425 * Walk the tree of relocations rooted at BO and accumulate the list of
1426 * validations to be performed and update the relocation buffers with
1427 * index values into the validation list.
1430 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1432 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1435 if (bo_gem->relocs == NULL)
1438 for (i = 0; i < bo_gem->reloc_count; i++) {
1439 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1441 if (target_bo == bo)
1444 /* Continue walking the tree depth-first. */
1445 drm_intel_gem_bo_process_reloc(target_bo);
1447 /* Add the target to the validate list */
1448 drm_intel_add_validate_buffer(target_bo);
1453 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1455 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1458 if (bo_gem->relocs == NULL)
1461 for (i = 0; i < bo_gem->reloc_count; i++) {
1462 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1465 if (target_bo == bo)
1468 /* Continue walking the tree depth-first. */
1469 drm_intel_gem_bo_process_reloc2(target_bo);
1471 need_fence = (bo_gem->reloc_target_info[i].flags &
1472 DRM_INTEL_RELOC_FENCE);
1474 /* Add the target to the validate list */
1475 drm_intel_add_validate_buffer2(target_bo, need_fence);
1481 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1485 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1486 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1487 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1489 /* Update the buffer offset */
1490 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1491 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1492 bo_gem->gem_handle, bo_gem->name, bo->offset,
1493 (unsigned long long)bufmgr_gem->exec_objects[i].
1495 bo->offset = bufmgr_gem->exec_objects[i].offset;
1501 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1505 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1506 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1507 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1509 /* Update the buffer offset */
1510 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1511 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1512 bo_gem->gem_handle, bo_gem->name, bo->offset,
1513 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1514 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1520 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1521 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1523 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1524 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1525 struct drm_i915_gem_execbuffer execbuf;
1528 if (bo_gem->has_error)
1531 pthread_mutex_lock(&bufmgr_gem->lock);
1532 /* Update indices and set up the validate list. */
1533 drm_intel_gem_bo_process_reloc(bo);
1535 /* Add the batch buffer to the validation list. There are no
1536 * relocations pointing to it.
1538 drm_intel_add_validate_buffer(bo);
1540 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1541 execbuf.buffer_count = bufmgr_gem->exec_count;
1542 execbuf.batch_start_offset = 0;
1543 execbuf.batch_len = used;
1544 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1545 execbuf.num_cliprects = num_cliprects;
1549 ret = drmIoctl(bufmgr_gem->fd,
1550 DRM_IOCTL_I915_GEM_EXECBUFFER,
1554 if (errno == ENOSPC) {
1555 DBG("Execbuffer fails to pin. "
1556 "Estimate: %u. Actual: %u. Available: %u\n",
1557 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1560 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1563 (unsigned int)bufmgr_gem->gtt_size);
1566 drm_intel_update_buffer_offsets(bufmgr_gem);
1568 if (bufmgr_gem->bufmgr.debug)
1569 drm_intel_gem_dump_validation_list(bufmgr_gem);
1571 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1572 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1573 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1575 /* Disconnect the buffer from the validate list */
1576 bo_gem->validate_index = -1;
1577 bufmgr_gem->exec_bos[i] = NULL;
1579 bufmgr_gem->exec_count = 0;
1580 pthread_mutex_unlock(&bufmgr_gem->lock);
1586 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1587 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1590 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1591 struct drm_i915_gem_execbuffer2 execbuf;
1594 switch (flags & 0x7) {
1598 if (!bufmgr_gem->has_blt)
1602 if (!bufmgr_gem->has_bsd)
1605 case I915_EXEC_RENDER:
1606 case I915_EXEC_DEFAULT:
1610 pthread_mutex_lock(&bufmgr_gem->lock);
1611 /* Update indices and set up the validate list. */
1612 drm_intel_gem_bo_process_reloc2(bo);
1614 /* Add the batch buffer to the validation list. There are no relocations
1617 drm_intel_add_validate_buffer2(bo, 0);
1619 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1620 execbuf.buffer_count = bufmgr_gem->exec_count;
1621 execbuf.batch_start_offset = 0;
1622 execbuf.batch_len = used;
1623 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1624 execbuf.num_cliprects = num_cliprects;
1627 execbuf.flags = flags;
1631 ret = drmIoctl(bufmgr_gem->fd,
1632 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1636 if (ret == -ENOSPC) {
1637 DBG("Execbuffer fails to pin. "
1638 "Estimate: %u. Actual: %u. Available: %u\n",
1639 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1640 bufmgr_gem->exec_count),
1641 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1642 bufmgr_gem->exec_count),
1643 (unsigned int) bufmgr_gem->gtt_size);
1646 drm_intel_update_buffer_offsets2(bufmgr_gem);
1648 if (bufmgr_gem->bufmgr.debug)
1649 drm_intel_gem_dump_validation_list(bufmgr_gem);
1651 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1652 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1653 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1655 /* Disconnect the buffer from the validate list */
1656 bo_gem->validate_index = -1;
1657 bufmgr_gem->exec_bos[i] = NULL;
1659 bufmgr_gem->exec_count = 0;
1660 pthread_mutex_unlock(&bufmgr_gem->lock);
1666 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1667 drm_clip_rect_t *cliprects, int num_cliprects,
1670 return drm_intel_gem_bo_mrb_exec2(bo, used,
1671 cliprects, num_cliprects, DR4,
1676 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1678 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1679 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1680 struct drm_i915_gem_pin pin;
1683 memset(&pin, 0, sizeof(pin));
1684 pin.handle = bo_gem->gem_handle;
1685 pin.alignment = alignment;
1687 ret = drmIoctl(bufmgr_gem->fd,
1688 DRM_IOCTL_I915_GEM_PIN,
1693 bo->offset = pin.offset;
1698 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1700 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1701 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1702 struct drm_i915_gem_unpin unpin;
1705 memset(&unpin, 0, sizeof(unpin));
1706 unpin.handle = bo_gem->gem_handle;
1708 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1716 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1717 uint32_t tiling_mode,
1720 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1721 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1722 struct drm_i915_gem_set_tiling set_tiling;
1725 if (bo_gem->global_name == 0 &&
1726 tiling_mode == bo_gem->tiling_mode &&
1727 stride == bo_gem->stride)
1730 memset(&set_tiling, 0, sizeof(set_tiling));
1732 /* set_tiling is slightly broken and overwrites the
1733 * input on the error path, so we have to open code
1736 set_tiling.handle = bo_gem->gem_handle;
1737 set_tiling.tiling_mode = tiling_mode;
1738 set_tiling.stride = stride;
1740 ret = ioctl(bufmgr_gem->fd,
1741 DRM_IOCTL_I915_GEM_SET_TILING,
1743 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1747 bo_gem->tiling_mode = set_tiling.tiling_mode;
1748 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1749 bo_gem->stride = set_tiling.stride;
1754 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1757 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1758 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1761 /* Linear buffers have no stride. By ensuring that we only ever use
1762 * stride 0 with linear buffers, we simplify our code.
1764 if (*tiling_mode == I915_TILING_NONE)
1767 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1769 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1771 *tiling_mode = bo_gem->tiling_mode;
1776 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1777 uint32_t * swizzle_mode)
1779 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1781 *tiling_mode = bo_gem->tiling_mode;
1782 *swizzle_mode = bo_gem->swizzle_mode;
1787 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1789 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1790 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1791 struct drm_gem_flink flink;
1794 if (!bo_gem->global_name) {
1795 memset(&flink, 0, sizeof(flink));
1796 flink.handle = bo_gem->gem_handle;
1798 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1801 bo_gem->global_name = flink.name;
1802 bo_gem->reusable = 0;
1804 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1807 *name = bo_gem->global_name;
1812 * Enables unlimited caching of buffer objects for reuse.
1814 * This is potentially very memory expensive, as the cache at each bucket
1815 * size is only bounded by how many buffers of that size we've managed to have
1816 * in flight at once.
1819 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1821 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1823 bufmgr_gem->bo_reuse = 1;
1827 * Enable use of fenced reloc type.
1829 * New code should enable this to avoid unnecessary fence register
1830 * allocation. If this option is not enabled, all relocs will have fence
1831 * register allocated.
1834 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1836 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1838 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1839 bufmgr_gem->fenced_relocs = 1;
1843 * Return the additional aperture space required by the tree of buffer objects
1847 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1849 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1853 if (bo == NULL || bo_gem->included_in_check_aperture)
1857 bo_gem->included_in_check_aperture = 1;
1859 for (i = 0; i < bo_gem->reloc_count; i++)
1861 drm_intel_gem_bo_get_aperture_space(bo_gem->
1862 reloc_target_info[i].bo);
1868 * Count the number of buffers in this list that need a fence reg
1870 * If the count is greater than the number of available regs, we'll have
1871 * to ask the caller to resubmit a batch with fewer tiled buffers.
1873 * This function over-counts if the same buffer is used multiple times.
1876 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1879 unsigned int total = 0;
1881 for (i = 0; i < count; i++) {
1882 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1887 total += bo_gem->reloc_tree_fences;
1893 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1894 * for the next drm_intel_bufmgr_check_aperture_space() call.
1897 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1899 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1902 if (bo == NULL || !bo_gem->included_in_check_aperture)
1905 bo_gem->included_in_check_aperture = 0;
1907 for (i = 0; i < bo_gem->reloc_count; i++)
1908 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1909 reloc_target_info[i].bo);
1913 * Return a conservative estimate for the amount of aperture required
1914 * for a collection of buffers. This may double-count some buffers.
1917 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1920 unsigned int total = 0;
1922 for (i = 0; i < count; i++) {
1923 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1925 total += bo_gem->reloc_tree_size;
1931 * Return the amount of aperture needed for a collection of buffers.
1932 * This avoids double counting any buffers, at the cost of looking
1933 * at every buffer in the set.
1936 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1939 unsigned int total = 0;
1941 for (i = 0; i < count; i++) {
1942 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1943 /* For the first buffer object in the array, we get an
1944 * accurate count back for its reloc_tree size (since nothing
1945 * had been flagged as being counted yet). We can save that
1946 * value out as a more conservative reloc_tree_size that
1947 * avoids double-counting target buffers. Since the first
1948 * buffer happens to usually be the batch buffer in our
1949 * callers, this can pull us back from doing the tree
1950 * walk on every new batch emit.
1953 drm_intel_bo_gem *bo_gem =
1954 (drm_intel_bo_gem *) bo_array[i];
1955 bo_gem->reloc_tree_size = total;
1959 for (i = 0; i < count; i++)
1960 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1965 * Return -1 if the batchbuffer should be flushed before attempting to
1966 * emit rendering referencing the buffers pointed to by bo_array.
1968 * This is required because if we try to emit a batchbuffer with relocations
1969 * to a tree of buffers that won't simultaneously fit in the aperture,
1970 * the rendering will return an error at a point where the software is not
1971 * prepared to recover from it.
1973 * However, we also want to emit the batchbuffer significantly before we reach
1974 * the limit, as a series of batchbuffers each of which references buffers
1975 * covering almost all of the aperture means that at each emit we end up
1976 * waiting to evict a buffer from the last rendering, and we get synchronous
1977 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1978 * get better parallelism.
1981 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1983 drm_intel_bufmgr_gem *bufmgr_gem =
1984 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1985 unsigned int total = 0;
1986 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1989 /* Check for fence reg constraints if necessary */
1990 if (bufmgr_gem->available_fences) {
1991 total_fences = drm_intel_gem_total_fences(bo_array, count);
1992 if (total_fences > bufmgr_gem->available_fences)
1996 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1998 if (total > threshold)
1999 total = drm_intel_gem_compute_batch_space(bo_array, count);
2001 if (total > threshold) {
2002 DBG("check_space: overflowed available aperture, "
2004 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2007 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2008 (int)bufmgr_gem->gtt_size / 1024);
2014 * Disable buffer reuse for objects which are shared with the kernel
2015 * as scanout buffers
2018 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2020 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2022 bo_gem->reusable = 0;
2027 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2029 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2031 return bo_gem->reusable;
2035 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2037 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2040 for (i = 0; i < bo_gem->reloc_count; i++) {
2041 if (bo_gem->reloc_target_info[i].bo == target_bo)
2043 if (bo == bo_gem->reloc_target_info[i].bo)
2045 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2053 /** Return true if target_bo is referenced by bo's relocation tree. */
2055 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2057 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2059 if (bo == NULL || target_bo == NULL)
2061 if (target_bo_gem->used_as_reloc_target)
2062 return _drm_intel_gem_bo_references(bo, target_bo);
2067 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2069 unsigned int i = bufmgr_gem->num_buckets;
2071 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2073 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2074 bufmgr_gem->cache_bucket[i].size = size;
2075 bufmgr_gem->num_buckets++;
2079 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2081 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2083 /* OK, so power of two buckets was too wasteful of memory.
2084 * Give 3 other sizes between each power of two, to hopefully
2085 * cover things accurately enough. (The alternative is
2086 * probably to just go for exact matching of sizes, and assume
2087 * that for things like composited window resize the tiled
2088 * width/height alignment and rounding of sizes to pages will
2089 * get us useful cache hit rates anyway)
2091 add_bucket(bufmgr_gem, 4096);
2092 add_bucket(bufmgr_gem, 4096 * 2);
2093 add_bucket(bufmgr_gem, 4096 * 3);
2095 /* Initialize the linked lists for BO reuse cache. */
2096 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2097 add_bucket(bufmgr_gem, size);
2099 add_bucket(bufmgr_gem, size + size * 1 / 4);
2100 add_bucket(bufmgr_gem, size + size * 2 / 4);
2101 add_bucket(bufmgr_gem, size + size * 3 / 4);
2106 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2107 * and manage map buffer objections.
2109 * \param fd File descriptor of the opened DRM device.
2112 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2114 drm_intel_bufmgr_gem *bufmgr_gem;
2115 struct drm_i915_gem_get_aperture aperture;
2116 drm_i915_getparam_t gp;
2120 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2121 if (bufmgr_gem == NULL)
2124 bufmgr_gem->fd = fd;
2126 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2131 ret = drmIoctl(bufmgr_gem->fd,
2132 DRM_IOCTL_I915_GEM_GET_APERTURE,
2136 bufmgr_gem->gtt_size = aperture.aper_available_size;
2138 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2140 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2141 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2142 "May lead to reduced performance or incorrect "
2144 (int)bufmgr_gem->gtt_size / 1024);
2147 gp.param = I915_PARAM_CHIPSET_ID;
2148 gp.value = &bufmgr_gem->pci_device;
2149 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2151 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2152 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2155 if (IS_GEN2(bufmgr_gem))
2156 bufmgr_gem->gen = 2;
2157 else if (IS_GEN3(bufmgr_gem))
2158 bufmgr_gem->gen = 3;
2159 else if (IS_GEN4(bufmgr_gem))
2160 bufmgr_gem->gen = 4;
2162 bufmgr_gem->gen = 6;
2164 gp.param = I915_PARAM_HAS_EXECBUF2;
2165 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2169 gp.param = I915_PARAM_HAS_BSD;
2170 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2171 bufmgr_gem->has_bsd = ret == 0;
2173 gp.param = I915_PARAM_HAS_BLT;
2174 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2175 bufmgr_gem->has_blt = ret == 0;
2177 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2178 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2179 bufmgr_gem->has_relaxed_fencing = ret == 0;
2181 if (bufmgr_gem->gen < 4) {
2182 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2183 gp.value = &bufmgr_gem->available_fences;
2184 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2186 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2188 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2190 bufmgr_gem->available_fences = 0;
2192 /* XXX The kernel reports the total number of fences,
2193 * including any that may be pinned.
2195 * We presume that there will be at least one pinned
2196 * fence for the scanout buffer, but there may be more
2197 * than one scanout and the user may be manually
2198 * pinning buffers. Let's move to execbuffer2 and
2199 * thereby forget the insanity of using fences...
2201 bufmgr_gem->available_fences -= 2;
2202 if (bufmgr_gem->available_fences < 0)
2203 bufmgr_gem->available_fences = 0;
2207 /* Let's go with one relocation per every 2 dwords (but round down a bit
2208 * since a power of two will mean an extra page allocation for the reloc
2211 * Every 4 was too few for the blender benchmark.
2213 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2215 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2216 bufmgr_gem->bufmgr.bo_alloc_for_render =
2217 drm_intel_gem_bo_alloc_for_render;
2218 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2219 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2220 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2221 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2222 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2223 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2224 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2225 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2226 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2227 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2228 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2229 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2230 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2231 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2232 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2233 /* Use the new one if available */
2235 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2236 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2238 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2239 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2240 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2241 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2242 bufmgr_gem->bufmgr.debug = 0;
2243 bufmgr_gem->bufmgr.check_aperture_space =
2244 drm_intel_gem_check_aperture_space;
2245 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2246 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2247 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2248 drm_intel_gem_get_pipe_from_crtc_id;
2249 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2251 DRMINITLISTHEAD(&bufmgr_gem->named);
2252 init_cache_buckets(bufmgr_gem);
2254 return &bufmgr_gem->bufmgr;