1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
57 #include "libdrm_lists.h"
58 #include "intel_bufmgr.h"
59 #include "intel_bufmgr_priv.h"
60 #include "intel_chipset.h"
65 #define DBG(...) do { \
66 if (bufmgr_gem->bufmgr.debug) \
67 fprintf(stderr, __VA_ARGS__); \
70 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
72 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
74 struct drm_intel_gem_bo_bucket {
79 typedef struct _drm_intel_bufmgr_gem {
80 drm_intel_bufmgr bufmgr;
88 struct drm_i915_gem_exec_object *exec_objects;
89 struct drm_i915_gem_exec_object2 *exec2_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
102 int available_fences;
105 unsigned int has_bsd : 1;
106 unsigned int has_blt : 1;
107 unsigned int has_relaxed_fencing : 1;
108 unsigned int bo_reuse : 1;
110 } drm_intel_bufmgr_gem;
112 #define DRM_INTEL_RELOC_FENCE (1<<0)
114 typedef struct _drm_intel_reloc_target_info {
117 } drm_intel_reloc_target;
119 struct _drm_intel_bo_gem {
127 * Kenel-assigned global name for this object
129 unsigned int global_name;
130 drmMMListHead name_list;
133 * Index of the buffer within the validation list while preparing a
134 * batchbuffer execution.
139 * Current tiling mode
141 uint32_t tiling_mode;
142 uint32_t swizzle_mode;
143 unsigned long stride;
147 /** Array passed to the DRM containing relocation information. */
148 struct drm_i915_gem_relocation_entry *relocs;
150 * Array of info structs corresponding to relocs[i].target_handle etc
152 drm_intel_reloc_target *reloc_target_info;
153 /** Number of entries in relocs */
155 /** Mapped address for the buffer, saved across map/unmap cycles */
157 /** GTT virtual address for the buffer, saved across map/unmap cycles */
164 * Boolean of whether this BO and its children have been included in
165 * the current drm_intel_bufmgr_check_aperture_space() total.
167 bool included_in_check_aperture;
170 * Boolean of whether this buffer has been used as a relocation
171 * target and had its size accounted for, and thus can't have any
172 * further relocations added to it.
174 bool used_as_reloc_target;
177 * Boolean of whether we have encountered an error whilst building the relocation tree.
182 * Boolean of whether this buffer can be re-used
187 * Size in bytes of this buffer and its relocation descendents.
189 * Used to avoid costly tree walking in
190 * drm_intel_bufmgr_check_aperture in the common case.
195 * Number of potential fence registers required by this buffer and its
198 int reloc_tree_fences;
202 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
205 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
208 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
209 uint32_t * swizzle_mode);
212 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
213 uint32_t tiling_mode,
216 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
219 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
221 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
224 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
225 uint32_t *tiling_mode)
227 unsigned long min_size, max_size;
230 if (*tiling_mode == I915_TILING_NONE)
233 /* 965+ just need multiples of page size for tiling */
234 if (bufmgr_gem->gen >= 4)
235 return ROUND_UP_TO(size, 4096);
237 /* Older chips need powers of two, of at least 512k or 1M */
238 if (bufmgr_gem->gen == 3) {
239 min_size = 1024*1024;
240 max_size = 128*1024*1024;
243 max_size = 64*1024*1024;
246 if (size > max_size) {
247 *tiling_mode = I915_TILING_NONE;
251 /* Do we need to allocate every page for the fence? */
252 if (bufmgr_gem->has_relaxed_fencing)
253 return ROUND_UP_TO(size, 4096);
255 for (i = min_size; i < size; i <<= 1)
262 * Round a given pitch up to the minimum required for X tiling on a
263 * given chip. We use 512 as the minimum to allow for a later tiling
267 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
268 unsigned long pitch, uint32_t *tiling_mode)
270 unsigned long tile_width;
273 /* If untiled, then just align it so that we can do rendering
274 * to it with the 3D engine.
276 if (*tiling_mode == I915_TILING_NONE)
277 return ALIGN(pitch, 64);
279 if (*tiling_mode == I915_TILING_X
280 || (IS_915(bufmgr_gem) && *tiling_mode == I915_TILING_Y))
285 /* 965 is flexible */
286 if (bufmgr_gem->gen >= 4)
287 return ROUND_UP_TO(pitch, tile_width);
289 /* The older hardware has a maximum pitch of 8192 with tiled
290 * surfaces, so fallback to untiled if it's too large.
293 *tiling_mode = I915_TILING_NONE;
294 return ALIGN(pitch, 64);
297 /* Pre-965 needs power of two tile width */
298 for (i = tile_width; i < pitch; i <<= 1)
304 static struct drm_intel_gem_bo_bucket *
305 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
310 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
311 struct drm_intel_gem_bo_bucket *bucket =
312 &bufmgr_gem->cache_bucket[i];
313 if (bucket->size >= size) {
322 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
326 for (i = 0; i < bufmgr_gem->exec_count; i++) {
327 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
328 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
330 if (bo_gem->relocs == NULL) {
331 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
336 for (j = 0; j < bo_gem->reloc_count; j++) {
337 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
338 drm_intel_bo_gem *target_gem =
339 (drm_intel_bo_gem *) target_bo;
341 DBG("%2d: %d (%s)@0x%08llx -> "
342 "%d (%s)@0x%08lx + 0x%08x\n",
344 bo_gem->gem_handle, bo_gem->name,
345 (unsigned long long)bo_gem->relocs[j].offset,
346 target_gem->gem_handle,
349 bo_gem->relocs[j].delta);
355 drm_intel_gem_bo_reference(drm_intel_bo *bo)
357 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
359 atomic_inc(&bo_gem->refcount);
363 * Adds the given buffer to the list of buffers to be validated (moved into the
364 * appropriate memory type) with the next batch submission.
366 * If a buffer is validated multiple times in a batch submission, it ends up
367 * with the intersection of the memory type flags and the union of the
371 drm_intel_add_validate_buffer(drm_intel_bo *bo)
373 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
374 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
377 if (bo_gem->validate_index != -1)
380 /* Extend the array of validation entries as necessary. */
381 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
382 int new_size = bufmgr_gem->exec_size * 2;
387 bufmgr_gem->exec_objects =
388 realloc(bufmgr_gem->exec_objects,
389 sizeof(*bufmgr_gem->exec_objects) * new_size);
390 bufmgr_gem->exec_bos =
391 realloc(bufmgr_gem->exec_bos,
392 sizeof(*bufmgr_gem->exec_bos) * new_size);
393 bufmgr_gem->exec_size = new_size;
396 index = bufmgr_gem->exec_count;
397 bo_gem->validate_index = index;
398 /* Fill in array entry */
399 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
400 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
401 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
402 bufmgr_gem->exec_objects[index].alignment = 0;
403 bufmgr_gem->exec_objects[index].offset = 0;
404 bufmgr_gem->exec_bos[index] = bo;
405 bufmgr_gem->exec_count++;
409 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
411 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
412 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
415 if (bo_gem->validate_index != -1) {
417 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
418 EXEC_OBJECT_NEEDS_FENCE;
422 /* Extend the array of validation entries as necessary. */
423 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
424 int new_size = bufmgr_gem->exec_size * 2;
429 bufmgr_gem->exec2_objects =
430 realloc(bufmgr_gem->exec2_objects,
431 sizeof(*bufmgr_gem->exec2_objects) * new_size);
432 bufmgr_gem->exec_bos =
433 realloc(bufmgr_gem->exec_bos,
434 sizeof(*bufmgr_gem->exec_bos) * new_size);
435 bufmgr_gem->exec_size = new_size;
438 index = bufmgr_gem->exec_count;
439 bo_gem->validate_index = index;
440 /* Fill in array entry */
441 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
442 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
443 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
444 bufmgr_gem->exec2_objects[index].alignment = 0;
445 bufmgr_gem->exec2_objects[index].offset = 0;
446 bufmgr_gem->exec_bos[index] = bo;
447 bufmgr_gem->exec2_objects[index].flags = 0;
448 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
449 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
451 bufmgr_gem->exec2_objects[index].flags |=
452 EXEC_OBJECT_NEEDS_FENCE;
454 bufmgr_gem->exec_count++;
457 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
461 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
462 drm_intel_bo_gem *bo_gem)
466 assert(!bo_gem->used_as_reloc_target);
468 /* The older chipsets are far-less flexible in terms of tiling,
469 * and require tiled buffer to be size aligned in the aperture.
470 * This means that in the worst possible case we will need a hole
471 * twice as large as the object in order for it to fit into the
472 * aperture. Optimal packing is for wimps.
474 size = bo_gem->bo.size;
475 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
478 if (bufmgr_gem->has_relaxed_fencing) {
479 if (bufmgr_gem->gen == 3)
480 min_size = 1024*1024;
484 while (min_size < size)
489 /* Account for worst-case alignment. */
493 bo_gem->reloc_tree_size = size;
497 drm_intel_setup_reloc_list(drm_intel_bo *bo)
499 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
500 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
501 unsigned int max_relocs = bufmgr_gem->max_relocs;
503 if (bo->size / 4 < max_relocs)
504 max_relocs = bo->size / 4;
506 bo_gem->relocs = malloc(max_relocs *
507 sizeof(struct drm_i915_gem_relocation_entry));
508 bo_gem->reloc_target_info = malloc(max_relocs *
509 sizeof(drm_intel_reloc_target));
510 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
511 bo_gem->has_error = true;
513 free (bo_gem->relocs);
514 bo_gem->relocs = NULL;
516 free (bo_gem->reloc_target_info);
517 bo_gem->reloc_target_info = NULL;
526 drm_intel_gem_bo_busy(drm_intel_bo *bo)
528 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
529 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
530 struct drm_i915_gem_busy busy;
533 memset(&busy, 0, sizeof(busy));
534 busy.handle = bo_gem->gem_handle;
536 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
538 return (ret == 0 && busy.busy);
542 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
543 drm_intel_bo_gem *bo_gem, int state)
545 struct drm_i915_gem_madvise madv;
547 madv.handle = bo_gem->gem_handle;
550 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
552 return madv.retained;
556 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
558 return drm_intel_gem_bo_madvise_internal
559 ((drm_intel_bufmgr_gem *) bo->bufmgr,
560 (drm_intel_bo_gem *) bo,
564 /* drop the oldest entries that have been purged by the kernel */
566 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
567 struct drm_intel_gem_bo_bucket *bucket)
569 while (!DRMLISTEMPTY(&bucket->head)) {
570 drm_intel_bo_gem *bo_gem;
572 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
573 bucket->head.next, head);
574 if (drm_intel_gem_bo_madvise_internal
575 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
578 DRMLISTDEL(&bo_gem->head);
579 drm_intel_gem_bo_free(&bo_gem->bo);
583 static drm_intel_bo *
584 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
588 uint32_t tiling_mode,
589 unsigned long stride)
591 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
592 drm_intel_bo_gem *bo_gem;
593 unsigned int page_size = getpagesize();
595 struct drm_intel_gem_bo_bucket *bucket;
596 bool alloc_from_cache;
597 unsigned long bo_size;
598 bool for_render = false;
600 if (flags & BO_ALLOC_FOR_RENDER)
603 /* Round the allocated size up to a power of two number of pages. */
604 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
606 /* If we don't have caching at this size, don't actually round the
609 if (bucket == NULL) {
611 if (bo_size < page_size)
614 bo_size = bucket->size;
617 pthread_mutex_lock(&bufmgr_gem->lock);
618 /* Get a buffer out of the cache if available */
620 alloc_from_cache = false;
621 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
623 /* Allocate new render-target BOs from the tail (MRU)
624 * of the list, as it will likely be hot in the GPU
625 * cache and in the aperture for us.
627 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
628 bucket->head.prev, head);
629 DRMLISTDEL(&bo_gem->head);
630 alloc_from_cache = true;
632 /* For non-render-target BOs (where we're probably
633 * going to map it first thing in order to fill it
634 * with data), check if the last BO in the cache is
635 * unbusy, and only reuse in that case. Otherwise,
636 * allocating a new buffer is probably faster than
637 * waiting for the GPU to finish.
639 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
640 bucket->head.next, head);
641 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
642 alloc_from_cache = true;
643 DRMLISTDEL(&bo_gem->head);
647 if (alloc_from_cache) {
648 if (!drm_intel_gem_bo_madvise_internal
649 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
650 drm_intel_gem_bo_free(&bo_gem->bo);
651 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
656 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
659 drm_intel_gem_bo_free(&bo_gem->bo);
664 pthread_mutex_unlock(&bufmgr_gem->lock);
666 if (!alloc_from_cache) {
667 struct drm_i915_gem_create create;
669 bo_gem = calloc(1, sizeof(*bo_gem));
673 bo_gem->bo.size = bo_size;
674 memset(&create, 0, sizeof(create));
675 create.size = bo_size;
677 ret = drmIoctl(bufmgr_gem->fd,
678 DRM_IOCTL_I915_GEM_CREATE,
680 bo_gem->gem_handle = create.handle;
681 bo_gem->bo.handle = bo_gem->gem_handle;
686 bo_gem->bo.bufmgr = bufmgr;
688 bo_gem->tiling_mode = I915_TILING_NONE;
689 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
692 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
695 drm_intel_gem_bo_free(&bo_gem->bo);
699 DRMINITLISTHEAD(&bo_gem->name_list);
703 atomic_set(&bo_gem->refcount, 1);
704 bo_gem->validate_index = -1;
705 bo_gem->reloc_tree_fences = 0;
706 bo_gem->used_as_reloc_target = false;
707 bo_gem->has_error = false;
708 bo_gem->reusable = true;
710 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
712 DBG("bo_create: buf %d (%s) %ldb\n",
713 bo_gem->gem_handle, bo_gem->name, size);
718 static drm_intel_bo *
719 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
722 unsigned int alignment)
724 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
726 I915_TILING_NONE, 0);
729 static drm_intel_bo *
730 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
733 unsigned int alignment)
735 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
736 I915_TILING_NONE, 0);
739 static drm_intel_bo *
740 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
741 int x, int y, int cpp, uint32_t *tiling_mode,
742 unsigned long *pitch, unsigned long flags)
744 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
745 unsigned long size, stride;
749 unsigned long aligned_y, height_alignment;
751 tiling = *tiling_mode;
753 /* If we're tiled, our allocations are in 8 or 32-row blocks,
754 * so failure to align our height means that we won't allocate
757 * If we're untiled, we still have to align to 2 rows high
758 * because the data port accesses 2x2 blocks even if the
759 * bottom row isn't to be rendered, so failure to align means
760 * we could walk off the end of the GTT and fault. This is
761 * documented on 965, and may be the case on older chipsets
762 * too so we try to be careful.
765 height_alignment = 2;
767 if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
768 height_alignment = 16;
769 else if (tiling == I915_TILING_X
770 || (IS_915(bufmgr_gem) && tiling == I915_TILING_Y))
771 height_alignment = 8;
772 else if (tiling == I915_TILING_Y)
773 height_alignment = 32;
774 aligned_y = ALIGN(y, height_alignment);
777 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
778 size = stride * aligned_y;
779 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
780 } while (*tiling_mode != tiling);
783 if (tiling == I915_TILING_NONE)
786 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
791 * Returns a drm_intel_bo wrapping the given buffer object handle.
793 * This can be used when one application needs to pass a buffer object
797 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
801 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
802 drm_intel_bo_gem *bo_gem;
804 struct drm_gem_open open_arg;
805 struct drm_i915_gem_get_tiling get_tiling;
808 /* At the moment most applications only have a few named bo.
809 * For instance, in a DRI client only the render buffers passed
810 * between X and the client are named. And since X returns the
811 * alternating names for the front/back buffer a linear search
812 * provides a sufficiently fast match.
814 for (list = bufmgr_gem->named.next;
815 list != &bufmgr_gem->named;
817 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
818 if (bo_gem->global_name == handle) {
819 drm_intel_gem_bo_reference(&bo_gem->bo);
824 bo_gem = calloc(1, sizeof(*bo_gem));
828 memset(&open_arg, 0, sizeof(open_arg));
829 open_arg.name = handle;
830 ret = drmIoctl(bufmgr_gem->fd,
834 DBG("Couldn't reference %s handle 0x%08x: %s\n",
835 name, handle, strerror(errno));
839 bo_gem->bo.size = open_arg.size;
840 bo_gem->bo.offset = 0;
841 bo_gem->bo.virtual = NULL;
842 bo_gem->bo.bufmgr = bufmgr;
844 atomic_set(&bo_gem->refcount, 1);
845 bo_gem->validate_index = -1;
846 bo_gem->gem_handle = open_arg.handle;
847 bo_gem->bo.handle = open_arg.handle;
848 bo_gem->global_name = handle;
849 bo_gem->reusable = false;
851 memset(&get_tiling, 0, sizeof(get_tiling));
852 get_tiling.handle = bo_gem->gem_handle;
853 ret = drmIoctl(bufmgr_gem->fd,
854 DRM_IOCTL_I915_GEM_GET_TILING,
857 drm_intel_gem_bo_unreference(&bo_gem->bo);
860 bo_gem->tiling_mode = get_tiling.tiling_mode;
861 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
862 /* XXX stride is unknown */
863 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
865 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
866 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
872 drm_intel_gem_bo_free(drm_intel_bo *bo)
874 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
875 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
876 struct drm_gem_close close;
879 if (bo_gem->mem_virtual)
880 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
881 if (bo_gem->gtt_virtual)
882 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
884 /* Close this object */
885 memset(&close, 0, sizeof(close));
886 close.handle = bo_gem->gem_handle;
887 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
889 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
890 bo_gem->gem_handle, bo_gem->name, strerror(errno));
895 /** Frees all cached buffers significantly older than @time. */
897 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
901 if (bufmgr_gem->time == time)
904 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
905 struct drm_intel_gem_bo_bucket *bucket =
906 &bufmgr_gem->cache_bucket[i];
908 while (!DRMLISTEMPTY(&bucket->head)) {
909 drm_intel_bo_gem *bo_gem;
911 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
912 bucket->head.next, head);
913 if (time - bo_gem->free_time <= 1)
916 DRMLISTDEL(&bo_gem->head);
918 drm_intel_gem_bo_free(&bo_gem->bo);
922 bufmgr_gem->time = time;
926 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
928 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
929 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
930 struct drm_intel_gem_bo_bucket *bucket;
933 /* Unreference all the target buffers */
934 for (i = 0; i < bo_gem->reloc_count; i++) {
935 if (bo_gem->reloc_target_info[i].bo != bo) {
936 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
937 reloc_target_info[i].bo,
941 bo_gem->reloc_count = 0;
942 bo_gem->used_as_reloc_target = false;
944 DBG("bo_unreference final: %d (%s)\n",
945 bo_gem->gem_handle, bo_gem->name);
947 /* release memory associated with this object */
948 if (bo_gem->reloc_target_info) {
949 free(bo_gem->reloc_target_info);
950 bo_gem->reloc_target_info = NULL;
952 if (bo_gem->relocs) {
953 free(bo_gem->relocs);
954 bo_gem->relocs = NULL;
957 DRMLISTDEL(&bo_gem->name_list);
959 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
960 /* Put the buffer into our internal cache for reuse if we can. */
961 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
962 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
963 I915_MADV_DONTNEED)) {
964 bo_gem->free_time = time;
967 bo_gem->validate_index = -1;
969 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
971 drm_intel_gem_bo_free(bo);
975 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
978 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
980 assert(atomic_read(&bo_gem->refcount) > 0);
981 if (atomic_dec_and_test(&bo_gem->refcount))
982 drm_intel_gem_bo_unreference_final(bo, time);
985 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
987 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
989 assert(atomic_read(&bo_gem->refcount) > 0);
990 if (atomic_dec_and_test(&bo_gem->refcount)) {
991 drm_intel_bufmgr_gem *bufmgr_gem =
992 (drm_intel_bufmgr_gem *) bo->bufmgr;
993 struct timespec time;
995 clock_gettime(CLOCK_MONOTONIC, &time);
997 pthread_mutex_lock(&bufmgr_gem->lock);
998 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
999 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1000 pthread_mutex_unlock(&bufmgr_gem->lock);
1004 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1006 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1007 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1008 struct drm_i915_gem_set_domain set_domain;
1011 pthread_mutex_lock(&bufmgr_gem->lock);
1013 /* Allow recursive mapping. Mesa may recursively map buffers with
1014 * nested display loops.
1016 if (!bo_gem->mem_virtual) {
1017 struct drm_i915_gem_mmap mmap_arg;
1019 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1021 memset(&mmap_arg, 0, sizeof(mmap_arg));
1022 mmap_arg.handle = bo_gem->gem_handle;
1023 mmap_arg.offset = 0;
1024 mmap_arg.size = bo->size;
1025 ret = drmIoctl(bufmgr_gem->fd,
1026 DRM_IOCTL_I915_GEM_MMAP,
1030 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1031 __FILE__, __LINE__, bo_gem->gem_handle,
1032 bo_gem->name, strerror(errno));
1033 pthread_mutex_unlock(&bufmgr_gem->lock);
1036 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1038 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1039 bo_gem->mem_virtual);
1040 bo->virtual = bo_gem->mem_virtual;
1042 set_domain.handle = bo_gem->gem_handle;
1043 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1045 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1047 set_domain.write_domain = 0;
1048 ret = drmIoctl(bufmgr_gem->fd,
1049 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1052 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1053 __FILE__, __LINE__, bo_gem->gem_handle,
1057 pthread_mutex_unlock(&bufmgr_gem->lock);
1062 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1064 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1065 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1066 struct drm_i915_gem_set_domain set_domain;
1069 pthread_mutex_lock(&bufmgr_gem->lock);
1071 /* Get a mapping of the buffer if we haven't before. */
1072 if (bo_gem->gtt_virtual == NULL) {
1073 struct drm_i915_gem_mmap_gtt mmap_arg;
1075 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1078 memset(&mmap_arg, 0, sizeof(mmap_arg));
1079 mmap_arg.handle = bo_gem->gem_handle;
1081 /* Get the fake offset back... */
1082 ret = drmIoctl(bufmgr_gem->fd,
1083 DRM_IOCTL_I915_GEM_MMAP_GTT,
1087 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1089 bo_gem->gem_handle, bo_gem->name,
1091 pthread_mutex_unlock(&bufmgr_gem->lock);
1096 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1097 MAP_SHARED, bufmgr_gem->fd,
1099 if (bo_gem->gtt_virtual == MAP_FAILED) {
1100 bo_gem->gtt_virtual = NULL;
1102 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1104 bo_gem->gem_handle, bo_gem->name,
1106 pthread_mutex_unlock(&bufmgr_gem->lock);
1111 bo->virtual = bo_gem->gtt_virtual;
1113 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1114 bo_gem->gtt_virtual);
1116 /* Now move it to the GTT domain so that the CPU caches are flushed */
1117 set_domain.handle = bo_gem->gem_handle;
1118 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1119 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1120 ret = drmIoctl(bufmgr_gem->fd,
1121 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1124 DBG("%s:%d: Error setting domain %d: %s\n",
1125 __FILE__, __LINE__, bo_gem->gem_handle,
1129 pthread_mutex_unlock(&bufmgr_gem->lock);
1134 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1136 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1142 pthread_mutex_lock(&bufmgr_gem->lock);
1144 pthread_mutex_unlock(&bufmgr_gem->lock);
1149 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1151 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1152 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1153 struct drm_i915_gem_sw_finish sw_finish;
1159 pthread_mutex_lock(&bufmgr_gem->lock);
1161 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1162 * results show up in a timely manner.
1164 sw_finish.handle = bo_gem->gem_handle;
1165 ret = drmIoctl(bufmgr_gem->fd,
1166 DRM_IOCTL_I915_GEM_SW_FINISH,
1168 ret = ret == -1 ? -errno : 0;
1171 pthread_mutex_unlock(&bufmgr_gem->lock);
1177 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1178 unsigned long size, const void *data)
1180 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1181 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1182 struct drm_i915_gem_pwrite pwrite;
1185 memset(&pwrite, 0, sizeof(pwrite));
1186 pwrite.handle = bo_gem->gem_handle;
1187 pwrite.offset = offset;
1189 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1190 ret = drmIoctl(bufmgr_gem->fd,
1191 DRM_IOCTL_I915_GEM_PWRITE,
1195 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1196 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1197 (int)size, strerror(errno));
1204 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1206 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1207 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1210 get_pipe_from_crtc_id.crtc_id = crtc_id;
1211 ret = drmIoctl(bufmgr_gem->fd,
1212 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1213 &get_pipe_from_crtc_id);
1215 /* We return -1 here to signal that we don't
1216 * know which pipe is associated with this crtc.
1217 * This lets the caller know that this information
1218 * isn't available; using the wrong pipe for
1219 * vblank waiting can cause the chipset to lock up
1224 return get_pipe_from_crtc_id.pipe;
1228 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1229 unsigned long size, void *data)
1231 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1232 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1233 struct drm_i915_gem_pread pread;
1236 memset(&pread, 0, sizeof(pread));
1237 pread.handle = bo_gem->gem_handle;
1238 pread.offset = offset;
1240 pread.data_ptr = (uint64_t) (uintptr_t) data;
1241 ret = drmIoctl(bufmgr_gem->fd,
1242 DRM_IOCTL_I915_GEM_PREAD,
1246 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1247 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1248 (int)size, strerror(errno));
1254 /** Waits for all GPU rendering with the object to have completed. */
1256 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1258 drm_intel_gem_bo_start_gtt_access(bo, 1);
1262 * Sets the object to the GTT read and possibly write domain, used by the X
1263 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1265 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1266 * can do tiled pixmaps this way.
1269 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1271 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1272 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1273 struct drm_i915_gem_set_domain set_domain;
1276 set_domain.handle = bo_gem->gem_handle;
1277 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1278 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1279 ret = drmIoctl(bufmgr_gem->fd,
1280 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1283 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1284 __FILE__, __LINE__, bo_gem->gem_handle,
1285 set_domain.read_domains, set_domain.write_domain,
1291 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1293 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1296 free(bufmgr_gem->exec2_objects);
1297 free(bufmgr_gem->exec_objects);
1298 free(bufmgr_gem->exec_bos);
1300 pthread_mutex_destroy(&bufmgr_gem->lock);
1302 /* Free any cached buffer objects we were going to reuse */
1303 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1304 struct drm_intel_gem_bo_bucket *bucket =
1305 &bufmgr_gem->cache_bucket[i];
1306 drm_intel_bo_gem *bo_gem;
1308 while (!DRMLISTEMPTY(&bucket->head)) {
1309 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1310 bucket->head.next, head);
1311 DRMLISTDEL(&bo_gem->head);
1313 drm_intel_gem_bo_free(&bo_gem->bo);
1321 * Adds the target buffer to the validation list and adds the relocation
1322 * to the reloc_buffer's relocation list.
1324 * The relocation entry at the given offset must already contain the
1325 * precomputed relocation value, because the kernel will optimize out
1326 * the relocation entry write when the buffer hasn't moved from the
1327 * last known offset in target_bo.
1330 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1331 drm_intel_bo *target_bo, uint32_t target_offset,
1332 uint32_t read_domains, uint32_t write_domain,
1335 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1336 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1337 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1338 bool fenced_command;
1340 if (bo_gem->has_error)
1343 if (target_bo_gem->has_error) {
1344 bo_gem->has_error = true;
1348 /* We never use HW fences for rendering on 965+ */
1349 if (bufmgr_gem->gen >= 4)
1352 fenced_command = need_fence;
1353 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1356 /* Create a new relocation list if needed */
1357 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1360 /* Check overflow */
1361 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1364 assert(offset <= bo->size - 4);
1365 assert((write_domain & (write_domain - 1)) == 0);
1367 /* Make sure that we're not adding a reloc to something whose size has
1368 * already been accounted for.
1370 assert(!bo_gem->used_as_reloc_target);
1371 if (target_bo_gem != bo_gem) {
1372 target_bo_gem->used_as_reloc_target = true;
1373 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1375 /* An object needing a fence is a tiled buffer, so it won't have
1376 * relocs to other buffers.
1379 target_bo_gem->reloc_tree_fences = 1;
1380 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1382 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1383 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1384 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1385 target_bo_gem->gem_handle;
1386 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1387 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1388 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1390 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1391 if (target_bo != bo)
1392 drm_intel_gem_bo_reference(target_bo);
1394 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1395 DRM_INTEL_RELOC_FENCE;
1397 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1399 bo_gem->reloc_count++;
1405 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1406 drm_intel_bo *target_bo, uint32_t target_offset,
1407 uint32_t read_domains, uint32_t write_domain)
1409 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1411 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1412 read_domains, write_domain,
1413 !bufmgr_gem->fenced_relocs);
1417 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1418 drm_intel_bo *target_bo,
1419 uint32_t target_offset,
1420 uint32_t read_domains, uint32_t write_domain)
1422 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1423 read_domains, write_domain, true);
1427 * Walk the tree of relocations rooted at BO and accumulate the list of
1428 * validations to be performed and update the relocation buffers with
1429 * index values into the validation list.
1432 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1434 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1437 if (bo_gem->relocs == NULL)
1440 for (i = 0; i < bo_gem->reloc_count; i++) {
1441 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1443 if (target_bo == bo)
1446 /* Continue walking the tree depth-first. */
1447 drm_intel_gem_bo_process_reloc(target_bo);
1449 /* Add the target to the validate list */
1450 drm_intel_add_validate_buffer(target_bo);
1455 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1457 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1460 if (bo_gem->relocs == NULL)
1463 for (i = 0; i < bo_gem->reloc_count; i++) {
1464 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1467 if (target_bo == bo)
1470 /* Continue walking the tree depth-first. */
1471 drm_intel_gem_bo_process_reloc2(target_bo);
1473 need_fence = (bo_gem->reloc_target_info[i].flags &
1474 DRM_INTEL_RELOC_FENCE);
1476 /* Add the target to the validate list */
1477 drm_intel_add_validate_buffer2(target_bo, need_fence);
1483 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1487 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1488 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1489 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1491 /* Update the buffer offset */
1492 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1493 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1494 bo_gem->gem_handle, bo_gem->name, bo->offset,
1495 (unsigned long long)bufmgr_gem->exec_objects[i].
1497 bo->offset = bufmgr_gem->exec_objects[i].offset;
1503 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1507 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1508 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1509 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1511 /* Update the buffer offset */
1512 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1513 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1514 bo_gem->gem_handle, bo_gem->name, bo->offset,
1515 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1516 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1522 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1523 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1525 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1526 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1527 struct drm_i915_gem_execbuffer execbuf;
1530 if (bo_gem->has_error)
1533 pthread_mutex_lock(&bufmgr_gem->lock);
1534 /* Update indices and set up the validate list. */
1535 drm_intel_gem_bo_process_reloc(bo);
1537 /* Add the batch buffer to the validation list. There are no
1538 * relocations pointing to it.
1540 drm_intel_add_validate_buffer(bo);
1542 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1543 execbuf.buffer_count = bufmgr_gem->exec_count;
1544 execbuf.batch_start_offset = 0;
1545 execbuf.batch_len = used;
1546 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1547 execbuf.num_cliprects = num_cliprects;
1551 ret = drmIoctl(bufmgr_gem->fd,
1552 DRM_IOCTL_I915_GEM_EXECBUFFER,
1556 if (errno == ENOSPC) {
1557 DBG("Execbuffer fails to pin. "
1558 "Estimate: %u. Actual: %u. Available: %u\n",
1559 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1562 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1565 (unsigned int)bufmgr_gem->gtt_size);
1568 drm_intel_update_buffer_offsets(bufmgr_gem);
1570 if (bufmgr_gem->bufmgr.debug)
1571 drm_intel_gem_dump_validation_list(bufmgr_gem);
1573 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1574 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1575 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1577 /* Disconnect the buffer from the validate list */
1578 bo_gem->validate_index = -1;
1579 bufmgr_gem->exec_bos[i] = NULL;
1581 bufmgr_gem->exec_count = 0;
1582 pthread_mutex_unlock(&bufmgr_gem->lock);
1588 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1589 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1592 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1593 struct drm_i915_gem_execbuffer2 execbuf;
1596 switch (flags & 0x7) {
1600 if (!bufmgr_gem->has_blt)
1604 if (!bufmgr_gem->has_bsd)
1607 case I915_EXEC_RENDER:
1608 case I915_EXEC_DEFAULT:
1612 pthread_mutex_lock(&bufmgr_gem->lock);
1613 /* Update indices and set up the validate list. */
1614 drm_intel_gem_bo_process_reloc2(bo);
1616 /* Add the batch buffer to the validation list. There are no relocations
1619 drm_intel_add_validate_buffer2(bo, 0);
1621 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1622 execbuf.buffer_count = bufmgr_gem->exec_count;
1623 execbuf.batch_start_offset = 0;
1624 execbuf.batch_len = used;
1625 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1626 execbuf.num_cliprects = num_cliprects;
1629 execbuf.flags = flags;
1633 ret = drmIoctl(bufmgr_gem->fd,
1634 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1638 if (ret == -ENOSPC) {
1639 DBG("Execbuffer fails to pin. "
1640 "Estimate: %u. Actual: %u. Available: %u\n",
1641 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1642 bufmgr_gem->exec_count),
1643 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1644 bufmgr_gem->exec_count),
1645 (unsigned int) bufmgr_gem->gtt_size);
1648 drm_intel_update_buffer_offsets2(bufmgr_gem);
1650 if (bufmgr_gem->bufmgr.debug)
1651 drm_intel_gem_dump_validation_list(bufmgr_gem);
1653 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1654 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1655 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1657 /* Disconnect the buffer from the validate list */
1658 bo_gem->validate_index = -1;
1659 bufmgr_gem->exec_bos[i] = NULL;
1661 bufmgr_gem->exec_count = 0;
1662 pthread_mutex_unlock(&bufmgr_gem->lock);
1668 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1669 drm_clip_rect_t *cliprects, int num_cliprects,
1672 return drm_intel_gem_bo_mrb_exec2(bo, used,
1673 cliprects, num_cliprects, DR4,
1678 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1680 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1681 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1682 struct drm_i915_gem_pin pin;
1685 memset(&pin, 0, sizeof(pin));
1686 pin.handle = bo_gem->gem_handle;
1687 pin.alignment = alignment;
1689 ret = drmIoctl(bufmgr_gem->fd,
1690 DRM_IOCTL_I915_GEM_PIN,
1695 bo->offset = pin.offset;
1700 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1702 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1703 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1704 struct drm_i915_gem_unpin unpin;
1707 memset(&unpin, 0, sizeof(unpin));
1708 unpin.handle = bo_gem->gem_handle;
1710 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1718 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1719 uint32_t tiling_mode,
1722 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1723 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1724 struct drm_i915_gem_set_tiling set_tiling;
1727 if (bo_gem->global_name == 0 &&
1728 tiling_mode == bo_gem->tiling_mode &&
1729 stride == bo_gem->stride)
1732 memset(&set_tiling, 0, sizeof(set_tiling));
1734 /* set_tiling is slightly broken and overwrites the
1735 * input on the error path, so we have to open code
1738 set_tiling.handle = bo_gem->gem_handle;
1739 set_tiling.tiling_mode = tiling_mode;
1740 set_tiling.stride = stride;
1742 ret = ioctl(bufmgr_gem->fd,
1743 DRM_IOCTL_I915_GEM_SET_TILING,
1745 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1749 bo_gem->tiling_mode = set_tiling.tiling_mode;
1750 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1751 bo_gem->stride = set_tiling.stride;
1756 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1759 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1760 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1763 /* Linear buffers have no stride. By ensuring that we only ever use
1764 * stride 0 with linear buffers, we simplify our code.
1766 if (*tiling_mode == I915_TILING_NONE)
1769 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1771 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1773 *tiling_mode = bo_gem->tiling_mode;
1778 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1779 uint32_t * swizzle_mode)
1781 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1783 *tiling_mode = bo_gem->tiling_mode;
1784 *swizzle_mode = bo_gem->swizzle_mode;
1789 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1791 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1792 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1793 struct drm_gem_flink flink;
1796 if (!bo_gem->global_name) {
1797 memset(&flink, 0, sizeof(flink));
1798 flink.handle = bo_gem->gem_handle;
1800 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1803 bo_gem->global_name = flink.name;
1804 bo_gem->reusable = false;
1806 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1809 *name = bo_gem->global_name;
1814 * Enables unlimited caching of buffer objects for reuse.
1816 * This is potentially very memory expensive, as the cache at each bucket
1817 * size is only bounded by how many buffers of that size we've managed to have
1818 * in flight at once.
1821 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1823 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1825 bufmgr_gem->bo_reuse = true;
1829 * Enable use of fenced reloc type.
1831 * New code should enable this to avoid unnecessary fence register
1832 * allocation. If this option is not enabled, all relocs will have fence
1833 * register allocated.
1836 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1838 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1840 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1841 bufmgr_gem->fenced_relocs = true;
1845 * Return the additional aperture space required by the tree of buffer objects
1849 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1851 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1855 if (bo == NULL || bo_gem->included_in_check_aperture)
1859 bo_gem->included_in_check_aperture = true;
1861 for (i = 0; i < bo_gem->reloc_count; i++)
1863 drm_intel_gem_bo_get_aperture_space(bo_gem->
1864 reloc_target_info[i].bo);
1870 * Count the number of buffers in this list that need a fence reg
1872 * If the count is greater than the number of available regs, we'll have
1873 * to ask the caller to resubmit a batch with fewer tiled buffers.
1875 * This function over-counts if the same buffer is used multiple times.
1878 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1881 unsigned int total = 0;
1883 for (i = 0; i < count; i++) {
1884 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1889 total += bo_gem->reloc_tree_fences;
1895 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1896 * for the next drm_intel_bufmgr_check_aperture_space() call.
1899 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1901 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1904 if (bo == NULL || !bo_gem->included_in_check_aperture)
1907 bo_gem->included_in_check_aperture = false;
1909 for (i = 0; i < bo_gem->reloc_count; i++)
1910 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1911 reloc_target_info[i].bo);
1915 * Return a conservative estimate for the amount of aperture required
1916 * for a collection of buffers. This may double-count some buffers.
1919 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1922 unsigned int total = 0;
1924 for (i = 0; i < count; i++) {
1925 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1927 total += bo_gem->reloc_tree_size;
1933 * Return the amount of aperture needed for a collection of buffers.
1934 * This avoids double counting any buffers, at the cost of looking
1935 * at every buffer in the set.
1938 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1941 unsigned int total = 0;
1943 for (i = 0; i < count; i++) {
1944 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1945 /* For the first buffer object in the array, we get an
1946 * accurate count back for its reloc_tree size (since nothing
1947 * had been flagged as being counted yet). We can save that
1948 * value out as a more conservative reloc_tree_size that
1949 * avoids double-counting target buffers. Since the first
1950 * buffer happens to usually be the batch buffer in our
1951 * callers, this can pull us back from doing the tree
1952 * walk on every new batch emit.
1955 drm_intel_bo_gem *bo_gem =
1956 (drm_intel_bo_gem *) bo_array[i];
1957 bo_gem->reloc_tree_size = total;
1961 for (i = 0; i < count; i++)
1962 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1967 * Return -1 if the batchbuffer should be flushed before attempting to
1968 * emit rendering referencing the buffers pointed to by bo_array.
1970 * This is required because if we try to emit a batchbuffer with relocations
1971 * to a tree of buffers that won't simultaneously fit in the aperture,
1972 * the rendering will return an error at a point where the software is not
1973 * prepared to recover from it.
1975 * However, we also want to emit the batchbuffer significantly before we reach
1976 * the limit, as a series of batchbuffers each of which references buffers
1977 * covering almost all of the aperture means that at each emit we end up
1978 * waiting to evict a buffer from the last rendering, and we get synchronous
1979 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1980 * get better parallelism.
1983 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1985 drm_intel_bufmgr_gem *bufmgr_gem =
1986 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1987 unsigned int total = 0;
1988 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1991 /* Check for fence reg constraints if necessary */
1992 if (bufmgr_gem->available_fences) {
1993 total_fences = drm_intel_gem_total_fences(bo_array, count);
1994 if (total_fences > bufmgr_gem->available_fences)
1998 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2000 if (total > threshold)
2001 total = drm_intel_gem_compute_batch_space(bo_array, count);
2003 if (total > threshold) {
2004 DBG("check_space: overflowed available aperture, "
2006 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2009 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2010 (int)bufmgr_gem->gtt_size / 1024);
2016 * Disable buffer reuse for objects which are shared with the kernel
2017 * as scanout buffers
2020 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2022 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2024 bo_gem->reusable = false;
2029 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2031 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2033 return bo_gem->reusable;
2037 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2039 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2042 for (i = 0; i < bo_gem->reloc_count; i++) {
2043 if (bo_gem->reloc_target_info[i].bo == target_bo)
2045 if (bo == bo_gem->reloc_target_info[i].bo)
2047 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2055 /** Return true if target_bo is referenced by bo's relocation tree. */
2057 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2059 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2061 if (bo == NULL || target_bo == NULL)
2063 if (target_bo_gem->used_as_reloc_target)
2064 return _drm_intel_gem_bo_references(bo, target_bo);
2069 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2071 unsigned int i = bufmgr_gem->num_buckets;
2073 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2075 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2076 bufmgr_gem->cache_bucket[i].size = size;
2077 bufmgr_gem->num_buckets++;
2081 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2083 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2085 /* OK, so power of two buckets was too wasteful of memory.
2086 * Give 3 other sizes between each power of two, to hopefully
2087 * cover things accurately enough. (The alternative is
2088 * probably to just go for exact matching of sizes, and assume
2089 * that for things like composited window resize the tiled
2090 * width/height alignment and rounding of sizes to pages will
2091 * get us useful cache hit rates anyway)
2093 add_bucket(bufmgr_gem, 4096);
2094 add_bucket(bufmgr_gem, 4096 * 2);
2095 add_bucket(bufmgr_gem, 4096 * 3);
2097 /* Initialize the linked lists for BO reuse cache. */
2098 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2099 add_bucket(bufmgr_gem, size);
2101 add_bucket(bufmgr_gem, size + size * 1 / 4);
2102 add_bucket(bufmgr_gem, size + size * 2 / 4);
2103 add_bucket(bufmgr_gem, size + size * 3 / 4);
2108 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2109 * and manage map buffer objections.
2111 * \param fd File descriptor of the opened DRM device.
2114 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2116 drm_intel_bufmgr_gem *bufmgr_gem;
2117 struct drm_i915_gem_get_aperture aperture;
2118 drm_i915_getparam_t gp;
2122 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2123 if (bufmgr_gem == NULL)
2126 bufmgr_gem->fd = fd;
2128 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2133 ret = drmIoctl(bufmgr_gem->fd,
2134 DRM_IOCTL_I915_GEM_GET_APERTURE,
2138 bufmgr_gem->gtt_size = aperture.aper_available_size;
2140 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2142 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2143 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2144 "May lead to reduced performance or incorrect "
2146 (int)bufmgr_gem->gtt_size / 1024);
2149 gp.param = I915_PARAM_CHIPSET_ID;
2150 gp.value = &bufmgr_gem->pci_device;
2151 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2153 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2154 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2157 if (IS_GEN2(bufmgr_gem))
2158 bufmgr_gem->gen = 2;
2159 else if (IS_GEN3(bufmgr_gem))
2160 bufmgr_gem->gen = 3;
2161 else if (IS_GEN4(bufmgr_gem))
2162 bufmgr_gem->gen = 4;
2164 bufmgr_gem->gen = 6;
2168 gp.param = I915_PARAM_HAS_EXECBUF2;
2169 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2173 gp.param = I915_PARAM_HAS_BSD;
2174 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2175 bufmgr_gem->has_bsd = ret == 0;
2177 gp.param = I915_PARAM_HAS_BLT;
2178 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2179 bufmgr_gem->has_blt = ret == 0;
2181 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2182 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2183 bufmgr_gem->has_relaxed_fencing = ret == 0;
2185 if (bufmgr_gem->gen < 4) {
2186 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2187 gp.value = &bufmgr_gem->available_fences;
2188 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2190 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2192 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2194 bufmgr_gem->available_fences = 0;
2196 /* XXX The kernel reports the total number of fences,
2197 * including any that may be pinned.
2199 * We presume that there will be at least one pinned
2200 * fence for the scanout buffer, but there may be more
2201 * than one scanout and the user may be manually
2202 * pinning buffers. Let's move to execbuffer2 and
2203 * thereby forget the insanity of using fences...
2205 bufmgr_gem->available_fences -= 2;
2206 if (bufmgr_gem->available_fences < 0)
2207 bufmgr_gem->available_fences = 0;
2211 /* Let's go with one relocation per every 2 dwords (but round down a bit
2212 * since a power of two will mean an extra page allocation for the reloc
2215 * Every 4 was too few for the blender benchmark.
2217 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2219 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2220 bufmgr_gem->bufmgr.bo_alloc_for_render =
2221 drm_intel_gem_bo_alloc_for_render;
2222 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2223 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2224 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2225 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2226 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2227 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2228 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2229 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2230 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2231 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2232 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2233 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2234 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2235 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2236 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2237 /* Use the new one if available */
2239 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2240 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2242 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2243 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2244 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2245 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2246 bufmgr_gem->bufmgr.debug = 0;
2247 bufmgr_gem->bufmgr.check_aperture_space =
2248 drm_intel_gem_check_aperture_space;
2249 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2250 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2251 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2252 drm_intel_gem_get_pipe_from_crtc_id;
2253 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2255 DRMINITLISTHEAD(&bufmgr_gem->named);
2256 init_cache_buckets(bufmgr_gem);
2258 return &bufmgr_gem->bufmgr;