1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
104 } drm_intel_bufmgr_gem;
106 #define DRM_INTEL_RELOC_FENCE (1<<0)
108 typedef struct _drm_intel_reloc_target_info {
111 } drm_intel_reloc_target;
113 struct _drm_intel_bo_gem {
121 * Kenel-assigned global name for this object
123 unsigned int global_name;
126 * Index of the buffer within the validation list while preparing a
127 * batchbuffer execution.
132 * Current tiling mode
134 uint32_t tiling_mode;
135 uint32_t swizzle_mode;
136 unsigned long stride;
140 /** Array passed to the DRM containing relocation information. */
141 struct drm_i915_gem_relocation_entry *relocs;
143 * Array of info structs corresponding to relocs[i].target_handle etc
145 drm_intel_reloc_target *reloc_target_info;
146 /** Number of entries in relocs */
148 /** Mapped address for the buffer, saved across map/unmap cycles */
150 /** GTT virtual address for the buffer, saved across map/unmap cycles */
157 * Boolean of whether this BO and its children have been included in
158 * the current drm_intel_bufmgr_check_aperture_space() total.
160 char included_in_check_aperture;
163 * Boolean of whether this buffer has been used as a relocation
164 * target and had its size accounted for, and thus can't have any
165 * further relocations added to it.
167 char used_as_reloc_target;
170 * Boolean of whether we have encountered an error whilst building the relocation tree.
175 * Boolean of whether this buffer can be re-used
180 * Size in bytes of this buffer and its relocation descendents.
182 * Used to avoid costly tree walking in
183 * drm_intel_bufmgr_check_aperture in the common case.
188 * Number of potential fence registers required by this buffer and its
191 int reloc_tree_fences;
195 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
198 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
201 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
202 uint32_t * swizzle_mode);
205 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
206 uint32_t tiling_mode,
209 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
212 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
214 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
217 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
218 uint32_t *tiling_mode)
220 unsigned long min_size, max_size;
223 if (*tiling_mode == I915_TILING_NONE)
226 /* 965+ just need multiples of page size for tiling */
227 if (bufmgr_gem->gen >= 4)
228 return ROUND_UP_TO(size, 4096);
230 /* Older chips need powers of two, of at least 512k or 1M */
231 if (bufmgr_gem->gen == 3) {
232 min_size = 1024*1024;
233 max_size = 128*1024*1024;
236 max_size = 64*1024*1024;
239 if (size > max_size) {
240 *tiling_mode = I915_TILING_NONE;
244 for (i = min_size; i < size; i <<= 1)
251 * Round a given pitch up to the minimum required for X tiling on a
252 * given chip. We use 512 as the minimum to allow for a later tiling
256 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
257 unsigned long pitch, uint32_t *tiling_mode)
259 unsigned long tile_width;
262 /* If untiled, then just align it so that we can do rendering
263 * to it with the 3D engine.
265 if (*tiling_mode == I915_TILING_NONE)
266 return ALIGN(pitch, 64);
268 if (*tiling_mode == I915_TILING_X)
273 /* 965 is flexible */
274 if (bufmgr_gem->gen >= 4)
275 return ROUND_UP_TO(pitch, tile_width);
277 /* The older hardware has a maximum pitch of 8192 with tiled
278 * surfaces, so fallback to untiled if it's too large.
281 *tiling_mode = I915_TILING_NONE;
282 return ALIGN(pitch, 64);
285 /* Pre-965 needs power of two tile width */
286 for (i = tile_width; i < pitch; i <<= 1)
292 static struct drm_intel_gem_bo_bucket *
293 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
298 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
299 struct drm_intel_gem_bo_bucket *bucket =
300 &bufmgr_gem->cache_bucket[i];
301 if (bucket->size >= size) {
310 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
314 for (i = 0; i < bufmgr_gem->exec_count; i++) {
315 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
316 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
318 if (bo_gem->relocs == NULL) {
319 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
324 for (j = 0; j < bo_gem->reloc_count; j++) {
325 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
326 drm_intel_bo_gem *target_gem =
327 (drm_intel_bo_gem *) target_bo;
329 DBG("%2d: %d (%s)@0x%08llx -> "
330 "%d (%s)@0x%08lx + 0x%08x\n",
332 bo_gem->gem_handle, bo_gem->name,
333 (unsigned long long)bo_gem->relocs[j].offset,
334 target_gem->gem_handle,
337 bo_gem->relocs[j].delta);
343 drm_intel_gem_bo_reference(drm_intel_bo *bo)
345 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
347 assert(atomic_read(&bo_gem->refcount) > 0);
348 atomic_inc(&bo_gem->refcount);
352 * Adds the given buffer to the list of buffers to be validated (moved into the
353 * appropriate memory type) with the next batch submission.
355 * If a buffer is validated multiple times in a batch submission, it ends up
356 * with the intersection of the memory type flags and the union of the
360 drm_intel_add_validate_buffer(drm_intel_bo *bo)
362 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
363 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
366 if (bo_gem->validate_index != -1)
369 /* Extend the array of validation entries as necessary. */
370 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
371 int new_size = bufmgr_gem->exec_size * 2;
376 bufmgr_gem->exec_objects =
377 realloc(bufmgr_gem->exec_objects,
378 sizeof(*bufmgr_gem->exec_objects) * new_size);
379 bufmgr_gem->exec_bos =
380 realloc(bufmgr_gem->exec_bos,
381 sizeof(*bufmgr_gem->exec_bos) * new_size);
382 bufmgr_gem->exec_size = new_size;
385 index = bufmgr_gem->exec_count;
386 bo_gem->validate_index = index;
387 /* Fill in array entry */
388 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
389 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
390 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
391 bufmgr_gem->exec_objects[index].alignment = 0;
392 bufmgr_gem->exec_objects[index].offset = 0;
393 bufmgr_gem->exec_bos[index] = bo;
394 bufmgr_gem->exec_count++;
398 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
400 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
401 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
404 if (bo_gem->validate_index != -1) {
406 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
407 EXEC_OBJECT_NEEDS_FENCE;
411 /* Extend the array of validation entries as necessary. */
412 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
413 int new_size = bufmgr_gem->exec_size * 2;
418 bufmgr_gem->exec2_objects =
419 realloc(bufmgr_gem->exec2_objects,
420 sizeof(*bufmgr_gem->exec2_objects) * new_size);
421 bufmgr_gem->exec_bos =
422 realloc(bufmgr_gem->exec_bos,
423 sizeof(*bufmgr_gem->exec_bos) * new_size);
424 bufmgr_gem->exec_size = new_size;
427 index = bufmgr_gem->exec_count;
428 bo_gem->validate_index = index;
429 /* Fill in array entry */
430 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
431 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
432 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
433 bufmgr_gem->exec2_objects[index].alignment = 0;
434 bufmgr_gem->exec2_objects[index].offset = 0;
435 bufmgr_gem->exec_bos[index] = bo;
436 bufmgr_gem->exec2_objects[index].flags = 0;
437 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
438 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
440 bufmgr_gem->exec2_objects[index].flags |=
441 EXEC_OBJECT_NEEDS_FENCE;
443 bufmgr_gem->exec_count++;
446 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
450 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
451 drm_intel_bo_gem *bo_gem)
455 assert(!bo_gem->used_as_reloc_target);
457 /* The older chipsets are far-less flexible in terms of tiling,
458 * and require tiled buffer to be size aligned in the aperture.
459 * This means that in the worst possible case we will need a hole
460 * twice as large as the object in order for it to fit into the
461 * aperture. Optimal packing is for wimps.
463 size = bo_gem->bo.size;
464 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
467 bo_gem->reloc_tree_size = size;
471 drm_intel_setup_reloc_list(drm_intel_bo *bo)
473 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
474 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
475 unsigned int max_relocs = bufmgr_gem->max_relocs;
477 if (bo->size / 4 < max_relocs)
478 max_relocs = bo->size / 4;
480 bo_gem->relocs = malloc(max_relocs *
481 sizeof(struct drm_i915_gem_relocation_entry));
482 bo_gem->reloc_target_info = malloc(max_relocs *
483 sizeof(drm_intel_reloc_target));
484 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
485 bo_gem->has_error = 1;
487 free (bo_gem->relocs);
488 bo_gem->relocs = NULL;
490 free (bo_gem->reloc_target_info);
491 bo_gem->reloc_target_info = NULL;
500 drm_intel_gem_bo_busy(drm_intel_bo *bo)
502 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
503 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
504 struct drm_i915_gem_busy busy;
507 memset(&busy, 0, sizeof(busy));
508 busy.handle = bo_gem->gem_handle;
510 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
512 return (ret == 0 && busy.busy);
516 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
517 drm_intel_bo_gem *bo_gem, int state)
519 struct drm_i915_gem_madvise madv;
521 madv.handle = bo_gem->gem_handle;
524 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
526 return madv.retained;
530 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
532 return drm_intel_gem_bo_madvise_internal
533 ((drm_intel_bufmgr_gem *) bo->bufmgr,
534 (drm_intel_bo_gem *) bo,
538 /* drop the oldest entries that have been purged by the kernel */
540 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
541 struct drm_intel_gem_bo_bucket *bucket)
543 while (!DRMLISTEMPTY(&bucket->head)) {
544 drm_intel_bo_gem *bo_gem;
546 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
547 bucket->head.next, head);
548 if (drm_intel_gem_bo_madvise_internal
549 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
552 DRMLISTDEL(&bo_gem->head);
553 drm_intel_gem_bo_free(&bo_gem->bo);
557 static drm_intel_bo *
558 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
562 uint32_t tiling_mode,
563 unsigned long stride)
565 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
566 drm_intel_bo_gem *bo_gem;
567 unsigned int page_size = getpagesize();
569 struct drm_intel_gem_bo_bucket *bucket;
570 int alloc_from_cache;
571 unsigned long bo_size;
574 if (flags & BO_ALLOC_FOR_RENDER)
577 /* Round the allocated size up to a power of two number of pages. */
578 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
580 /* If we don't have caching at this size, don't actually round the
583 if (bucket == NULL) {
585 if (bo_size < page_size)
588 bo_size = bucket->size;
591 pthread_mutex_lock(&bufmgr_gem->lock);
592 /* Get a buffer out of the cache if available */
594 alloc_from_cache = 0;
595 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
597 /* Allocate new render-target BOs from the tail (MRU)
598 * of the list, as it will likely be hot in the GPU
599 * cache and in the aperture for us.
601 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
602 bucket->head.prev, head);
603 DRMLISTDEL(&bo_gem->head);
604 alloc_from_cache = 1;
606 /* For non-render-target BOs (where we're probably
607 * going to map it first thing in order to fill it
608 * with data), check if the last BO in the cache is
609 * unbusy, and only reuse in that case. Otherwise,
610 * allocating a new buffer is probably faster than
611 * waiting for the GPU to finish.
613 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
614 bucket->head.next, head);
615 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
616 alloc_from_cache = 1;
617 DRMLISTDEL(&bo_gem->head);
621 if (alloc_from_cache) {
622 if (!drm_intel_gem_bo_madvise_internal
623 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
624 drm_intel_gem_bo_free(&bo_gem->bo);
625 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
630 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
633 drm_intel_gem_bo_free(&bo_gem->bo);
638 pthread_mutex_unlock(&bufmgr_gem->lock);
640 if (!alloc_from_cache) {
641 struct drm_i915_gem_create create;
643 bo_gem = calloc(1, sizeof(*bo_gem));
647 bo_gem->bo.size = bo_size;
648 memset(&create, 0, sizeof(create));
649 create.size = bo_size;
651 ret = drmIoctl(bufmgr_gem->fd,
652 DRM_IOCTL_I915_GEM_CREATE,
654 bo_gem->gem_handle = create.handle;
655 bo_gem->bo.handle = bo_gem->gem_handle;
660 bo_gem->bo.bufmgr = bufmgr;
662 bo_gem->tiling_mode = I915_TILING_NONE;
663 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
666 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
669 drm_intel_gem_bo_free(&bo_gem->bo);
675 atomic_set(&bo_gem->refcount, 1);
676 bo_gem->validate_index = -1;
677 bo_gem->reloc_tree_fences = 0;
678 bo_gem->used_as_reloc_target = 0;
679 bo_gem->has_error = 0;
680 bo_gem->reusable = 1;
682 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
684 DBG("bo_create: buf %d (%s) %ldb\n",
685 bo_gem->gem_handle, bo_gem->name, size);
690 static drm_intel_bo *
691 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
694 unsigned int alignment)
696 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
698 I915_TILING_NONE, 0);
701 static drm_intel_bo *
702 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
705 unsigned int alignment)
707 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
708 I915_TILING_NONE, 0);
711 static drm_intel_bo *
712 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
713 int x, int y, int cpp, uint32_t *tiling_mode,
714 unsigned long *pitch, unsigned long flags)
716 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
717 unsigned long size, stride;
721 unsigned long aligned_y;
723 tiling = *tiling_mode;
725 /* If we're tiled, our allocations are in 8 or 32-row blocks,
726 * so failure to align our height means that we won't allocate
729 * If we're untiled, we still have to align to 2 rows high
730 * because the data port accesses 2x2 blocks even if the
731 * bottom row isn't to be rendered, so failure to align means
732 * we could walk off the end of the GTT and fault. This is
733 * documented on 965, and may be the case on older chipsets
734 * too so we try to be careful.
737 if (tiling == I915_TILING_NONE)
738 aligned_y = ALIGN(y, 2);
739 else if (tiling == I915_TILING_X)
740 aligned_y = ALIGN(y, 8);
741 else if (tiling == I915_TILING_Y)
742 aligned_y = ALIGN(y, 32);
745 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
746 size = stride * aligned_y;
747 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
748 } while (*tiling_mode != tiling);
751 if (tiling == I915_TILING_NONE)
754 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
759 * Returns a drm_intel_bo wrapping the given buffer object handle.
761 * This can be used when one application needs to pass a buffer object
765 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
769 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
770 drm_intel_bo_gem *bo_gem;
772 struct drm_gem_open open_arg;
773 struct drm_i915_gem_get_tiling get_tiling;
775 bo_gem = calloc(1, sizeof(*bo_gem));
779 memset(&open_arg, 0, sizeof(open_arg));
780 open_arg.name = handle;
781 ret = drmIoctl(bufmgr_gem->fd,
785 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
786 name, handle, strerror(errno));
790 bo_gem->bo.size = open_arg.size;
791 bo_gem->bo.offset = 0;
792 bo_gem->bo.virtual = NULL;
793 bo_gem->bo.bufmgr = bufmgr;
795 atomic_set(&bo_gem->refcount, 1);
796 bo_gem->validate_index = -1;
797 bo_gem->gem_handle = open_arg.handle;
798 bo_gem->global_name = handle;
799 bo_gem->reusable = 0;
801 memset(&get_tiling, 0, sizeof(get_tiling));
802 get_tiling.handle = bo_gem->gem_handle;
803 ret = drmIoctl(bufmgr_gem->fd,
804 DRM_IOCTL_I915_GEM_GET_TILING,
807 drm_intel_gem_bo_unreference(&bo_gem->bo);
810 bo_gem->tiling_mode = get_tiling.tiling_mode;
811 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
812 /* XXX stride is unknown */
813 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
815 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
821 drm_intel_gem_bo_free(drm_intel_bo *bo)
823 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
824 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
825 struct drm_gem_close close;
828 if (bo_gem->mem_virtual)
829 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
830 if (bo_gem->gtt_virtual)
831 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
833 /* Close this object */
834 memset(&close, 0, sizeof(close));
835 close.handle = bo_gem->gem_handle;
836 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
839 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
840 bo_gem->gem_handle, bo_gem->name, strerror(errno));
845 /** Frees all cached buffers significantly older than @time. */
847 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
851 if (bufmgr_gem->time == time)
854 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
855 struct drm_intel_gem_bo_bucket *bucket =
856 &bufmgr_gem->cache_bucket[i];
858 while (!DRMLISTEMPTY(&bucket->head)) {
859 drm_intel_bo_gem *bo_gem;
861 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
862 bucket->head.next, head);
863 if (time - bo_gem->free_time <= 1)
866 DRMLISTDEL(&bo_gem->head);
868 drm_intel_gem_bo_free(&bo_gem->bo);
872 bufmgr_gem->time = time;
876 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
878 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
879 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
880 struct drm_intel_gem_bo_bucket *bucket;
883 /* Unreference all the target buffers */
884 for (i = 0; i < bo_gem->reloc_count; i++) {
885 if (bo_gem->reloc_target_info[i].bo != bo) {
886 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
887 reloc_target_info[i].bo,
891 bo_gem->reloc_count = 0;
892 bo_gem->used_as_reloc_target = 0;
894 DBG("bo_unreference final: %d (%s)\n",
895 bo_gem->gem_handle, bo_gem->name);
897 /* release memory associated with this object */
898 if (bo_gem->reloc_target_info) {
899 free(bo_gem->reloc_target_info);
900 bo_gem->reloc_target_info = NULL;
902 if (bo_gem->relocs) {
903 free(bo_gem->relocs);
904 bo_gem->relocs = NULL;
907 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
908 /* Put the buffer into our internal cache for reuse if we can. */
909 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
910 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
911 I915_MADV_DONTNEED)) {
912 bo_gem->free_time = time;
915 bo_gem->validate_index = -1;
917 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
919 drm_intel_gem_bo_free(bo);
923 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
926 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
928 assert(atomic_read(&bo_gem->refcount) > 0);
929 if (atomic_dec_and_test(&bo_gem->refcount))
930 drm_intel_gem_bo_unreference_final(bo, time);
933 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
935 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
937 assert(atomic_read(&bo_gem->refcount) > 0);
938 if (atomic_dec_and_test(&bo_gem->refcount)) {
939 drm_intel_bufmgr_gem *bufmgr_gem =
940 (drm_intel_bufmgr_gem *) bo->bufmgr;
941 struct timespec time;
943 clock_gettime(CLOCK_MONOTONIC, &time);
945 pthread_mutex_lock(&bufmgr_gem->lock);
946 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
947 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
948 pthread_mutex_unlock(&bufmgr_gem->lock);
952 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
954 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
955 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
956 struct drm_i915_gem_set_domain set_domain;
959 pthread_mutex_lock(&bufmgr_gem->lock);
961 /* Allow recursive mapping. Mesa may recursively map buffers with
962 * nested display loops.
964 if (!bo_gem->mem_virtual) {
965 struct drm_i915_gem_mmap mmap_arg;
967 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
969 memset(&mmap_arg, 0, sizeof(mmap_arg));
970 mmap_arg.handle = bo_gem->gem_handle;
972 mmap_arg.size = bo->size;
973 ret = drmIoctl(bufmgr_gem->fd,
974 DRM_IOCTL_I915_GEM_MMAP,
979 "%s:%d: Error mapping buffer %d (%s): %s .\n",
980 __FILE__, __LINE__, bo_gem->gem_handle,
981 bo_gem->name, strerror(errno));
982 pthread_mutex_unlock(&bufmgr_gem->lock);
985 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
987 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
988 bo_gem->mem_virtual);
989 bo->virtual = bo_gem->mem_virtual;
991 set_domain.handle = bo_gem->gem_handle;
992 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
994 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
996 set_domain.write_domain = 0;
997 ret = drmIoctl(bufmgr_gem->fd,
998 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1001 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
1002 __FILE__, __LINE__, bo_gem->gem_handle,
1006 pthread_mutex_unlock(&bufmgr_gem->lock);
1011 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1013 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1014 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1015 struct drm_i915_gem_set_domain set_domain;
1018 pthread_mutex_lock(&bufmgr_gem->lock);
1020 /* Get a mapping of the buffer if we haven't before. */
1021 if (bo_gem->gtt_virtual == NULL) {
1022 struct drm_i915_gem_mmap_gtt mmap_arg;
1024 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1027 memset(&mmap_arg, 0, sizeof(mmap_arg));
1028 mmap_arg.handle = bo_gem->gem_handle;
1030 /* Get the fake offset back... */
1031 ret = drmIoctl(bufmgr_gem->fd,
1032 DRM_IOCTL_I915_GEM_MMAP_GTT,
1037 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
1039 bo_gem->gem_handle, bo_gem->name,
1041 pthread_mutex_unlock(&bufmgr_gem->lock);
1046 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1047 MAP_SHARED, bufmgr_gem->fd,
1049 if (bo_gem->gtt_virtual == MAP_FAILED) {
1050 bo_gem->gtt_virtual = NULL;
1053 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1055 bo_gem->gem_handle, bo_gem->name,
1057 pthread_mutex_unlock(&bufmgr_gem->lock);
1062 bo->virtual = bo_gem->gtt_virtual;
1064 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1065 bo_gem->gtt_virtual);
1067 /* Now move it to the GTT domain so that the CPU caches are flushed */
1068 set_domain.handle = bo_gem->gem_handle;
1069 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1070 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1071 ret = drmIoctl(bufmgr_gem->fd,
1072 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1075 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1076 __FILE__, __LINE__, bo_gem->gem_handle,
1080 pthread_mutex_unlock(&bufmgr_gem->lock);
1085 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1087 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1088 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1094 assert(bo_gem->gtt_virtual != NULL);
1096 pthread_mutex_lock(&bufmgr_gem->lock);
1098 pthread_mutex_unlock(&bufmgr_gem->lock);
1103 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1105 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1106 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1107 struct drm_i915_gem_sw_finish sw_finish;
1113 assert(bo_gem->mem_virtual != NULL);
1115 pthread_mutex_lock(&bufmgr_gem->lock);
1117 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1118 * results show up in a timely manner.
1120 sw_finish.handle = bo_gem->gem_handle;
1121 ret = drmIoctl(bufmgr_gem->fd,
1122 DRM_IOCTL_I915_GEM_SW_FINISH,
1124 ret = ret == -1 ? -errno : 0;
1127 pthread_mutex_unlock(&bufmgr_gem->lock);
1133 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1134 unsigned long size, const void *data)
1136 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1137 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1138 struct drm_i915_gem_pwrite pwrite;
1141 memset(&pwrite, 0, sizeof(pwrite));
1142 pwrite.handle = bo_gem->gem_handle;
1143 pwrite.offset = offset;
1145 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1146 ret = drmIoctl(bufmgr_gem->fd,
1147 DRM_IOCTL_I915_GEM_PWRITE,
1152 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1153 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1154 (int)size, strerror(errno));
1161 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1163 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1164 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1167 get_pipe_from_crtc_id.crtc_id = crtc_id;
1168 ret = drmIoctl(bufmgr_gem->fd,
1169 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1170 &get_pipe_from_crtc_id);
1172 /* We return -1 here to signal that we don't
1173 * know which pipe is associated with this crtc.
1174 * This lets the caller know that this information
1175 * isn't available; using the wrong pipe for
1176 * vblank waiting can cause the chipset to lock up
1181 return get_pipe_from_crtc_id.pipe;
1185 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1186 unsigned long size, void *data)
1188 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1189 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1190 struct drm_i915_gem_pread pread;
1193 memset(&pread, 0, sizeof(pread));
1194 pread.handle = bo_gem->gem_handle;
1195 pread.offset = offset;
1197 pread.data_ptr = (uint64_t) (uintptr_t) data;
1198 ret = drmIoctl(bufmgr_gem->fd,
1199 DRM_IOCTL_I915_GEM_PREAD,
1204 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1205 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1206 (int)size, strerror(errno));
1212 /** Waits for all GPU rendering to the object to have completed. */
1214 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1216 drm_intel_gem_bo_start_gtt_access(bo, 0);
1220 * Sets the object to the GTT read and possibly write domain, used by the X
1221 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1223 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1224 * can do tiled pixmaps this way.
1227 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1229 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1230 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1231 struct drm_i915_gem_set_domain set_domain;
1234 set_domain.handle = bo_gem->gem_handle;
1235 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1236 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1237 ret = drmIoctl(bufmgr_gem->fd,
1238 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1242 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1243 __FILE__, __LINE__, bo_gem->gem_handle,
1244 set_domain.read_domains, set_domain.write_domain,
1250 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1252 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1255 free(bufmgr_gem->exec2_objects);
1256 free(bufmgr_gem->exec_objects);
1257 free(bufmgr_gem->exec_bos);
1259 pthread_mutex_destroy(&bufmgr_gem->lock);
1261 /* Free any cached buffer objects we were going to reuse */
1262 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1263 struct drm_intel_gem_bo_bucket *bucket =
1264 &bufmgr_gem->cache_bucket[i];
1265 drm_intel_bo_gem *bo_gem;
1267 while (!DRMLISTEMPTY(&bucket->head)) {
1268 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1269 bucket->head.next, head);
1270 DRMLISTDEL(&bo_gem->head);
1272 drm_intel_gem_bo_free(&bo_gem->bo);
1280 * Adds the target buffer to the validation list and adds the relocation
1281 * to the reloc_buffer's relocation list.
1283 * The relocation entry at the given offset must already contain the
1284 * precomputed relocation value, because the kernel will optimize out
1285 * the relocation entry write when the buffer hasn't moved from the
1286 * last known offset in target_bo.
1289 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1290 drm_intel_bo *target_bo, uint32_t target_offset,
1291 uint32_t read_domains, uint32_t write_domain,
1294 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1295 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1296 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1298 if (bo_gem->has_error)
1301 if (target_bo_gem->has_error) {
1302 bo_gem->has_error = 1;
1306 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1309 /* We never use HW fences for rendering on 965+ */
1310 if (bufmgr_gem->gen >= 4)
1313 /* Create a new relocation list if needed */
1314 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1317 /* Check overflow */
1318 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1321 assert(offset <= bo->size - 4);
1322 assert((write_domain & (write_domain - 1)) == 0);
1324 /* Make sure that we're not adding a reloc to something whose size has
1325 * already been accounted for.
1327 assert(!bo_gem->used_as_reloc_target);
1328 if (target_bo_gem != bo_gem) {
1329 target_bo_gem->used_as_reloc_target = 1;
1330 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1332 /* An object needing a fence is a tiled buffer, so it won't have
1333 * relocs to other buffers.
1336 target_bo_gem->reloc_tree_fences = 1;
1337 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1339 /* Flag the target to disallow further relocations in it. */
1341 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1342 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1343 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1344 target_bo_gem->gem_handle;
1345 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1346 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1347 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1349 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1350 if (target_bo != bo)
1351 drm_intel_gem_bo_reference(target_bo);
1353 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1354 DRM_INTEL_RELOC_FENCE;
1356 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1358 bo_gem->reloc_count++;
1364 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1365 drm_intel_bo *target_bo, uint32_t target_offset,
1366 uint32_t read_domains, uint32_t write_domain)
1368 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1370 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1371 read_domains, write_domain,
1372 !bufmgr_gem->fenced_relocs);
1376 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1377 drm_intel_bo *target_bo,
1378 uint32_t target_offset,
1379 uint32_t read_domains, uint32_t write_domain)
1381 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1382 read_domains, write_domain, 1);
1386 * Walk the tree of relocations rooted at BO and accumulate the list of
1387 * validations to be performed and update the relocation buffers with
1388 * index values into the validation list.
1391 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1393 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1396 if (bo_gem->relocs == NULL)
1399 for (i = 0; i < bo_gem->reloc_count; i++) {
1400 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1402 if (target_bo == bo)
1405 /* Continue walking the tree depth-first. */
1406 drm_intel_gem_bo_process_reloc(target_bo);
1408 /* Add the target to the validate list */
1409 drm_intel_add_validate_buffer(target_bo);
1414 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1416 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1419 if (bo_gem->relocs == NULL)
1422 for (i = 0; i < bo_gem->reloc_count; i++) {
1423 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1426 if (target_bo == bo)
1429 /* Continue walking the tree depth-first. */
1430 drm_intel_gem_bo_process_reloc2(target_bo);
1432 need_fence = (bo_gem->reloc_target_info[i].flags &
1433 DRM_INTEL_RELOC_FENCE);
1435 /* Add the target to the validate list */
1436 drm_intel_add_validate_buffer2(target_bo, need_fence);
1442 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1446 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1447 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1448 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1450 /* Update the buffer offset */
1451 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1452 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1453 bo_gem->gem_handle, bo_gem->name, bo->offset,
1454 (unsigned long long)bufmgr_gem->exec_objects[i].
1456 bo->offset = bufmgr_gem->exec_objects[i].offset;
1462 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1466 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1467 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1468 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1470 /* Update the buffer offset */
1471 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1472 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1473 bo_gem->gem_handle, bo_gem->name, bo->offset,
1474 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1475 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1481 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1482 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1484 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1485 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1486 struct drm_i915_gem_execbuffer execbuf;
1489 if (bo_gem->has_error)
1492 pthread_mutex_lock(&bufmgr_gem->lock);
1493 /* Update indices and set up the validate list. */
1494 drm_intel_gem_bo_process_reloc(bo);
1496 /* Add the batch buffer to the validation list. There are no
1497 * relocations pointing to it.
1499 drm_intel_add_validate_buffer(bo);
1501 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1502 execbuf.buffer_count = bufmgr_gem->exec_count;
1503 execbuf.batch_start_offset = 0;
1504 execbuf.batch_len = used;
1505 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1506 execbuf.num_cliprects = num_cliprects;
1510 ret = drmIoctl(bufmgr_gem->fd,
1511 DRM_IOCTL_I915_GEM_EXECBUFFER,
1515 if (errno == ENOSPC) {
1517 "Execbuffer fails to pin. "
1518 "Estimate: %u. Actual: %u. Available: %u\n",
1519 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1522 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1525 (unsigned int)bufmgr_gem->gtt_size);
1528 drm_intel_update_buffer_offsets(bufmgr_gem);
1530 if (bufmgr_gem->bufmgr.debug)
1531 drm_intel_gem_dump_validation_list(bufmgr_gem);
1533 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1534 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1535 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1537 /* Disconnect the buffer from the validate list */
1538 bo_gem->validate_index = -1;
1539 bufmgr_gem->exec_bos[i] = NULL;
1541 bufmgr_gem->exec_count = 0;
1542 pthread_mutex_unlock(&bufmgr_gem->lock);
1548 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1549 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1552 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1553 struct drm_i915_gem_execbuffer2 execbuf;
1556 if ((ring_flag != I915_EXEC_RENDER) && (ring_flag != I915_EXEC_BSD))
1559 pthread_mutex_lock(&bufmgr_gem->lock);
1560 /* Update indices and set up the validate list. */
1561 drm_intel_gem_bo_process_reloc2(bo);
1563 /* Add the batch buffer to the validation list. There are no relocations
1566 drm_intel_add_validate_buffer2(bo, 0);
1568 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1569 execbuf.buffer_count = bufmgr_gem->exec_count;
1570 execbuf.batch_start_offset = 0;
1571 execbuf.batch_len = used;
1572 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1573 execbuf.num_cliprects = num_cliprects;
1576 execbuf.flags = ring_flag;
1580 ret = drmIoctl(bufmgr_gem->fd,
1581 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1585 if (ret == -ENOSPC) {
1587 "Execbuffer fails to pin. "
1588 "Estimate: %u. Actual: %u. Available: %u\n",
1589 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1590 bufmgr_gem->exec_count),
1591 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1592 bufmgr_gem->exec_count),
1593 (unsigned int) bufmgr_gem->gtt_size);
1596 drm_intel_update_buffer_offsets2(bufmgr_gem);
1598 if (bufmgr_gem->bufmgr.debug)
1599 drm_intel_gem_dump_validation_list(bufmgr_gem);
1601 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1602 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1603 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1605 /* Disconnect the buffer from the validate list */
1606 bo_gem->validate_index = -1;
1607 bufmgr_gem->exec_bos[i] = NULL;
1609 bufmgr_gem->exec_count = 0;
1610 pthread_mutex_unlock(&bufmgr_gem->lock);
1616 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1617 drm_clip_rect_t *cliprects, int num_cliprects,
1620 return drm_intel_gem_bo_mrb_exec2(bo, used,
1621 cliprects, num_cliprects, DR4,
1626 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1628 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1629 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1630 struct drm_i915_gem_pin pin;
1633 memset(&pin, 0, sizeof(pin));
1634 pin.handle = bo_gem->gem_handle;
1635 pin.alignment = alignment;
1637 ret = drmIoctl(bufmgr_gem->fd,
1638 DRM_IOCTL_I915_GEM_PIN,
1643 bo->offset = pin.offset;
1648 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1650 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1651 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1652 struct drm_i915_gem_unpin unpin;
1655 memset(&unpin, 0, sizeof(unpin));
1656 unpin.handle = bo_gem->gem_handle;
1658 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1666 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1667 uint32_t tiling_mode,
1670 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1671 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1672 struct drm_i915_gem_set_tiling set_tiling;
1675 if (bo_gem->global_name == 0 &&
1676 tiling_mode == bo_gem->tiling_mode &&
1677 stride == bo_gem->stride)
1680 memset(&set_tiling, 0, sizeof(set_tiling));
1682 /* set_tiling is slightly broken and overwrites the
1683 * input on the error path, so we have to open code
1686 set_tiling.handle = bo_gem->gem_handle;
1687 set_tiling.tiling_mode = tiling_mode;
1688 set_tiling.stride = stride;
1690 ret = ioctl(bufmgr_gem->fd,
1691 DRM_IOCTL_I915_GEM_SET_TILING,
1693 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1697 bo_gem->tiling_mode = set_tiling.tiling_mode;
1698 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1699 bo_gem->stride = set_tiling.stride;
1704 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1707 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1708 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1711 /* Linear buffers have no stride. By ensuring that we only ever use
1712 * stride 0 with linear buffers, we simplify our code.
1714 if (*tiling_mode == I915_TILING_NONE)
1717 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1719 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1721 *tiling_mode = bo_gem->tiling_mode;
1726 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1727 uint32_t * swizzle_mode)
1729 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1731 *tiling_mode = bo_gem->tiling_mode;
1732 *swizzle_mode = bo_gem->swizzle_mode;
1737 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1739 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1740 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1741 struct drm_gem_flink flink;
1744 if (!bo_gem->global_name) {
1745 memset(&flink, 0, sizeof(flink));
1746 flink.handle = bo_gem->gem_handle;
1748 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1751 bo_gem->global_name = flink.name;
1752 bo_gem->reusable = 0;
1755 *name = bo_gem->global_name;
1760 * Enables unlimited caching of buffer objects for reuse.
1762 * This is potentially very memory expensive, as the cache at each bucket
1763 * size is only bounded by how many buffers of that size we've managed to have
1764 * in flight at once.
1767 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1769 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1771 bufmgr_gem->bo_reuse = 1;
1775 * Enable use of fenced reloc type.
1777 * New code should enable this to avoid unnecessary fence register
1778 * allocation. If this option is not enabled, all relocs will have fence
1779 * register allocated.
1782 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1784 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1786 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1787 bufmgr_gem->fenced_relocs = 1;
1791 * Return the additional aperture space required by the tree of buffer objects
1795 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1797 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1801 if (bo == NULL || bo_gem->included_in_check_aperture)
1805 bo_gem->included_in_check_aperture = 1;
1807 for (i = 0; i < bo_gem->reloc_count; i++)
1809 drm_intel_gem_bo_get_aperture_space(bo_gem->
1810 reloc_target_info[i].bo);
1816 * Count the number of buffers in this list that need a fence reg
1818 * If the count is greater than the number of available regs, we'll have
1819 * to ask the caller to resubmit a batch with fewer tiled buffers.
1821 * This function over-counts if the same buffer is used multiple times.
1824 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1827 unsigned int total = 0;
1829 for (i = 0; i < count; i++) {
1830 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1835 total += bo_gem->reloc_tree_fences;
1841 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1842 * for the next drm_intel_bufmgr_check_aperture_space() call.
1845 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1847 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1850 if (bo == NULL || !bo_gem->included_in_check_aperture)
1853 bo_gem->included_in_check_aperture = 0;
1855 for (i = 0; i < bo_gem->reloc_count; i++)
1856 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1857 reloc_target_info[i].bo);
1861 * Return a conservative estimate for the amount of aperture required
1862 * for a collection of buffers. This may double-count some buffers.
1865 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1868 unsigned int total = 0;
1870 for (i = 0; i < count; i++) {
1871 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1873 total += bo_gem->reloc_tree_size;
1879 * Return the amount of aperture needed for a collection of buffers.
1880 * This avoids double counting any buffers, at the cost of looking
1881 * at every buffer in the set.
1884 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1887 unsigned int total = 0;
1889 for (i = 0; i < count; i++) {
1890 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1891 /* For the first buffer object in the array, we get an
1892 * accurate count back for its reloc_tree size (since nothing
1893 * had been flagged as being counted yet). We can save that
1894 * value out as a more conservative reloc_tree_size that
1895 * avoids double-counting target buffers. Since the first
1896 * buffer happens to usually be the batch buffer in our
1897 * callers, this can pull us back from doing the tree
1898 * walk on every new batch emit.
1901 drm_intel_bo_gem *bo_gem =
1902 (drm_intel_bo_gem *) bo_array[i];
1903 bo_gem->reloc_tree_size = total;
1907 for (i = 0; i < count; i++)
1908 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1913 * Return -1 if the batchbuffer should be flushed before attempting to
1914 * emit rendering referencing the buffers pointed to by bo_array.
1916 * This is required because if we try to emit a batchbuffer with relocations
1917 * to a tree of buffers that won't simultaneously fit in the aperture,
1918 * the rendering will return an error at a point where the software is not
1919 * prepared to recover from it.
1921 * However, we also want to emit the batchbuffer significantly before we reach
1922 * the limit, as a series of batchbuffers each of which references buffers
1923 * covering almost all of the aperture means that at each emit we end up
1924 * waiting to evict a buffer from the last rendering, and we get synchronous
1925 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1926 * get better parallelism.
1929 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1931 drm_intel_bufmgr_gem *bufmgr_gem =
1932 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1933 unsigned int total = 0;
1934 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1937 /* Check for fence reg constraints if necessary */
1938 if (bufmgr_gem->available_fences) {
1939 total_fences = drm_intel_gem_total_fences(bo_array, count);
1940 if (total_fences > bufmgr_gem->available_fences)
1944 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1946 if (total > threshold)
1947 total = drm_intel_gem_compute_batch_space(bo_array, count);
1949 if (total > threshold) {
1950 DBG("check_space: overflowed available aperture, "
1952 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1955 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1956 (int)bufmgr_gem->gtt_size / 1024);
1962 * Disable buffer reuse for objects which are shared with the kernel
1963 * as scanout buffers
1966 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1968 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1970 bo_gem->reusable = 0;
1975 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
1977 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1979 return bo_gem->reusable;
1983 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1985 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1988 for (i = 0; i < bo_gem->reloc_count; i++) {
1989 if (bo_gem->reloc_target_info[i].bo == target_bo)
1991 if (bo == bo_gem->reloc_target_info[i].bo)
1993 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2001 /** Return true if target_bo is referenced by bo's relocation tree. */
2003 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2005 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2007 if (bo == NULL || target_bo == NULL)
2009 if (target_bo_gem->used_as_reloc_target)
2010 return _drm_intel_gem_bo_references(bo, target_bo);
2015 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2017 unsigned int i = bufmgr_gem->num_buckets;
2019 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2021 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2022 bufmgr_gem->cache_bucket[i].size = size;
2023 bufmgr_gem->num_buckets++;
2027 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2029 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2031 /* OK, so power of two buckets was too wasteful of memory.
2032 * Give 3 other sizes between each power of two, to hopefully
2033 * cover things accurately enough. (The alternative is
2034 * probably to just go for exact matching of sizes, and assume
2035 * that for things like composited window resize the tiled
2036 * width/height alignment and rounding of sizes to pages will
2037 * get us useful cache hit rates anyway)
2039 add_bucket(bufmgr_gem, 4096);
2040 add_bucket(bufmgr_gem, 4096 * 2);
2041 add_bucket(bufmgr_gem, 4096 * 3);
2043 /* Initialize the linked lists for BO reuse cache. */
2044 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2045 add_bucket(bufmgr_gem, size);
2047 add_bucket(bufmgr_gem, size + size * 1 / 4);
2048 add_bucket(bufmgr_gem, size + size * 2 / 4);
2049 add_bucket(bufmgr_gem, size + size * 3 / 4);
2054 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2055 * and manage map buffer objections.
2057 * \param fd File descriptor of the opened DRM device.
2060 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2062 drm_intel_bufmgr_gem *bufmgr_gem;
2063 struct drm_i915_gem_get_aperture aperture;
2064 drm_i915_getparam_t gp;
2066 int exec2 = 0, has_bsd = 0;
2068 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2069 if (bufmgr_gem == NULL)
2072 bufmgr_gem->fd = fd;
2074 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2079 ret = drmIoctl(bufmgr_gem->fd,
2080 DRM_IOCTL_I915_GEM_GET_APERTURE,
2084 bufmgr_gem->gtt_size = aperture.aper_available_size;
2086 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2088 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2089 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2090 "May lead to reduced performance or incorrect "
2092 (int)bufmgr_gem->gtt_size / 1024);
2095 gp.param = I915_PARAM_CHIPSET_ID;
2096 gp.value = &bufmgr_gem->pci_device;
2097 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2099 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2100 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2103 if (IS_GEN2(bufmgr_gem))
2104 bufmgr_gem->gen = 2;
2105 else if (IS_GEN3(bufmgr_gem))
2106 bufmgr_gem->gen = 3;
2107 else if (IS_GEN4(bufmgr_gem))
2108 bufmgr_gem->gen = 4;
2110 bufmgr_gem->gen = 6;
2112 gp.param = I915_PARAM_HAS_EXECBUF2;
2113 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2117 gp.param = I915_PARAM_HAS_BSD;
2118 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2122 if (bufmgr_gem->gen < 4) {
2123 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2124 gp.value = &bufmgr_gem->available_fences;
2125 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2127 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2129 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2131 bufmgr_gem->available_fences = 0;
2133 /* XXX The kernel reports the total number of fences,
2134 * including any that may be pinned.
2136 * We presume that there will be at least one pinned
2137 * fence for the scanout buffer, but there may be more
2138 * than one scanout and the user may be manually
2139 * pinning buffers. Let's move to execbuffer2 and
2140 * thereby forget the insanity of using fences...
2142 bufmgr_gem->available_fences -= 2;
2143 if (bufmgr_gem->available_fences < 0)
2144 bufmgr_gem->available_fences = 0;
2148 /* Let's go with one relocation per every 2 dwords (but round down a bit
2149 * since a power of two will mean an extra page allocation for the reloc
2152 * Every 4 was too few for the blender benchmark.
2154 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2156 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2157 bufmgr_gem->bufmgr.bo_alloc_for_render =
2158 drm_intel_gem_bo_alloc_for_render;
2159 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2160 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2161 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2162 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2163 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2164 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2165 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2166 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2167 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2168 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2169 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2170 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2171 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2172 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2173 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2174 /* Use the new one if available */
2176 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2178 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2180 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2181 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2182 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2183 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2184 bufmgr_gem->bufmgr.debug = 0;
2185 bufmgr_gem->bufmgr.check_aperture_space =
2186 drm_intel_gem_check_aperture_space;
2187 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2188 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2189 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2190 drm_intel_gem_get_pipe_from_crtc_id;
2191 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2193 init_cache_buckets(bufmgr_gem);
2195 return &bufmgr_gem->bufmgr;