1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 struct drm_i915_gem_exec_object2 *exec2_objects;
91 drm_intel_bo **exec_bos;
95 /** Array of lists of cached gem objects of power-of-two sizes */
96 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
104 } drm_intel_bufmgr_gem;
106 #define DRM_INTEL_RELOC_FENCE (1<<0)
108 typedef struct _drm_intel_reloc_target_info {
111 } drm_intel_reloc_target;
113 struct _drm_intel_bo_gem {
121 * Kenel-assigned global name for this object
123 unsigned int global_name;
126 * Index of the buffer within the validation list while preparing a
127 * batchbuffer execution.
132 * Current tiling mode
134 uint32_t tiling_mode;
135 uint32_t swizzle_mode;
139 /** Array passed to the DRM containing relocation information. */
140 struct drm_i915_gem_relocation_entry *relocs;
142 * Array of info structs corresponding to relocs[i].target_handle etc
144 drm_intel_reloc_target *reloc_target_info;
145 /** Number of entries in relocs */
147 /** Mapped address for the buffer, saved across map/unmap cycles */
149 /** GTT virtual address for the buffer, saved across map/unmap cycles */
156 * Boolean of whether this BO and its children have been included in
157 * the current drm_intel_bufmgr_check_aperture_space() total.
159 char included_in_check_aperture;
162 * Boolean of whether this buffer has been used as a relocation
163 * target and had its size accounted for, and thus can't have any
164 * further relocations added to it.
166 char used_as_reloc_target;
169 * Boolean of whether we have encountered an error whilst building the relocation tree.
174 * Boolean of whether this buffer can be re-used
179 * Size in bytes of this buffer and its relocation descendents.
181 * Used to avoid costly tree walking in
182 * drm_intel_bufmgr_check_aperture in the common case.
187 * Number of potential fence registers required by this buffer and its
190 int reloc_tree_fences;
194 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
197 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
200 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
201 uint32_t * swizzle_mode);
204 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
207 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
210 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
212 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
215 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
216 uint32_t *tiling_mode)
218 unsigned long min_size, max_size;
221 if (*tiling_mode == I915_TILING_NONE)
224 /* 965+ just need multiples of page size for tiling */
225 if (bufmgr_gem->gen >= 4)
226 return ROUND_UP_TO(size, 4096);
228 /* Older chips need powers of two, of at least 512k or 1M */
229 if (bufmgr_gem->gen == 2) {
230 min_size = 1024*1024;
231 max_size = 128*1024*1024;
234 max_size = 64*1024*1024;
237 if (size > max_size) {
238 *tiling_mode = I915_TILING_NONE;
242 for (i = min_size; i < size; i <<= 1)
249 * Round a given pitch up to the minimum required for X tiling on a
250 * given chip. We use 512 as the minimum to allow for a later tiling
254 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
255 unsigned long pitch, uint32_t tiling_mode)
257 unsigned long tile_width = 512;
260 if (tiling_mode == I915_TILING_NONE)
261 return ROUND_UP_TO(pitch, tile_width);
263 /* 965 is flexible */
264 if (bufmgr_gem->gen >= 4)
265 return ROUND_UP_TO(pitch, tile_width);
267 /* Pre-965 needs power of two tile width */
268 for (i = tile_width; i < pitch; i <<= 1)
274 static struct drm_intel_gem_bo_bucket *
275 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
280 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
281 struct drm_intel_gem_bo_bucket *bucket =
282 &bufmgr_gem->cache_bucket[i];
283 if (bucket->size >= size) {
292 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
296 for (i = 0; i < bufmgr_gem->exec_count; i++) {
297 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
298 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
300 if (bo_gem->relocs == NULL) {
301 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
306 for (j = 0; j < bo_gem->reloc_count; j++) {
307 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
308 drm_intel_bo_gem *target_gem =
309 (drm_intel_bo_gem *) target_bo;
311 DBG("%2d: %d (%s)@0x%08llx -> "
312 "%d (%s)@0x%08lx + 0x%08x\n",
314 bo_gem->gem_handle, bo_gem->name,
315 (unsigned long long)bo_gem->relocs[j].offset,
316 target_gem->gem_handle,
319 bo_gem->relocs[j].delta);
325 drm_intel_gem_bo_reference(drm_intel_bo *bo)
327 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
329 assert(atomic_read(&bo_gem->refcount) > 0);
330 atomic_inc(&bo_gem->refcount);
334 * Adds the given buffer to the list of buffers to be validated (moved into the
335 * appropriate memory type) with the next batch submission.
337 * If a buffer is validated multiple times in a batch submission, it ends up
338 * with the intersection of the memory type flags and the union of the
342 drm_intel_add_validate_buffer(drm_intel_bo *bo)
344 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
345 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
348 if (bo_gem->validate_index != -1)
351 /* Extend the array of validation entries as necessary. */
352 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
353 int new_size = bufmgr_gem->exec_size * 2;
358 bufmgr_gem->exec_objects =
359 realloc(bufmgr_gem->exec_objects,
360 sizeof(*bufmgr_gem->exec_objects) * new_size);
361 bufmgr_gem->exec_bos =
362 realloc(bufmgr_gem->exec_bos,
363 sizeof(*bufmgr_gem->exec_bos) * new_size);
364 bufmgr_gem->exec_size = new_size;
367 index = bufmgr_gem->exec_count;
368 bo_gem->validate_index = index;
369 /* Fill in array entry */
370 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
371 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
372 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
373 bufmgr_gem->exec_objects[index].alignment = 0;
374 bufmgr_gem->exec_objects[index].offset = 0;
375 bufmgr_gem->exec_bos[index] = bo;
376 bufmgr_gem->exec_count++;
380 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
382 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
383 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
386 if (bo_gem->validate_index != -1)
389 /* Extend the array of validation entries as necessary. */
390 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
391 int new_size = bufmgr_gem->exec_size * 2;
396 bufmgr_gem->exec2_objects =
397 realloc(bufmgr_gem->exec2_objects,
398 sizeof(*bufmgr_gem->exec2_objects) * new_size);
399 bufmgr_gem->exec_bos =
400 realloc(bufmgr_gem->exec_bos,
401 sizeof(*bufmgr_gem->exec_bos) * new_size);
402 bufmgr_gem->exec_size = new_size;
405 index = bufmgr_gem->exec_count;
406 bo_gem->validate_index = index;
407 /* Fill in array entry */
408 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
409 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
410 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
411 bufmgr_gem->exec2_objects[index].alignment = 0;
412 bufmgr_gem->exec2_objects[index].offset = 0;
413 bufmgr_gem->exec_bos[index] = bo;
414 bufmgr_gem->exec2_objects[index].flags = 0;
415 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
416 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
418 bufmgr_gem->exec2_objects[index].flags |=
419 EXEC_OBJECT_NEEDS_FENCE;
421 bufmgr_gem->exec_count++;
424 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
428 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
429 drm_intel_bo_gem *bo_gem)
433 assert(!bo_gem->used_as_reloc_target);
435 /* The older chipsets are far-less flexible in terms of tiling,
436 * and require tiled buffer to be size aligned in the aperture.
437 * This means that in the worst possible case we will need a hole
438 * twice as large as the object in order for it to fit into the
439 * aperture. Optimal packing is for wimps.
441 size = bo_gem->bo.size;
442 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
445 bo_gem->reloc_tree_size = size;
449 drm_intel_setup_reloc_list(drm_intel_bo *bo)
451 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
452 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
453 unsigned int max_relocs = bufmgr_gem->max_relocs;
455 if (bo->size / 4 < max_relocs)
456 max_relocs = bo->size / 4;
458 bo_gem->relocs = malloc(max_relocs *
459 sizeof(struct drm_i915_gem_relocation_entry));
460 bo_gem->reloc_target_info = malloc(max_relocs *
461 sizeof(drm_intel_reloc_target *));
462 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
463 bo_gem->has_error = 1;
465 free (bo_gem->relocs);
466 bo_gem->relocs = NULL;
468 free (bo_gem->reloc_target_info);
469 bo_gem->reloc_target_info = NULL;
478 drm_intel_gem_bo_busy(drm_intel_bo *bo)
480 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
481 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
482 struct drm_i915_gem_busy busy;
485 memset(&busy, 0, sizeof(busy));
486 busy.handle = bo_gem->gem_handle;
489 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
490 } while (ret == -1 && errno == EINTR);
492 return (ret == 0 && busy.busy);
496 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
497 drm_intel_bo_gem *bo_gem, int state)
499 struct drm_i915_gem_madvise madv;
501 madv.handle = bo_gem->gem_handle;
504 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
506 return madv.retained;
510 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
512 return drm_intel_gem_bo_madvise_internal
513 ((drm_intel_bufmgr_gem *) bo->bufmgr,
514 (drm_intel_bo_gem *) bo,
518 /* drop the oldest entries that have been purged by the kernel */
520 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
521 struct drm_intel_gem_bo_bucket *bucket)
523 while (!DRMLISTEMPTY(&bucket->head)) {
524 drm_intel_bo_gem *bo_gem;
526 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
527 bucket->head.next, head);
528 if (drm_intel_gem_bo_madvise_internal
529 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
532 DRMLISTDEL(&bo_gem->head);
533 drm_intel_gem_bo_free(&bo_gem->bo);
537 static drm_intel_bo *
538 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
543 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
544 drm_intel_bo_gem *bo_gem;
545 unsigned int page_size = getpagesize();
547 struct drm_intel_gem_bo_bucket *bucket;
548 int alloc_from_cache;
549 unsigned long bo_size;
552 if (flags & BO_ALLOC_FOR_RENDER)
555 /* Round the allocated size up to a power of two number of pages. */
556 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
558 /* If we don't have caching at this size, don't actually round the
561 if (bucket == NULL) {
563 if (bo_size < page_size)
566 bo_size = bucket->size;
569 pthread_mutex_lock(&bufmgr_gem->lock);
570 /* Get a buffer out of the cache if available */
572 alloc_from_cache = 0;
573 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
575 /* Allocate new render-target BOs from the tail (MRU)
576 * of the list, as it will likely be hot in the GPU
577 * cache and in the aperture for us.
579 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
580 bucket->head.prev, head);
581 DRMLISTDEL(&bo_gem->head);
582 alloc_from_cache = 1;
584 /* For non-render-target BOs (where we're probably
585 * going to map it first thing in order to fill it
586 * with data), check if the last BO in the cache is
587 * unbusy, and only reuse in that case. Otherwise,
588 * allocating a new buffer is probably faster than
589 * waiting for the GPU to finish.
591 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
592 bucket->head.next, head);
593 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
594 alloc_from_cache = 1;
595 DRMLISTDEL(&bo_gem->head);
599 if (alloc_from_cache) {
600 if (!drm_intel_gem_bo_madvise_internal
601 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
602 drm_intel_gem_bo_free(&bo_gem->bo);
603 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
609 pthread_mutex_unlock(&bufmgr_gem->lock);
611 if (!alloc_from_cache) {
612 struct drm_i915_gem_create create;
614 bo_gem = calloc(1, sizeof(*bo_gem));
618 bo_gem->bo.size = bo_size;
619 memset(&create, 0, sizeof(create));
620 create.size = bo_size;
623 ret = ioctl(bufmgr_gem->fd,
624 DRM_IOCTL_I915_GEM_CREATE,
626 } while (ret == -1 && errno == EINTR);
627 bo_gem->gem_handle = create.handle;
628 bo_gem->bo.handle = bo_gem->gem_handle;
633 bo_gem->bo.bufmgr = bufmgr;
637 atomic_set(&bo_gem->refcount, 1);
638 bo_gem->validate_index = -1;
639 bo_gem->reloc_tree_fences = 0;
640 bo_gem->used_as_reloc_target = 0;
641 bo_gem->has_error = 0;
642 bo_gem->tiling_mode = I915_TILING_NONE;
643 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
644 bo_gem->reusable = 1;
646 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
648 DBG("bo_create: buf %d (%s) %ldb\n",
649 bo_gem->gem_handle, bo_gem->name, size);
654 static drm_intel_bo *
655 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
658 unsigned int alignment)
660 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
661 BO_ALLOC_FOR_RENDER);
664 static drm_intel_bo *
665 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
668 unsigned int alignment)
670 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
673 static drm_intel_bo *
674 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
675 int x, int y, int cpp, uint32_t *tiling_mode,
676 unsigned long *pitch, unsigned long flags)
678 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
680 unsigned long size, stride, aligned_y = y;
683 if (*tiling_mode == I915_TILING_NONE)
684 aligned_y = ALIGN(y, 2);
685 else if (*tiling_mode == I915_TILING_X)
686 aligned_y = ALIGN(y, 8);
687 else if (*tiling_mode == I915_TILING_Y)
688 aligned_y = ALIGN(y, 32);
691 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
692 size = stride * aligned_y;
693 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
695 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
699 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
701 drm_intel_gem_bo_unreference(bo);
711 * Returns a drm_intel_bo wrapping the given buffer object handle.
713 * This can be used when one application needs to pass a buffer object
717 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
721 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
722 drm_intel_bo_gem *bo_gem;
724 struct drm_gem_open open_arg;
725 struct drm_i915_gem_get_tiling get_tiling;
727 bo_gem = calloc(1, sizeof(*bo_gem));
731 memset(&open_arg, 0, sizeof(open_arg));
732 open_arg.name = handle;
734 ret = ioctl(bufmgr_gem->fd,
737 } while (ret == -1 && errno == EINTR);
739 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
740 name, handle, strerror(errno));
744 bo_gem->bo.size = open_arg.size;
745 bo_gem->bo.offset = 0;
746 bo_gem->bo.virtual = NULL;
747 bo_gem->bo.bufmgr = bufmgr;
749 atomic_set(&bo_gem->refcount, 1);
750 bo_gem->validate_index = -1;
751 bo_gem->gem_handle = open_arg.handle;
752 bo_gem->global_name = handle;
753 bo_gem->reusable = 0;
755 memset(&get_tiling, 0, sizeof(get_tiling));
756 get_tiling.handle = bo_gem->gem_handle;
757 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
759 drm_intel_gem_bo_unreference(&bo_gem->bo);
762 bo_gem->tiling_mode = get_tiling.tiling_mode;
763 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
764 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
766 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
772 drm_intel_gem_bo_free(drm_intel_bo *bo)
774 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
775 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
776 struct drm_gem_close close;
779 if (bo_gem->mem_virtual)
780 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
781 if (bo_gem->gtt_virtual)
782 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
784 /* Close this object */
785 memset(&close, 0, sizeof(close));
786 close.handle = bo_gem->gem_handle;
787 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
790 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
791 bo_gem->gem_handle, bo_gem->name, strerror(errno));
796 /** Frees all cached buffers significantly older than @time. */
798 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
802 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
803 struct drm_intel_gem_bo_bucket *bucket =
804 &bufmgr_gem->cache_bucket[i];
806 while (!DRMLISTEMPTY(&bucket->head)) {
807 drm_intel_bo_gem *bo_gem;
809 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
810 bucket->head.next, head);
811 if (time - bo_gem->free_time <= 1)
814 DRMLISTDEL(&bo_gem->head);
816 drm_intel_gem_bo_free(&bo_gem->bo);
822 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
824 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
825 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
826 struct drm_intel_gem_bo_bucket *bucket;
827 uint32_t tiling_mode;
830 /* Unreference all the target buffers */
831 for (i = 0; i < bo_gem->reloc_count; i++) {
832 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
833 reloc_target_info[i].bo,
836 bo_gem->reloc_count = 0;
837 bo_gem->used_as_reloc_target = 0;
839 DBG("bo_unreference final: %d (%s)\n",
840 bo_gem->gem_handle, bo_gem->name);
842 /* release memory associated with this object */
843 if (bo_gem->reloc_target_info) {
844 free(bo_gem->reloc_target_info);
845 bo_gem->reloc_target_info = NULL;
847 if (bo_gem->relocs) {
848 free(bo_gem->relocs);
849 bo_gem->relocs = NULL;
852 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
853 /* Put the buffer into our internal cache for reuse if we can. */
854 tiling_mode = I915_TILING_NONE;
855 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
856 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
857 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
858 I915_MADV_DONTNEED)) {
859 bo_gem->free_time = time;
862 bo_gem->validate_index = -1;
864 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
866 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
868 drm_intel_gem_bo_free(bo);
872 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
875 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
877 assert(atomic_read(&bo_gem->refcount) > 0);
878 if (atomic_dec_and_test(&bo_gem->refcount))
879 drm_intel_gem_bo_unreference_final(bo, time);
882 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
884 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
886 assert(atomic_read(&bo_gem->refcount) > 0);
887 if (atomic_dec_and_test(&bo_gem->refcount)) {
888 drm_intel_bufmgr_gem *bufmgr_gem =
889 (drm_intel_bufmgr_gem *) bo->bufmgr;
890 struct timespec time;
892 clock_gettime(CLOCK_MONOTONIC, &time);
894 pthread_mutex_lock(&bufmgr_gem->lock);
895 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
896 pthread_mutex_unlock(&bufmgr_gem->lock);
900 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
902 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
903 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
904 struct drm_i915_gem_set_domain set_domain;
907 pthread_mutex_lock(&bufmgr_gem->lock);
909 /* Allow recursive mapping. Mesa may recursively map buffers with
910 * nested display loops.
912 if (!bo_gem->mem_virtual) {
913 struct drm_i915_gem_mmap mmap_arg;
915 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
917 memset(&mmap_arg, 0, sizeof(mmap_arg));
918 mmap_arg.handle = bo_gem->gem_handle;
920 mmap_arg.size = bo->size;
922 ret = ioctl(bufmgr_gem->fd,
923 DRM_IOCTL_I915_GEM_MMAP,
925 } while (ret == -1 && errno == EINTR);
929 "%s:%d: Error mapping buffer %d (%s): %s .\n",
930 __FILE__, __LINE__, bo_gem->gem_handle,
931 bo_gem->name, strerror(errno));
932 pthread_mutex_unlock(&bufmgr_gem->lock);
935 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
937 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
938 bo_gem->mem_virtual);
939 bo->virtual = bo_gem->mem_virtual;
941 set_domain.handle = bo_gem->gem_handle;
942 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
944 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
946 set_domain.write_domain = 0;
948 ret = ioctl(bufmgr_gem->fd,
949 DRM_IOCTL_I915_GEM_SET_DOMAIN,
951 } while (ret == -1 && errno == EINTR);
954 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
955 __FILE__, __LINE__, bo_gem->gem_handle,
957 pthread_mutex_unlock(&bufmgr_gem->lock);
961 pthread_mutex_unlock(&bufmgr_gem->lock);
966 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
968 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
969 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
970 struct drm_i915_gem_set_domain set_domain;
973 pthread_mutex_lock(&bufmgr_gem->lock);
975 /* Get a mapping of the buffer if we haven't before. */
976 if (bo_gem->gtt_virtual == NULL) {
977 struct drm_i915_gem_mmap_gtt mmap_arg;
979 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
982 memset(&mmap_arg, 0, sizeof(mmap_arg));
983 mmap_arg.handle = bo_gem->gem_handle;
985 /* Get the fake offset back... */
987 ret = ioctl(bufmgr_gem->fd,
988 DRM_IOCTL_I915_GEM_MMAP_GTT,
990 } while (ret == -1 && errno == EINTR);
994 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
996 bo_gem->gem_handle, bo_gem->name,
998 pthread_mutex_unlock(&bufmgr_gem->lock);
1003 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1004 MAP_SHARED, bufmgr_gem->fd,
1006 if (bo_gem->gtt_virtual == MAP_FAILED) {
1007 bo_gem->gtt_virtual = NULL;
1010 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1012 bo_gem->gem_handle, bo_gem->name,
1014 pthread_mutex_unlock(&bufmgr_gem->lock);
1019 bo->virtual = bo_gem->gtt_virtual;
1021 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1022 bo_gem->gtt_virtual);
1024 /* Now move it to the GTT domain so that the CPU caches are flushed */
1025 set_domain.handle = bo_gem->gem_handle;
1026 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1027 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1029 ret = ioctl(bufmgr_gem->fd,
1030 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1032 } while (ret == -1 && errno == EINTR);
1036 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1037 __FILE__, __LINE__, bo_gem->gem_handle,
1041 pthread_mutex_unlock(&bufmgr_gem->lock);
1046 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1048 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1049 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1055 assert(bo_gem->gtt_virtual != NULL);
1057 pthread_mutex_lock(&bufmgr_gem->lock);
1059 pthread_mutex_unlock(&bufmgr_gem->lock);
1064 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1066 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1067 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1068 struct drm_i915_gem_sw_finish sw_finish;
1074 assert(bo_gem->mem_virtual != NULL);
1076 pthread_mutex_lock(&bufmgr_gem->lock);
1078 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1079 * results show up in a timely manner.
1081 sw_finish.handle = bo_gem->gem_handle;
1083 ret = ioctl(bufmgr_gem->fd,
1084 DRM_IOCTL_I915_GEM_SW_FINISH,
1086 } while (ret == -1 && errno == EINTR);
1089 pthread_mutex_unlock(&bufmgr_gem->lock);
1094 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1095 unsigned long size, const void *data)
1097 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1098 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1099 struct drm_i915_gem_pwrite pwrite;
1102 memset(&pwrite, 0, sizeof(pwrite));
1103 pwrite.handle = bo_gem->gem_handle;
1104 pwrite.offset = offset;
1106 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1108 ret = ioctl(bufmgr_gem->fd,
1109 DRM_IOCTL_I915_GEM_PWRITE,
1111 } while (ret == -1 && errno == EINTR);
1114 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1115 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1116 (int)size, strerror(errno));
1122 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1124 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1125 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1128 get_pipe_from_crtc_id.crtc_id = crtc_id;
1129 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1130 &get_pipe_from_crtc_id);
1132 /* We return -1 here to signal that we don't
1133 * know which pipe is associated with this crtc.
1134 * This lets the caller know that this information
1135 * isn't available; using the wrong pipe for
1136 * vblank waiting can cause the chipset to lock up
1141 return get_pipe_from_crtc_id.pipe;
1145 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1146 unsigned long size, void *data)
1148 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1149 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1150 struct drm_i915_gem_pread pread;
1153 memset(&pread, 0, sizeof(pread));
1154 pread.handle = bo_gem->gem_handle;
1155 pread.offset = offset;
1157 pread.data_ptr = (uint64_t) (uintptr_t) data;
1159 ret = ioctl(bufmgr_gem->fd,
1160 DRM_IOCTL_I915_GEM_PREAD,
1162 } while (ret == -1 && errno == EINTR);
1166 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1167 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1168 (int)size, strerror(errno));
1173 /** Waits for all GPU rendering to the object to have completed. */
1175 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1177 drm_intel_gem_bo_start_gtt_access(bo, 0);
1181 * Sets the object to the GTT read and possibly write domain, used by the X
1182 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1184 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1185 * can do tiled pixmaps this way.
1188 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1190 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1191 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1192 struct drm_i915_gem_set_domain set_domain;
1195 set_domain.handle = bo_gem->gem_handle;
1196 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1197 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1199 ret = ioctl(bufmgr_gem->fd,
1200 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1202 } while (ret == -1 && errno == EINTR);
1205 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1206 __FILE__, __LINE__, bo_gem->gem_handle,
1207 set_domain.read_domains, set_domain.write_domain,
1213 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1215 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1218 free(bufmgr_gem->exec2_objects);
1219 free(bufmgr_gem->exec_objects);
1220 free(bufmgr_gem->exec_bos);
1222 pthread_mutex_destroy(&bufmgr_gem->lock);
1224 /* Free any cached buffer objects we were going to reuse */
1225 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1226 struct drm_intel_gem_bo_bucket *bucket =
1227 &bufmgr_gem->cache_bucket[i];
1228 drm_intel_bo_gem *bo_gem;
1230 while (!DRMLISTEMPTY(&bucket->head)) {
1231 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1232 bucket->head.next, head);
1233 DRMLISTDEL(&bo_gem->head);
1235 drm_intel_gem_bo_free(&bo_gem->bo);
1243 * Adds the target buffer to the validation list and adds the relocation
1244 * to the reloc_buffer's relocation list.
1246 * The relocation entry at the given offset must already contain the
1247 * precomputed relocation value, because the kernel will optimize out
1248 * the relocation entry write when the buffer hasn't moved from the
1249 * last known offset in target_bo.
1252 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1253 drm_intel_bo *target_bo, uint32_t target_offset,
1254 uint32_t read_domains, uint32_t write_domain,
1257 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1258 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1259 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1261 if (bo_gem->has_error)
1264 if (target_bo_gem->has_error) {
1265 bo_gem->has_error = 1;
1269 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1272 /* We never use HW fences for rendering on 965+ */
1273 if (bufmgr_gem->gen >= 4)
1276 /* Create a new relocation list if needed */
1277 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1280 /* Check overflow */
1281 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1284 assert(offset <= bo->size - 4);
1285 assert((write_domain & (write_domain - 1)) == 0);
1287 /* Make sure that we're not adding a reloc to something whose size has
1288 * already been accounted for.
1290 assert(!bo_gem->used_as_reloc_target);
1291 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1292 /* An object needing a fence is a tiled buffer, so it won't have
1293 * relocs to other buffers.
1296 target_bo_gem->reloc_tree_fences = 1;
1297 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1299 /* Flag the target to disallow further relocations in it. */
1300 target_bo_gem->used_as_reloc_target = 1;
1302 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1303 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1304 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1305 target_bo_gem->gem_handle;
1306 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1307 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1308 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1310 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1311 drm_intel_gem_bo_reference(target_bo);
1313 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1314 DRM_INTEL_RELOC_FENCE;
1316 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1318 bo_gem->reloc_count++;
1324 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1325 drm_intel_bo *target_bo, uint32_t target_offset,
1326 uint32_t read_domains, uint32_t write_domain)
1328 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1330 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1331 read_domains, write_domain,
1332 !bufmgr_gem->fenced_relocs);
1336 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1337 drm_intel_bo *target_bo,
1338 uint32_t target_offset,
1339 uint32_t read_domains, uint32_t write_domain)
1341 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1342 read_domains, write_domain, 1);
1346 * Walk the tree of relocations rooted at BO and accumulate the list of
1347 * validations to be performed and update the relocation buffers with
1348 * index values into the validation list.
1351 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1353 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1356 if (bo_gem->relocs == NULL)
1359 for (i = 0; i < bo_gem->reloc_count; i++) {
1360 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1362 /* Continue walking the tree depth-first. */
1363 drm_intel_gem_bo_process_reloc(target_bo);
1365 /* Add the target to the validate list */
1366 drm_intel_add_validate_buffer(target_bo);
1371 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1373 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1376 if (bo_gem->relocs == NULL)
1379 for (i = 0; i < bo_gem->reloc_count; i++) {
1380 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1383 /* Continue walking the tree depth-first. */
1384 drm_intel_gem_bo_process_reloc2(target_bo);
1386 need_fence = (bo_gem->reloc_target_info[i].flags &
1387 DRM_INTEL_RELOC_FENCE);
1389 /* Add the target to the validate list */
1390 drm_intel_add_validate_buffer2(target_bo, need_fence);
1396 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1400 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1401 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1402 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1404 /* Update the buffer offset */
1405 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1406 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1407 bo_gem->gem_handle, bo_gem->name, bo->offset,
1408 (unsigned long long)bufmgr_gem->exec_objects[i].
1410 bo->offset = bufmgr_gem->exec_objects[i].offset;
1416 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1420 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1421 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1422 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1424 /* Update the buffer offset */
1425 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1426 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1427 bo_gem->gem_handle, bo_gem->name, bo->offset,
1428 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1429 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1435 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1436 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1438 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1439 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1440 struct drm_i915_gem_execbuffer execbuf;
1443 if (bo_gem->has_error)
1446 pthread_mutex_lock(&bufmgr_gem->lock);
1447 /* Update indices and set up the validate list. */
1448 drm_intel_gem_bo_process_reloc(bo);
1450 /* Add the batch buffer to the validation list. There are no
1451 * relocations pointing to it.
1453 drm_intel_add_validate_buffer(bo);
1455 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1456 execbuf.buffer_count = bufmgr_gem->exec_count;
1457 execbuf.batch_start_offset = 0;
1458 execbuf.batch_len = used;
1459 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1460 execbuf.num_cliprects = num_cliprects;
1465 ret = ioctl(bufmgr_gem->fd,
1466 DRM_IOCTL_I915_GEM_EXECBUFFER,
1468 } while (ret != 0 && errno == EINTR);
1472 if (errno == ENOSPC) {
1474 "Execbuffer fails to pin. "
1475 "Estimate: %u. Actual: %u. Available: %u\n",
1476 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1479 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1482 (unsigned int)bufmgr_gem->gtt_size);
1485 drm_intel_update_buffer_offsets(bufmgr_gem);
1487 if (bufmgr_gem->bufmgr.debug)
1488 drm_intel_gem_dump_validation_list(bufmgr_gem);
1490 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1491 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1492 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1494 /* Disconnect the buffer from the validate list */
1495 bo_gem->validate_index = -1;
1496 bufmgr_gem->exec_bos[i] = NULL;
1498 bufmgr_gem->exec_count = 0;
1499 pthread_mutex_unlock(&bufmgr_gem->lock);
1505 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1506 drm_clip_rect_t *cliprects, int num_cliprects,
1509 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1510 struct drm_i915_gem_execbuffer2 execbuf;
1513 pthread_mutex_lock(&bufmgr_gem->lock);
1514 /* Update indices and set up the validate list. */
1515 drm_intel_gem_bo_process_reloc2(bo);
1517 /* Add the batch buffer to the validation list. There are no relocations
1520 drm_intel_add_validate_buffer2(bo, 0);
1522 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1523 execbuf.buffer_count = bufmgr_gem->exec_count;
1524 execbuf.batch_start_offset = 0;
1525 execbuf.batch_len = used;
1526 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1527 execbuf.num_cliprects = num_cliprects;
1535 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
1537 } while (ret != 0 && errno == EAGAIN);
1539 if (ret != 0 && errno == ENOMEM) {
1541 "Execbuffer fails to pin. "
1542 "Estimate: %u. Actual: %u. Available: %u\n",
1543 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1544 bufmgr_gem->exec_count),
1545 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1546 bufmgr_gem->exec_count),
1547 (unsigned int) bufmgr_gem->gtt_size);
1549 drm_intel_update_buffer_offsets2(bufmgr_gem);
1551 if (bufmgr_gem->bufmgr.debug)
1552 drm_intel_gem_dump_validation_list(bufmgr_gem);
1554 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1555 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1556 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1558 /* Disconnect the buffer from the validate list */
1559 bo_gem->validate_index = -1;
1560 bufmgr_gem->exec_bos[i] = NULL;
1562 bufmgr_gem->exec_count = 0;
1563 pthread_mutex_unlock(&bufmgr_gem->lock);
1569 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1571 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1572 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1573 struct drm_i915_gem_pin pin;
1576 memset(&pin, 0, sizeof(pin));
1577 pin.handle = bo_gem->gem_handle;
1578 pin.alignment = alignment;
1581 ret = ioctl(bufmgr_gem->fd,
1582 DRM_IOCTL_I915_GEM_PIN,
1584 } while (ret == -1 && errno == EINTR);
1589 bo->offset = pin.offset;
1594 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1596 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1597 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1598 struct drm_i915_gem_unpin unpin;
1601 memset(&unpin, 0, sizeof(unpin));
1602 unpin.handle = bo_gem->gem_handle;
1604 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1612 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1615 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1616 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1617 struct drm_i915_gem_set_tiling set_tiling;
1620 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1623 memset(&set_tiling, 0, sizeof(set_tiling));
1624 set_tiling.handle = bo_gem->gem_handle;
1627 set_tiling.tiling_mode = *tiling_mode;
1628 set_tiling.stride = stride;
1630 ret = ioctl(bufmgr_gem->fd,
1631 DRM_IOCTL_I915_GEM_SET_TILING,
1633 } while (ret == -1 && errno == EINTR);
1634 bo_gem->tiling_mode = set_tiling.tiling_mode;
1635 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1637 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1639 *tiling_mode = bo_gem->tiling_mode;
1640 return ret == 0 ? 0 : -errno;
1644 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1645 uint32_t * swizzle_mode)
1647 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1649 *tiling_mode = bo_gem->tiling_mode;
1650 *swizzle_mode = bo_gem->swizzle_mode;
1655 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1657 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1658 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1659 struct drm_gem_flink flink;
1662 if (!bo_gem->global_name) {
1663 memset(&flink, 0, sizeof(flink));
1664 flink.handle = bo_gem->gem_handle;
1666 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1669 bo_gem->global_name = flink.name;
1670 bo_gem->reusable = 0;
1673 *name = bo_gem->global_name;
1678 * Enables unlimited caching of buffer objects for reuse.
1680 * This is potentially very memory expensive, as the cache at each bucket
1681 * size is only bounded by how many buffers of that size we've managed to have
1682 * in flight at once.
1685 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1687 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1689 bufmgr_gem->bo_reuse = 1;
1693 * Enable use of fenced reloc type.
1695 * New code should enable this to avoid unnecessary fence register
1696 * allocation. If this option is not enabled, all relocs will have fence
1697 * register allocated.
1700 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1702 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1704 bufmgr_gem->fenced_relocs = 1;
1708 * Return the additional aperture space required by the tree of buffer objects
1712 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1714 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1718 if (bo == NULL || bo_gem->included_in_check_aperture)
1722 bo_gem->included_in_check_aperture = 1;
1724 for (i = 0; i < bo_gem->reloc_count; i++)
1726 drm_intel_gem_bo_get_aperture_space(bo_gem->
1727 reloc_target_info[i].bo);
1733 * Count the number of buffers in this list that need a fence reg
1735 * If the count is greater than the number of available regs, we'll have
1736 * to ask the caller to resubmit a batch with fewer tiled buffers.
1738 * This function over-counts if the same buffer is used multiple times.
1741 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1744 unsigned int total = 0;
1746 for (i = 0; i < count; i++) {
1747 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1752 total += bo_gem->reloc_tree_fences;
1758 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1759 * for the next drm_intel_bufmgr_check_aperture_space() call.
1762 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1764 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1767 if (bo == NULL || !bo_gem->included_in_check_aperture)
1770 bo_gem->included_in_check_aperture = 0;
1772 for (i = 0; i < bo_gem->reloc_count; i++)
1773 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1774 reloc_target_info[i].bo);
1778 * Return a conservative estimate for the amount of aperture required
1779 * for a collection of buffers. This may double-count some buffers.
1782 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1785 unsigned int total = 0;
1787 for (i = 0; i < count; i++) {
1788 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1790 total += bo_gem->reloc_tree_size;
1796 * Return the amount of aperture needed for a collection of buffers.
1797 * This avoids double counting any buffers, at the cost of looking
1798 * at every buffer in the set.
1801 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1804 unsigned int total = 0;
1806 for (i = 0; i < count; i++) {
1807 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1808 /* For the first buffer object in the array, we get an
1809 * accurate count back for its reloc_tree size (since nothing
1810 * had been flagged as being counted yet). We can save that
1811 * value out as a more conservative reloc_tree_size that
1812 * avoids double-counting target buffers. Since the first
1813 * buffer happens to usually be the batch buffer in our
1814 * callers, this can pull us back from doing the tree
1815 * walk on every new batch emit.
1818 drm_intel_bo_gem *bo_gem =
1819 (drm_intel_bo_gem *) bo_array[i];
1820 bo_gem->reloc_tree_size = total;
1824 for (i = 0; i < count; i++)
1825 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1830 * Return -1 if the batchbuffer should be flushed before attempting to
1831 * emit rendering referencing the buffers pointed to by bo_array.
1833 * This is required because if we try to emit a batchbuffer with relocations
1834 * to a tree of buffers that won't simultaneously fit in the aperture,
1835 * the rendering will return an error at a point where the software is not
1836 * prepared to recover from it.
1838 * However, we also want to emit the batchbuffer significantly before we reach
1839 * the limit, as a series of batchbuffers each of which references buffers
1840 * covering almost all of the aperture means that at each emit we end up
1841 * waiting to evict a buffer from the last rendering, and we get synchronous
1842 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1843 * get better parallelism.
1846 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1848 drm_intel_bufmgr_gem *bufmgr_gem =
1849 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1850 unsigned int total = 0;
1851 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1854 /* Check for fence reg constraints if necessary */
1855 if (bufmgr_gem->available_fences) {
1856 total_fences = drm_intel_gem_total_fences(bo_array, count);
1857 if (total_fences > bufmgr_gem->available_fences)
1861 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1863 if (total > threshold)
1864 total = drm_intel_gem_compute_batch_space(bo_array, count);
1866 if (total > threshold) {
1867 DBG("check_space: overflowed available aperture, "
1869 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1872 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1873 (int)bufmgr_gem->gtt_size / 1024);
1879 * Disable buffer reuse for objects which are shared with the kernel
1880 * as scanout buffers
1883 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1885 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1887 bo_gem->reusable = 0;
1892 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1894 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1897 for (i = 0; i < bo_gem->reloc_count; i++) {
1898 if (bo_gem->reloc_target_info[i].bo == target_bo)
1900 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
1908 /** Return true if target_bo is referenced by bo's relocation tree. */
1910 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1912 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1914 if (bo == NULL || target_bo == NULL)
1916 if (target_bo_gem->used_as_reloc_target)
1917 return _drm_intel_gem_bo_references(bo, target_bo);
1922 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1923 * and manage map buffer objections.
1925 * \param fd File descriptor of the opened DRM device.
1928 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1930 drm_intel_bufmgr_gem *bufmgr_gem;
1931 struct drm_i915_gem_get_aperture aperture;
1932 drm_i915_getparam_t gp;
1937 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1938 if (bufmgr_gem == NULL)
1941 bufmgr_gem->fd = fd;
1943 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1948 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1951 bufmgr_gem->gtt_size = aperture.aper_available_size;
1953 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1955 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1956 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1957 "May lead to reduced performance or incorrect "
1959 (int)bufmgr_gem->gtt_size / 1024);
1962 gp.param = I915_PARAM_CHIPSET_ID;
1963 gp.value = &bufmgr_gem->pci_device;
1964 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1966 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1967 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1970 if (IS_GEN2(bufmgr_gem))
1971 bufmgr_gem->gen = 2;
1972 else if (IS_GEN3(bufmgr_gem))
1973 bufmgr_gem->gen = 3;
1974 else if (IS_GEN4(bufmgr_gem))
1975 bufmgr_gem->gen = 4;
1977 bufmgr_gem->gen = 6;
1979 gp.param = I915_PARAM_HAS_EXECBUF2;
1980 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1984 if (bufmgr_gem->gen < 4) {
1985 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1986 gp.value = &bufmgr_gem->available_fences;
1987 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1989 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1991 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1993 bufmgr_gem->available_fences = 0;
1995 /* XXX The kernel reports the total number of fences,
1996 * including any that may be pinned.
1998 * We presume that there will be at least one pinned
1999 * fence for the scanout buffer, but there may be more
2000 * than one scanout and the user may be manually
2001 * pinning buffers. Let's move to execbuffer2 and
2002 * thereby forget the insanity of using fences...
2004 bufmgr_gem->available_fences -= 2;
2005 if (bufmgr_gem->available_fences < 0)
2006 bufmgr_gem->available_fences = 0;
2010 /* Let's go with one relocation per every 2 dwords (but round down a bit
2011 * since a power of two will mean an extra page allocation for the reloc
2014 * Every 4 was too few for the blender benchmark.
2016 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2018 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2019 bufmgr_gem->bufmgr.bo_alloc_for_render =
2020 drm_intel_gem_bo_alloc_for_render;
2021 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2022 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2023 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2024 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2025 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2026 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2027 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2028 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2029 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2030 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2031 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2032 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2033 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2034 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2035 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2036 /* Use the new one if available */
2038 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2040 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2041 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2042 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2043 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2044 bufmgr_gem->bufmgr.debug = 0;
2045 bufmgr_gem->bufmgr.check_aperture_space =
2046 drm_intel_gem_check_aperture_space;
2047 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2048 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2049 drm_intel_gem_get_pipe_from_crtc_id;
2050 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2052 /* Initialize the linked lists for BO reuse cache. */
2053 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
2054 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2055 bufmgr_gem->cache_bucket[i].size = size;
2058 return &bufmgr_gem->bufmgr;