1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
111 * Kenel-assigned global name for this object
113 unsigned int global_name;
116 * Index of the buffer within the validation list while preparing a
117 * batchbuffer execution.
122 * Current tiling mode
124 uint32_t tiling_mode;
125 uint32_t swizzle_mode;
129 /** Array passed to the DRM containing relocation information. */
130 struct drm_i915_gem_relocation_entry *relocs;
131 /** Array of bos corresponding to relocs[i].target_handle */
132 drm_intel_bo **reloc_target_bo;
133 /** Number of entries in relocs */
135 /** Mapped address for the buffer, saved across map/unmap cycles */
137 /** GTT virtual address for the buffer, saved across map/unmap cycles */
144 * Boolean of whether this BO and its children have been included in
145 * the current drm_intel_bufmgr_check_aperture_space() total.
147 char included_in_check_aperture;
150 * Boolean of whether this buffer has been used as a relocation
151 * target and had its size accounted for, and thus can't have any
152 * further relocations added to it.
154 char used_as_reloc_target;
157 * Boolean of whether this buffer can be re-used
162 * Size in bytes of this buffer and its relocation descendents.
164 * Used to avoid costly tree walking in
165 * drm_intel_bufmgr_check_aperture in the common case.
170 * Number of potential fence registers required by this buffer and its
173 int reloc_tree_fences;
177 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
180 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
183 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
184 uint32_t * swizzle_mode);
187 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
190 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
193 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
195 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
198 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
199 uint32_t *tiling_mode)
201 unsigned long min_size, max_size;
204 if (*tiling_mode == I915_TILING_NONE)
207 /* 965+ just need multiples of page size for tiling */
208 if (IS_I965G(bufmgr_gem))
209 return ROUND_UP_TO(size, 4096);
211 /* Older chips need powers of two, of at least 512k or 1M */
212 if (IS_I9XX(bufmgr_gem)) {
213 min_size = 1024*1024;
214 max_size = 128*1024*1024;
217 max_size = 64*1024*1024;
220 if (size > max_size) {
221 *tiling_mode = I915_TILING_NONE;
225 for (i = min_size; i < size; i <<= 1)
232 * Round a given pitch up to the minimum required for X tiling on a
233 * given chip. We use 512 as the minimum to allow for a later tiling
237 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
238 unsigned long pitch, uint32_t tiling_mode)
240 unsigned long tile_width = 512;
243 if (tiling_mode == I915_TILING_NONE)
244 return ROUND_UP_TO(pitch, tile_width);
246 /* 965 is flexible */
247 if (IS_I965G(bufmgr_gem))
248 return ROUND_UP_TO(pitch, tile_width);
250 /* Pre-965 needs power of two tile width */
251 for (i = tile_width; i < pitch; i <<= 1)
257 static struct drm_intel_gem_bo_bucket *
258 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
263 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
264 struct drm_intel_gem_bo_bucket *bucket =
265 &bufmgr_gem->cache_bucket[i];
266 if (bucket->size >= size) {
275 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
279 for (i = 0; i < bufmgr_gem->exec_count; i++) {
280 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
281 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
283 if (bo_gem->relocs == NULL) {
284 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
289 for (j = 0; j < bo_gem->reloc_count; j++) {
290 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
291 drm_intel_bo_gem *target_gem =
292 (drm_intel_bo_gem *) target_bo;
294 DBG("%2d: %d (%s)@0x%08llx -> "
295 "%d (%s)@0x%08lx + 0x%08x\n",
297 bo_gem->gem_handle, bo_gem->name,
298 (unsigned long long)bo_gem->relocs[j].offset,
299 target_gem->gem_handle,
302 bo_gem->relocs[j].delta);
308 drm_intel_gem_bo_reference(drm_intel_bo *bo)
310 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
312 assert(atomic_read(&bo_gem->refcount) > 0);
313 atomic_inc(&bo_gem->refcount);
317 * Adds the given buffer to the list of buffers to be validated (moved into the
318 * appropriate memory type) with the next batch submission.
320 * If a buffer is validated multiple times in a batch submission, it ends up
321 * with the intersection of the memory type flags and the union of the
325 drm_intel_add_validate_buffer(drm_intel_bo *bo)
327 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
328 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
331 if (bo_gem->validate_index != -1)
334 /* Extend the array of validation entries as necessary. */
335 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
336 int new_size = bufmgr_gem->exec_size * 2;
341 bufmgr_gem->exec_objects =
342 realloc(bufmgr_gem->exec_objects,
343 sizeof(*bufmgr_gem->exec_objects) * new_size);
344 bufmgr_gem->exec_bos =
345 realloc(bufmgr_gem->exec_bos,
346 sizeof(*bufmgr_gem->exec_bos) * new_size);
347 bufmgr_gem->exec_size = new_size;
350 index = bufmgr_gem->exec_count;
351 bo_gem->validate_index = index;
352 /* Fill in array entry */
353 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
354 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
355 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
356 bufmgr_gem->exec_objects[index].alignment = 0;
357 bufmgr_gem->exec_objects[index].offset = 0;
358 bufmgr_gem->exec_bos[index] = bo;
359 bufmgr_gem->exec_count++;
362 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
366 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
367 drm_intel_bo_gem *bo_gem)
371 assert(!bo_gem->used_as_reloc_target);
373 /* The older chipsets are far-less flexible in terms of tiling,
374 * and require tiled buffer to be size aligned in the aperture.
375 * This means that in the worst possible case we will need a hole
376 * twice as large as the object in order for it to fit into the
377 * aperture. Optimal packing is for wimps.
379 size = bo_gem->bo.size;
380 if (!IS_I965G(bufmgr_gem) && bo_gem->tiling_mode != I915_TILING_NONE)
383 bo_gem->reloc_tree_size = size;
387 drm_intel_setup_reloc_list(drm_intel_bo *bo)
389 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
390 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
391 unsigned int max_relocs = bufmgr_gem->max_relocs;
393 if (bo->size / 4 < max_relocs)
394 max_relocs = bo->size / 4;
396 bo_gem->relocs = malloc(max_relocs *
397 sizeof(struct drm_i915_gem_relocation_entry));
398 bo_gem->reloc_target_bo = malloc(max_relocs * sizeof(drm_intel_bo *));
404 drm_intel_gem_bo_busy(drm_intel_bo *bo)
406 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
407 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
408 struct drm_i915_gem_busy busy;
411 memset(&busy, 0, sizeof(busy));
412 busy.handle = bo_gem->gem_handle;
415 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
416 } while (ret == -1 && errno == EINTR);
418 return (ret == 0 && busy.busy);
422 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
423 drm_intel_bo_gem *bo_gem, int state)
425 struct drm_i915_gem_madvise madv;
427 madv.handle = bo_gem->gem_handle;
430 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
432 return madv.retained;
436 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
438 return drm_intel_gem_bo_madvise_internal
439 ((drm_intel_bufmgr_gem *) bo->bufmgr,
440 (drm_intel_bo_gem *) bo,
444 /* drop the oldest entries that have been purged by the kernel */
446 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
447 struct drm_intel_gem_bo_bucket *bucket)
449 while (!DRMLISTEMPTY(&bucket->head)) {
450 drm_intel_bo_gem *bo_gem;
452 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
453 bucket->head.next, head);
454 if (drm_intel_gem_bo_madvise_internal
455 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
458 DRMLISTDEL(&bo_gem->head);
459 drm_intel_gem_bo_free(&bo_gem->bo);
463 static drm_intel_bo *
464 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
469 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
470 drm_intel_bo_gem *bo_gem;
471 unsigned int page_size = getpagesize();
473 struct drm_intel_gem_bo_bucket *bucket;
474 int alloc_from_cache;
475 unsigned long bo_size;
478 if (flags & BO_ALLOC_FOR_RENDER)
481 /* Round the allocated size up to a power of two number of pages. */
482 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
484 /* If we don't have caching at this size, don't actually round the
487 if (bucket == NULL) {
489 if (bo_size < page_size)
492 bo_size = bucket->size;
495 pthread_mutex_lock(&bufmgr_gem->lock);
496 /* Get a buffer out of the cache if available */
498 alloc_from_cache = 0;
499 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
501 /* Allocate new render-target BOs from the tail (MRU)
502 * of the list, as it will likely be hot in the GPU
503 * cache and in the aperture for us.
505 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
506 bucket->head.prev, head);
507 DRMLISTDEL(&bo_gem->head);
508 alloc_from_cache = 1;
510 /* For non-render-target BOs (where we're probably
511 * going to map it first thing in order to fill it
512 * with data), check if the last BO in the cache is
513 * unbusy, and only reuse in that case. Otherwise,
514 * allocating a new buffer is probably faster than
515 * waiting for the GPU to finish.
517 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
518 bucket->head.next, head);
519 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
520 alloc_from_cache = 1;
521 DRMLISTDEL(&bo_gem->head);
525 if (alloc_from_cache) {
526 if (!drm_intel_gem_bo_madvise_internal
527 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
528 drm_intel_gem_bo_free(&bo_gem->bo);
529 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
535 pthread_mutex_unlock(&bufmgr_gem->lock);
537 if (!alloc_from_cache) {
538 struct drm_i915_gem_create create;
540 bo_gem = calloc(1, sizeof(*bo_gem));
544 bo_gem->bo.size = bo_size;
545 memset(&create, 0, sizeof(create));
546 create.size = bo_size;
549 ret = ioctl(bufmgr_gem->fd,
550 DRM_IOCTL_I915_GEM_CREATE,
552 } while (ret == -1 && errno == EINTR);
553 bo_gem->gem_handle = create.handle;
554 bo_gem->bo.handle = bo_gem->gem_handle;
559 bo_gem->bo.bufmgr = bufmgr;
563 atomic_set(&bo_gem->refcount, 1);
564 bo_gem->validate_index = -1;
565 bo_gem->reloc_tree_fences = 0;
566 bo_gem->used_as_reloc_target = 0;
567 bo_gem->tiling_mode = I915_TILING_NONE;
568 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
569 bo_gem->reusable = 1;
571 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
573 DBG("bo_create: buf %d (%s) %ldb\n",
574 bo_gem->gem_handle, bo_gem->name, size);
579 static drm_intel_bo *
580 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
583 unsigned int alignment)
585 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
586 BO_ALLOC_FOR_RENDER);
589 static drm_intel_bo *
590 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
593 unsigned int alignment)
595 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
598 static drm_intel_bo *
599 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
600 int x, int y, int cpp, uint32_t *tiling_mode,
601 unsigned long *pitch, unsigned long flags)
603 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
605 unsigned long size, stride, aligned_y = y;
608 if (*tiling_mode == I915_TILING_NONE)
609 aligned_y = ALIGN(y, 2);
610 else if (*tiling_mode == I915_TILING_X)
611 aligned_y = ALIGN(y, 8);
612 else if (*tiling_mode == I915_TILING_Y)
613 aligned_y = ALIGN(y, 32);
616 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
617 size = stride * aligned_y;
618 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
620 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
624 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
626 drm_intel_gem_bo_unreference(bo);
636 * Returns a drm_intel_bo wrapping the given buffer object handle.
638 * This can be used when one application needs to pass a buffer object
642 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
646 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
647 drm_intel_bo_gem *bo_gem;
649 struct drm_gem_open open_arg;
650 struct drm_i915_gem_get_tiling get_tiling;
652 bo_gem = calloc(1, sizeof(*bo_gem));
656 memset(&open_arg, 0, sizeof(open_arg));
657 open_arg.name = handle;
659 ret = ioctl(bufmgr_gem->fd,
662 } while (ret == -1 && errno == EINTR);
664 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
665 name, handle, strerror(errno));
669 bo_gem->bo.size = open_arg.size;
670 bo_gem->bo.offset = 0;
671 bo_gem->bo.virtual = NULL;
672 bo_gem->bo.bufmgr = bufmgr;
674 atomic_set(&bo_gem->refcount, 1);
675 bo_gem->validate_index = -1;
676 bo_gem->gem_handle = open_arg.handle;
677 bo_gem->global_name = handle;
678 bo_gem->reusable = 0;
680 memset(&get_tiling, 0, sizeof(get_tiling));
681 get_tiling.handle = bo_gem->gem_handle;
682 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
684 drm_intel_gem_bo_unreference(&bo_gem->bo);
687 bo_gem->tiling_mode = get_tiling.tiling_mode;
688 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
689 if (bo_gem->tiling_mode == I915_TILING_NONE)
690 bo_gem->reloc_tree_fences = 0;
692 bo_gem->reloc_tree_fences = 1;
693 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
695 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
701 drm_intel_gem_bo_free(drm_intel_bo *bo)
703 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
704 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
705 struct drm_gem_close close;
708 if (bo_gem->mem_virtual)
709 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
710 if (bo_gem->gtt_virtual)
711 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
713 free(bo_gem->reloc_target_bo);
714 free(bo_gem->relocs);
716 /* Close this object */
717 memset(&close, 0, sizeof(close));
718 close.handle = bo_gem->gem_handle;
719 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
722 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
723 bo_gem->gem_handle, bo_gem->name, strerror(errno));
728 /** Frees all cached buffers significantly older than @time. */
730 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
734 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
735 struct drm_intel_gem_bo_bucket *bucket =
736 &bufmgr_gem->cache_bucket[i];
738 while (!DRMLISTEMPTY(&bucket->head)) {
739 drm_intel_bo_gem *bo_gem;
741 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
742 bucket->head.next, head);
743 if (time - bo_gem->free_time <= 1)
746 DRMLISTDEL(&bo_gem->head);
748 drm_intel_gem_bo_free(&bo_gem->bo);
754 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
756 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
757 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
758 struct drm_intel_gem_bo_bucket *bucket;
759 uint32_t tiling_mode;
762 /* Unreference all the target buffers */
763 for (i = 0; i < bo_gem->reloc_count; i++) {
764 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
768 bo_gem->reloc_count = 0;
769 bo_gem->used_as_reloc_target = 0;
771 DBG("bo_unreference final: %d (%s)\n",
772 bo_gem->gem_handle, bo_gem->name);
774 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
775 /* Put the buffer into our internal cache for reuse if we can. */
776 tiling_mode = I915_TILING_NONE;
777 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
778 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
779 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
780 I915_MADV_DONTNEED)) {
781 bo_gem->free_time = time;
784 bo_gem->validate_index = -1;
786 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
788 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
790 drm_intel_gem_bo_free(bo);
794 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
797 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
799 assert(atomic_read(&bo_gem->refcount) > 0);
800 if (atomic_dec_and_test(&bo_gem->refcount))
801 drm_intel_gem_bo_unreference_final(bo, time);
804 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
806 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
808 assert(atomic_read(&bo_gem->refcount) > 0);
809 if (atomic_dec_and_test(&bo_gem->refcount)) {
810 drm_intel_bufmgr_gem *bufmgr_gem =
811 (drm_intel_bufmgr_gem *) bo->bufmgr;
812 struct timespec time;
814 clock_gettime(CLOCK_MONOTONIC, &time);
816 pthread_mutex_lock(&bufmgr_gem->lock);
817 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
818 pthread_mutex_unlock(&bufmgr_gem->lock);
822 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
824 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
825 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
826 struct drm_i915_gem_set_domain set_domain;
829 pthread_mutex_lock(&bufmgr_gem->lock);
831 /* Allow recursive mapping. Mesa may recursively map buffers with
832 * nested display loops.
834 if (!bo_gem->mem_virtual) {
835 struct drm_i915_gem_mmap mmap_arg;
837 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
839 memset(&mmap_arg, 0, sizeof(mmap_arg));
840 mmap_arg.handle = bo_gem->gem_handle;
842 mmap_arg.size = bo->size;
844 ret = ioctl(bufmgr_gem->fd,
845 DRM_IOCTL_I915_GEM_MMAP,
847 } while (ret == -1 && errno == EINTR);
851 "%s:%d: Error mapping buffer %d (%s): %s .\n",
852 __FILE__, __LINE__, bo_gem->gem_handle,
853 bo_gem->name, strerror(errno));
854 pthread_mutex_unlock(&bufmgr_gem->lock);
857 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
859 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
860 bo_gem->mem_virtual);
861 bo->virtual = bo_gem->mem_virtual;
863 set_domain.handle = bo_gem->gem_handle;
864 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
866 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
868 set_domain.write_domain = 0;
870 ret = ioctl(bufmgr_gem->fd,
871 DRM_IOCTL_I915_GEM_SET_DOMAIN,
873 } while (ret == -1 && errno == EINTR);
876 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
877 __FILE__, __LINE__, bo_gem->gem_handle,
879 pthread_mutex_unlock(&bufmgr_gem->lock);
883 pthread_mutex_unlock(&bufmgr_gem->lock);
888 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
890 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
891 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
892 struct drm_i915_gem_set_domain set_domain;
895 pthread_mutex_lock(&bufmgr_gem->lock);
897 /* Get a mapping of the buffer if we haven't before. */
898 if (bo_gem->gtt_virtual == NULL) {
899 struct drm_i915_gem_mmap_gtt mmap_arg;
901 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
904 memset(&mmap_arg, 0, sizeof(mmap_arg));
905 mmap_arg.handle = bo_gem->gem_handle;
907 /* Get the fake offset back... */
909 ret = ioctl(bufmgr_gem->fd,
910 DRM_IOCTL_I915_GEM_MMAP_GTT,
912 } while (ret == -1 && errno == EINTR);
916 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
918 bo_gem->gem_handle, bo_gem->name,
920 pthread_mutex_unlock(&bufmgr_gem->lock);
925 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
926 MAP_SHARED, bufmgr_gem->fd,
928 if (bo_gem->gtt_virtual == MAP_FAILED) {
931 "%s:%d: Error mapping buffer %d (%s): %s .\n",
933 bo_gem->gem_handle, bo_gem->name,
935 pthread_mutex_unlock(&bufmgr_gem->lock);
940 bo->virtual = bo_gem->gtt_virtual;
942 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
943 bo_gem->gtt_virtual);
945 /* Now move it to the GTT domain so that the CPU caches are flushed */
946 set_domain.handle = bo_gem->gem_handle;
947 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
948 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
950 ret = ioctl(bufmgr_gem->fd,
951 DRM_IOCTL_I915_GEM_SET_DOMAIN,
953 } while (ret == -1 && errno == EINTR);
957 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
958 __FILE__, __LINE__, bo_gem->gem_handle,
962 pthread_mutex_unlock(&bufmgr_gem->lock);
967 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
969 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
970 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
976 assert(bo_gem->gtt_virtual != NULL);
978 pthread_mutex_lock(&bufmgr_gem->lock);
980 pthread_mutex_unlock(&bufmgr_gem->lock);
985 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
987 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
988 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
989 struct drm_i915_gem_sw_finish sw_finish;
995 assert(bo_gem->mem_virtual != NULL);
997 pthread_mutex_lock(&bufmgr_gem->lock);
999 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1000 * results show up in a timely manner.
1002 sw_finish.handle = bo_gem->gem_handle;
1004 ret = ioctl(bufmgr_gem->fd,
1005 DRM_IOCTL_I915_GEM_SW_FINISH,
1007 } while (ret == -1 && errno == EINTR);
1010 pthread_mutex_unlock(&bufmgr_gem->lock);
1015 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1016 unsigned long size, const void *data)
1018 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1019 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1020 struct drm_i915_gem_pwrite pwrite;
1023 memset(&pwrite, 0, sizeof(pwrite));
1024 pwrite.handle = bo_gem->gem_handle;
1025 pwrite.offset = offset;
1027 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1029 ret = ioctl(bufmgr_gem->fd,
1030 DRM_IOCTL_I915_GEM_PWRITE,
1032 } while (ret == -1 && errno == EINTR);
1035 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1036 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1037 (int)size, strerror(errno));
1043 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1045 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1046 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1049 get_pipe_from_crtc_id.crtc_id = crtc_id;
1050 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1051 &get_pipe_from_crtc_id);
1053 /* We return -1 here to signal that we don't
1054 * know which pipe is associated with this crtc.
1055 * This lets the caller know that this information
1056 * isn't available; using the wrong pipe for
1057 * vblank waiting can cause the chipset to lock up
1062 return get_pipe_from_crtc_id.pipe;
1066 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1067 unsigned long size, void *data)
1069 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1070 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1071 struct drm_i915_gem_pread pread;
1074 memset(&pread, 0, sizeof(pread));
1075 pread.handle = bo_gem->gem_handle;
1076 pread.offset = offset;
1078 pread.data_ptr = (uint64_t) (uintptr_t) data;
1080 ret = ioctl(bufmgr_gem->fd,
1081 DRM_IOCTL_I915_GEM_PREAD,
1083 } while (ret == -1 && errno == EINTR);
1087 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1088 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1089 (int)size, strerror(errno));
1094 /** Waits for all GPU rendering to the object to have completed. */
1096 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1098 drm_intel_gem_bo_start_gtt_access(bo, 0);
1102 * Sets the object to the GTT read and possibly write domain, used by the X
1103 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1105 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1106 * can do tiled pixmaps this way.
1109 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1111 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1112 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1113 struct drm_i915_gem_set_domain set_domain;
1116 set_domain.handle = bo_gem->gem_handle;
1117 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1118 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1120 ret = ioctl(bufmgr_gem->fd,
1121 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1123 } while (ret == -1 && errno == EINTR);
1126 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1127 __FILE__, __LINE__, bo_gem->gem_handle,
1128 set_domain.read_domains, set_domain.write_domain,
1134 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1136 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1139 free(bufmgr_gem->exec_objects);
1140 free(bufmgr_gem->exec_bos);
1142 pthread_mutex_destroy(&bufmgr_gem->lock);
1144 /* Free any cached buffer objects we were going to reuse */
1145 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1146 struct drm_intel_gem_bo_bucket *bucket =
1147 &bufmgr_gem->cache_bucket[i];
1148 drm_intel_bo_gem *bo_gem;
1150 while (!DRMLISTEMPTY(&bucket->head)) {
1151 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1152 bucket->head.next, head);
1153 DRMLISTDEL(&bo_gem->head);
1155 drm_intel_gem_bo_free(&bo_gem->bo);
1163 * Adds the target buffer to the validation list and adds the relocation
1164 * to the reloc_buffer's relocation list.
1166 * The relocation entry at the given offset must already contain the
1167 * precomputed relocation value, because the kernel will optimize out
1168 * the relocation entry write when the buffer hasn't moved from the
1169 * last known offset in target_bo.
1172 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1173 drm_intel_bo *target_bo, uint32_t target_offset,
1174 uint32_t read_domains, uint32_t write_domain)
1176 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1177 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1178 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1180 pthread_mutex_lock(&bufmgr_gem->lock);
1182 /* Create a new relocation list if needed */
1183 if (bo_gem->relocs == NULL)
1184 drm_intel_setup_reloc_list(bo);
1186 /* Check overflow */
1187 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1190 assert(offset <= bo->size - 4);
1191 assert((write_domain & (write_domain - 1)) == 0);
1193 /* Make sure that we're not adding a reloc to something whose size has
1194 * already been accounted for.
1196 assert(!bo_gem->used_as_reloc_target);
1197 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1198 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1200 /* Flag the target to disallow further relocations in it. */
1201 target_bo_gem->used_as_reloc_target = 1;
1203 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1204 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1205 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1206 target_bo_gem->gem_handle;
1207 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1208 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1209 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1211 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1212 drm_intel_gem_bo_reference(target_bo);
1214 bo_gem->reloc_count++;
1216 pthread_mutex_unlock(&bufmgr_gem->lock);
1222 * Walk the tree of relocations rooted at BO and accumulate the list of
1223 * validations to be performed and update the relocation buffers with
1224 * index values into the validation list.
1227 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1229 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1232 if (bo_gem->relocs == NULL)
1235 for (i = 0; i < bo_gem->reloc_count; i++) {
1236 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1238 /* Continue walking the tree depth-first. */
1239 drm_intel_gem_bo_process_reloc(target_bo);
1241 /* Add the target to the validate list */
1242 drm_intel_add_validate_buffer(target_bo);
1247 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1251 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1252 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1253 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1255 /* Update the buffer offset */
1256 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1257 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1258 bo_gem->gem_handle, bo_gem->name, bo->offset,
1259 (unsigned long long)bufmgr_gem->exec_objects[i].
1261 bo->offset = bufmgr_gem->exec_objects[i].offset;
1267 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1268 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1270 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1271 struct drm_i915_gem_execbuffer execbuf;
1274 pthread_mutex_lock(&bufmgr_gem->lock);
1275 /* Update indices and set up the validate list. */
1276 drm_intel_gem_bo_process_reloc(bo);
1278 /* Add the batch buffer to the validation list. There are no
1279 * relocations pointing to it.
1281 drm_intel_add_validate_buffer(bo);
1283 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1284 execbuf.buffer_count = bufmgr_gem->exec_count;
1285 execbuf.batch_start_offset = 0;
1286 execbuf.batch_len = used;
1287 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1288 execbuf.num_cliprects = num_cliprects;
1293 ret = ioctl(bufmgr_gem->fd,
1294 DRM_IOCTL_I915_GEM_EXECBUFFER,
1296 } while (ret != 0 && errno == EINTR);
1300 if (errno == ENOSPC) {
1302 "Execbuffer fails to pin. "
1303 "Estimate: %u. Actual: %u. Available: %u\n",
1304 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1307 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1310 (unsigned int)bufmgr_gem->gtt_size);
1313 drm_intel_update_buffer_offsets(bufmgr_gem);
1315 if (bufmgr_gem->bufmgr.debug)
1316 drm_intel_gem_dump_validation_list(bufmgr_gem);
1318 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1319 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1320 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1322 /* Disconnect the buffer from the validate list */
1323 bo_gem->validate_index = -1;
1324 bufmgr_gem->exec_bos[i] = NULL;
1326 bufmgr_gem->exec_count = 0;
1327 pthread_mutex_unlock(&bufmgr_gem->lock);
1333 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1335 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1336 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1337 struct drm_i915_gem_pin pin;
1340 memset(&pin, 0, sizeof(pin));
1341 pin.handle = bo_gem->gem_handle;
1342 pin.alignment = alignment;
1345 ret = ioctl(bufmgr_gem->fd,
1346 DRM_IOCTL_I915_GEM_PIN,
1348 } while (ret == -1 && errno == EINTR);
1353 bo->offset = pin.offset;
1358 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1360 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1361 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1362 struct drm_i915_gem_unpin unpin;
1365 memset(&unpin, 0, sizeof(unpin));
1366 unpin.handle = bo_gem->gem_handle;
1368 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1376 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1379 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1380 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1381 struct drm_i915_gem_set_tiling set_tiling;
1384 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1387 /* If we're going from non-tiling to tiling, bump fence count */
1388 if (bo_gem->tiling_mode == I915_TILING_NONE)
1389 bo_gem->reloc_tree_fences++;
1391 memset(&set_tiling, 0, sizeof(set_tiling));
1392 set_tiling.handle = bo_gem->gem_handle;
1393 set_tiling.tiling_mode = *tiling_mode;
1394 set_tiling.stride = stride;
1397 ret = ioctl(bufmgr_gem->fd,
1398 DRM_IOCTL_I915_GEM_SET_TILING,
1400 } while (ret == -1 && errno == EINTR);
1402 *tiling_mode = bo_gem->tiling_mode;
1405 bo_gem->tiling_mode = set_tiling.tiling_mode;
1406 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1408 /* If we're going from tiling to non-tiling, drop fence count */
1409 if (bo_gem->tiling_mode == I915_TILING_NONE)
1410 bo_gem->reloc_tree_fences--;
1412 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1414 *tiling_mode = bo_gem->tiling_mode;
1419 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1420 uint32_t * swizzle_mode)
1422 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1424 *tiling_mode = bo_gem->tiling_mode;
1425 *swizzle_mode = bo_gem->swizzle_mode;
1430 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1432 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1433 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1434 struct drm_gem_flink flink;
1437 if (!bo_gem->global_name) {
1438 memset(&flink, 0, sizeof(flink));
1439 flink.handle = bo_gem->gem_handle;
1441 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1444 bo_gem->global_name = flink.name;
1445 bo_gem->reusable = 0;
1448 *name = bo_gem->global_name;
1453 * Enables unlimited caching of buffer objects for reuse.
1455 * This is potentially very memory expensive, as the cache at each bucket
1456 * size is only bounded by how many buffers of that size we've managed to have
1457 * in flight at once.
1460 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1462 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1464 bufmgr_gem->bo_reuse = 1;
1468 * Return the additional aperture space required by the tree of buffer objects
1472 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1474 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1478 if (bo == NULL || bo_gem->included_in_check_aperture)
1482 bo_gem->included_in_check_aperture = 1;
1484 for (i = 0; i < bo_gem->reloc_count; i++)
1486 drm_intel_gem_bo_get_aperture_space(bo_gem->
1487 reloc_target_bo[i]);
1493 * Count the number of buffers in this list that need a fence reg
1495 * If the count is greater than the number of available regs, we'll have
1496 * to ask the caller to resubmit a batch with fewer tiled buffers.
1498 * This function over-counts if the same buffer is used multiple times.
1501 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1504 unsigned int total = 0;
1506 for (i = 0; i < count; i++) {
1507 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1512 total += bo_gem->reloc_tree_fences;
1518 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1519 * for the next drm_intel_bufmgr_check_aperture_space() call.
1522 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1524 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1527 if (bo == NULL || !bo_gem->included_in_check_aperture)
1530 bo_gem->included_in_check_aperture = 0;
1532 for (i = 0; i < bo_gem->reloc_count; i++)
1533 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1534 reloc_target_bo[i]);
1538 * Return a conservative estimate for the amount of aperture required
1539 * for a collection of buffers. This may double-count some buffers.
1542 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1545 unsigned int total = 0;
1547 for (i = 0; i < count; i++) {
1548 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1550 total += bo_gem->reloc_tree_size;
1556 * Return the amount of aperture needed for a collection of buffers.
1557 * This avoids double counting any buffers, at the cost of looking
1558 * at every buffer in the set.
1561 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1564 unsigned int total = 0;
1566 for (i = 0; i < count; i++) {
1567 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1568 /* For the first buffer object in the array, we get an
1569 * accurate count back for its reloc_tree size (since nothing
1570 * had been flagged as being counted yet). We can save that
1571 * value out as a more conservative reloc_tree_size that
1572 * avoids double-counting target buffers. Since the first
1573 * buffer happens to usually be the batch buffer in our
1574 * callers, this can pull us back from doing the tree
1575 * walk on every new batch emit.
1578 drm_intel_bo_gem *bo_gem =
1579 (drm_intel_bo_gem *) bo_array[i];
1580 bo_gem->reloc_tree_size = total;
1584 for (i = 0; i < count; i++)
1585 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1590 * Return -1 if the batchbuffer should be flushed before attempting to
1591 * emit rendering referencing the buffers pointed to by bo_array.
1593 * This is required because if we try to emit a batchbuffer with relocations
1594 * to a tree of buffers that won't simultaneously fit in the aperture,
1595 * the rendering will return an error at a point where the software is not
1596 * prepared to recover from it.
1598 * However, we also want to emit the batchbuffer significantly before we reach
1599 * the limit, as a series of batchbuffers each of which references buffers
1600 * covering almost all of the aperture means that at each emit we end up
1601 * waiting to evict a buffer from the last rendering, and we get synchronous
1602 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1603 * get better parallelism.
1606 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1608 drm_intel_bufmgr_gem *bufmgr_gem =
1609 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1610 unsigned int total = 0;
1611 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1614 /* Check for fence reg constraints if necessary */
1615 if (bufmgr_gem->available_fences) {
1616 total_fences = drm_intel_gem_total_fences(bo_array, count);
1617 if (total_fences > bufmgr_gem->available_fences)
1621 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1623 if (total > threshold)
1624 total = drm_intel_gem_compute_batch_space(bo_array, count);
1626 if (total > threshold) {
1627 DBG("check_space: overflowed available aperture, "
1629 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1632 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1633 (int)bufmgr_gem->gtt_size / 1024);
1639 * Disable buffer reuse for objects which are shared with the kernel
1640 * as scanout buffers
1643 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1645 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1647 bo_gem->reusable = 0;
1652 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1654 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1657 for (i = 0; i < bo_gem->reloc_count; i++) {
1658 if (bo_gem->reloc_target_bo[i] == target_bo)
1660 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i],
1668 /** Return true if target_bo is referenced by bo's relocation tree. */
1670 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1672 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1674 if (bo == NULL || target_bo == NULL)
1676 if (target_bo_gem->used_as_reloc_target)
1677 return _drm_intel_gem_bo_references(bo, target_bo);
1682 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1683 * and manage map buffer objections.
1685 * \param fd File descriptor of the opened DRM device.
1688 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1690 drm_intel_bufmgr_gem *bufmgr_gem;
1691 struct drm_i915_gem_get_aperture aperture;
1692 drm_i915_getparam_t gp;
1696 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1697 bufmgr_gem->fd = fd;
1699 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1704 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1707 bufmgr_gem->gtt_size = aperture.aper_available_size;
1709 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1711 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1712 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1713 "May lead to reduced performance or incorrect "
1715 (int)bufmgr_gem->gtt_size / 1024);
1718 gp.param = I915_PARAM_CHIPSET_ID;
1719 gp.value = &bufmgr_gem->pci_device;
1720 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1722 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1723 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1726 if (!IS_I965G(bufmgr_gem)) {
1727 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1728 gp.value = &bufmgr_gem->available_fences;
1729 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1731 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1733 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1735 bufmgr_gem->available_fences = 0;
1739 /* Let's go with one relocation per every 2 dwords (but round down a bit
1740 * since a power of two will mean an extra page allocation for the reloc
1743 * Every 4 was too few for the blender benchmark.
1745 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1747 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1748 bufmgr_gem->bufmgr.bo_alloc_for_render =
1749 drm_intel_gem_bo_alloc_for_render;
1750 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
1751 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1752 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1753 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1754 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1755 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1756 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1757 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1758 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1759 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1760 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1761 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1762 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1763 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1764 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1765 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1766 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
1767 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1768 bufmgr_gem->bufmgr.debug = 0;
1769 bufmgr_gem->bufmgr.check_aperture_space =
1770 drm_intel_gem_check_aperture_space;
1771 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1772 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
1773 drm_intel_gem_get_pipe_from_crtc_id;
1774 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1776 /* Initialize the linked lists for BO reuse cache. */
1777 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1778 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1779 bufmgr_gem->cache_bucket[i].size = size;
1782 return &bufmgr_gem->bufmgr;