1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
53 #include <sys/types.h>
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
104 } drm_intel_bufmgr_gem;
106 #define DRM_INTEL_RELOC_FENCE (1<<0)
108 typedef struct _drm_intel_reloc_target_info {
111 } drm_intel_reloc_target;
113 struct _drm_intel_bo_gem {
121 * Kenel-assigned global name for this object
123 unsigned int global_name;
126 * Index of the buffer within the validation list while preparing a
127 * batchbuffer execution.
132 * Current tiling mode
134 uint32_t tiling_mode;
135 uint32_t swizzle_mode;
136 unsigned long stride;
140 /** Array passed to the DRM containing relocation information. */
141 struct drm_i915_gem_relocation_entry *relocs;
143 * Array of info structs corresponding to relocs[i].target_handle etc
145 drm_intel_reloc_target *reloc_target_info;
146 /** Number of entries in relocs */
148 /** Mapped address for the buffer, saved across map/unmap cycles */
150 /** GTT virtual address for the buffer, saved across map/unmap cycles */
157 * Boolean of whether this BO and its children have been included in
158 * the current drm_intel_bufmgr_check_aperture_space() total.
160 char included_in_check_aperture;
163 * Boolean of whether this buffer has been used as a relocation
164 * target and had its size accounted for, and thus can't have any
165 * further relocations added to it.
167 char used_as_reloc_target;
170 * Boolean of whether we have encountered an error whilst building the relocation tree.
175 * Boolean of whether this buffer can be re-used
180 * Size in bytes of this buffer and its relocation descendents.
182 * Used to avoid costly tree walking in
183 * drm_intel_bufmgr_check_aperture in the common case.
188 * Number of potential fence registers required by this buffer and its
191 int reloc_tree_fences;
195 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
198 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
201 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
202 uint32_t * swizzle_mode);
205 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
206 uint32_t tiling_mode,
209 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
212 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
214 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
217 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
218 uint32_t *tiling_mode)
220 unsigned long min_size, max_size;
223 if (*tiling_mode == I915_TILING_NONE)
226 /* 965+ just need multiples of page size for tiling */
227 if (bufmgr_gem->gen >= 4)
228 return ROUND_UP_TO(size, 4096);
230 /* Older chips need powers of two, of at least 512k or 1M */
231 if (bufmgr_gem->gen == 3) {
232 min_size = 1024*1024;
233 max_size = 128*1024*1024;
236 max_size = 64*1024*1024;
239 if (size > max_size) {
240 *tiling_mode = I915_TILING_NONE;
244 for (i = min_size; i < size; i <<= 1)
251 * Round a given pitch up to the minimum required for X tiling on a
252 * given chip. We use 512 as the minimum to allow for a later tiling
256 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
257 unsigned long pitch, uint32_t *tiling_mode)
259 unsigned long tile_width;
262 /* If untiled, then just align it so that we can do rendering
263 * to it with the 3D engine.
265 if (*tiling_mode == I915_TILING_NONE)
266 return ALIGN(pitch, 64);
268 if (*tiling_mode == I915_TILING_X)
273 /* 965 is flexible */
274 if (bufmgr_gem->gen >= 4)
275 return ROUND_UP_TO(pitch, tile_width);
277 /* The older hardware has a maximum pitch of 8192 with tiled
278 * surfaces, so fallback to untiled if it's too large.
281 *tiling_mode = I915_TILING_NONE;
282 return ALIGN(pitch, 64);
285 /* Pre-965 needs power of two tile width */
286 for (i = tile_width; i < pitch; i <<= 1)
292 static struct drm_intel_gem_bo_bucket *
293 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
298 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
299 struct drm_intel_gem_bo_bucket *bucket =
300 &bufmgr_gem->cache_bucket[i];
301 if (bucket->size >= size) {
310 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
314 for (i = 0; i < bufmgr_gem->exec_count; i++) {
315 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
316 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
318 if (bo_gem->relocs == NULL) {
319 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
324 for (j = 0; j < bo_gem->reloc_count; j++) {
325 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
326 drm_intel_bo_gem *target_gem =
327 (drm_intel_bo_gem *) target_bo;
329 DBG("%2d: %d (%s)@0x%08llx -> "
330 "%d (%s)@0x%08lx + 0x%08x\n",
332 bo_gem->gem_handle, bo_gem->name,
333 (unsigned long long)bo_gem->relocs[j].offset,
334 target_gem->gem_handle,
337 bo_gem->relocs[j].delta);
343 drm_intel_gem_bo_reference(drm_intel_bo *bo)
345 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
347 assert(atomic_read(&bo_gem->refcount) > 0);
348 atomic_inc(&bo_gem->refcount);
352 * Adds the given buffer to the list of buffers to be validated (moved into the
353 * appropriate memory type) with the next batch submission.
355 * If a buffer is validated multiple times in a batch submission, it ends up
356 * with the intersection of the memory type flags and the union of the
360 drm_intel_add_validate_buffer(drm_intel_bo *bo)
362 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
363 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
366 if (bo_gem->validate_index != -1)
369 /* Extend the array of validation entries as necessary. */
370 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
371 int new_size = bufmgr_gem->exec_size * 2;
376 bufmgr_gem->exec_objects =
377 realloc(bufmgr_gem->exec_objects,
378 sizeof(*bufmgr_gem->exec_objects) * new_size);
379 bufmgr_gem->exec_bos =
380 realloc(bufmgr_gem->exec_bos,
381 sizeof(*bufmgr_gem->exec_bos) * new_size);
382 bufmgr_gem->exec_size = new_size;
385 index = bufmgr_gem->exec_count;
386 bo_gem->validate_index = index;
387 /* Fill in array entry */
388 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
389 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
390 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
391 bufmgr_gem->exec_objects[index].alignment = 0;
392 bufmgr_gem->exec_objects[index].offset = 0;
393 bufmgr_gem->exec_bos[index] = bo;
394 bufmgr_gem->exec_count++;
398 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
400 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
401 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
404 if (bo_gem->validate_index != -1) {
406 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
407 EXEC_OBJECT_NEEDS_FENCE;
411 /* Extend the array of validation entries as necessary. */
412 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
413 int new_size = bufmgr_gem->exec_size * 2;
418 bufmgr_gem->exec2_objects =
419 realloc(bufmgr_gem->exec2_objects,
420 sizeof(*bufmgr_gem->exec2_objects) * new_size);
421 bufmgr_gem->exec_bos =
422 realloc(bufmgr_gem->exec_bos,
423 sizeof(*bufmgr_gem->exec_bos) * new_size);
424 bufmgr_gem->exec_size = new_size;
427 index = bufmgr_gem->exec_count;
428 bo_gem->validate_index = index;
429 /* Fill in array entry */
430 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
431 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
432 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
433 bufmgr_gem->exec2_objects[index].alignment = 0;
434 bufmgr_gem->exec2_objects[index].offset = 0;
435 bufmgr_gem->exec_bos[index] = bo;
436 bufmgr_gem->exec2_objects[index].flags = 0;
437 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
438 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
440 bufmgr_gem->exec2_objects[index].flags |=
441 EXEC_OBJECT_NEEDS_FENCE;
443 bufmgr_gem->exec_count++;
446 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
450 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
451 drm_intel_bo_gem *bo_gem)
455 assert(!bo_gem->used_as_reloc_target);
457 /* The older chipsets are far-less flexible in terms of tiling,
458 * and require tiled buffer to be size aligned in the aperture.
459 * This means that in the worst possible case we will need a hole
460 * twice as large as the object in order for it to fit into the
461 * aperture. Optimal packing is for wimps.
463 size = bo_gem->bo.size;
464 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
467 bo_gem->reloc_tree_size = size;
471 drm_intel_setup_reloc_list(drm_intel_bo *bo)
473 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
474 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
475 unsigned int max_relocs = bufmgr_gem->max_relocs;
477 if (bo->size / 4 < max_relocs)
478 max_relocs = bo->size / 4;
480 bo_gem->relocs = malloc(max_relocs *
481 sizeof(struct drm_i915_gem_relocation_entry));
482 bo_gem->reloc_target_info = malloc(max_relocs *
483 sizeof(drm_intel_reloc_target));
484 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
485 bo_gem->has_error = 1;
487 free (bo_gem->relocs);
488 bo_gem->relocs = NULL;
490 free (bo_gem->reloc_target_info);
491 bo_gem->reloc_target_info = NULL;
500 drm_intel_gem_bo_busy(drm_intel_bo *bo)
502 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
503 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
504 struct drm_i915_gem_busy busy;
507 memset(&busy, 0, sizeof(busy));
508 busy.handle = bo_gem->gem_handle;
511 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
512 } while (ret == -1 && errno == EINTR);
514 return (ret == 0 && busy.busy);
518 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
519 drm_intel_bo_gem *bo_gem, int state)
521 struct drm_i915_gem_madvise madv;
523 madv.handle = bo_gem->gem_handle;
526 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
528 return madv.retained;
532 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
534 return drm_intel_gem_bo_madvise_internal
535 ((drm_intel_bufmgr_gem *) bo->bufmgr,
536 (drm_intel_bo_gem *) bo,
540 /* drop the oldest entries that have been purged by the kernel */
542 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
543 struct drm_intel_gem_bo_bucket *bucket)
545 while (!DRMLISTEMPTY(&bucket->head)) {
546 drm_intel_bo_gem *bo_gem;
548 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
549 bucket->head.next, head);
550 if (drm_intel_gem_bo_madvise_internal
551 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
554 DRMLISTDEL(&bo_gem->head);
555 drm_intel_gem_bo_free(&bo_gem->bo);
559 static drm_intel_bo *
560 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
564 uint32_t tiling_mode,
565 unsigned long stride)
567 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
568 drm_intel_bo_gem *bo_gem;
569 unsigned int page_size = getpagesize();
571 struct drm_intel_gem_bo_bucket *bucket;
572 int alloc_from_cache;
573 unsigned long bo_size;
576 if (flags & BO_ALLOC_FOR_RENDER)
579 /* Round the allocated size up to a power of two number of pages. */
580 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
582 /* If we don't have caching at this size, don't actually round the
585 if (bucket == NULL) {
587 if (bo_size < page_size)
590 bo_size = bucket->size;
593 pthread_mutex_lock(&bufmgr_gem->lock);
594 /* Get a buffer out of the cache if available */
596 alloc_from_cache = 0;
597 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
599 /* Allocate new render-target BOs from the tail (MRU)
600 * of the list, as it will likely be hot in the GPU
601 * cache and in the aperture for us.
603 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
604 bucket->head.prev, head);
605 DRMLISTDEL(&bo_gem->head);
606 alloc_from_cache = 1;
608 /* For non-render-target BOs (where we're probably
609 * going to map it first thing in order to fill it
610 * with data), check if the last BO in the cache is
611 * unbusy, and only reuse in that case. Otherwise,
612 * allocating a new buffer is probably faster than
613 * waiting for the GPU to finish.
615 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
616 bucket->head.next, head);
617 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
618 alloc_from_cache = 1;
619 DRMLISTDEL(&bo_gem->head);
623 if (alloc_from_cache) {
624 if (!drm_intel_gem_bo_madvise_internal
625 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
626 drm_intel_gem_bo_free(&bo_gem->bo);
627 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
632 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
635 drm_intel_gem_bo_free(&bo_gem->bo);
640 pthread_mutex_unlock(&bufmgr_gem->lock);
642 if (!alloc_from_cache) {
643 struct drm_i915_gem_create create;
645 bo_gem = calloc(1, sizeof(*bo_gem));
649 bo_gem->bo.size = bo_size;
650 memset(&create, 0, sizeof(create));
651 create.size = bo_size;
654 ret = ioctl(bufmgr_gem->fd,
655 DRM_IOCTL_I915_GEM_CREATE,
657 } while (ret == -1 && errno == EINTR);
658 bo_gem->gem_handle = create.handle;
659 bo_gem->bo.handle = bo_gem->gem_handle;
664 bo_gem->bo.bufmgr = bufmgr;
666 bo_gem->tiling_mode = I915_TILING_NONE;
667 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
670 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
673 drm_intel_gem_bo_free(&bo_gem->bo);
679 atomic_set(&bo_gem->refcount, 1);
680 bo_gem->validate_index = -1;
681 bo_gem->reloc_tree_fences = 0;
682 bo_gem->used_as_reloc_target = 0;
683 bo_gem->has_error = 0;
684 bo_gem->reusable = 1;
686 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
688 DBG("bo_create: buf %d (%s) %ldb\n",
689 bo_gem->gem_handle, bo_gem->name, size);
694 static drm_intel_bo *
695 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
698 unsigned int alignment)
700 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
702 I915_TILING_NONE, 0);
705 static drm_intel_bo *
706 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
709 unsigned int alignment)
711 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
712 I915_TILING_NONE, 0);
715 static drm_intel_bo *
716 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
717 int x, int y, int cpp, uint32_t *tiling_mode,
718 unsigned long *pitch, unsigned long flags)
720 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
721 unsigned long size, stride;
725 unsigned long aligned_y;
727 tiling = *tiling_mode;
729 /* If we're tiled, our allocations are in 8 or 32-row blocks,
730 * so failure to align our height means that we won't allocate
733 * If we're untiled, we still have to align to 2 rows high
734 * because the data port accesses 2x2 blocks even if the
735 * bottom row isn't to be rendered, so failure to align means
736 * we could walk off the end of the GTT and fault. This is
737 * documented on 965, and may be the case on older chipsets
738 * too so we try to be careful.
741 if (tiling == I915_TILING_NONE)
742 aligned_y = ALIGN(y, 2);
743 else if (tiling == I915_TILING_X)
744 aligned_y = ALIGN(y, 8);
745 else if (tiling == I915_TILING_Y)
746 aligned_y = ALIGN(y, 32);
749 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
750 size = stride * aligned_y;
751 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
752 } while (*tiling_mode != tiling);
755 if (tiling == I915_TILING_NONE)
758 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
763 * Returns a drm_intel_bo wrapping the given buffer object handle.
765 * This can be used when one application needs to pass a buffer object
769 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
773 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
774 drm_intel_bo_gem *bo_gem;
776 struct drm_gem_open open_arg;
777 struct drm_i915_gem_get_tiling get_tiling;
779 bo_gem = calloc(1, sizeof(*bo_gem));
783 memset(&open_arg, 0, sizeof(open_arg));
784 open_arg.name = handle;
786 ret = ioctl(bufmgr_gem->fd,
789 } while (ret == -1 && errno == EINTR);
791 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
792 name, handle, strerror(errno));
796 bo_gem->bo.size = open_arg.size;
797 bo_gem->bo.offset = 0;
798 bo_gem->bo.virtual = NULL;
799 bo_gem->bo.bufmgr = bufmgr;
801 atomic_set(&bo_gem->refcount, 1);
802 bo_gem->validate_index = -1;
803 bo_gem->gem_handle = open_arg.handle;
804 bo_gem->global_name = handle;
805 bo_gem->reusable = 0;
807 memset(&get_tiling, 0, sizeof(get_tiling));
808 get_tiling.handle = bo_gem->gem_handle;
809 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
811 drm_intel_gem_bo_unreference(&bo_gem->bo);
814 bo_gem->tiling_mode = get_tiling.tiling_mode;
815 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
816 /* XXX stride is unknown */
817 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
819 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
825 drm_intel_gem_bo_free(drm_intel_bo *bo)
827 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
828 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
829 struct drm_gem_close close;
832 if (bo_gem->mem_virtual)
833 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
834 if (bo_gem->gtt_virtual)
835 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
837 /* Close this object */
838 memset(&close, 0, sizeof(close));
839 close.handle = bo_gem->gem_handle;
840 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
843 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
844 bo_gem->gem_handle, bo_gem->name, strerror(errno));
849 /** Frees all cached buffers significantly older than @time. */
851 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
855 if (bufmgr_gem->time == time)
858 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
859 struct drm_intel_gem_bo_bucket *bucket =
860 &bufmgr_gem->cache_bucket[i];
862 while (!DRMLISTEMPTY(&bucket->head)) {
863 drm_intel_bo_gem *bo_gem;
865 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
866 bucket->head.next, head);
867 if (time - bo_gem->free_time <= 1)
870 DRMLISTDEL(&bo_gem->head);
872 drm_intel_gem_bo_free(&bo_gem->bo);
876 bufmgr_gem->time = time;
880 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
882 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
883 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
884 struct drm_intel_gem_bo_bucket *bucket;
887 /* Unreference all the target buffers */
888 for (i = 0; i < bo_gem->reloc_count; i++) {
889 if (bo_gem->reloc_target_info[i].bo != bo) {
890 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
891 reloc_target_info[i].bo,
895 bo_gem->reloc_count = 0;
896 bo_gem->used_as_reloc_target = 0;
898 DBG("bo_unreference final: %d (%s)\n",
899 bo_gem->gem_handle, bo_gem->name);
901 /* release memory associated with this object */
902 if (bo_gem->reloc_target_info) {
903 free(bo_gem->reloc_target_info);
904 bo_gem->reloc_target_info = NULL;
906 if (bo_gem->relocs) {
907 free(bo_gem->relocs);
908 bo_gem->relocs = NULL;
911 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
912 /* Put the buffer into our internal cache for reuse if we can. */
913 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
914 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
915 I915_MADV_DONTNEED)) {
916 bo_gem->free_time = time;
919 bo_gem->validate_index = -1;
921 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
923 drm_intel_gem_bo_free(bo);
927 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
930 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
932 assert(atomic_read(&bo_gem->refcount) > 0);
933 if (atomic_dec_and_test(&bo_gem->refcount))
934 drm_intel_gem_bo_unreference_final(bo, time);
937 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
939 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
941 assert(atomic_read(&bo_gem->refcount) > 0);
942 if (atomic_dec_and_test(&bo_gem->refcount)) {
943 drm_intel_bufmgr_gem *bufmgr_gem =
944 (drm_intel_bufmgr_gem *) bo->bufmgr;
945 struct timespec time;
947 clock_gettime(CLOCK_MONOTONIC, &time);
949 pthread_mutex_lock(&bufmgr_gem->lock);
950 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
951 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
952 pthread_mutex_unlock(&bufmgr_gem->lock);
956 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
958 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
959 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
960 struct drm_i915_gem_set_domain set_domain;
963 pthread_mutex_lock(&bufmgr_gem->lock);
965 /* Allow recursive mapping. Mesa may recursively map buffers with
966 * nested display loops.
968 if (!bo_gem->mem_virtual) {
969 struct drm_i915_gem_mmap mmap_arg;
971 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
973 memset(&mmap_arg, 0, sizeof(mmap_arg));
974 mmap_arg.handle = bo_gem->gem_handle;
976 mmap_arg.size = bo->size;
978 ret = ioctl(bufmgr_gem->fd,
979 DRM_IOCTL_I915_GEM_MMAP,
981 } while (ret == -1 && errno == EINTR);
985 "%s:%d: Error mapping buffer %d (%s): %s .\n",
986 __FILE__, __LINE__, bo_gem->gem_handle,
987 bo_gem->name, strerror(errno));
988 pthread_mutex_unlock(&bufmgr_gem->lock);
991 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
993 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
994 bo_gem->mem_virtual);
995 bo->virtual = bo_gem->mem_virtual;
997 set_domain.handle = bo_gem->gem_handle;
998 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1000 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1002 set_domain.write_domain = 0;
1004 ret = ioctl(bufmgr_gem->fd,
1005 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1007 } while (ret == -1 && errno == EINTR);
1009 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
1010 __FILE__, __LINE__, bo_gem->gem_handle,
1014 pthread_mutex_unlock(&bufmgr_gem->lock);
1019 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1021 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1022 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1023 struct drm_i915_gem_set_domain set_domain;
1026 pthread_mutex_lock(&bufmgr_gem->lock);
1028 /* Get a mapping of the buffer if we haven't before. */
1029 if (bo_gem->gtt_virtual == NULL) {
1030 struct drm_i915_gem_mmap_gtt mmap_arg;
1032 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1035 memset(&mmap_arg, 0, sizeof(mmap_arg));
1036 mmap_arg.handle = bo_gem->gem_handle;
1038 /* Get the fake offset back... */
1040 ret = ioctl(bufmgr_gem->fd,
1041 DRM_IOCTL_I915_GEM_MMAP_GTT,
1043 } while (ret == -1 && errno == EINTR);
1047 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
1049 bo_gem->gem_handle, bo_gem->name,
1051 pthread_mutex_unlock(&bufmgr_gem->lock);
1056 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1057 MAP_SHARED, bufmgr_gem->fd,
1059 if (bo_gem->gtt_virtual == MAP_FAILED) {
1060 bo_gem->gtt_virtual = NULL;
1063 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1065 bo_gem->gem_handle, bo_gem->name,
1067 pthread_mutex_unlock(&bufmgr_gem->lock);
1072 bo->virtual = bo_gem->gtt_virtual;
1074 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1075 bo_gem->gtt_virtual);
1077 /* Now move it to the GTT domain so that the CPU caches are flushed */
1078 set_domain.handle = bo_gem->gem_handle;
1079 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1080 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1082 ret = ioctl(bufmgr_gem->fd,
1083 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1085 } while (ret == -1 && errno == EINTR);
1087 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1088 __FILE__, __LINE__, bo_gem->gem_handle,
1092 pthread_mutex_unlock(&bufmgr_gem->lock);
1097 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1099 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1100 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1106 assert(bo_gem->gtt_virtual != NULL);
1108 pthread_mutex_lock(&bufmgr_gem->lock);
1110 pthread_mutex_unlock(&bufmgr_gem->lock);
1115 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1117 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1118 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1119 struct drm_i915_gem_sw_finish sw_finish;
1125 assert(bo_gem->mem_virtual != NULL);
1127 pthread_mutex_lock(&bufmgr_gem->lock);
1129 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1130 * results show up in a timely manner.
1132 sw_finish.handle = bo_gem->gem_handle;
1134 ret = ioctl(bufmgr_gem->fd,
1135 DRM_IOCTL_I915_GEM_SW_FINISH,
1137 } while (ret == -1 && errno == EINTR);
1138 ret = ret == -1 ? -errno : 0;
1141 pthread_mutex_unlock(&bufmgr_gem->lock);
1147 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1148 unsigned long size, const void *data)
1150 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1151 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1152 struct drm_i915_gem_pwrite pwrite;
1155 memset(&pwrite, 0, sizeof(pwrite));
1156 pwrite.handle = bo_gem->gem_handle;
1157 pwrite.offset = offset;
1159 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1161 ret = ioctl(bufmgr_gem->fd,
1162 DRM_IOCTL_I915_GEM_PWRITE,
1164 } while (ret == -1 && errno == EINTR);
1168 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1169 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1170 (int)size, strerror(errno));
1177 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1179 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1180 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1183 get_pipe_from_crtc_id.crtc_id = crtc_id;
1184 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1185 &get_pipe_from_crtc_id);
1187 /* We return -1 here to signal that we don't
1188 * know which pipe is associated with this crtc.
1189 * This lets the caller know that this information
1190 * isn't available; using the wrong pipe for
1191 * vblank waiting can cause the chipset to lock up
1196 return get_pipe_from_crtc_id.pipe;
1200 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1201 unsigned long size, void *data)
1203 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1204 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1205 struct drm_i915_gem_pread pread;
1208 memset(&pread, 0, sizeof(pread));
1209 pread.handle = bo_gem->gem_handle;
1210 pread.offset = offset;
1212 pread.data_ptr = (uint64_t) (uintptr_t) data;
1214 ret = ioctl(bufmgr_gem->fd,
1215 DRM_IOCTL_I915_GEM_PREAD,
1217 } while (ret == -1 && errno == EINTR);
1221 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1222 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1223 (int)size, strerror(errno));
1229 /** Waits for all GPU rendering to the object to have completed. */
1231 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1233 drm_intel_gem_bo_start_gtt_access(bo, 0);
1237 * Sets the object to the GTT read and possibly write domain, used by the X
1238 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1240 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1241 * can do tiled pixmaps this way.
1244 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1246 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1247 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1248 struct drm_i915_gem_set_domain set_domain;
1251 set_domain.handle = bo_gem->gem_handle;
1252 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1253 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1255 ret = ioctl(bufmgr_gem->fd,
1256 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1258 } while (ret == -1 && errno == EINTR);
1261 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1262 __FILE__, __LINE__, bo_gem->gem_handle,
1263 set_domain.read_domains, set_domain.write_domain,
1269 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1271 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1274 free(bufmgr_gem->exec2_objects);
1275 free(bufmgr_gem->exec_objects);
1276 free(bufmgr_gem->exec_bos);
1278 pthread_mutex_destroy(&bufmgr_gem->lock);
1280 /* Free any cached buffer objects we were going to reuse */
1281 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1282 struct drm_intel_gem_bo_bucket *bucket =
1283 &bufmgr_gem->cache_bucket[i];
1284 drm_intel_bo_gem *bo_gem;
1286 while (!DRMLISTEMPTY(&bucket->head)) {
1287 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1288 bucket->head.next, head);
1289 DRMLISTDEL(&bo_gem->head);
1291 drm_intel_gem_bo_free(&bo_gem->bo);
1299 * Adds the target buffer to the validation list and adds the relocation
1300 * to the reloc_buffer's relocation list.
1302 * The relocation entry at the given offset must already contain the
1303 * precomputed relocation value, because the kernel will optimize out
1304 * the relocation entry write when the buffer hasn't moved from the
1305 * last known offset in target_bo.
1308 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1309 drm_intel_bo *target_bo, uint32_t target_offset,
1310 uint32_t read_domains, uint32_t write_domain,
1313 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1314 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1315 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1317 if (bo_gem->has_error)
1320 if (target_bo_gem->has_error) {
1321 bo_gem->has_error = 1;
1325 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1328 /* We never use HW fences for rendering on 965+ */
1329 if (bufmgr_gem->gen >= 4)
1332 /* Create a new relocation list if needed */
1333 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1336 /* Check overflow */
1337 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1340 assert(offset <= bo->size - 4);
1341 assert((write_domain & (write_domain - 1)) == 0);
1343 /* Make sure that we're not adding a reloc to something whose size has
1344 * already been accounted for.
1346 assert(!bo_gem->used_as_reloc_target);
1347 if (target_bo_gem != bo_gem) {
1348 target_bo_gem->used_as_reloc_target = 1;
1349 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1351 /* An object needing a fence is a tiled buffer, so it won't have
1352 * relocs to other buffers.
1355 target_bo_gem->reloc_tree_fences = 1;
1356 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1358 /* Flag the target to disallow further relocations in it. */
1360 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1361 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1362 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1363 target_bo_gem->gem_handle;
1364 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1365 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1366 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1368 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1369 if (target_bo != bo)
1370 drm_intel_gem_bo_reference(target_bo);
1372 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1373 DRM_INTEL_RELOC_FENCE;
1375 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1377 bo_gem->reloc_count++;
1383 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1384 drm_intel_bo *target_bo, uint32_t target_offset,
1385 uint32_t read_domains, uint32_t write_domain)
1387 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1389 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1390 read_domains, write_domain,
1391 !bufmgr_gem->fenced_relocs);
1395 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1396 drm_intel_bo *target_bo,
1397 uint32_t target_offset,
1398 uint32_t read_domains, uint32_t write_domain)
1400 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1401 read_domains, write_domain, 1);
1405 * Walk the tree of relocations rooted at BO and accumulate the list of
1406 * validations to be performed and update the relocation buffers with
1407 * index values into the validation list.
1410 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1412 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1415 if (bo_gem->relocs == NULL)
1418 for (i = 0; i < bo_gem->reloc_count; i++) {
1419 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1421 if (target_bo == bo)
1424 /* Continue walking the tree depth-first. */
1425 drm_intel_gem_bo_process_reloc(target_bo);
1427 /* Add the target to the validate list */
1428 drm_intel_add_validate_buffer(target_bo);
1433 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1435 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1438 if (bo_gem->relocs == NULL)
1441 for (i = 0; i < bo_gem->reloc_count; i++) {
1442 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1445 if (target_bo == bo)
1448 /* Continue walking the tree depth-first. */
1449 drm_intel_gem_bo_process_reloc2(target_bo);
1451 need_fence = (bo_gem->reloc_target_info[i].flags &
1452 DRM_INTEL_RELOC_FENCE);
1454 /* Add the target to the validate list */
1455 drm_intel_add_validate_buffer2(target_bo, need_fence);
1461 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1465 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1466 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1467 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1469 /* Update the buffer offset */
1470 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1471 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1472 bo_gem->gem_handle, bo_gem->name, bo->offset,
1473 (unsigned long long)bufmgr_gem->exec_objects[i].
1475 bo->offset = bufmgr_gem->exec_objects[i].offset;
1481 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1485 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1486 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1487 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1489 /* Update the buffer offset */
1490 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1491 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1492 bo_gem->gem_handle, bo_gem->name, bo->offset,
1493 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1494 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1500 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1501 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1503 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1504 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1505 struct drm_i915_gem_execbuffer execbuf;
1508 if (bo_gem->has_error)
1511 pthread_mutex_lock(&bufmgr_gem->lock);
1512 /* Update indices and set up the validate list. */
1513 drm_intel_gem_bo_process_reloc(bo);
1515 /* Add the batch buffer to the validation list. There are no
1516 * relocations pointing to it.
1518 drm_intel_add_validate_buffer(bo);
1520 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1521 execbuf.buffer_count = bufmgr_gem->exec_count;
1522 execbuf.batch_start_offset = 0;
1523 execbuf.batch_len = used;
1524 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1525 execbuf.num_cliprects = num_cliprects;
1530 ret = ioctl(bufmgr_gem->fd,
1531 DRM_IOCTL_I915_GEM_EXECBUFFER,
1533 } while (ret != 0 && errno == EINTR);
1537 if (errno == ENOSPC) {
1539 "Execbuffer fails to pin. "
1540 "Estimate: %u. Actual: %u. Available: %u\n",
1541 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1544 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1547 (unsigned int)bufmgr_gem->gtt_size);
1550 drm_intel_update_buffer_offsets(bufmgr_gem);
1552 if (bufmgr_gem->bufmgr.debug)
1553 drm_intel_gem_dump_validation_list(bufmgr_gem);
1555 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1556 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1557 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1559 /* Disconnect the buffer from the validate list */
1560 bo_gem->validate_index = -1;
1561 bufmgr_gem->exec_bos[i] = NULL;
1563 bufmgr_gem->exec_count = 0;
1564 pthread_mutex_unlock(&bufmgr_gem->lock);
1570 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1571 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1574 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1575 struct drm_i915_gem_execbuffer2 execbuf;
1578 if ((ring_flag != I915_EXEC_RENDER) && (ring_flag != I915_EXEC_BSD))
1581 pthread_mutex_lock(&bufmgr_gem->lock);
1582 /* Update indices and set up the validate list. */
1583 drm_intel_gem_bo_process_reloc2(bo);
1585 /* Add the batch buffer to the validation list. There are no relocations
1588 drm_intel_add_validate_buffer2(bo, 0);
1590 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1591 execbuf.buffer_count = bufmgr_gem->exec_count;
1592 execbuf.batch_start_offset = 0;
1593 execbuf.batch_len = used;
1594 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1595 execbuf.num_cliprects = num_cliprects;
1598 execbuf.flags = ring_flag;
1603 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
1605 } while (ret != 0 && errno == EINTR);
1609 if (ret == -ENOSPC) {
1611 "Execbuffer fails to pin. "
1612 "Estimate: %u. Actual: %u. Available: %u\n",
1613 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1614 bufmgr_gem->exec_count),
1615 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1616 bufmgr_gem->exec_count),
1617 (unsigned int) bufmgr_gem->gtt_size);
1620 drm_intel_update_buffer_offsets2(bufmgr_gem);
1622 if (bufmgr_gem->bufmgr.debug)
1623 drm_intel_gem_dump_validation_list(bufmgr_gem);
1625 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1626 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1627 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1629 /* Disconnect the buffer from the validate list */
1630 bo_gem->validate_index = -1;
1631 bufmgr_gem->exec_bos[i] = NULL;
1633 bufmgr_gem->exec_count = 0;
1634 pthread_mutex_unlock(&bufmgr_gem->lock);
1640 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1641 drm_clip_rect_t *cliprects, int num_cliprects,
1644 return drm_intel_gem_bo_mrb_exec2(bo, used,
1645 cliprects, num_cliprects, DR4,
1650 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1652 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1653 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1654 struct drm_i915_gem_pin pin;
1657 memset(&pin, 0, sizeof(pin));
1658 pin.handle = bo_gem->gem_handle;
1659 pin.alignment = alignment;
1662 ret = ioctl(bufmgr_gem->fd,
1663 DRM_IOCTL_I915_GEM_PIN,
1665 } while (ret == -1 && errno == EINTR);
1670 bo->offset = pin.offset;
1675 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1677 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1678 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1679 struct drm_i915_gem_unpin unpin;
1682 memset(&unpin, 0, sizeof(unpin));
1683 unpin.handle = bo_gem->gem_handle;
1685 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1693 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1694 uint32_t tiling_mode,
1697 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1698 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1699 struct drm_i915_gem_set_tiling set_tiling;
1702 if (bo_gem->global_name == 0 &&
1703 tiling_mode == bo_gem->tiling_mode &&
1704 stride == bo_gem->stride)
1707 memset(&set_tiling, 0, sizeof(set_tiling));
1709 set_tiling.handle = bo_gem->gem_handle;
1710 set_tiling.tiling_mode = tiling_mode;
1711 set_tiling.stride = stride;
1713 ret = ioctl(bufmgr_gem->fd,
1714 DRM_IOCTL_I915_GEM_SET_TILING,
1716 } while (ret == -1 && errno == EINTR);
1720 bo_gem->tiling_mode = set_tiling.tiling_mode;
1721 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1722 bo_gem->stride = set_tiling.stride;
1727 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1730 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1731 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1734 /* Linear buffers have no stride. By ensuring that we only ever use
1735 * stride 0 with linear buffers, we simplify our code.
1737 if (*tiling_mode == I915_TILING_NONE)
1740 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1742 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1744 *tiling_mode = bo_gem->tiling_mode;
1749 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1750 uint32_t * swizzle_mode)
1752 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1754 *tiling_mode = bo_gem->tiling_mode;
1755 *swizzle_mode = bo_gem->swizzle_mode;
1760 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1762 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1763 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1764 struct drm_gem_flink flink;
1767 if (!bo_gem->global_name) {
1768 memset(&flink, 0, sizeof(flink));
1769 flink.handle = bo_gem->gem_handle;
1771 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1774 bo_gem->global_name = flink.name;
1775 bo_gem->reusable = 0;
1778 *name = bo_gem->global_name;
1783 * Enables unlimited caching of buffer objects for reuse.
1785 * This is potentially very memory expensive, as the cache at each bucket
1786 * size is only bounded by how many buffers of that size we've managed to have
1787 * in flight at once.
1790 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1792 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1794 bufmgr_gem->bo_reuse = 1;
1798 * Enable use of fenced reloc type.
1800 * New code should enable this to avoid unnecessary fence register
1801 * allocation. If this option is not enabled, all relocs will have fence
1802 * register allocated.
1805 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1807 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1809 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1810 bufmgr_gem->fenced_relocs = 1;
1814 * Return the additional aperture space required by the tree of buffer objects
1818 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1820 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1824 if (bo == NULL || bo_gem->included_in_check_aperture)
1828 bo_gem->included_in_check_aperture = 1;
1830 for (i = 0; i < bo_gem->reloc_count; i++)
1832 drm_intel_gem_bo_get_aperture_space(bo_gem->
1833 reloc_target_info[i].bo);
1839 * Count the number of buffers in this list that need a fence reg
1841 * If the count is greater than the number of available regs, we'll have
1842 * to ask the caller to resubmit a batch with fewer tiled buffers.
1844 * This function over-counts if the same buffer is used multiple times.
1847 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1850 unsigned int total = 0;
1852 for (i = 0; i < count; i++) {
1853 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1858 total += bo_gem->reloc_tree_fences;
1864 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1865 * for the next drm_intel_bufmgr_check_aperture_space() call.
1868 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1870 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1873 if (bo == NULL || !bo_gem->included_in_check_aperture)
1876 bo_gem->included_in_check_aperture = 0;
1878 for (i = 0; i < bo_gem->reloc_count; i++)
1879 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1880 reloc_target_info[i].bo);
1884 * Return a conservative estimate for the amount of aperture required
1885 * for a collection of buffers. This may double-count some buffers.
1888 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1891 unsigned int total = 0;
1893 for (i = 0; i < count; i++) {
1894 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1896 total += bo_gem->reloc_tree_size;
1902 * Return the amount of aperture needed for a collection of buffers.
1903 * This avoids double counting any buffers, at the cost of looking
1904 * at every buffer in the set.
1907 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1910 unsigned int total = 0;
1912 for (i = 0; i < count; i++) {
1913 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1914 /* For the first buffer object in the array, we get an
1915 * accurate count back for its reloc_tree size (since nothing
1916 * had been flagged as being counted yet). We can save that
1917 * value out as a more conservative reloc_tree_size that
1918 * avoids double-counting target buffers. Since the first
1919 * buffer happens to usually be the batch buffer in our
1920 * callers, this can pull us back from doing the tree
1921 * walk on every new batch emit.
1924 drm_intel_bo_gem *bo_gem =
1925 (drm_intel_bo_gem *) bo_array[i];
1926 bo_gem->reloc_tree_size = total;
1930 for (i = 0; i < count; i++)
1931 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1936 * Return -1 if the batchbuffer should be flushed before attempting to
1937 * emit rendering referencing the buffers pointed to by bo_array.
1939 * This is required because if we try to emit a batchbuffer with relocations
1940 * to a tree of buffers that won't simultaneously fit in the aperture,
1941 * the rendering will return an error at a point where the software is not
1942 * prepared to recover from it.
1944 * However, we also want to emit the batchbuffer significantly before we reach
1945 * the limit, as a series of batchbuffers each of which references buffers
1946 * covering almost all of the aperture means that at each emit we end up
1947 * waiting to evict a buffer from the last rendering, and we get synchronous
1948 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1949 * get better parallelism.
1952 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1954 drm_intel_bufmgr_gem *bufmgr_gem =
1955 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1956 unsigned int total = 0;
1957 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1960 /* Check for fence reg constraints if necessary */
1961 if (bufmgr_gem->available_fences) {
1962 total_fences = drm_intel_gem_total_fences(bo_array, count);
1963 if (total_fences > bufmgr_gem->available_fences)
1967 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1969 if (total > threshold)
1970 total = drm_intel_gem_compute_batch_space(bo_array, count);
1972 if (total > threshold) {
1973 DBG("check_space: overflowed available aperture, "
1975 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1978 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1979 (int)bufmgr_gem->gtt_size / 1024);
1985 * Disable buffer reuse for objects which are shared with the kernel
1986 * as scanout buffers
1989 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1991 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1993 bo_gem->reusable = 0;
1998 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2000 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2002 return bo_gem->reusable;
2006 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2008 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2011 for (i = 0; i < bo_gem->reloc_count; i++) {
2012 if (bo_gem->reloc_target_info[i].bo == target_bo)
2014 if (bo == bo_gem->reloc_target_info[i].bo)
2016 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2024 /** Return true if target_bo is referenced by bo's relocation tree. */
2026 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2028 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2030 if (bo == NULL || target_bo == NULL)
2032 if (target_bo_gem->used_as_reloc_target)
2033 return _drm_intel_gem_bo_references(bo, target_bo);
2038 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2040 unsigned int i = bufmgr_gem->num_buckets;
2042 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2044 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2045 bufmgr_gem->cache_bucket[i].size = size;
2046 bufmgr_gem->num_buckets++;
2050 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2052 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2054 /* OK, so power of two buckets was too wasteful of memory.
2055 * Give 3 other sizes between each power of two, to hopefully
2056 * cover things accurately enough. (The alternative is
2057 * probably to just go for exact matching of sizes, and assume
2058 * that for things like composited window resize the tiled
2059 * width/height alignment and rounding of sizes to pages will
2060 * get us useful cache hit rates anyway)
2062 add_bucket(bufmgr_gem, 4096);
2063 add_bucket(bufmgr_gem, 4096 * 2);
2064 add_bucket(bufmgr_gem, 4096 * 3);
2066 /* Initialize the linked lists for BO reuse cache. */
2067 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2068 add_bucket(bufmgr_gem, size);
2070 add_bucket(bufmgr_gem, size + size * 1 / 4);
2071 add_bucket(bufmgr_gem, size + size * 2 / 4);
2072 add_bucket(bufmgr_gem, size + size * 3 / 4);
2077 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2078 * and manage map buffer objections.
2080 * \param fd File descriptor of the opened DRM device.
2083 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2085 drm_intel_bufmgr_gem *bufmgr_gem;
2086 struct drm_i915_gem_get_aperture aperture;
2087 drm_i915_getparam_t gp;
2089 int exec2 = 0, has_bsd = 0;
2091 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2092 if (bufmgr_gem == NULL)
2095 bufmgr_gem->fd = fd;
2097 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2102 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
2105 bufmgr_gem->gtt_size = aperture.aper_available_size;
2107 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2109 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2110 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2111 "May lead to reduced performance or incorrect "
2113 (int)bufmgr_gem->gtt_size / 1024);
2116 gp.param = I915_PARAM_CHIPSET_ID;
2117 gp.value = &bufmgr_gem->pci_device;
2118 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2120 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2121 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2124 if (IS_GEN2(bufmgr_gem))
2125 bufmgr_gem->gen = 2;
2126 else if (IS_GEN3(bufmgr_gem))
2127 bufmgr_gem->gen = 3;
2128 else if (IS_GEN4(bufmgr_gem))
2129 bufmgr_gem->gen = 4;
2131 bufmgr_gem->gen = 6;
2133 gp.param = I915_PARAM_HAS_EXECBUF2;
2134 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2138 gp.param = I915_PARAM_HAS_BSD;
2139 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2143 if (bufmgr_gem->gen < 4) {
2144 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2145 gp.value = &bufmgr_gem->available_fences;
2146 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2148 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2150 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2152 bufmgr_gem->available_fences = 0;
2154 /* XXX The kernel reports the total number of fences,
2155 * including any that may be pinned.
2157 * We presume that there will be at least one pinned
2158 * fence for the scanout buffer, but there may be more
2159 * than one scanout and the user may be manually
2160 * pinning buffers. Let's move to execbuffer2 and
2161 * thereby forget the insanity of using fences...
2163 bufmgr_gem->available_fences -= 2;
2164 if (bufmgr_gem->available_fences < 0)
2165 bufmgr_gem->available_fences = 0;
2169 /* Let's go with one relocation per every 2 dwords (but round down a bit
2170 * since a power of two will mean an extra page allocation for the reloc
2173 * Every 4 was too few for the blender benchmark.
2175 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2177 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2178 bufmgr_gem->bufmgr.bo_alloc_for_render =
2179 drm_intel_gem_bo_alloc_for_render;
2180 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2181 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2182 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2183 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2184 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2185 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2186 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2187 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2188 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2189 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2190 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2191 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2192 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2193 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2194 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2195 /* Use the new one if available */
2197 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2199 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2201 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2202 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2203 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2204 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2205 bufmgr_gem->bufmgr.debug = 0;
2206 bufmgr_gem->bufmgr.check_aperture_space =
2207 drm_intel_gem_check_aperture_space;
2208 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2209 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2210 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2211 drm_intel_gem_get_pipe_from_crtc_id;
2212 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2214 init_cache_buckets(bufmgr_gem);
2216 return &bufmgr_gem->bufmgr;