1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <xf86atomic.h>
50 #include <sys/ioctl.h>
52 #include <sys/types.h>
57 #define ETIME ETIMEDOUT
59 #include "libdrm_macros.h"
60 #include "libdrm_lists.h"
61 #include "intel_bufmgr.h"
62 #include "intel_bufmgr_priv.h"
63 #include "intel_chipset.h"
77 #define memclear(s) memset(&s, 0, sizeof(s))
79 #define DBG(...) do { \
80 if (bufmgr_gem->bufmgr.debug) \
81 fprintf(stderr, __VA_ARGS__); \
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
85 #define MAX2(A, B) ((A) > (B) ? (A) : (B))
88 * upper_32_bits - return bits 32-63 of a number
89 * @n: the number we're accessing
91 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
92 * the "right shift count >= width of type" warning when that quantity is
95 #define upper_32_bits(n) ((__u32)(((n) >> 16) >> 16))
98 * lower_32_bits - return bits 0-31 of a number
99 * @n: the number we're accessing
101 #define lower_32_bits(n) ((__u32)(n))
103 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
105 struct drm_intel_gem_bo_bucket {
110 typedef struct _drm_intel_bufmgr_gem {
111 drm_intel_bufmgr bufmgr;
119 pthread_mutex_t lock;
121 struct drm_i915_gem_exec_object *exec_objects;
122 struct drm_i915_gem_exec_object2 *exec2_objects;
123 drm_intel_bo **exec_bos;
127 /** Array of lists of cached gem objects of power-of-two sizes */
128 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
132 drmMMListHead managers;
134 drm_intel_bo_gem *name_table;
135 drm_intel_bo_gem *handle_table;
137 drmMMListHead vma_cache;
138 int vma_count, vma_open, vma_max;
141 int available_fences;
144 unsigned int has_bsd : 1;
145 unsigned int has_blt : 1;
146 unsigned int has_relaxed_fencing : 1;
147 unsigned int has_llc : 1;
148 unsigned int has_wait_timeout : 1;
149 unsigned int bo_reuse : 1;
150 unsigned int no_exec : 1;
151 unsigned int has_vebox : 1;
152 unsigned int has_exec_async : 1;
160 } drm_intel_bufmgr_gem;
162 #define DRM_INTEL_RELOC_FENCE (1<<0)
164 typedef struct _drm_intel_reloc_target_info {
167 } drm_intel_reloc_target;
169 struct _drm_intel_bo_gem {
177 * Kenel-assigned global name for this object
179 * List contains both flink named and prime fd'd objects
181 unsigned int global_name;
183 UT_hash_handle handle_hh;
184 UT_hash_handle name_hh;
187 * Index of the buffer within the validation list while preparing a
188 * batchbuffer execution.
193 * Current tiling mode
195 uint32_t tiling_mode;
196 uint32_t swizzle_mode;
197 unsigned long stride;
199 unsigned long kflags;
203 /** Array passed to the DRM containing relocation information. */
204 struct drm_i915_gem_relocation_entry *relocs;
206 * Array of info structs corresponding to relocs[i].target_handle etc
208 drm_intel_reloc_target *reloc_target_info;
209 /** Number of entries in relocs */
211 /** Array of BOs that are referenced by this buffer and will be softpinned */
212 drm_intel_bo **softpin_target;
213 /** Number softpinned BOs that are referenced by this buffer */
214 int softpin_target_count;
215 /** Maximum amount of softpinned BOs that are referenced by this buffer */
216 int softpin_target_size;
218 /** Mapped address for the buffer, saved across map/unmap cycles */
220 /** GTT virtual address for the buffer, saved across map/unmap cycles */
222 /** WC CPU address for the buffer, saved across map/unmap cycles */
225 * Virtual address of the buffer allocated by user, used for userptr
230 drmMMListHead vma_list;
236 * Boolean of whether this BO and its children have been included in
237 * the current drm_intel_bufmgr_check_aperture_space() total.
239 bool included_in_check_aperture;
242 * Boolean of whether this buffer has been used as a relocation
243 * target and had its size accounted for, and thus can't have any
244 * further relocations added to it.
246 bool used_as_reloc_target;
249 * Boolean of whether we have encountered an error whilst building the relocation tree.
254 * Boolean of whether this buffer can be re-used
259 * Boolean of whether the GPU is definitely not accessing the buffer.
261 * This is only valid when reusable, since non-reusable
262 * buffers are those that have been shared with other
263 * processes, so we don't know their state.
268 * Boolean of whether this buffer was allocated with userptr
273 * Boolean of whether this buffer can be placed in the full 48-bit
274 * address range on gen8+.
276 * By default, buffers will be keep in a 32-bit range, unless this
277 * flag is explicitly set.
279 bool use_48b_address_range;
282 * Whether this buffer is softpinned at offset specified by the user
287 * Size in bytes of this buffer and its relocation descendents.
289 * Used to avoid costly tree walking in
290 * drm_intel_bufmgr_check_aperture in the common case.
295 * Number of potential fence registers required by this buffer and its
298 int reloc_tree_fences;
300 /** Flags that we may need to do the SW_FINISH ioctl on unmap. */
301 bool mapped_cpu_write;
305 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
308 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
311 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
312 uint32_t * swizzle_mode);
315 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
316 uint32_t tiling_mode,
319 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
322 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
324 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
326 static inline drm_intel_bo_gem *to_bo_gem(drm_intel_bo *bo)
328 return (drm_intel_bo_gem *)bo;
332 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
333 uint32_t *tiling_mode)
335 unsigned long min_size, max_size;
338 if (*tiling_mode == I915_TILING_NONE)
341 /* 965+ just need multiples of page size for tiling */
342 if (bufmgr_gem->gen >= 4)
343 return ROUND_UP_TO(size, 4096);
345 /* Older chips need powers of two, of at least 512k or 1M */
346 if (bufmgr_gem->gen == 3) {
347 min_size = 1024*1024;
348 max_size = 128*1024*1024;
351 max_size = 64*1024*1024;
354 if (size > max_size) {
355 *tiling_mode = I915_TILING_NONE;
359 /* Do we need to allocate every page for the fence? */
360 if (bufmgr_gem->has_relaxed_fencing)
361 return ROUND_UP_TO(size, 4096);
363 for (i = min_size; i < size; i <<= 1)
370 * Round a given pitch up to the minimum required for X tiling on a
371 * given chip. We use 512 as the minimum to allow for a later tiling
375 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
376 unsigned long pitch, uint32_t *tiling_mode)
378 unsigned long tile_width;
381 /* If untiled, then just align it so that we can do rendering
382 * to it with the 3D engine.
384 if (*tiling_mode == I915_TILING_NONE)
385 return ALIGN(pitch, 64);
387 if (*tiling_mode == I915_TILING_X
388 || (IS_915(bufmgr_gem->pci_device)
389 && *tiling_mode == I915_TILING_Y))
394 /* 965 is flexible */
395 if (bufmgr_gem->gen >= 4)
396 return ROUND_UP_TO(pitch, tile_width);
398 /* The older hardware has a maximum pitch of 8192 with tiled
399 * surfaces, so fallback to untiled if it's too large.
402 *tiling_mode = I915_TILING_NONE;
403 return ALIGN(pitch, 64);
406 /* Pre-965 needs power of two tile width */
407 for (i = tile_width; i < pitch; i <<= 1)
413 static struct drm_intel_gem_bo_bucket *
414 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
419 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
420 struct drm_intel_gem_bo_bucket *bucket =
421 &bufmgr_gem->cache_bucket[i];
422 if (bucket->size >= size) {
431 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
435 for (i = 0; i < bufmgr_gem->exec_count; i++) {
436 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
437 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
439 if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) {
440 DBG("%2d: %d %s(%s)\n", i, bo_gem->gem_handle,
441 bo_gem->is_softpin ? "*" : "",
446 for (j = 0; j < bo_gem->reloc_count; j++) {
447 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
448 drm_intel_bo_gem *target_gem =
449 (drm_intel_bo_gem *) target_bo;
451 DBG("%2d: %d %s(%s)@0x%08x %08x -> "
452 "%d (%s)@0x%08x %08x + 0x%08x\n",
455 bo_gem->is_softpin ? "*" : "",
457 upper_32_bits(bo_gem->relocs[j].offset),
458 lower_32_bits(bo_gem->relocs[j].offset),
459 target_gem->gem_handle,
461 upper_32_bits(target_bo->offset64),
462 lower_32_bits(target_bo->offset64),
463 bo_gem->relocs[j].delta);
466 for (j = 0; j < bo_gem->softpin_target_count; j++) {
467 drm_intel_bo *target_bo = bo_gem->softpin_target[j];
468 drm_intel_bo_gem *target_gem =
469 (drm_intel_bo_gem *) target_bo;
470 DBG("%2d: %d %s(%s) -> "
471 "%d *(%s)@0x%08x %08x\n",
474 bo_gem->is_softpin ? "*" : "",
476 target_gem->gem_handle,
478 upper_32_bits(target_bo->offset64),
479 lower_32_bits(target_bo->offset64));
485 drm_intel_gem_bo_reference(drm_intel_bo *bo)
487 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
489 atomic_inc(&bo_gem->refcount);
493 * Adds the given buffer to the list of buffers to be validated (moved into the
494 * appropriate memory type) with the next batch submission.
496 * If a buffer is validated multiple times in a batch submission, it ends up
497 * with the intersection of the memory type flags and the union of the
501 drm_intel_add_validate_buffer(drm_intel_bo *bo)
503 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
504 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
507 if (bo_gem->validate_index != -1)
510 /* Extend the array of validation entries as necessary. */
511 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
512 int new_size = bufmgr_gem->exec_size * 2;
517 bufmgr_gem->exec_objects =
518 realloc(bufmgr_gem->exec_objects,
519 sizeof(*bufmgr_gem->exec_objects) * new_size);
520 bufmgr_gem->exec_bos =
521 realloc(bufmgr_gem->exec_bos,
522 sizeof(*bufmgr_gem->exec_bos) * new_size);
523 bufmgr_gem->exec_size = new_size;
526 index = bufmgr_gem->exec_count;
527 bo_gem->validate_index = index;
528 /* Fill in array entry */
529 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
530 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
531 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
532 bufmgr_gem->exec_objects[index].alignment = bo->align;
533 bufmgr_gem->exec_objects[index].offset = 0;
534 bufmgr_gem->exec_bos[index] = bo;
535 bufmgr_gem->exec_count++;
539 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
541 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
542 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
547 flags |= EXEC_OBJECT_NEEDS_FENCE;
548 if (bo_gem->use_48b_address_range)
549 flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
550 if (bo_gem->is_softpin)
551 flags |= EXEC_OBJECT_PINNED;
553 if (bo_gem->validate_index != -1) {
554 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= flags;
558 /* Extend the array of validation entries as necessary. */
559 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
560 int new_size = bufmgr_gem->exec_size * 2;
565 bufmgr_gem->exec2_objects =
566 realloc(bufmgr_gem->exec2_objects,
567 sizeof(*bufmgr_gem->exec2_objects) * new_size);
568 bufmgr_gem->exec_bos =
569 realloc(bufmgr_gem->exec_bos,
570 sizeof(*bufmgr_gem->exec_bos) * new_size);
571 bufmgr_gem->exec_size = new_size;
574 index = bufmgr_gem->exec_count;
575 bo_gem->validate_index = index;
576 /* Fill in array entry */
577 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
578 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
579 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
580 bufmgr_gem->exec2_objects[index].alignment = bo->align;
581 bufmgr_gem->exec2_objects[index].offset = bo->offset64;
582 bufmgr_gem->exec2_objects[index].flags = flags | bo_gem->kflags;
583 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
584 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
585 bufmgr_gem->exec_bos[index] = bo;
586 bufmgr_gem->exec_count++;
589 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
593 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
594 drm_intel_bo_gem *bo_gem,
595 unsigned int alignment)
599 assert(!bo_gem->used_as_reloc_target);
601 /* The older chipsets are far-less flexible in terms of tiling,
602 * and require tiled buffer to be size aligned in the aperture.
603 * This means that in the worst possible case we will need a hole
604 * twice as large as the object in order for it to fit into the
605 * aperture. Optimal packing is for wimps.
607 size = bo_gem->bo.size;
608 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
609 unsigned int min_size;
611 if (bufmgr_gem->has_relaxed_fencing) {
612 if (bufmgr_gem->gen == 3)
613 min_size = 1024*1024;
617 while (min_size < size)
622 /* Account for worst-case alignment. */
623 alignment = MAX2(alignment, min_size);
626 bo_gem->reloc_tree_size = size + alignment;
630 drm_intel_setup_reloc_list(drm_intel_bo *bo)
632 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
633 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
634 unsigned int max_relocs = bufmgr_gem->max_relocs;
636 if (bo->size / 4 < max_relocs)
637 max_relocs = bo->size / 4;
639 bo_gem->relocs = malloc(max_relocs *
640 sizeof(struct drm_i915_gem_relocation_entry));
641 bo_gem->reloc_target_info = malloc(max_relocs *
642 sizeof(drm_intel_reloc_target));
643 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
644 bo_gem->has_error = true;
646 free (bo_gem->relocs);
647 bo_gem->relocs = NULL;
649 free (bo_gem->reloc_target_info);
650 bo_gem->reloc_target_info = NULL;
659 drm_intel_gem_bo_busy(drm_intel_bo *bo)
661 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
662 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
663 struct drm_i915_gem_busy busy;
666 if (bo_gem->reusable && bo_gem->idle)
670 busy.handle = bo_gem->gem_handle;
672 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
674 bo_gem->idle = !busy.busy;
679 return (ret == 0 && busy.busy);
683 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
684 drm_intel_bo_gem *bo_gem, int state)
686 struct drm_i915_gem_madvise madv;
689 madv.handle = bo_gem->gem_handle;
692 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
694 return madv.retained;
698 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
700 return drm_intel_gem_bo_madvise_internal
701 ((drm_intel_bufmgr_gem *) bo->bufmgr,
702 (drm_intel_bo_gem *) bo,
706 /* drop the oldest entries that have been purged by the kernel */
708 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
709 struct drm_intel_gem_bo_bucket *bucket)
711 while (!DRMLISTEMPTY(&bucket->head)) {
712 drm_intel_bo_gem *bo_gem;
714 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
715 bucket->head.next, head);
716 if (drm_intel_gem_bo_madvise_internal
717 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
720 DRMLISTDEL(&bo_gem->head);
721 drm_intel_gem_bo_free(&bo_gem->bo);
725 static drm_intel_bo *
726 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
730 uint32_t tiling_mode,
731 unsigned long stride,
732 unsigned int alignment)
734 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
735 drm_intel_bo_gem *bo_gem;
736 unsigned int page_size = getpagesize();
738 struct drm_intel_gem_bo_bucket *bucket;
739 bool alloc_from_cache;
740 unsigned long bo_size;
741 bool for_render = false;
743 if (flags & BO_ALLOC_FOR_RENDER)
746 /* Round the allocated size up to a power of two number of pages. */
747 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
749 /* If we don't have caching at this size, don't actually round the
752 if (bucket == NULL) {
754 if (bo_size < page_size)
757 bo_size = bucket->size;
760 pthread_mutex_lock(&bufmgr_gem->lock);
761 /* Get a buffer out of the cache if available */
763 alloc_from_cache = false;
764 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
766 /* Allocate new render-target BOs from the tail (MRU)
767 * of the list, as it will likely be hot in the GPU
768 * cache and in the aperture for us.
770 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
771 bucket->head.prev, head);
772 DRMLISTDEL(&bo_gem->head);
773 alloc_from_cache = true;
774 bo_gem->bo.align = alignment;
776 assert(alignment == 0);
777 /* For non-render-target BOs (where we're probably
778 * going to map it first thing in order to fill it
779 * with data), check if the last BO in the cache is
780 * unbusy, and only reuse in that case. Otherwise,
781 * allocating a new buffer is probably faster than
782 * waiting for the GPU to finish.
784 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
785 bucket->head.next, head);
786 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
787 alloc_from_cache = true;
788 DRMLISTDEL(&bo_gem->head);
792 if (alloc_from_cache) {
793 if (!drm_intel_gem_bo_madvise_internal
794 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
795 drm_intel_gem_bo_free(&bo_gem->bo);
796 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
801 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
804 drm_intel_gem_bo_free(&bo_gem->bo);
810 if (!alloc_from_cache) {
811 struct drm_i915_gem_create create;
813 bo_gem = calloc(1, sizeof(*bo_gem));
817 /* drm_intel_gem_bo_free calls DRMLISTDEL() for an uninitialized
818 list (vma_list), so better set the list head here */
819 DRMINITLISTHEAD(&bo_gem->vma_list);
821 bo_gem->bo.size = bo_size;
824 create.size = bo_size;
826 ret = drmIoctl(bufmgr_gem->fd,
827 DRM_IOCTL_I915_GEM_CREATE,
834 bo_gem->gem_handle = create.handle;
835 bo_gem->bo.handle = bo_gem->gem_handle;
836 bo_gem->bo.bufmgr = bufmgr;
837 bo_gem->bo.align = alignment;
839 bo_gem->tiling_mode = I915_TILING_NONE;
840 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
843 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
848 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
849 gem_handle, sizeof(bo_gem->gem_handle),
854 atomic_set(&bo_gem->refcount, 1);
855 bo_gem->validate_index = -1;
856 bo_gem->reloc_tree_fences = 0;
857 bo_gem->used_as_reloc_target = false;
858 bo_gem->has_error = false;
859 bo_gem->reusable = true;
860 bo_gem->use_48b_address_range = false;
862 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, alignment);
863 pthread_mutex_unlock(&bufmgr_gem->lock);
865 DBG("bo_create: buf %d (%s) %ldb\n",
866 bo_gem->gem_handle, bo_gem->name, size);
871 drm_intel_gem_bo_free(&bo_gem->bo);
873 pthread_mutex_unlock(&bufmgr_gem->lock);
877 static drm_intel_bo *
878 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
881 unsigned int alignment)
883 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
889 static drm_intel_bo *
890 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
893 unsigned int alignment)
895 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
896 I915_TILING_NONE, 0, 0);
899 static drm_intel_bo *
900 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
901 int x, int y, int cpp, uint32_t *tiling_mode,
902 unsigned long *pitch, unsigned long flags)
904 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
905 unsigned long size, stride;
909 unsigned long aligned_y, height_alignment;
911 tiling = *tiling_mode;
913 /* If we're tiled, our allocations are in 8 or 32-row blocks,
914 * so failure to align our height means that we won't allocate
917 * If we're untiled, we still have to align to 2 rows high
918 * because the data port accesses 2x2 blocks even if the
919 * bottom row isn't to be rendered, so failure to align means
920 * we could walk off the end of the GTT and fault. This is
921 * documented on 965, and may be the case on older chipsets
922 * too so we try to be careful.
925 height_alignment = 2;
927 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
928 height_alignment = 16;
929 else if (tiling == I915_TILING_X
930 || (IS_915(bufmgr_gem->pci_device)
931 && tiling == I915_TILING_Y))
932 height_alignment = 8;
933 else if (tiling == I915_TILING_Y)
934 height_alignment = 32;
935 aligned_y = ALIGN(y, height_alignment);
938 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
939 size = stride * aligned_y;
940 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
941 } while (*tiling_mode != tiling);
944 if (tiling == I915_TILING_NONE)
947 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
951 static drm_intel_bo *
952 drm_intel_gem_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
955 uint32_t tiling_mode,
960 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
961 drm_intel_bo_gem *bo_gem;
963 struct drm_i915_gem_userptr userptr;
965 /* Tiling with userptr surfaces is not supported
966 * on all hardware so refuse it for time being.
968 if (tiling_mode != I915_TILING_NONE)
971 bo_gem = calloc(1, sizeof(*bo_gem));
975 atomic_set(&bo_gem->refcount, 1);
976 DRMINITLISTHEAD(&bo_gem->vma_list);
978 bo_gem->bo.size = size;
981 userptr.user_ptr = (__u64)((unsigned long)addr);
982 userptr.user_size = size;
983 userptr.flags = flags;
985 ret = drmIoctl(bufmgr_gem->fd,
986 DRM_IOCTL_I915_GEM_USERPTR,
989 DBG("bo_create_userptr: "
990 "ioctl failed with user ptr %p size 0x%lx, "
991 "user flags 0x%lx\n", addr, size, flags);
996 pthread_mutex_lock(&bufmgr_gem->lock);
998 bo_gem->gem_handle = userptr.handle;
999 bo_gem->bo.handle = bo_gem->gem_handle;
1000 bo_gem->bo.bufmgr = bufmgr;
1001 bo_gem->is_userptr = true;
1002 bo_gem->bo.virtual = addr;
1003 /* Save the address provided by user */
1004 bo_gem->user_virtual = addr;
1005 bo_gem->tiling_mode = I915_TILING_NONE;
1006 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
1009 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
1010 gem_handle, sizeof(bo_gem->gem_handle),
1013 bo_gem->name = name;
1014 bo_gem->validate_index = -1;
1015 bo_gem->reloc_tree_fences = 0;
1016 bo_gem->used_as_reloc_target = false;
1017 bo_gem->has_error = false;
1018 bo_gem->reusable = false;
1019 bo_gem->use_48b_address_range = false;
1021 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
1022 pthread_mutex_unlock(&bufmgr_gem->lock);
1024 DBG("bo_create_userptr: "
1025 "ptr %p buf %d (%s) size %ldb, stride 0x%x, tile mode %d\n",
1026 addr, bo_gem->gem_handle, bo_gem->name,
1027 size, stride, tiling_mode);
1033 has_userptr(drm_intel_bufmgr_gem *bufmgr_gem)
1038 struct drm_i915_gem_userptr userptr;
1040 pgsz = sysconf(_SC_PAGESIZE);
1043 ret = posix_memalign(&ptr, pgsz, pgsz);
1045 DBG("Failed to get a page (%ld) for userptr detection!\n",
1051 userptr.user_ptr = (__u64)(unsigned long)ptr;
1052 userptr.user_size = pgsz;
1055 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_USERPTR, &userptr);
1057 if (errno == ENODEV && userptr.flags == 0) {
1058 userptr.flags = I915_USERPTR_UNSYNCHRONIZED;
1065 /* We don't release the userptr bo here as we want to keep the
1066 * kernel mm tracking alive for our lifetime. The first time we
1067 * create a userptr object the kernel has to install a mmu_notifer
1068 * which is a heavyweight operation (e.g. it requires taking all
1069 * mm_locks and stop_machine()).
1072 bufmgr_gem->userptr_active.ptr = ptr;
1073 bufmgr_gem->userptr_active.handle = userptr.handle;
1078 static drm_intel_bo *
1079 check_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
1082 uint32_t tiling_mode,
1085 unsigned long flags)
1087 if (has_userptr((drm_intel_bufmgr_gem *)bufmgr))
1088 bufmgr->bo_alloc_userptr = drm_intel_gem_bo_alloc_userptr;
1090 bufmgr->bo_alloc_userptr = NULL;
1092 return drm_intel_bo_alloc_userptr(bufmgr, name, addr,
1093 tiling_mode, stride, size, flags);
1097 * Returns a drm_intel_bo wrapping the given buffer object handle.
1099 * This can be used when one application needs to pass a buffer object
1103 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
1105 unsigned int handle)
1107 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1108 drm_intel_bo_gem *bo_gem;
1110 struct drm_gem_open open_arg;
1111 struct drm_i915_gem_get_tiling get_tiling;
1113 /* At the moment most applications only have a few named bo.
1114 * For instance, in a DRI client only the render buffers passed
1115 * between X and the client are named. And since X returns the
1116 * alternating names for the front/back buffer a linear search
1117 * provides a sufficiently fast match.
1119 pthread_mutex_lock(&bufmgr_gem->lock);
1120 HASH_FIND(name_hh, bufmgr_gem->name_table,
1121 &handle, sizeof(handle), bo_gem);
1123 drm_intel_gem_bo_reference(&bo_gem->bo);
1128 open_arg.name = handle;
1129 ret = drmIoctl(bufmgr_gem->fd,
1133 DBG("Couldn't reference %s handle 0x%08x: %s\n",
1134 name, handle, strerror(errno));
1138 /* Now see if someone has used a prime handle to get this
1139 * object from the kernel before by looking through the list
1140 * again for a matching gem_handle
1142 HASH_FIND(handle_hh, bufmgr_gem->handle_table,
1143 &open_arg.handle, sizeof(open_arg.handle), bo_gem);
1145 drm_intel_gem_bo_reference(&bo_gem->bo);
1149 bo_gem = calloc(1, sizeof(*bo_gem));
1153 atomic_set(&bo_gem->refcount, 1);
1154 DRMINITLISTHEAD(&bo_gem->vma_list);
1156 bo_gem->bo.size = open_arg.size;
1157 bo_gem->bo.offset = 0;
1158 bo_gem->bo.offset64 = 0;
1159 bo_gem->bo.virtual = NULL;
1160 bo_gem->bo.bufmgr = bufmgr;
1161 bo_gem->name = name;
1162 bo_gem->validate_index = -1;
1163 bo_gem->gem_handle = open_arg.handle;
1164 bo_gem->bo.handle = open_arg.handle;
1165 bo_gem->global_name = handle;
1166 bo_gem->reusable = false;
1167 bo_gem->use_48b_address_range = false;
1169 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
1170 gem_handle, sizeof(bo_gem->gem_handle), bo_gem);
1171 HASH_ADD(name_hh, bufmgr_gem->name_table,
1172 global_name, sizeof(bo_gem->global_name), bo_gem);
1174 memclear(get_tiling);
1175 get_tiling.handle = bo_gem->gem_handle;
1176 ret = drmIoctl(bufmgr_gem->fd,
1177 DRM_IOCTL_I915_GEM_GET_TILING,
1182 bo_gem->tiling_mode = get_tiling.tiling_mode;
1183 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
1184 /* XXX stride is unknown */
1185 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
1186 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
1189 pthread_mutex_unlock(&bufmgr_gem->lock);
1193 drm_intel_gem_bo_free(&bo_gem->bo);
1194 pthread_mutex_unlock(&bufmgr_gem->lock);
1199 drm_intel_gem_bo_free(drm_intel_bo *bo)
1201 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1202 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1203 struct drm_gem_close close;
1206 DRMLISTDEL(&bo_gem->vma_list);
1207 if (bo_gem->mem_virtual) {
1208 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0));
1209 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1210 bufmgr_gem->vma_count--;
1212 if (bo_gem->wc_virtual) {
1213 VG(VALGRIND_FREELIKE_BLOCK(bo_gem->wc_virtual, 0));
1214 drm_munmap(bo_gem->wc_virtual, bo_gem->bo.size);
1215 bufmgr_gem->vma_count--;
1217 if (bo_gem->gtt_virtual) {
1218 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1219 bufmgr_gem->vma_count--;
1222 if (bo_gem->global_name)
1223 HASH_DELETE(name_hh, bufmgr_gem->name_table, bo_gem);
1224 HASH_DELETE(handle_hh, bufmgr_gem->handle_table, bo_gem);
1226 /* Close this object */
1228 close.handle = bo_gem->gem_handle;
1229 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
1231 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
1232 bo_gem->gem_handle, bo_gem->name, strerror(errno));
1238 drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo)
1241 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1243 if (bo_gem->mem_virtual)
1244 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size);
1246 if (bo_gem->wc_virtual)
1247 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->wc_virtual, bo->size);
1249 if (bo_gem->gtt_virtual)
1250 VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size);
1254 /** Frees all cached buffers significantly older than @time. */
1256 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
1260 if (bufmgr_gem->time == time)
1263 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1264 struct drm_intel_gem_bo_bucket *bucket =
1265 &bufmgr_gem->cache_bucket[i];
1267 while (!DRMLISTEMPTY(&bucket->head)) {
1268 drm_intel_bo_gem *bo_gem;
1270 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1271 bucket->head.next, head);
1272 if (time - bo_gem->free_time <= 1)
1275 DRMLISTDEL(&bo_gem->head);
1277 drm_intel_gem_bo_free(&bo_gem->bo);
1281 bufmgr_gem->time = time;
1284 static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
1288 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
1289 bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max);
1291 if (bufmgr_gem->vma_max < 0)
1294 /* We may need to evict a few entries in order to create new mmaps */
1295 limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open;
1299 while (bufmgr_gem->vma_count > limit) {
1300 drm_intel_bo_gem *bo_gem;
1302 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1303 bufmgr_gem->vma_cache.next,
1305 assert(bo_gem->map_count == 0);
1306 DRMLISTDELINIT(&bo_gem->vma_list);
1308 if (bo_gem->mem_virtual) {
1309 drm_munmap(bo_gem->mem_virtual, bo_gem->bo.size);
1310 bo_gem->mem_virtual = NULL;
1311 bufmgr_gem->vma_count--;
1313 if (bo_gem->wc_virtual) {
1314 drm_munmap(bo_gem->wc_virtual, bo_gem->bo.size);
1315 bo_gem->wc_virtual = NULL;
1316 bufmgr_gem->vma_count--;
1318 if (bo_gem->gtt_virtual) {
1319 drm_munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
1320 bo_gem->gtt_virtual = NULL;
1321 bufmgr_gem->vma_count--;
1326 static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1327 drm_intel_bo_gem *bo_gem)
1329 bufmgr_gem->vma_open--;
1330 DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache);
1331 if (bo_gem->mem_virtual)
1332 bufmgr_gem->vma_count++;
1333 if (bo_gem->wc_virtual)
1334 bufmgr_gem->vma_count++;
1335 if (bo_gem->gtt_virtual)
1336 bufmgr_gem->vma_count++;
1337 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1340 static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem,
1341 drm_intel_bo_gem *bo_gem)
1343 bufmgr_gem->vma_open++;
1344 DRMLISTDEL(&bo_gem->vma_list);
1345 if (bo_gem->mem_virtual)
1346 bufmgr_gem->vma_count--;
1347 if (bo_gem->wc_virtual)
1348 bufmgr_gem->vma_count--;
1349 if (bo_gem->gtt_virtual)
1350 bufmgr_gem->vma_count--;
1351 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
1355 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
1357 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1358 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1359 struct drm_intel_gem_bo_bucket *bucket;
1362 /* Unreference all the target buffers */
1363 for (i = 0; i < bo_gem->reloc_count; i++) {
1364 if (bo_gem->reloc_target_info[i].bo != bo) {
1365 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1366 reloc_target_info[i].bo,
1370 for (i = 0; i < bo_gem->softpin_target_count; i++)
1371 drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i],
1374 bo_gem->reloc_count = 0;
1375 bo_gem->used_as_reloc_target = false;
1376 bo_gem->softpin_target_count = 0;
1378 DBG("bo_unreference final: %d (%s)\n",
1379 bo_gem->gem_handle, bo_gem->name);
1381 /* release memory associated with this object */
1382 if (bo_gem->reloc_target_info) {
1383 free(bo_gem->reloc_target_info);
1384 bo_gem->reloc_target_info = NULL;
1386 if (bo_gem->relocs) {
1387 free(bo_gem->relocs);
1388 bo_gem->relocs = NULL;
1390 if (bo_gem->softpin_target) {
1391 free(bo_gem->softpin_target);
1392 bo_gem->softpin_target = NULL;
1393 bo_gem->softpin_target_size = 0;
1396 /* Clear any left-over mappings */
1397 if (bo_gem->map_count) {
1398 DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count);
1399 bo_gem->map_count = 0;
1400 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1401 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1404 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
1405 /* Put the buffer into our internal cache for reuse if we can. */
1406 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
1407 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
1408 I915_MADV_DONTNEED)) {
1409 bo_gem->free_time = time;
1411 bo_gem->name = NULL;
1412 bo_gem->validate_index = -1;
1414 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
1416 drm_intel_gem_bo_free(bo);
1420 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
1423 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1425 assert(atomic_read(&bo_gem->refcount) > 0);
1426 if (atomic_dec_and_test(&bo_gem->refcount))
1427 drm_intel_gem_bo_unreference_final(bo, time);
1430 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
1432 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1434 assert(atomic_read(&bo_gem->refcount) > 0);
1436 if (atomic_add_unless(&bo_gem->refcount, -1, 1)) {
1437 drm_intel_bufmgr_gem *bufmgr_gem =
1438 (drm_intel_bufmgr_gem *) bo->bufmgr;
1439 struct timespec time;
1441 clock_gettime(CLOCK_MONOTONIC, &time);
1443 pthread_mutex_lock(&bufmgr_gem->lock);
1445 if (atomic_dec_and_test(&bo_gem->refcount)) {
1446 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
1447 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1450 pthread_mutex_unlock(&bufmgr_gem->lock);
1454 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1456 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1457 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1458 struct drm_i915_gem_set_domain set_domain;
1461 if (bo_gem->is_userptr) {
1462 /* Return the same user ptr */
1463 bo->virtual = bo_gem->user_virtual;
1467 pthread_mutex_lock(&bufmgr_gem->lock);
1469 if (bo_gem->map_count++ == 0)
1470 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1472 if (!bo_gem->mem_virtual) {
1473 struct drm_i915_gem_mmap mmap_arg;
1475 DBG("bo_map: %d (%s), map_count=%d\n",
1476 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1479 mmap_arg.handle = bo_gem->gem_handle;
1480 mmap_arg.size = bo->size;
1481 ret = drmIoctl(bufmgr_gem->fd,
1482 DRM_IOCTL_I915_GEM_MMAP,
1486 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1487 __FILE__, __LINE__, bo_gem->gem_handle,
1488 bo_gem->name, strerror(errno));
1489 if (--bo_gem->map_count == 0)
1490 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1491 pthread_mutex_unlock(&bufmgr_gem->lock);
1494 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1495 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1497 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1498 bo_gem->mem_virtual);
1499 bo->virtual = bo_gem->mem_virtual;
1501 memclear(set_domain);
1502 set_domain.handle = bo_gem->gem_handle;
1503 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1505 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1507 set_domain.write_domain = 0;
1508 ret = drmIoctl(bufmgr_gem->fd,
1509 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1512 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1513 __FILE__, __LINE__, bo_gem->gem_handle,
1518 bo_gem->mapped_cpu_write = true;
1520 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1521 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
1522 pthread_mutex_unlock(&bufmgr_gem->lock);
1528 map_gtt(drm_intel_bo *bo)
1530 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1531 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1534 if (bo_gem->is_userptr)
1537 if (bo_gem->map_count++ == 0)
1538 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
1540 /* Get a mapping of the buffer if we haven't before. */
1541 if (bo_gem->gtt_virtual == NULL) {
1542 struct drm_i915_gem_mmap_gtt mmap_arg;
1544 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1545 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
1548 mmap_arg.handle = bo_gem->gem_handle;
1550 /* Get the fake offset back... */
1551 ret = drmIoctl(bufmgr_gem->fd,
1552 DRM_IOCTL_I915_GEM_MMAP_GTT,
1556 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1558 bo_gem->gem_handle, bo_gem->name,
1560 if (--bo_gem->map_count == 0)
1561 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1566 bo_gem->gtt_virtual = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
1567 MAP_SHARED, bufmgr_gem->fd,
1569 if (bo_gem->gtt_virtual == MAP_FAILED) {
1570 bo_gem->gtt_virtual = NULL;
1572 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1574 bo_gem->gem_handle, bo_gem->name,
1576 if (--bo_gem->map_count == 0)
1577 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1582 bo->virtual = bo_gem->gtt_virtual;
1584 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1585 bo_gem->gtt_virtual);
1591 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1593 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1594 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1595 struct drm_i915_gem_set_domain set_domain;
1598 pthread_mutex_lock(&bufmgr_gem->lock);
1602 pthread_mutex_unlock(&bufmgr_gem->lock);
1606 /* Now move it to the GTT domain so that the GPU and CPU
1607 * caches are flushed and the GPU isn't actively using the
1610 * The pagefault handler does this domain change for us when
1611 * it has unbound the BO from the GTT, but it's up to us to
1612 * tell it when we're about to use things if we had done
1613 * rendering and it still happens to be bound to the GTT.
1615 memclear(set_domain);
1616 set_domain.handle = bo_gem->gem_handle;
1617 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1618 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1619 ret = drmIoctl(bufmgr_gem->fd,
1620 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1623 DBG("%s:%d: Error setting domain %d: %s\n",
1624 __FILE__, __LINE__, bo_gem->gem_handle,
1628 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1629 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1630 pthread_mutex_unlock(&bufmgr_gem->lock);
1636 * Performs a mapping of the buffer object like the normal GTT
1637 * mapping, but avoids waiting for the GPU to be done reading from or
1638 * rendering to the buffer.
1640 * This is used in the implementation of GL_ARB_map_buffer_range: The
1641 * user asks to create a buffer, then does a mapping, fills some
1642 * space, runs a drawing command, then asks to map it again without
1643 * synchronizing because it guarantees that it won't write over the
1644 * data that the GPU is busy using (or, more specifically, that if it
1645 * does write over the data, it acknowledges that rendering is
1650 drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
1652 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1653 #ifdef HAVE_VALGRIND
1654 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1658 /* If the CPU cache isn't coherent with the GTT, then use a
1659 * regular synchronized mapping. The problem is that we don't
1660 * track where the buffer was last used on the CPU side in
1661 * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so
1662 * we would potentially corrupt the buffer even when the user
1663 * does reasonable things.
1665 if (!bufmgr_gem->has_llc)
1666 return drm_intel_gem_bo_map_gtt(bo);
1668 pthread_mutex_lock(&bufmgr_gem->lock);
1672 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1673 VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
1676 pthread_mutex_unlock(&bufmgr_gem->lock);
1681 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1683 drm_intel_bufmgr_gem *bufmgr_gem;
1684 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1690 if (bo_gem->is_userptr)
1693 bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1695 pthread_mutex_lock(&bufmgr_gem->lock);
1697 if (bo_gem->map_count <= 0) {
1698 DBG("attempted to unmap an unmapped bo\n");
1699 pthread_mutex_unlock(&bufmgr_gem->lock);
1700 /* Preserve the old behaviour of just treating this as a
1701 * no-op rather than reporting the error.
1706 if (bo_gem->mapped_cpu_write) {
1707 struct drm_i915_gem_sw_finish sw_finish;
1709 /* Cause a flush to happen if the buffer's pinned for
1710 * scanout, so the results show up in a timely manner.
1711 * Unlike GTT set domains, this only does work if the
1712 * buffer should be scanout-related.
1714 memclear(sw_finish);
1715 sw_finish.handle = bo_gem->gem_handle;
1716 ret = drmIoctl(bufmgr_gem->fd,
1717 DRM_IOCTL_I915_GEM_SW_FINISH,
1719 ret = ret == -1 ? -errno : 0;
1721 bo_gem->mapped_cpu_write = false;
1724 /* We need to unmap after every innovation as we cannot track
1725 * an open vma for every bo as that will exhaust the system
1726 * limits and cause later failures.
1728 if (--bo_gem->map_count == 0) {
1729 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
1730 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
1733 pthread_mutex_unlock(&bufmgr_gem->lock);
1739 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1741 return drm_intel_gem_bo_unmap(bo);
1745 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1746 unsigned long size, const void *data)
1748 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1749 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1750 struct drm_i915_gem_pwrite pwrite;
1753 if (bo_gem->is_userptr)
1757 pwrite.handle = bo_gem->gem_handle;
1758 pwrite.offset = offset;
1760 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1761 ret = drmIoctl(bufmgr_gem->fd,
1762 DRM_IOCTL_I915_GEM_PWRITE,
1766 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1767 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1768 (int)size, strerror(errno));
1775 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1777 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1778 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1781 memclear(get_pipe_from_crtc_id);
1782 get_pipe_from_crtc_id.crtc_id = crtc_id;
1783 ret = drmIoctl(bufmgr_gem->fd,
1784 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1785 &get_pipe_from_crtc_id);
1787 /* We return -1 here to signal that we don't
1788 * know which pipe is associated with this crtc.
1789 * This lets the caller know that this information
1790 * isn't available; using the wrong pipe for
1791 * vblank waiting can cause the chipset to lock up
1796 return get_pipe_from_crtc_id.pipe;
1800 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1801 unsigned long size, void *data)
1803 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1804 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1805 struct drm_i915_gem_pread pread;
1808 if (bo_gem->is_userptr)
1812 pread.handle = bo_gem->gem_handle;
1813 pread.offset = offset;
1815 pread.data_ptr = (uint64_t) (uintptr_t) data;
1816 ret = drmIoctl(bufmgr_gem->fd,
1817 DRM_IOCTL_I915_GEM_PREAD,
1821 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1822 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1823 (int)size, strerror(errno));
1829 /** Waits for all GPU rendering with the object to have completed. */
1831 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1833 drm_intel_gem_bo_start_gtt_access(bo, 1);
1837 * Waits on a BO for the given amount of time.
1839 * @bo: buffer object to wait for
1840 * @timeout_ns: amount of time to wait in nanoseconds.
1841 * If value is less than 0, an infinite wait will occur.
1843 * Returns 0 if the wait was successful ie. the last batch referencing the
1844 * object has completed within the allotted time. Otherwise some negative return
1845 * value describes the error. Of particular interest is -ETIME when the wait has
1846 * failed to yield the desired result.
1848 * Similar to drm_intel_gem_bo_wait_rendering except a timeout parameter allows
1849 * the operation to give up after a certain amount of time. Another subtle
1850 * difference is the internal locking semantics are different (this variant does
1851 * not hold the lock for the duration of the wait). This makes the wait subject
1852 * to a larger userspace race window.
1854 * The implementation shall wait until the object is no longer actively
1855 * referenced within a batch buffer at the time of the call. The wait will
1856 * not guarantee that the buffer is re-issued via another thread, or an flinked
1857 * handle. Userspace must make sure this race does not occur if such precision
1860 * Note that some kernels have broken the inifite wait for negative values
1861 * promise, upgrade to latest stable kernels if this is the case.
1864 drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
1866 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1867 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1868 struct drm_i915_gem_wait wait;
1871 if (!bufmgr_gem->has_wait_timeout) {
1872 DBG("%s:%d: Timed wait is not supported. Falling back to "
1873 "infinite wait\n", __FILE__, __LINE__);
1875 drm_intel_gem_bo_wait_rendering(bo);
1878 return drm_intel_gem_bo_busy(bo) ? -ETIME : 0;
1883 wait.bo_handle = bo_gem->gem_handle;
1884 wait.timeout_ns = timeout_ns;
1885 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1893 * Sets the object to the GTT read and possibly write domain, used by the X
1894 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1896 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1897 * can do tiled pixmaps this way.
1900 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1902 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1903 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1904 struct drm_i915_gem_set_domain set_domain;
1907 memclear(set_domain);
1908 set_domain.handle = bo_gem->gem_handle;
1909 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1910 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1911 ret = drmIoctl(bufmgr_gem->fd,
1912 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1915 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1916 __FILE__, __LINE__, bo_gem->gem_handle,
1917 set_domain.read_domains, set_domain.write_domain,
1923 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1925 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1926 struct drm_gem_close close_bo;
1929 free(bufmgr_gem->exec2_objects);
1930 free(bufmgr_gem->exec_objects);
1931 free(bufmgr_gem->exec_bos);
1933 pthread_mutex_destroy(&bufmgr_gem->lock);
1935 /* Free any cached buffer objects we were going to reuse */
1936 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1937 struct drm_intel_gem_bo_bucket *bucket =
1938 &bufmgr_gem->cache_bucket[i];
1939 drm_intel_bo_gem *bo_gem;
1941 while (!DRMLISTEMPTY(&bucket->head)) {
1942 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1943 bucket->head.next, head);
1944 DRMLISTDEL(&bo_gem->head);
1946 drm_intel_gem_bo_free(&bo_gem->bo);
1950 /* Release userptr bo kept hanging around for optimisation. */
1951 if (bufmgr_gem->userptr_active.ptr) {
1953 close_bo.handle = bufmgr_gem->userptr_active.handle;
1954 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close_bo);
1955 free(bufmgr_gem->userptr_active.ptr);
1958 "Failed to release test userptr object! (%d) "
1959 "i915 kernel driver may not be sane!\n", errno);
1966 * Adds the target buffer to the validation list and adds the relocation
1967 * to the reloc_buffer's relocation list.
1969 * The relocation entry at the given offset must already contain the
1970 * precomputed relocation value, because the kernel will optimize out
1971 * the relocation entry write when the buffer hasn't moved from the
1972 * last known offset in target_bo.
1975 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1976 drm_intel_bo *target_bo, uint32_t target_offset,
1977 uint32_t read_domains, uint32_t write_domain,
1980 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1981 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1982 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1983 bool fenced_command;
1985 if (bo_gem->has_error)
1988 if (target_bo_gem->has_error) {
1989 bo_gem->has_error = true;
1993 /* We never use HW fences for rendering on 965+ */
1994 if (bufmgr_gem->gen >= 4)
1997 fenced_command = need_fence;
1998 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
2001 /* Create a new relocation list if needed */
2002 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
2005 /* Check overflow */
2006 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
2009 assert(offset <= bo->size - 4);
2010 assert((write_domain & (write_domain - 1)) == 0);
2012 /* An object needing a fence is a tiled buffer, so it won't have
2013 * relocs to other buffers.
2016 assert(target_bo_gem->reloc_count == 0);
2017 target_bo_gem->reloc_tree_fences = 1;
2020 /* Make sure that we're not adding a reloc to something whose size has
2021 * already been accounted for.
2023 assert(!bo_gem->used_as_reloc_target);
2024 if (target_bo_gem != bo_gem) {
2025 target_bo_gem->used_as_reloc_target = true;
2026 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
2027 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
2030 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
2031 if (target_bo != bo)
2032 drm_intel_gem_bo_reference(target_bo);
2034 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
2035 DRM_INTEL_RELOC_FENCE;
2037 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
2039 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
2040 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
2041 bo_gem->relocs[bo_gem->reloc_count].target_handle =
2042 target_bo_gem->gem_handle;
2043 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
2044 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
2045 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset64;
2046 bo_gem->reloc_count++;
2052 drm_intel_gem_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
2054 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2055 bo_gem->use_48b_address_range = enable;
2059 drm_intel_gem_bo_add_softpin_target(drm_intel_bo *bo, drm_intel_bo *target_bo)
2061 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2062 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2063 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2064 if (bo_gem->has_error)
2067 if (target_bo_gem->has_error) {
2068 bo_gem->has_error = true;
2072 if (!target_bo_gem->is_softpin)
2074 if (target_bo_gem == bo_gem)
2077 if (bo_gem->softpin_target_count == bo_gem->softpin_target_size) {
2078 int new_size = bo_gem->softpin_target_size * 2;
2080 new_size = bufmgr_gem->max_relocs;
2082 bo_gem->softpin_target = realloc(bo_gem->softpin_target, new_size *
2083 sizeof(drm_intel_bo *));
2084 if (!bo_gem->softpin_target)
2087 bo_gem->softpin_target_size = new_size;
2089 bo_gem->softpin_target[bo_gem->softpin_target_count] = target_bo;
2090 drm_intel_gem_bo_reference(target_bo);
2091 bo_gem->softpin_target_count++;
2097 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
2098 drm_intel_bo *target_bo, uint32_t target_offset,
2099 uint32_t read_domains, uint32_t write_domain)
2101 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2102 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)target_bo;
2104 if (target_bo_gem->is_softpin)
2105 return drm_intel_gem_bo_add_softpin_target(bo, target_bo);
2107 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
2108 read_domains, write_domain,
2109 !bufmgr_gem->fenced_relocs);
2113 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
2114 drm_intel_bo *target_bo,
2115 uint32_t target_offset,
2116 uint32_t read_domains, uint32_t write_domain)
2118 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
2119 read_domains, write_domain, true);
2123 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
2125 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2127 return bo_gem->reloc_count;
2131 * Removes existing relocation entries in the BO after "start".
2133 * This allows a user to avoid a two-step process for state setup with
2134 * counting up all the buffer objects and doing a
2135 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
2136 * relocations for the state setup. Instead, save the state of the
2137 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
2138 * state, and then check if it still fits in the aperture.
2140 * Any further drm_intel_bufmgr_check_aperture_space() queries
2141 * involving this buffer in the tree are undefined after this call.
2143 * This also removes all softpinned targets being referenced by the BO.
2146 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
2148 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2149 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2151 struct timespec time;
2153 clock_gettime(CLOCK_MONOTONIC, &time);
2155 assert(bo_gem->reloc_count >= start);
2157 /* Unreference the cleared target buffers */
2158 pthread_mutex_lock(&bufmgr_gem->lock);
2160 for (i = start; i < bo_gem->reloc_count; i++) {
2161 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->reloc_target_info[i].bo;
2162 if (&target_bo_gem->bo != bo) {
2163 bo_gem->reloc_tree_fences -= target_bo_gem->reloc_tree_fences;
2164 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo,
2168 bo_gem->reloc_count = start;
2170 for (i = 0; i < bo_gem->softpin_target_count; i++) {
2171 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) bo_gem->softpin_target[i];
2172 drm_intel_gem_bo_unreference_locked_timed(&target_bo_gem->bo, time.tv_sec);
2174 bo_gem->softpin_target_count = 0;
2176 pthread_mutex_unlock(&bufmgr_gem->lock);
2181 * Walk the tree of relocations rooted at BO and accumulate the list of
2182 * validations to be performed and update the relocation buffers with
2183 * index values into the validation list.
2186 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
2188 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2191 if (bo_gem->relocs == NULL)
2194 for (i = 0; i < bo_gem->reloc_count; i++) {
2195 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2197 if (target_bo == bo)
2200 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2202 /* Continue walking the tree depth-first. */
2203 drm_intel_gem_bo_process_reloc(target_bo);
2205 /* Add the target to the validate list */
2206 drm_intel_add_validate_buffer(target_bo);
2211 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
2213 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2216 if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL)
2219 for (i = 0; i < bo_gem->reloc_count; i++) {
2220 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
2223 if (target_bo == bo)
2226 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2228 /* Continue walking the tree depth-first. */
2229 drm_intel_gem_bo_process_reloc2(target_bo);
2231 need_fence = (bo_gem->reloc_target_info[i].flags &
2232 DRM_INTEL_RELOC_FENCE);
2234 /* Add the target to the validate list */
2235 drm_intel_add_validate_buffer2(target_bo, need_fence);
2238 for (i = 0; i < bo_gem->softpin_target_count; i++) {
2239 drm_intel_bo *target_bo = bo_gem->softpin_target[i];
2241 if (target_bo == bo)
2244 drm_intel_gem_bo_mark_mmaps_incoherent(bo);
2245 drm_intel_gem_bo_process_reloc2(target_bo);
2246 drm_intel_add_validate_buffer2(target_bo, false);
2252 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
2256 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2257 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2258 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2260 /* Update the buffer offset */
2261 if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
2262 DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
2263 bo_gem->gem_handle, bo_gem->name,
2264 upper_32_bits(bo->offset64),
2265 lower_32_bits(bo->offset64),
2266 upper_32_bits(bufmgr_gem->exec_objects[i].offset),
2267 lower_32_bits(bufmgr_gem->exec_objects[i].offset));
2268 bo->offset64 = bufmgr_gem->exec_objects[i].offset;
2269 bo->offset = bufmgr_gem->exec_objects[i].offset;
2275 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
2279 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2280 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
2281 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
2283 /* Update the buffer offset */
2284 if (bufmgr_gem->exec2_objects[i].offset != bo->offset64) {
2285 /* If we're seeing softpinned object here it means that the kernel
2286 * has relocated our object... Indicating a programming error
2288 assert(!bo_gem->is_softpin);
2289 DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
2290 bo_gem->gem_handle, bo_gem->name,
2291 upper_32_bits(bo->offset64),
2292 lower_32_bits(bo->offset64),
2293 upper_32_bits(bufmgr_gem->exec2_objects[i].offset),
2294 lower_32_bits(bufmgr_gem->exec2_objects[i].offset));
2295 bo->offset64 = bufmgr_gem->exec2_objects[i].offset;
2296 bo->offset = bufmgr_gem->exec2_objects[i].offset;
2302 drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
2303 int x1, int y1, int width, int height,
2304 enum aub_dump_bmp_format format,
2305 int pitch, int offset)
2310 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
2311 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
2313 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2314 struct drm_i915_gem_execbuffer execbuf;
2317 if (to_bo_gem(bo)->has_error)
2320 pthread_mutex_lock(&bufmgr_gem->lock);
2321 /* Update indices and set up the validate list. */
2322 drm_intel_gem_bo_process_reloc(bo);
2324 /* Add the batch buffer to the validation list. There are no
2325 * relocations pointing to it.
2327 drm_intel_add_validate_buffer(bo);
2330 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
2331 execbuf.buffer_count = bufmgr_gem->exec_count;
2332 execbuf.batch_start_offset = 0;
2333 execbuf.batch_len = used;
2334 execbuf.cliprects_ptr = (uintptr_t) cliprects;
2335 execbuf.num_cliprects = num_cliprects;
2339 ret = drmIoctl(bufmgr_gem->fd,
2340 DRM_IOCTL_I915_GEM_EXECBUFFER,
2344 if (errno == ENOSPC) {
2345 DBG("Execbuffer fails to pin. "
2346 "Estimate: %u. Actual: %u. Available: %u\n",
2347 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2350 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2353 (unsigned int)bufmgr_gem->gtt_size);
2356 drm_intel_update_buffer_offsets(bufmgr_gem);
2358 if (bufmgr_gem->bufmgr.debug)
2359 drm_intel_gem_dump_validation_list(bufmgr_gem);
2361 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2362 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);
2364 bo_gem->idle = false;
2366 /* Disconnect the buffer from the validate list */
2367 bo_gem->validate_index = -1;
2368 bufmgr_gem->exec_bos[i] = NULL;
2370 bufmgr_gem->exec_count = 0;
2371 pthread_mutex_unlock(&bufmgr_gem->lock);
2377 do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx,
2378 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2379 int in_fence, int *out_fence,
2382 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
2383 struct drm_i915_gem_execbuffer2 execbuf;
2387 if (to_bo_gem(bo)->has_error)
2390 switch (flags & 0x7) {
2394 if (!bufmgr_gem->has_blt)
2398 if (!bufmgr_gem->has_bsd)
2401 case I915_EXEC_VEBOX:
2402 if (!bufmgr_gem->has_vebox)
2405 case I915_EXEC_RENDER:
2406 case I915_EXEC_DEFAULT:
2410 pthread_mutex_lock(&bufmgr_gem->lock);
2411 /* Update indices and set up the validate list. */
2412 drm_intel_gem_bo_process_reloc2(bo);
2414 /* Add the batch buffer to the validation list. There are no relocations
2417 drm_intel_add_validate_buffer2(bo, 0);
2420 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
2421 execbuf.buffer_count = bufmgr_gem->exec_count;
2422 execbuf.batch_start_offset = 0;
2423 execbuf.batch_len = used;
2424 execbuf.cliprects_ptr = (uintptr_t)cliprects;
2425 execbuf.num_cliprects = num_cliprects;
2428 execbuf.flags = flags;
2430 i915_execbuffer2_set_context_id(execbuf, 0);
2432 i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id);
2434 if (in_fence != -1) {
2435 execbuf.rsvd2 = in_fence;
2436 execbuf.flags |= I915_EXEC_FENCE_IN;
2438 if (out_fence != NULL) {
2440 execbuf.flags |= I915_EXEC_FENCE_OUT;
2443 if (bufmgr_gem->no_exec)
2444 goto skip_execution;
2446 ret = drmIoctl(bufmgr_gem->fd,
2447 DRM_IOCTL_I915_GEM_EXECBUFFER2_WR,
2451 if (ret == -ENOSPC) {
2452 DBG("Execbuffer fails to pin. "
2453 "Estimate: %u. Actual: %u. Available: %u\n",
2454 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
2455 bufmgr_gem->exec_count),
2456 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
2457 bufmgr_gem->exec_count),
2458 (unsigned int) bufmgr_gem->gtt_size);
2461 drm_intel_update_buffer_offsets2(bufmgr_gem);
2463 if (ret == 0 && out_fence != NULL)
2464 *out_fence = execbuf.rsvd2 >> 32;
2467 if (bufmgr_gem->bufmgr.debug)
2468 drm_intel_gem_dump_validation_list(bufmgr_gem);
2470 for (i = 0; i < bufmgr_gem->exec_count; i++) {
2471 drm_intel_bo_gem *bo_gem = to_bo_gem(bufmgr_gem->exec_bos[i]);
2473 bo_gem->idle = false;
2475 /* Disconnect the buffer from the validate list */
2476 bo_gem->validate_index = -1;
2477 bufmgr_gem->exec_bos[i] = NULL;
2479 bufmgr_gem->exec_count = 0;
2480 pthread_mutex_unlock(&bufmgr_gem->lock);
2486 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
2487 drm_clip_rect_t *cliprects, int num_cliprects,
2490 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2491 -1, NULL, I915_EXEC_RENDER);
2495 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
2496 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
2499 return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
2504 drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
2505 int used, unsigned int flags)
2507 return do_exec2(bo, used, ctx, NULL, 0, 0, -1, NULL, flags);
2511 drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
2512 drm_intel_context *ctx,
2518 return do_exec2(bo, used, ctx, NULL, 0, 0, in_fence, out_fence, flags);
2522 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
2524 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2525 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2526 struct drm_i915_gem_pin pin;
2530 pin.handle = bo_gem->gem_handle;
2531 pin.alignment = alignment;
2533 ret = drmIoctl(bufmgr_gem->fd,
2534 DRM_IOCTL_I915_GEM_PIN,
2539 bo->offset64 = pin.offset;
2540 bo->offset = pin.offset;
2545 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
2547 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2548 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2549 struct drm_i915_gem_unpin unpin;
2553 unpin.handle = bo_gem->gem_handle;
2555 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
2563 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
2564 uint32_t tiling_mode,
2567 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2568 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2569 struct drm_i915_gem_set_tiling set_tiling;
2572 if (bo_gem->global_name == 0 &&
2573 tiling_mode == bo_gem->tiling_mode &&
2574 stride == bo_gem->stride)
2577 memset(&set_tiling, 0, sizeof(set_tiling));
2579 /* set_tiling is slightly broken and overwrites the
2580 * input on the error path, so we have to open code
2583 set_tiling.handle = bo_gem->gem_handle;
2584 set_tiling.tiling_mode = tiling_mode;
2585 set_tiling.stride = stride;
2587 ret = ioctl(bufmgr_gem->fd,
2588 DRM_IOCTL_I915_GEM_SET_TILING,
2590 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
2594 bo_gem->tiling_mode = set_tiling.tiling_mode;
2595 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
2596 bo_gem->stride = set_tiling.stride;
2601 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2604 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2605 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2608 /* Tiling with userptr surfaces is not supported
2609 * on all hardware so refuse it for time being.
2611 if (bo_gem->is_userptr)
2614 /* Linear buffers have no stride. By ensuring that we only ever use
2615 * stride 0 with linear buffers, we simplify our code.
2617 if (*tiling_mode == I915_TILING_NONE)
2620 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
2622 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
2624 *tiling_mode = bo_gem->tiling_mode;
2629 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
2630 uint32_t * swizzle_mode)
2632 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2634 *tiling_mode = bo_gem->tiling_mode;
2635 *swizzle_mode = bo_gem->swizzle_mode;
2640 drm_intel_gem_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
2642 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2644 bo_gem->is_softpin = true;
2645 bo->offset64 = offset;
2646 bo->offset = offset;
2651 drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
2653 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2656 drm_intel_bo_gem *bo_gem;
2657 struct drm_i915_gem_get_tiling get_tiling;
2659 pthread_mutex_lock(&bufmgr_gem->lock);
2660 ret = drmPrimeFDToHandle(bufmgr_gem->fd, prime_fd, &handle);
2662 DBG("create_from_prime: failed to obtain handle from fd: %s\n", strerror(errno));
2663 pthread_mutex_unlock(&bufmgr_gem->lock);
2668 * See if the kernel has already returned this buffer to us. Just as
2669 * for named buffers, we must not create two bo's pointing at the same
2672 HASH_FIND(handle_hh, bufmgr_gem->handle_table,
2673 &handle, sizeof(handle), bo_gem);
2675 drm_intel_gem_bo_reference(&bo_gem->bo);
2679 bo_gem = calloc(1, sizeof(*bo_gem));
2683 atomic_set(&bo_gem->refcount, 1);
2684 DRMINITLISTHEAD(&bo_gem->vma_list);
2686 /* Determine size of bo. The fd-to-handle ioctl really should
2687 * return the size, but it doesn't. If we have kernel 3.12 or
2688 * later, we can lseek on the prime fd to get the size. Older
2689 * kernels will just fail, in which case we fall back to the
2690 * provided (estimated or guess size). */
2691 ret = lseek(prime_fd, 0, SEEK_END);
2693 bo_gem->bo.size = ret;
2695 bo_gem->bo.size = size;
2697 bo_gem->bo.handle = handle;
2698 bo_gem->bo.bufmgr = bufmgr;
2700 bo_gem->gem_handle = handle;
2701 HASH_ADD(handle_hh, bufmgr_gem->handle_table,
2702 gem_handle, sizeof(bo_gem->gem_handle), bo_gem);
2704 bo_gem->name = "prime";
2705 bo_gem->validate_index = -1;
2706 bo_gem->reloc_tree_fences = 0;
2707 bo_gem->used_as_reloc_target = false;
2708 bo_gem->has_error = false;
2709 bo_gem->reusable = false;
2710 bo_gem->use_48b_address_range = false;
2712 memclear(get_tiling);
2713 get_tiling.handle = bo_gem->gem_handle;
2714 if (drmIoctl(bufmgr_gem->fd,
2715 DRM_IOCTL_I915_GEM_GET_TILING,
2719 bo_gem->tiling_mode = get_tiling.tiling_mode;
2720 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
2721 /* XXX stride is unknown */
2722 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem, 0);
2725 pthread_mutex_unlock(&bufmgr_gem->lock);
2729 drm_intel_gem_bo_free(&bo_gem->bo);
2730 pthread_mutex_unlock(&bufmgr_gem->lock);
2735 drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
2737 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2738 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2740 if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
2741 DRM_CLOEXEC, prime_fd) != 0)
2744 bo_gem->reusable = false;
2750 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
2752 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
2753 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2755 if (!bo_gem->global_name) {
2756 struct drm_gem_flink flink;
2759 flink.handle = bo_gem->gem_handle;
2760 if (drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink))
2763 pthread_mutex_lock(&bufmgr_gem->lock);
2764 if (!bo_gem->global_name) {
2765 bo_gem->global_name = flink.name;
2766 bo_gem->reusable = false;
2768 HASH_ADD(name_hh, bufmgr_gem->name_table,
2769 global_name, sizeof(bo_gem->global_name),
2772 pthread_mutex_unlock(&bufmgr_gem->lock);
2775 *name = bo_gem->global_name;
2780 * Enables unlimited caching of buffer objects for reuse.
2782 * This is potentially very memory expensive, as the cache at each bucket
2783 * size is only bounded by how many buffers of that size we've managed to have
2784 * in flight at once.
2787 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
2789 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2791 bufmgr_gem->bo_reuse = true;
2795 * Disables implicit synchronisation before executing the bo
2797 * This will cause rendering corruption unless you correctly manage explicit
2798 * fences for all rendering involving this buffer - including use by others.
2799 * Disabling the implicit serialisation is only required if that serialisation
2800 * is too coarse (for example, you have split the buffer into many
2801 * non-overlapping regions and are sharing the whole buffer between concurrent
2802 * independent command streams).
2804 * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC,
2805 * which can be checked using drm_intel_bufmgr_can_disable_implicit_sync,
2806 * or subsequent execbufs involving the bo will generate EINVAL.
2809 drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo)
2811 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2813 bo_gem->kflags |= EXEC_OBJECT_ASYNC;
2817 * Query whether the kernel supports disabling of its implicit synchronisation
2818 * before execbuf. See drm_intel_gem_bo_disable_implicit_sync()
2821 drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr)
2823 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
2825 return bufmgr_gem->has_exec_async;
2829 * Enable use of fenced reloc type.
2831 * New code should enable this to avoid unnecessary fence register
2832 * allocation. If this option is not enabled, all relocs will have fence
2833 * register allocated.
2836 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
2838 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
2840 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
2841 bufmgr_gem->fenced_relocs = true;
2845 * Return the additional aperture space required by the tree of buffer objects
2849 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
2851 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2855 if (bo == NULL || bo_gem->included_in_check_aperture)
2859 bo_gem->included_in_check_aperture = true;
2861 for (i = 0; i < bo_gem->reloc_count; i++)
2863 drm_intel_gem_bo_get_aperture_space(bo_gem->
2864 reloc_target_info[i].bo);
2870 * Count the number of buffers in this list that need a fence reg
2872 * If the count is greater than the number of available regs, we'll have
2873 * to ask the caller to resubmit a batch with fewer tiled buffers.
2875 * This function over-counts if the same buffer is used multiple times.
2878 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
2881 unsigned int total = 0;
2883 for (i = 0; i < count; i++) {
2884 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2889 total += bo_gem->reloc_tree_fences;
2895 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
2896 * for the next drm_intel_bufmgr_check_aperture_space() call.
2899 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
2901 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2904 if (bo == NULL || !bo_gem->included_in_check_aperture)
2907 bo_gem->included_in_check_aperture = false;
2909 for (i = 0; i < bo_gem->reloc_count; i++)
2910 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
2911 reloc_target_info[i].bo);
2915 * Return a conservative estimate for the amount of aperture required
2916 * for a collection of buffers. This may double-count some buffers.
2919 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
2922 unsigned int total = 0;
2924 for (i = 0; i < count; i++) {
2925 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
2927 total += bo_gem->reloc_tree_size;
2933 * Return the amount of aperture needed for a collection of buffers.
2934 * This avoids double counting any buffers, at the cost of looking
2935 * at every buffer in the set.
2938 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
2941 unsigned int total = 0;
2943 for (i = 0; i < count; i++) {
2944 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
2945 /* For the first buffer object in the array, we get an
2946 * accurate count back for its reloc_tree size (since nothing
2947 * had been flagged as being counted yet). We can save that
2948 * value out as a more conservative reloc_tree_size that
2949 * avoids double-counting target buffers. Since the first
2950 * buffer happens to usually be the batch buffer in our
2951 * callers, this can pull us back from doing the tree
2952 * walk on every new batch emit.
2955 drm_intel_bo_gem *bo_gem =
2956 (drm_intel_bo_gem *) bo_array[i];
2957 bo_gem->reloc_tree_size = total;
2961 for (i = 0; i < count; i++)
2962 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2967 * Return -1 if the batchbuffer should be flushed before attempting to
2968 * emit rendering referencing the buffers pointed to by bo_array.
2970 * This is required because if we try to emit a batchbuffer with relocations
2971 * to a tree of buffers that won't simultaneously fit in the aperture,
2972 * the rendering will return an error at a point where the software is not
2973 * prepared to recover from it.
2975 * However, we also want to emit the batchbuffer significantly before we reach
2976 * the limit, as a series of batchbuffers each of which references buffers
2977 * covering almost all of the aperture means that at each emit we end up
2978 * waiting to evict a buffer from the last rendering, and we get synchronous
2979 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2980 * get better parallelism.
2983 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2985 drm_intel_bufmgr_gem *bufmgr_gem =
2986 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2987 unsigned int total = 0;
2988 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2991 /* Check for fence reg constraints if necessary */
2992 if (bufmgr_gem->available_fences) {
2993 total_fences = drm_intel_gem_total_fences(bo_array, count);
2994 if (total_fences > bufmgr_gem->available_fences)
2998 total = drm_intel_gem_estimate_batch_space(bo_array, count);
3000 if (total > threshold)
3001 total = drm_intel_gem_compute_batch_space(bo_array, count);
3003 if (total > threshold) {
3004 DBG("check_space: overflowed available aperture, "
3006 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
3009 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
3010 (int)bufmgr_gem->gtt_size / 1024);
3016 * Disable buffer reuse for objects which are shared with the kernel
3017 * as scanout buffers
3020 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
3022 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3024 bo_gem->reusable = false;
3029 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
3031 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3033 return bo_gem->reusable;
3037 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
3039 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3042 for (i = 0; i < bo_gem->reloc_count; i++) {
3043 if (bo_gem->reloc_target_info[i].bo == target_bo)
3045 if (bo == bo_gem->reloc_target_info[i].bo)
3047 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
3052 for (i = 0; i< bo_gem->softpin_target_count; i++) {
3053 if (bo_gem->softpin_target[i] == target_bo)
3055 if (_drm_intel_gem_bo_references(bo_gem->softpin_target[i], target_bo))
3062 /** Return true if target_bo is referenced by bo's relocation tree. */
3064 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
3066 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
3068 if (bo == NULL || target_bo == NULL)
3070 if (target_bo_gem->used_as_reloc_target)
3071 return _drm_intel_gem_bo_references(bo, target_bo);
3076 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
3078 unsigned int i = bufmgr_gem->num_buckets;
3080 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
3082 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
3083 bufmgr_gem->cache_bucket[i].size = size;
3084 bufmgr_gem->num_buckets++;
3088 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
3090 unsigned long size, cache_max_size = 64 * 1024 * 1024;
3092 /* OK, so power of two buckets was too wasteful of memory.
3093 * Give 3 other sizes between each power of two, to hopefully
3094 * cover things accurately enough. (The alternative is
3095 * probably to just go for exact matching of sizes, and assume
3096 * that for things like composited window resize the tiled
3097 * width/height alignment and rounding of sizes to pages will
3098 * get us useful cache hit rates anyway)
3100 add_bucket(bufmgr_gem, 4096);
3101 add_bucket(bufmgr_gem, 4096 * 2);
3102 add_bucket(bufmgr_gem, 4096 * 3);
3104 /* Initialize the linked lists for BO reuse cache. */
3105 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
3106 add_bucket(bufmgr_gem, size);
3108 add_bucket(bufmgr_gem, size + size * 1 / 4);
3109 add_bucket(bufmgr_gem, size + size * 2 / 4);
3110 add_bucket(bufmgr_gem, size + size * 3 / 4);
3115 drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
3117 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3119 bufmgr_gem->vma_max = limit;
3121 drm_intel_gem_bo_purge_vma_cache(bufmgr_gem);
3125 parse_devid_override(const char *devid_override)
3127 static const struct {
3131 { "brw", PCI_CHIP_I965_GM },
3132 { "g4x", PCI_CHIP_GM45_GM },
3133 { "ilk", PCI_CHIP_ILD_G },
3134 { "snb", PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS },
3135 { "ivb", PCI_CHIP_IVYBRIDGE_S_GT2 },
3136 { "hsw", PCI_CHIP_HASWELL_CRW_E_GT3 },
3137 { "byt", PCI_CHIP_VALLEYVIEW_3 },
3138 { "bdw", 0x1620 | BDW_ULX },
3139 { "skl", PCI_CHIP_SKYLAKE_DT_GT2 },
3140 { "kbl", PCI_CHIP_KABYLAKE_DT_GT2 },
3144 for (i = 0; i < ARRAY_SIZE(name_map); i++) {
3145 if (!strcmp(name_map[i].name, devid_override))
3146 return name_map[i].pci_id;
3149 return strtod(devid_override, NULL);
3153 * Get the PCI ID for the device. This can be overridden by setting the
3154 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
3157 get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem)
3159 char *devid_override;
3162 drm_i915_getparam_t gp;
3164 if (geteuid() == getuid()) {
3165 devid_override = getenv("INTEL_DEVID_OVERRIDE");
3166 if (devid_override) {
3167 bufmgr_gem->no_exec = true;
3168 return parse_devid_override(devid_override);
3173 gp.param = I915_PARAM_CHIPSET_ID;
3175 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3177 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
3178 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
3184 drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
3186 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3188 return bufmgr_gem->pci_device;
3192 * Sets the AUB filename.
3194 * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
3195 * for it to have any effect.
3198 drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
3199 const char *filename)
3204 * Sets up AUB dumping.
3206 * This is a trace file format that can be used with the simulator.
3207 * Packets are emitted in a format somewhat like GPU command packets.
3208 * You can set up a GTT and upload your objects into the referenced
3209 * space, then send off batchbuffers and get BMPs out the other end.
3212 drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
3214 fprintf(stderr, "libdrm aub dumping is deprecated.\n\n"
3215 "Use intel_aubdump from intel-gpu-tools instead. Install intel-gpu-tools,\n"
3216 "then run (for example)\n\n"
3217 "\t$ intel_aubdump --output=trace.aub glxgears -geometry 500x500\n\n"
3218 "See the intel_aubdump man page for more details.\n");
3222 drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
3224 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3225 struct drm_i915_gem_context_create create;
3226 drm_intel_context *context = NULL;
3229 context = calloc(1, sizeof(*context));
3234 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
3236 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
3242 context->ctx_id = create.ctx_id;
3243 context->bufmgr = bufmgr;
3249 drm_intel_gem_context_get_id(drm_intel_context *ctx, uint32_t *ctx_id)
3254 *ctx_id = ctx->ctx_id;
3260 drm_intel_gem_context_destroy(drm_intel_context *ctx)
3262 drm_intel_bufmgr_gem *bufmgr_gem;
3263 struct drm_i915_gem_context_destroy destroy;
3271 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3272 destroy.ctx_id = ctx->ctx_id;
3273 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY,
3276 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
3283 drm_intel_get_reset_stats(drm_intel_context *ctx,
3284 uint32_t *reset_count,
3288 drm_intel_bufmgr_gem *bufmgr_gem;
3289 struct drm_i915_reset_stats stats;
3297 bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
3298 stats.ctx_id = ctx->ctx_id;
3299 ret = drmIoctl(bufmgr_gem->fd,
3300 DRM_IOCTL_I915_GET_RESET_STATS,
3303 if (reset_count != NULL)
3304 *reset_count = stats.reset_count;
3307 *active = stats.batch_active;
3309 if (pending != NULL)
3310 *pending = stats.batch_pending;
3317 drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
3321 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3322 struct drm_i915_reg_read reg_read;
3326 reg_read.offset = offset;
3328 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
3330 *result = reg_read.val;
3335 drm_intel_get_subslice_total(int fd, unsigned int *subslice_total)
3337 drm_i915_getparam_t gp;
3341 gp.value = (int*)subslice_total;
3342 gp.param = I915_PARAM_SUBSLICE_TOTAL;
3343 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3351 drm_intel_get_eu_total(int fd, unsigned int *eu_total)
3353 drm_i915_getparam_t gp;
3357 gp.value = (int*)eu_total;
3358 gp.param = I915_PARAM_EU_TOTAL;
3359 ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
3367 drm_intel_get_pooled_eu(int fd)
3369 drm_i915_getparam_t gp;
3373 gp.param = I915_PARAM_HAS_POOLED_EU;
3375 if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
3382 drm_intel_get_min_eu_in_pool(int fd)
3384 drm_i915_getparam_t gp;
3388 gp.param = I915_PARAM_MIN_EU_IN_POOL;
3390 if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
3397 * Annotate the given bo for use in aub dumping.
3399 * \param annotations is an array of drm_intel_aub_annotation objects
3400 * describing the type of data in various sections of the bo. Each
3401 * element of the array specifies the type and subtype of a section of
3402 * the bo, and the past-the-end offset of that section. The elements
3403 * of \c annotations must be sorted so that ending_offset is
3406 * \param count is the number of elements in the \c annotations array.
3407 * If \c count is zero, then \c annotations will not be dereferenced.
3409 * Annotations are copied into a private data structure, so caller may
3410 * re-use the memory pointed to by \c annotations after the call
3413 * Annotations are stored for the lifetime of the bo; to reset to the
3414 * default state (no annotations), call this function with a \c count
3418 drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
3419 drm_intel_aub_annotation *annotations,
3424 static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
3425 static drmMMListHead bufmgr_list = { &bufmgr_list, &bufmgr_list };
3427 static drm_intel_bufmgr_gem *
3428 drm_intel_bufmgr_gem_find(int fd)
3430 drm_intel_bufmgr_gem *bufmgr_gem;
3432 DRMLISTFOREACHENTRY(bufmgr_gem, &bufmgr_list, managers) {
3433 if (bufmgr_gem->fd == fd) {
3434 atomic_inc(&bufmgr_gem->refcount);
3443 drm_intel_bufmgr_gem_unref(drm_intel_bufmgr *bufmgr)
3445 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
3447 if (atomic_add_unless(&bufmgr_gem->refcount, -1, 1)) {
3448 pthread_mutex_lock(&bufmgr_list_mutex);
3450 if (atomic_dec_and_test(&bufmgr_gem->refcount)) {
3451 DRMLISTDEL(&bufmgr_gem->managers);
3452 drm_intel_bufmgr_gem_destroy(bufmgr);
3455 pthread_mutex_unlock(&bufmgr_list_mutex);
3459 void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo)
3461 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
3462 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3464 if (bo_gem->gtt_virtual)
3465 return bo_gem->gtt_virtual;
3467 if (bo_gem->is_userptr)
3470 pthread_mutex_lock(&bufmgr_gem->lock);
3471 if (bo_gem->gtt_virtual == NULL) {
3472 struct drm_i915_gem_mmap_gtt mmap_arg;
3475 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
3476 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
3478 if (bo_gem->map_count++ == 0)
3479 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
3482 mmap_arg.handle = bo_gem->gem_handle;
3484 /* Get the fake offset back... */
3486 if (drmIoctl(bufmgr_gem->fd,
3487 DRM_IOCTL_I915_GEM_MMAP_GTT,
3490 ptr = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
3491 MAP_SHARED, bufmgr_gem->fd,
3494 if (ptr == MAP_FAILED) {
3495 if (--bo_gem->map_count == 0)
3496 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
3500 bo_gem->gtt_virtual = ptr;
3502 pthread_mutex_unlock(&bufmgr_gem->lock);
3504 return bo_gem->gtt_virtual;
3507 void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo)
3509 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
3510 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3512 if (bo_gem->mem_virtual)
3513 return bo_gem->mem_virtual;
3515 if (bo_gem->is_userptr) {
3516 /* Return the same user ptr */
3517 return bo_gem->user_virtual;
3520 pthread_mutex_lock(&bufmgr_gem->lock);
3521 if (!bo_gem->mem_virtual) {
3522 struct drm_i915_gem_mmap mmap_arg;
3524 if (bo_gem->map_count++ == 0)
3525 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
3527 DBG("bo_map: %d (%s), map_count=%d\n",
3528 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
3531 mmap_arg.handle = bo_gem->gem_handle;
3532 mmap_arg.size = bo->size;
3533 if (drmIoctl(bufmgr_gem->fd,
3534 DRM_IOCTL_I915_GEM_MMAP,
3536 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
3537 __FILE__, __LINE__, bo_gem->gem_handle,
3538 bo_gem->name, strerror(errno));
3539 if (--bo_gem->map_count == 0)
3540 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
3542 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
3543 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
3546 pthread_mutex_unlock(&bufmgr_gem->lock);
3548 return bo_gem->mem_virtual;
3551 void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo)
3553 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
3554 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
3556 if (bo_gem->wc_virtual)
3557 return bo_gem->wc_virtual;
3559 if (bo_gem->is_userptr)
3562 pthread_mutex_lock(&bufmgr_gem->lock);
3563 if (!bo_gem->wc_virtual) {
3564 struct drm_i915_gem_mmap mmap_arg;
3566 if (bo_gem->map_count++ == 0)
3567 drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
3569 DBG("bo_map: %d (%s), map_count=%d\n",
3570 bo_gem->gem_handle, bo_gem->name, bo_gem->map_count);
3573 mmap_arg.handle = bo_gem->gem_handle;
3574 mmap_arg.size = bo->size;
3575 mmap_arg.flags = I915_MMAP_WC;
3576 if (drmIoctl(bufmgr_gem->fd,
3577 DRM_IOCTL_I915_GEM_MMAP,
3579 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
3580 __FILE__, __LINE__, bo_gem->gem_handle,
3581 bo_gem->name, strerror(errno));
3582 if (--bo_gem->map_count == 0)
3583 drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem);
3585 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
3586 bo_gem->wc_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
3589 pthread_mutex_unlock(&bufmgr_gem->lock);
3591 return bo_gem->wc_virtual;
3595 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
3596 * and manage map buffer objections.
3598 * \param fd File descriptor of the opened DRM device.
3601 drm_intel_bufmgr_gem_init(int fd, int batch_size)
3603 drm_intel_bufmgr_gem *bufmgr_gem;
3604 struct drm_i915_gem_get_aperture aperture;
3605 drm_i915_getparam_t gp;
3609 pthread_mutex_lock(&bufmgr_list_mutex);
3611 bufmgr_gem = drm_intel_bufmgr_gem_find(fd);
3615 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
3616 if (bufmgr_gem == NULL)
3619 bufmgr_gem->fd = fd;
3620 atomic_set(&bufmgr_gem->refcount, 1);
3622 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
3629 ret = drmIoctl(bufmgr_gem->fd,
3630 DRM_IOCTL_I915_GEM_GET_APERTURE,
3634 bufmgr_gem->gtt_size = aperture.aper_available_size;
3636 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
3638 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
3639 fprintf(stderr, "Assuming %dkB available aperture size.\n"
3640 "May lead to reduced performance or incorrect "
3642 (int)bufmgr_gem->gtt_size / 1024);
3645 bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem);
3647 if (IS_GEN2(bufmgr_gem->pci_device))
3648 bufmgr_gem->gen = 2;
3649 else if (IS_GEN3(bufmgr_gem->pci_device))
3650 bufmgr_gem->gen = 3;
3651 else if (IS_GEN4(bufmgr_gem->pci_device))
3652 bufmgr_gem->gen = 4;
3653 else if (IS_GEN5(bufmgr_gem->pci_device))
3654 bufmgr_gem->gen = 5;
3655 else if (IS_GEN6(bufmgr_gem->pci_device))
3656 bufmgr_gem->gen = 6;
3657 else if (IS_GEN7(bufmgr_gem->pci_device))
3658 bufmgr_gem->gen = 7;
3659 else if (IS_GEN8(bufmgr_gem->pci_device))
3660 bufmgr_gem->gen = 8;
3661 else if (IS_GEN9(bufmgr_gem->pci_device))
3662 bufmgr_gem->gen = 9;
3669 if (IS_GEN3(bufmgr_gem->pci_device) &&
3670 bufmgr_gem->gtt_size > 256*1024*1024) {
3671 /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
3672 * be used for tiled blits. To simplify the accounting, just
3673 * subtract the unmappable part (fixed to 256MB on all known
3674 * gen3 devices) if the kernel advertises it. */
3675 bufmgr_gem->gtt_size -= 256*1024*1024;
3681 gp.param = I915_PARAM_HAS_EXECBUF2;
3682 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3686 gp.param = I915_PARAM_HAS_BSD;
3687 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3688 bufmgr_gem->has_bsd = ret == 0;
3690 gp.param = I915_PARAM_HAS_BLT;
3691 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3692 bufmgr_gem->has_blt = ret == 0;
3694 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
3695 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3696 bufmgr_gem->has_relaxed_fencing = ret == 0;
3698 gp.param = I915_PARAM_HAS_EXEC_ASYNC;
3699 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3700 bufmgr_gem->has_exec_async = ret == 0;
3702 bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr;
3704 gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
3705 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3706 bufmgr_gem->has_wait_timeout = ret == 0;
3708 gp.param = I915_PARAM_HAS_LLC;
3709 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3711 /* Kernel does not supports HAS_LLC query, fallback to GPU
3712 * generation detection and assume that we have LLC on GEN6/7
3714 bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
3715 IS_GEN7(bufmgr_gem->pci_device));
3717 bufmgr_gem->has_llc = *gp.value;
3719 gp.param = I915_PARAM_HAS_VEBOX;
3720 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3721 bufmgr_gem->has_vebox = (ret == 0) & (*gp.value > 0);
3723 gp.param = I915_PARAM_HAS_EXEC_SOFTPIN;
3724 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3725 if (ret == 0 && *gp.value > 0)
3726 bufmgr_gem->bufmgr.bo_set_softpin_offset = drm_intel_gem_bo_set_softpin_offset;
3728 if (bufmgr_gem->gen < 4) {
3729 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
3730 gp.value = &bufmgr_gem->available_fences;
3731 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3733 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
3735 fprintf(stderr, "param: %d, val: %d\n", gp.param,
3737 bufmgr_gem->available_fences = 0;
3739 /* XXX The kernel reports the total number of fences,
3740 * including any that may be pinned.
3742 * We presume that there will be at least one pinned
3743 * fence for the scanout buffer, but there may be more
3744 * than one scanout and the user may be manually
3745 * pinning buffers. Let's move to execbuffer2 and
3746 * thereby forget the insanity of using fences...
3748 bufmgr_gem->available_fences -= 2;
3749 if (bufmgr_gem->available_fences < 0)
3750 bufmgr_gem->available_fences = 0;
3754 if (bufmgr_gem->gen >= 8) {
3755 gp.param = I915_PARAM_HAS_ALIASING_PPGTT;
3756 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
3757 if (ret == 0 && *gp.value == 3)
3758 bufmgr_gem->bufmgr.bo_use_48b_address_range = drm_intel_gem_bo_use_48b_address_range;
3761 /* Let's go with one relocation per every 2 dwords (but round down a bit
3762 * since a power of two will mean an extra page allocation for the reloc
3765 * Every 4 was too few for the blender benchmark.
3767 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
3769 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
3770 bufmgr_gem->bufmgr.bo_alloc_for_render =
3771 drm_intel_gem_bo_alloc_for_render;
3772 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
3773 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
3774 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
3775 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
3776 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
3777 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
3778 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
3779 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
3780 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
3781 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
3782 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
3783 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
3784 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
3785 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
3786 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
3787 /* Use the new one if available */
3789 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
3790 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
3792 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
3793 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
3794 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
3795 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_unref;
3796 bufmgr_gem->bufmgr.debug = 0;
3797 bufmgr_gem->bufmgr.check_aperture_space =
3798 drm_intel_gem_check_aperture_space;
3799 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
3800 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
3801 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
3802 drm_intel_gem_get_pipe_from_crtc_id;
3803 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
3805 init_cache_buckets(bufmgr_gem);
3807 DRMINITLISTHEAD(&bufmgr_gem->vma_cache);
3808 bufmgr_gem->vma_max = -1; /* unlimited by default */
3810 DRMLISTADD(&bufmgr_gem->managers, &bufmgr_list);
3813 pthread_mutex_unlock(&bufmgr_list_mutex);
3815 return bufmgr_gem != NULL ? &bufmgr_gem->bufmgr : NULL;