1 famicom cartridge bus simulator 'kazzo'
2 unagi development team / 2009.10.08
5 - USB communication to PC
6 - read and write access for ROM cartridge
7 - program access for flash memory cartridge
8 - composed of few parts
9 - firmware is powered by V-USB
10 http://www.obdev.at/products/vusb/index.html
11 - firmware and host software are opensource, licenced by GPL v2
13 kazzo was named from Japanese traditional fish '鰹'.
17 firmware source code and Makefile. To complile, required WinAVR
20 source codes for kazzo_test.exe
22 module source codes for kazzo from 'unagi'
24 device driver for Windows
26 loop back test client binary for Windows
27 kazzo_mega16.hex kazzo_mega164p.hex
28 firmware hex file written in S Record
29 kazzo_schematics.pdf kazzo_schematics.png
30 schematics graphic data
31 notice! U1 pin number is assigned ATmega16 QFP.
35 It was written how to request to kazzo.
37 GPL v2 licencing document
39 Host software 'unagi' is not included in this package. 'unagi's binary
40 and source codes are available from official project page.
41 http://unagi.sourceforge.jp/
43 ----AVR fusebit configuration----
44 ATmega164P: low byte 0xee, high byte 0xd9, extended byte 0xff
45 CKDIV8:1 CKOUT:1 SUT:10 CKSEL:1110
46 OCDEN:1 JTAGEN:1 SPIEN:0 WDTON:1 EESAVE:1 BOOTSZ:00 BOOTRST:1
48 ATmega16: low byte 0xae, high byte 0xc9
49 BODLEVEL:1 BODEN:0 SUT:10 CKSEL:1110
50 OCDEN:1 JTAGEN:1 SPIEN:0 CKOPT:0 EESAVE:1 BOOTSZ:00 BOOTRST:1
52 ----list of parts-----
54 -----+-------------------
55 U1 |ATmega164P or ATmega16
57 CN1 |type B female USB socket
58 CN2 |3x2 pin header, 2.54 mm spacing
59 CN3 |30x2 pin cardedge connecter, 2.54 mm spacing
63 D1,D2|3.6 V zener diode
64 X1 |16.0 MHz ceramic resonator
65 C1,C2|0.1uF ceramic capacitor
66 CP1 |10uF electric capacitor
70 ----pin assignment----
71 See schematics for switch, register, diode and capacitor connection.
73 CN3: cartridge connector CN1: USB socket type B
74 +-----+ +---+ U1: ATmega164P (DIP)
75 GND| 1 31|+5V +5V|1 4|GND +--v--+
76 CPU A11| 2 32|CPU PHI2 D-|2 3|D+ D0| 1 40|A0
77 CPU A10| 3 33|CPU A12 +---+ D1| 2 39|A1
78 CPU A9| 4 34|CPU A13 CN2: ISP conncetor D2| 3 38|A2
79 CPU A8| 5 35|CPU A14 +---+ D3| 4 37|A3
80 CPU A7| 6 36|CPU D7 MISO|1 2|Vcc D4| 5 36|A4
81 CPU A6| 7 37|CPU D6 SCK|3 4|MOSI MOSI/D5| 6 35|A5
82 CPU A5| 8 38|CPU D5 Reset#|5 6|GND MISO/D6| 7 34|A6
83 CPU A4| 9 39|CPU D4 +---+ SCK/D7| 8 33|A7
84 CPU A3|10 40|CPU D3 U2: 74HC574 Reset#| 9 32|+5V
85 CPU A2|11 41|CPU D2 +--v--+ Vcc|10 31|GND
86 CPU A1|12 42|CPU D1 GND| 1 20|Vcc GND|11 30|+5V
87 CPU A0|13 43|CPU D0 D0| 2 19|A8 XTAL1|12 29|AHL
88 CPU R/W|14 44|CPU ROMCS# D1| 3 18|A9 XTAL2|13 28|VRAM CS#
89 CPU IRQ#|15 45|SOUND IN D2| 4 17|A10 NC|14 27|PPU WR#
90 GND|16 46|SOUND OUT D3| 5 16|A11 NC|15 26|PPU RD#
91 PPU RD#|17 47|PPU WR# D4| 6 15|A12 USB D+|16 25|NC
92 VRAM A10|18 48|VRAM CS# D5| 7 14|A13 CPU IRQ#|17 24|CPU R/W
93 PPU A6|19 49|PPU A13# D6| 8 13|CPU A14 USB D-|18 23|CPU ROMCS#
94 PPU A5|20 50|PPU A7 D7| 9 12|PPU A13# VRAM A10|19 22|CPU PHI2
95 PPU A4|21 51|PPU A8 GND|10 11|AHL NC|20 21|NC
96 PPU A3|22 52|PPU A9 +-----+ +-----+
108 - AHL is Address High Latch.
109 - NC is No Connection.
110 - # is negative logic signal.
112 -- shared by U1, U2, CN3(CPU and PPU).
113 -- D5-D7 are shared by ISP signal.
114 - A0-A13 are addressbus.
115 -- A0-A7 are shared by U1, CN3(CPU and PPU)
116 -- A8-A13 are shared by U2, CN3(CPU and PPU)
117 - CPU A14 and PPU A13# are uniq address buses.
118 - U1 can substitute ATmega16.
119 - SOUND IN and SOUND OUT has no connection.
120 - If you need power switch, short JP1.
121 - If you need reset switch, open JP2.