1 famicom cartridge bus simulator 'kazzo'
2 unagi development team / 2009.10.08
3 firmware version 0.1.2 / 2010.01.10
6 - USB-to-PC communication
7 - ROM cartridge read and write access
8 - programming access for flash memory cartridge
9 - composed of few, mostly off-the-shelf parts
10 - firmware is powered by V-USB
11 http://www.obdev.at/products/vusb/index.html
12 - firmware and host software are open source, licenced by GPL v2
14 kazzo was named after the Japanese traditional fish '鰹'.
18 firmware source code and Makefile. In order to complile, WinAVR
19 environment is required.
21 source codes for kazzo_test.exe
23 module source codes for kazzo from 'unagi'
25 device driver for Windows
27 loop back test client binary for Windows
28 kazzo_mega16.hex kazzo_mega164p.hex
29 firmware hex file written in Intel-Hex Record format
31 schematics graphic file
32 (note: U1 pin number is assigned as ATmega16 QFP.)
36 directions on how to send USB request commands to kazzo.
38 GPL v2 licencing document
40 Host software 'unagi' is not included in this package. unagi's binary
41 and source codes are available from the official project page.
42 http://unagi.sourceforge.jp/
44 ----AVR fusebit configuration----
45 ATmega164P: low byte 0xee, high byte 0xd9, extended byte 0xff
46 CKDIV8:1 CKOUT:1 SUT:10 CKSEL:1110
47 OCDEN:1 JTAGEN:1 SPIEN:0 WDTON:1 EESAVE:1 BOOTSZ:00 BOOTRST:1
49 ATmega16: low byte 0xae, high byte 0xc9
50 BODLEVEL:1 BODEN:0 SUT:10 CKSEL:1110
51 OCDEN:1 JTAGEN:1 SPIEN:0 CKOPT:0 EESAVE:1 BOOTSZ:00 BOOTRST:1
53 ----list of parts-----
55 -----+-------------------
56 U1 |ATmega164P or ATmega16
58 CN1 |type B female USB socket
59 CN2 |3x2 pin header, 2.54 mm spacing
60 CN3 |30x2 pin cartridge connector, 2.54 mm spacing
64 D1,D2|3.6 V zener diode
65 X1 |16.0 MHz ceramic resonator
66 C1,C2|0.1uF ceramic capacitor
67 CP1 |10uF electric capacitor
71 ----pin assignment----
72 See the schematics file for switch, register, diode and capacitor connection.
74 CN3: cartridge connector CN1: USB socket type B
75 +-----+ +---+ U1: ATmega164P (DIP)
76 GND| 1 31|+5V +5V|1 4|GND +--v--+
77 CPU A11| 2 32|CPU PHI2 D-|2 3|D+ D0| 1 40|A0
78 CPU A10| 3 33|CPU A12 +---+ D1| 2 39|A1
79 CPU A9| 4 34|CPU A13 CN2: ISP connector D2| 3 38|A2
80 CPU A8| 5 35|CPU A14 +---+ D3| 4 37|A3
81 CPU A7| 6 36|CPU D7 MISO|1 2|Vcc D4| 5 36|A4
82 CPU A6| 7 37|CPU D6 SCK|3 4|MOSI MOSI/D5| 6 35|A5
83 CPU A5| 8 38|CPU D5 Reset#|5 6|GND MISO/D6| 7 34|A6
84 CPU A4| 9 39|CPU D4 +---+ SCK/D7| 8 33|A7
85 CPU A3|10 40|CPU D3 U2: 74HC574 Reset#| 9 32|+5V
86 CPU A2|11 41|CPU D2 +--v--+ Vcc|10 31|GND
87 CPU A1|12 42|CPU D1 GND| 1 20|Vcc GND|11 30|+5V
88 CPU A0|13 43|CPU D0 D0| 2 19|A8 XTAL1|12 29|AHL
89 CPU R/W|14 44|CPU ROMCS# D1| 3 18|A9 XTAL2|13 28|VRAM CS#
90 CPU IRQ#|15 45|SOUND IN D2| 4 17|A10 NC|14 27|PPU WR#
91 GND|16 46|SOUND OUT D3| 5 16|A11 NC|15 26|PPU RD#
92 PPU RD#|17 47|PPU WR# D4| 6 15|A12 USB D+|16 25|NC
93 VRAM A10|18 48|VRAM CS# D5| 7 14|A13 CPU IRQ#|17 24|CPU R/W
94 PPU A6|19 49|PPU A13# D6| 8 13|CPU A14 USB D-|18 23|CPU ROMCS#
95 PPU A5|20 50|PPU A7 D7| 9 12|PPU A13# VRAM A10|19 22|CPU PHI2
96 PPU A4|21 51|PPU A8 GND|10 11|AHL NC|20 21|NC
97 PPU A3|22 52|PPU A9 +-----+ +-----+
109 - AHL is Address High Latch.
110 - NC is No Connection.
111 - # is negative logic signal.
112 - D0-D7 are data buses.
113 -- shared by U1, U2, CN3(CPU and PPU).
114 -- D5-D7 are shared by ISP signal.
115 - A0-A13 are address buses.
116 -- A0-A7 are shared by U1, CN3(CPU and PPU)
117 -- A8-A13 are shared by U2, CN3(CPU and PPU)
118 - CPU A14 and PPU A13# are unique address buses.
119 - U1 can substitute ATmega16.
120 - SOUND IN and SOUND OUT have no connection.
121 - If a power switch is unnecessary, short JP1.
122 - If a reset switch is unnecessary, open JP2.