1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/ScopeExit.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/LowLevelType.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/TargetFrameLowering.h"
30 #include "llvm/CodeGen/TargetLowering.h"
31 #include "llvm/CodeGen/TargetPassConfig.h"
32 #include "llvm/CodeGen/TargetRegisterInfo.h"
33 #include "llvm/CodeGen/TargetSubtargetInfo.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/Constant.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DebugInfo.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GetElementPtrTypeIterator.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/IR/InstrTypes.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Metadata.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/IR/User.h"
51 #include "llvm/IR/Value.h"
52 #include "llvm/MC/MCContext.h"
53 #include "llvm/Pass.h"
54 #include "llvm/Support/Casting.h"
55 #include "llvm/Support/CodeGen.h"
56 #include "llvm/Support/Debug.h"
57 #include "llvm/Support/ErrorHandling.h"
58 #include "llvm/Support/LowLevelTypeImpl.h"
59 #include "llvm/Support/MathExtras.h"
60 #include "llvm/Support/raw_ostream.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetMachine.h"
71 #define DEBUG_TYPE "irtranslator"
75 char IRTranslator::ID = 0;
77 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
79 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
80 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
83 static void reportTranslationError(MachineFunction &MF,
84 const TargetPassConfig &TPC,
85 OptimizationRemarkEmitter &ORE,
86 OptimizationRemarkMissed &R) {
87 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
89 // Print the function name explicitly if we don't have a debug location (which
90 // makes the diagnostic less useful) or if we're going to emit a raw error.
91 if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
92 R << (" (in function: " + MF.getName() + ")").str();
94 if (TPC.isGlobalISelAbortEnabled())
95 report_fatal_error(R.getMsg());
100 IRTranslator::IRTranslator() : MachineFunctionPass(ID) {
101 initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
104 void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
105 AU.addRequired<TargetPassConfig>();
106 MachineFunctionPass::getAnalysisUsage(AU);
109 unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
110 unsigned &ValReg = ValToVReg[&Val];
115 // Fill ValRegsSequence with the sequence of registers
116 // we need to concat together to produce the value.
117 assert(Val.getType()->isSized() &&
118 "Don't know how to create an empty vreg");
120 MRI->createGenericVirtualRegister(getLLTForType(*Val.getType(), *DL));
123 if (auto CV = dyn_cast<Constant>(&Val)) {
124 bool Success = translate(*CV, VReg);
126 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
127 MF->getFunction()->getSubprogram(),
128 &MF->getFunction()->getEntryBlock());
129 R << "unable to translate constant: " << ore::NV("Type", Val.getType());
130 reportTranslationError(*MF, *TPC, *ORE, R);
138 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
139 if (FrameIndices.find(&AI) != FrameIndices.end())
140 return FrameIndices[&AI];
142 unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
144 ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
146 // Always allocate at least one byte.
147 Size = std::max(Size, 1u);
149 unsigned Alignment = AI.getAlignment();
151 Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
153 int &FI = FrameIndices[&AI];
154 FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
158 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
159 unsigned Alignment = 0;
160 Type *ValTy = nullptr;
161 if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
162 Alignment = SI->getAlignment();
163 ValTy = SI->getValueOperand()->getType();
164 } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
165 Alignment = LI->getAlignment();
166 ValTy = LI->getType();
168 OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
169 R << "unable to translate memop: " << ore::NV("Opcode", &I);
170 reportTranslationError(*MF, *TPC, *ORE, R);
174 return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
177 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
178 MachineBasicBlock *&MBB = BBToMBB[&BB];
179 assert(MBB && "BasicBlock was not encountered before");
183 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
184 assert(NewPred && "new predecessor must be a real MachineBasicBlock");
185 MachinePreds[Edge].push_back(NewPred);
188 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
189 MachineIRBuilder &MIRBuilder) {
190 // FIXME: handle signed/unsigned wrapping flags.
192 // Get or create a virtual register for each value.
193 // Unless the value is a Constant => loadimm cst?
194 // or inline constant each time?
195 // Creation of a virtual register needs to have a size.
196 unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
197 unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
198 unsigned Res = getOrCreateVReg(U);
199 MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
203 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
204 // -0.0 - X --> G_FNEG
205 if (isa<Constant>(U.getOperand(0)) &&
206 U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
207 MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
208 .addDef(getOrCreateVReg(U))
209 .addUse(getOrCreateVReg(*U.getOperand(1)));
212 return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
215 bool IRTranslator::translateCompare(const User &U,
216 MachineIRBuilder &MIRBuilder) {
217 const CmpInst *CI = dyn_cast<CmpInst>(&U);
218 unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
219 unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
220 unsigned Res = getOrCreateVReg(U);
221 CmpInst::Predicate Pred =
222 CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
223 cast<ConstantExpr>(U).getPredicate());
224 if (CmpInst::isIntPredicate(Pred))
225 MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
226 else if (Pred == CmpInst::FCMP_FALSE)
227 MIRBuilder.buildCopy(
228 Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
229 else if (Pred == CmpInst::FCMP_TRUE)
230 MIRBuilder.buildCopy(
231 Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
233 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
238 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
239 const ReturnInst &RI = cast<ReturnInst>(U);
240 const Value *Ret = RI.getReturnValue();
241 if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
243 // The target may mess up with the insertion point, but
244 // this is not important as a return is the last instruction
245 // of the block anyway.
246 return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
249 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
250 const BranchInst &BrInst = cast<BranchInst>(U);
252 if (!BrInst.isUnconditional()) {
253 // We want a G_BRCOND to the true BB followed by an unconditional branch.
254 unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
255 const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
256 MachineBasicBlock &TrueBB = getMBB(TrueTgt);
257 MIRBuilder.buildBrCond(Tst, TrueBB);
260 const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
261 MachineBasicBlock &TgtBB = getMBB(BrTgt);
262 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
264 // If the unconditional target is the layout successor, fallthrough.
265 if (!CurBB.isLayoutSuccessor(&TgtBB))
266 MIRBuilder.buildBr(TgtBB);
269 for (const BasicBlock *Succ : BrInst.successors())
270 CurBB.addSuccessor(&getMBB(*Succ));
274 bool IRTranslator::translateSwitch(const User &U,
275 MachineIRBuilder &MIRBuilder) {
276 // For now, just translate as a chain of conditional branches.
277 // FIXME: could we share most of the logic/code in
278 // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
279 // At first sight, it seems most of the logic in there is independent of
280 // SelectionDAG-specifics and a lot of work went in to optimize switch
281 // lowering in there.
283 const SwitchInst &SwInst = cast<SwitchInst>(U);
284 const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
285 const BasicBlock *OrigBB = SwInst.getParent();
287 LLT LLTi1 = getLLTForType(*Type::getInt1Ty(U.getContext()), *DL);
288 for (auto &CaseIt : SwInst.cases()) {
289 const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
290 const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
291 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
292 MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
293 const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
294 MachineBasicBlock &TrueMBB = getMBB(*TrueBB);
296 MIRBuilder.buildBrCond(Tst, TrueMBB);
297 CurMBB.addSuccessor(&TrueMBB);
298 addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
300 MachineBasicBlock *FalseMBB =
301 MF->CreateMachineBasicBlock(SwInst.getParent());
302 // Insert the comparison blocks one after the other.
303 MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
304 MIRBuilder.buildBr(*FalseMBB);
305 CurMBB.addSuccessor(FalseMBB);
307 MIRBuilder.setMBB(*FalseMBB);
309 // handle default case
310 const BasicBlock *DefaultBB = SwInst.getDefaultDest();
311 MachineBasicBlock &DefaultMBB = getMBB(*DefaultBB);
312 MIRBuilder.buildBr(DefaultMBB);
313 MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
314 CurMBB.addSuccessor(&DefaultMBB);
315 addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
320 bool IRTranslator::translateIndirectBr(const User &U,
321 MachineIRBuilder &MIRBuilder) {
322 const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
324 const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
325 MIRBuilder.buildBrIndirect(Tgt);
328 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
329 for (const BasicBlock *Succ : BrInst.successors())
330 CurBB.addSuccessor(&getMBB(*Succ));
335 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
336 const LoadInst &LI = cast<LoadInst>(U);
338 auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
339 : MachineMemOperand::MONone;
340 Flags |= MachineMemOperand::MOLoad;
342 if (DL->getTypeStoreSize(LI.getType()) == 0)
345 unsigned Res = getOrCreateVReg(LI);
346 unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
348 MIRBuilder.buildLoad(
350 *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
351 Flags, DL->getTypeStoreSize(LI.getType()),
352 getMemOpAlignment(LI), AAMDNodes(), nullptr,
353 LI.getSyncScopeID(), LI.getOrdering()));
357 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
358 const StoreInst &SI = cast<StoreInst>(U);
359 auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
360 : MachineMemOperand::MONone;
361 Flags |= MachineMemOperand::MOStore;
363 if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
366 unsigned Val = getOrCreateVReg(*SI.getValueOperand());
367 unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
369 MIRBuilder.buildStore(
371 *MF->getMachineMemOperand(
372 MachinePointerInfo(SI.getPointerOperand()), Flags,
373 DL->getTypeStoreSize(SI.getValueOperand()->getType()),
374 getMemOpAlignment(SI), AAMDNodes(), nullptr, SI.getSyncScopeID(),
379 bool IRTranslator::translateExtractValue(const User &U,
380 MachineIRBuilder &MIRBuilder) {
381 const Value *Src = U.getOperand(0);
382 Type *Int32Ty = Type::getInt32Ty(U.getContext());
383 SmallVector<Value *, 1> Indices;
385 // If Src is a single element ConstantStruct, translate extractvalue
386 // to that element to avoid inserting a cast instruction.
387 if (auto CS = dyn_cast<ConstantStruct>(Src))
388 if (CS->getNumOperands() == 1) {
389 unsigned Res = getOrCreateVReg(*CS->getOperand(0));
394 // getIndexedOffsetInType is designed for GEPs, so the first index is the
395 // usual array element rather than looking into the actual aggregate.
396 Indices.push_back(ConstantInt::get(Int32Ty, 0));
398 if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
399 for (auto Idx : EVI->indices())
400 Indices.push_back(ConstantInt::get(Int32Ty, Idx));
402 for (unsigned i = 1; i < U.getNumOperands(); ++i)
403 Indices.push_back(U.getOperand(i));
406 uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
408 unsigned Res = getOrCreateVReg(U);
409 MIRBuilder.buildExtract(Res, getOrCreateVReg(*Src), Offset);
414 bool IRTranslator::translateInsertValue(const User &U,
415 MachineIRBuilder &MIRBuilder) {
416 const Value *Src = U.getOperand(0);
417 Type *Int32Ty = Type::getInt32Ty(U.getContext());
418 SmallVector<Value *, 1> Indices;
420 // getIndexedOffsetInType is designed for GEPs, so the first index is the
421 // usual array element rather than looking into the actual aggregate.
422 Indices.push_back(ConstantInt::get(Int32Ty, 0));
424 if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
425 for (auto Idx : IVI->indices())
426 Indices.push_back(ConstantInt::get(Int32Ty, Idx));
428 for (unsigned i = 2; i < U.getNumOperands(); ++i)
429 Indices.push_back(U.getOperand(i));
432 uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
434 unsigned Res = getOrCreateVReg(U);
435 unsigned Inserted = getOrCreateVReg(*U.getOperand(1));
436 MIRBuilder.buildInsert(Res, getOrCreateVReg(*Src), Inserted, Offset);
441 bool IRTranslator::translateSelect(const User &U,
442 MachineIRBuilder &MIRBuilder) {
443 unsigned Res = getOrCreateVReg(U);
444 unsigned Tst = getOrCreateVReg(*U.getOperand(0));
445 unsigned Op0 = getOrCreateVReg(*U.getOperand(1));
446 unsigned Op1 = getOrCreateVReg(*U.getOperand(2));
447 MIRBuilder.buildSelect(Res, Tst, Op0, Op1);
451 bool IRTranslator::translateBitCast(const User &U,
452 MachineIRBuilder &MIRBuilder) {
453 // If we're bitcasting to the source type, we can reuse the source vreg.
454 if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
455 getLLTForType(*U.getType(), *DL)) {
456 // Get the source vreg now, to avoid invalidating ValToVReg.
457 unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
458 unsigned &Reg = ValToVReg[&U];
459 // If we already assigned a vreg for this bitcast, we can't change that.
460 // Emit a copy to satisfy the users we already emitted.
462 MIRBuilder.buildCopy(Reg, SrcReg);
467 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
470 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
471 MachineIRBuilder &MIRBuilder) {
472 unsigned Op = getOrCreateVReg(*U.getOperand(0));
473 unsigned Res = getOrCreateVReg(U);
474 MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
478 bool IRTranslator::translateGetElementPtr(const User &U,
479 MachineIRBuilder &MIRBuilder) {
480 // FIXME: support vector GEPs.
481 if (U.getType()->isVectorTy())
484 Value &Op0 = *U.getOperand(0);
485 unsigned BaseReg = getOrCreateVReg(Op0);
486 Type *PtrIRTy = Op0.getType();
487 LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
488 Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
489 LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
492 for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
494 const Value *Idx = GTI.getOperand();
495 if (StructType *StTy = GTI.getStructTypeOrNull()) {
496 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
497 Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
500 uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
502 // If this is a scalar constant or a splat vector of constants,
503 // handle it quickly.
504 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
505 Offset += ElementSize * CI->getSExtValue();
510 unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
512 getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
513 MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
515 BaseReg = NewBaseReg;
519 // N = N + Idx * ElementSize;
520 unsigned ElementSizeReg =
521 getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));
523 unsigned IdxReg = getOrCreateVReg(*Idx);
524 if (MRI->getType(IdxReg) != OffsetTy) {
525 unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
526 MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
530 unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
531 MIRBuilder.buildMul(OffsetReg, ElementSizeReg, IdxReg);
533 unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
534 MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
535 BaseReg = NewBaseReg;
540 unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
541 MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
545 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
549 bool IRTranslator::translateMemfunc(const CallInst &CI,
550 MachineIRBuilder &MIRBuilder,
552 LLT SizeTy = getLLTForType(*CI.getArgOperand(2)->getType(), *DL);
553 Type *DstTy = CI.getArgOperand(0)->getType();
554 if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
555 SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
558 SmallVector<CallLowering::ArgInfo, 8> Args;
559 for (int i = 0; i < 3; ++i) {
560 const auto &Arg = CI.getArgOperand(i);
561 Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
566 case Intrinsic::memmove:
567 case Intrinsic::memcpy: {
568 Type *SrcTy = CI.getArgOperand(1)->getType();
569 if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
571 Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
574 case Intrinsic::memset:
581 return CLI->lowerCall(MIRBuilder, CI.getCallingConv(),
582 MachineOperand::CreateES(Callee),
583 CallLowering::ArgInfo(0, CI.getType()), Args);
586 void IRTranslator::getStackGuard(unsigned DstReg,
587 MachineIRBuilder &MIRBuilder) {
588 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
589 MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
590 auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
593 auto &TLI = *MF->getSubtarget().getTargetLowering();
594 Value *Global = TLI.getSDagStackGuard(*MF->getFunction()->getParent());
598 MachinePointerInfo MPInfo(Global);
599 MachineInstr::mmo_iterator MemRefs = MF->allocateMemRefsArray(1);
600 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
601 MachineMemOperand::MODereferenceable;
603 MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
604 DL->getPointerABIAlignment(0));
605 MIB.setMemRefs(MemRefs, MemRefs + 1);
608 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
609 MachineIRBuilder &MIRBuilder) {
610 LLT Ty = getLLTForType(*CI.getOperand(0)->getType(), *DL);
611 LLT s1 = LLT::scalar(1);
612 unsigned Width = Ty.getSizeInBits();
613 unsigned Res = MRI->createGenericVirtualRegister(Ty);
614 unsigned Overflow = MRI->createGenericVirtualRegister(s1);
615 auto MIB = MIRBuilder.buildInstr(Op)
618 .addUse(getOrCreateVReg(*CI.getOperand(0)))
619 .addUse(getOrCreateVReg(*CI.getOperand(1)));
621 if (Op == TargetOpcode::G_UADDE || Op == TargetOpcode::G_USUBE) {
622 unsigned Zero = getOrCreateVReg(
623 *Constant::getNullValue(Type::getInt1Ty(CI.getContext())));
627 MIRBuilder.buildSequence(getOrCreateVReg(CI), {Res, Overflow}, {0, Width});
631 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
632 MachineIRBuilder &MIRBuilder) {
636 case Intrinsic::lifetime_start:
637 case Intrinsic::lifetime_end:
638 // Stack coloring is not enabled in O0 (which we care about now) so we can
639 // drop these. Make sure someone notices when we start compiling at higher
641 if (MF->getTarget().getOptLevel() != CodeGenOpt::None)
644 case Intrinsic::dbg_declare: {
645 const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
646 assert(DI.getVariable() && "Missing variable");
648 const Value *Address = DI.getAddress();
649 if (!Address || isa<UndefValue>(Address)) {
650 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
654 assert(DI.getVariable()->isValidLocationForIntrinsic(
655 MIRBuilder.getDebugLoc()) &&
656 "Expected inlined-at fields to agree");
657 auto AI = dyn_cast<AllocaInst>(Address);
658 if (AI && AI->isStaticAlloca()) {
659 // Static allocas are tracked at the MF level, no need for DBG_VALUE
660 // instructions (in fact, they get ignored if they *do* exist).
661 MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(),
662 getOrCreateFrameIndex(*AI), DI.getDebugLoc());
664 MIRBuilder.buildDirectDbgValue(getOrCreateVReg(*Address),
665 DI.getVariable(), DI.getExpression());
668 case Intrinsic::vaend:
669 // No target I know of cares about va_end. Certainly no in-tree target
670 // does. Simplest intrinsic ever!
672 case Intrinsic::vastart: {
673 auto &TLI = *MF->getSubtarget().getTargetLowering();
674 Value *Ptr = CI.getArgOperand(0);
675 unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
677 MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
678 .addUse(getOrCreateVReg(*Ptr))
679 .addMemOperand(MF->getMachineMemOperand(
680 MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0));
683 case Intrinsic::dbg_value: {
684 // This form of DBG_VALUE is target-independent.
685 const DbgValueInst &DI = cast<DbgValueInst>(CI);
686 const Value *V = DI.getValue();
687 assert(DI.getVariable()->isValidLocationForIntrinsic(
688 MIRBuilder.getDebugLoc()) &&
689 "Expected inlined-at fields to agree");
691 // Currently the optimizer can produce this; insert an undef to
692 // help debugging. Probably the optimizer should not do this.
693 MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
694 } else if (const auto *CI = dyn_cast<Constant>(V)) {
695 MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
697 unsigned Reg = getOrCreateVReg(*V);
698 // FIXME: This does not handle register-indirect values at offset 0. The
699 // direct/indirect thing shouldn't really be handled by something as
700 // implicit as reg+noreg vs reg+imm in the first palce, but it seems
701 // pretty baked in right now.
702 MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
706 case Intrinsic::uadd_with_overflow:
707 return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDE, MIRBuilder);
708 case Intrinsic::sadd_with_overflow:
709 return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
710 case Intrinsic::usub_with_overflow:
711 return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBE, MIRBuilder);
712 case Intrinsic::ssub_with_overflow:
713 return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
714 case Intrinsic::umul_with_overflow:
715 return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
716 case Intrinsic::smul_with_overflow:
717 return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
719 MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
720 .addDef(getOrCreateVReg(CI))
721 .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
722 .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
725 MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
726 .addDef(getOrCreateVReg(CI))
727 .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
729 case Intrinsic::exp2:
730 MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
731 .addDef(getOrCreateVReg(CI))
732 .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
735 MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
736 .addDef(getOrCreateVReg(CI))
737 .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
739 case Intrinsic::log2:
740 MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
741 .addDef(getOrCreateVReg(CI))
742 .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
745 MIRBuilder.buildInstr(TargetOpcode::G_FMA)
746 .addDef(getOrCreateVReg(CI))
747 .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
748 .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
749 .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
751 case Intrinsic::memcpy:
752 case Intrinsic::memmove:
753 case Intrinsic::memset:
754 return translateMemfunc(CI, MIRBuilder, ID);
755 case Intrinsic::eh_typeid_for: {
756 GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
757 unsigned Reg = getOrCreateVReg(CI);
758 unsigned TypeID = MF->getTypeIDFor(GV);
759 MIRBuilder.buildConstant(Reg, TypeID);
762 case Intrinsic::objectsize: {
763 // If we don't know by now, we're never going to know.
764 const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
766 MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
769 case Intrinsic::stackguard:
770 getStackGuard(getOrCreateVReg(CI), MIRBuilder);
772 case Intrinsic::stackprotector: {
773 LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
774 unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
775 getStackGuard(GuardVal, MIRBuilder);
777 AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
778 MIRBuilder.buildStore(
779 GuardVal, getOrCreateVReg(*Slot),
780 *MF->getMachineMemOperand(
781 MachinePointerInfo::getFixedStack(*MF,
782 getOrCreateFrameIndex(*Slot)),
783 MachineMemOperand::MOStore | MachineMemOperand::MOVolatile,
784 PtrTy.getSizeInBits() / 8, 8));
791 bool IRTranslator::translateInlineAsm(const CallInst &CI,
792 MachineIRBuilder &MIRBuilder) {
793 const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
794 if (!IA.getConstraintString().empty())
797 unsigned ExtraInfo = 0;
798 if (IA.hasSideEffects())
799 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
800 if (IA.getDialect() == InlineAsm::AD_Intel)
801 ExtraInfo |= InlineAsm::Extra_AsmDialect;
803 MIRBuilder.buildInstr(TargetOpcode::INLINEASM)
804 .addExternalSymbol(IA.getAsmString().c_str())
810 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
811 const CallInst &CI = cast<CallInst>(U);
812 auto TII = MF->getTarget().getIntrinsicInfo();
813 const Function *F = CI.getCalledFunction();
815 if (CI.isInlineAsm())
816 return translateInlineAsm(CI, MIRBuilder);
818 if (!F || !F->isIntrinsic()) {
819 unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
820 SmallVector<unsigned, 8> Args;
821 for (auto &Arg: CI.arg_operands())
822 Args.push_back(getOrCreateVReg(*Arg));
824 MF->getFrameInfo().setHasCalls(true);
825 return CLI->lowerCall(MIRBuilder, &CI, Res, Args, [&]() {
826 return getOrCreateVReg(*CI.getCalledValue());
830 Intrinsic::ID ID = F->getIntrinsicID();
831 if (TII && ID == Intrinsic::not_intrinsic)
832 ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
834 assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
836 if (translateKnownIntrinsic(CI, ID, MIRBuilder))
839 unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
840 MachineInstrBuilder MIB =
841 MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
843 for (auto &Arg : CI.arg_operands()) {
844 // Some intrinsics take metadata parameters. Reject them.
845 if (isa<MetadataAsValue>(Arg))
847 MIB.addUse(getOrCreateVReg(*Arg));
850 // Add a MachineMemOperand if it is a target mem intrinsic.
851 const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
852 TargetLowering::IntrinsicInfo Info;
853 // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
854 if (TLI.getTgtMemIntrinsic(Info, CI, ID)) {
855 MachineMemOperand::Flags Flags =
856 Info.vol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
858 Info.readMem ? MachineMemOperand::MOLoad : MachineMemOperand::MOStore;
859 uint64_t Size = Info.memVT.getStoreSize();
860 MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
861 Flags, Size, Info.align));
867 bool IRTranslator::translateInvoke(const User &U,
868 MachineIRBuilder &MIRBuilder) {
869 const InvokeInst &I = cast<InvokeInst>(U);
870 MCContext &Context = MF->getContext();
872 const BasicBlock *ReturnBB = I.getSuccessor(0);
873 const BasicBlock *EHPadBB = I.getSuccessor(1);
875 const Value *Callee = I.getCalledValue();
876 const Function *Fn = dyn_cast<Function>(Callee);
877 if (isa<InlineAsm>(Callee))
880 // FIXME: support invoking patchpoint and statepoint intrinsics.
881 if (Fn && Fn->isIntrinsic())
884 // FIXME: support whatever these are.
885 if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
888 // FIXME: support Windows exception handling.
889 if (!isa<LandingPadInst>(EHPadBB->front()))
892 // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
893 // the region covered by the try.
894 MCSymbol *BeginSymbol = Context.createTempSymbol();
895 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
897 unsigned Res = I.getType()->isVoidTy() ? 0 : getOrCreateVReg(I);
898 SmallVector<unsigned, 8> Args;
899 for (auto &Arg: I.arg_operands())
900 Args.push_back(getOrCreateVReg(*Arg));
902 if (!CLI->lowerCall(MIRBuilder, &I, Res, Args,
903 [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
906 MCSymbol *EndSymbol = Context.createTempSymbol();
907 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
909 // FIXME: track probabilities.
910 MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
911 &ReturnMBB = getMBB(*ReturnBB);
912 MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
913 MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
914 MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
915 MIRBuilder.buildBr(ReturnMBB);
920 bool IRTranslator::translateLandingPad(const User &U,
921 MachineIRBuilder &MIRBuilder) {
922 const LandingPadInst &LP = cast<LandingPadInst>(U);
924 MachineBasicBlock &MBB = MIRBuilder.getMBB();
925 addLandingPadInfo(LP, MBB);
929 // If there aren't registers to copy the values into (e.g., during SjLj
930 // exceptions), then don't bother.
931 auto &TLI = *MF->getSubtarget().getTargetLowering();
932 const Constant *PersonalityFn = MF->getFunction()->getPersonalityFn();
933 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
934 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
937 // If landingpad's return type is token type, we don't create DAG nodes
938 // for its exception pointer and selector value. The extraction of exception
939 // pointer or selector value from token type landingpads is not currently
941 if (LP.getType()->isTokenTy())
944 // Add a label to mark the beginning of the landing pad. Deletion of the
945 // landing pad can thus be detected via the MachineModuleInfo.
946 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
947 .addSym(MF->addLandingPad(&MBB));
949 LLT Ty = getLLTForType(*LP.getType(), *DL);
950 unsigned Undef = MRI->createGenericVirtualRegister(Ty);
951 MIRBuilder.buildUndef(Undef);
953 SmallVector<LLT, 2> Tys;
954 for (Type *Ty : cast<StructType>(LP.getType())->elements())
955 Tys.push_back(getLLTForType(*Ty, *DL));
956 assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
958 // Mark exception register as live in.
959 unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
963 MBB.addLiveIn(ExceptionReg);
964 unsigned VReg = MRI->createGenericVirtualRegister(Tys[0]),
965 Tmp = MRI->createGenericVirtualRegister(Ty);
966 MIRBuilder.buildCopy(VReg, ExceptionReg);
967 MIRBuilder.buildInsert(Tmp, Undef, VReg, 0);
969 unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
973 MBB.addLiveIn(SelectorReg);
975 // N.b. the exception selector register always has pointer type and may not
976 // match the actual IR-level type in the landingpad so an extra cast is
978 unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
979 MIRBuilder.buildCopy(PtrVReg, SelectorReg);
981 VReg = MRI->createGenericVirtualRegister(Tys[1]);
982 MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT).addDef(VReg).addUse(PtrVReg);
983 MIRBuilder.buildInsert(getOrCreateVReg(LP), Tmp, VReg,
984 Tys[0].getSizeInBits());
988 bool IRTranslator::translateAlloca(const User &U,
989 MachineIRBuilder &MIRBuilder) {
990 auto &AI = cast<AllocaInst>(U);
992 if (AI.isStaticAlloca()) {
993 unsigned Res = getOrCreateVReg(AI);
994 int FI = getOrCreateFrameIndex(AI);
995 MIRBuilder.buildFrameIndex(Res, FI);
999 // Now we're in the harder dynamic case.
1000 Type *Ty = AI.getAllocatedType();
1002 std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1004 unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1006 Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1007 LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1008 if (MRI->getType(NumElts) != IntPtrTy) {
1009 unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1010 MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1014 unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1016 getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1017 MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1019 LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1020 auto &TLI = *MF->getSubtarget().getTargetLowering();
1021 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1023 unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1024 MIRBuilder.buildCopy(SPTmp, SPReg);
1026 unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1027 MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1029 // Handle alignment. We have to realign if the allocation granule was smaller
1030 // than stack alignment, or the specific alloca requires more than stack
1032 unsigned StackAlign =
1033 MF->getSubtarget().getFrameLowering()->getStackAlignment();
1034 Align = std::max(Align, StackAlign);
1035 if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1036 // Round the size of the allocation up to the stack alignment size
1037 // by add SA-1 to the size. This doesn't overflow because we're computing
1038 // an address inside an alloca.
1039 unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1040 MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1041 AllocTmp = AlignedAlloc;
1044 MIRBuilder.buildCopy(SPReg, AllocTmp);
1045 MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1047 MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1048 assert(MF->getFrameInfo().hasVarSizedObjects());
1052 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1053 // FIXME: We may need more info about the type. Because of how LLT works,
1054 // we're completely discarding the i64/double distinction here (amongst
1055 // others). Fortunately the ABIs I know of where that matters don't use va_arg
1056 // anyway but that's not guaranteed.
1057 MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1058 .addDef(getOrCreateVReg(U))
1059 .addUse(getOrCreateVReg(*U.getOperand(0)))
1060 .addImm(DL->getABITypeAlignment(U.getType()));
1064 bool IRTranslator::translateInsertElement(const User &U,
1065 MachineIRBuilder &MIRBuilder) {
1066 // If it is a <1 x Ty> vector, use the scalar as it is
1067 // not a legal vector type in LLT.
1068 if (U.getType()->getVectorNumElements() == 1) {
1069 unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1070 ValToVReg[&U] = Elt;
1073 unsigned Res = getOrCreateVReg(U);
1074 unsigned Val = getOrCreateVReg(*U.getOperand(0));
1075 unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1076 unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1077 MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1081 bool IRTranslator::translateExtractElement(const User &U,
1082 MachineIRBuilder &MIRBuilder) {
1083 // If it is a <1 x Ty> vector, use the scalar as it is
1084 // not a legal vector type in LLT.
1085 if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1086 unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1087 ValToVReg[&U] = Elt;
1090 unsigned Res = getOrCreateVReg(U);
1091 unsigned Val = getOrCreateVReg(*U.getOperand(0));
1092 unsigned Idx = getOrCreateVReg(*U.getOperand(1));
1093 MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1097 bool IRTranslator::translateShuffleVector(const User &U,
1098 MachineIRBuilder &MIRBuilder) {
1099 MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1100 .addDef(getOrCreateVReg(U))
1101 .addUse(getOrCreateVReg(*U.getOperand(0)))
1102 .addUse(getOrCreateVReg(*U.getOperand(1)))
1103 .addUse(getOrCreateVReg(*U.getOperand(2)));
1107 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1108 const PHINode &PI = cast<PHINode>(U);
1109 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI);
1110 MIB.addDef(getOrCreateVReg(PI));
1112 PendingPHIs.emplace_back(&PI, MIB.getInstr());
1116 void IRTranslator::finishPendingPhis() {
1117 for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
1118 const PHINode *PI = Phi.first;
1119 MachineInstrBuilder MIB(*MF, Phi.second);
1121 // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
1122 // won't create extra control flow here, otherwise we need to find the
1123 // dominating predecessor here (or perhaps force the weirder IRTranslators
1124 // to provide a simple boundary).
1125 SmallSet<const BasicBlock *, 4> HandledPreds;
1127 for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
1128 auto IRPred = PI->getIncomingBlock(i);
1129 if (HandledPreds.count(IRPred))
1132 HandledPreds.insert(IRPred);
1133 unsigned ValReg = getOrCreateVReg(*PI->getIncomingValue(i));
1134 for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
1135 assert(Pred->isSuccessor(MIB->getParent()) &&
1136 "incorrect CFG at MachineBasicBlock level");
1144 bool IRTranslator::translate(const Instruction &Inst) {
1145 CurBuilder.setDebugLoc(Inst.getDebugLoc());
1146 switch(Inst.getOpcode()) {
1147 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1148 case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
1149 #include "llvm/IR/Instruction.def"
1155 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
1156 if (auto CI = dyn_cast<ConstantInt>(&C))
1157 EntryBuilder.buildConstant(Reg, *CI);
1158 else if (auto CF = dyn_cast<ConstantFP>(&C))
1159 EntryBuilder.buildFConstant(Reg, *CF);
1160 else if (isa<UndefValue>(C))
1161 EntryBuilder.buildUndef(Reg);
1162 else if (isa<ConstantPointerNull>(C))
1163 EntryBuilder.buildConstant(Reg, 0);
1164 else if (auto GV = dyn_cast<GlobalValue>(&C))
1165 EntryBuilder.buildGlobalValue(Reg, GV);
1166 else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
1167 if (!CAZ->getType()->isVectorTy())
1169 // Return the scalar if it is a <1 x Ty> vector.
1170 if (CAZ->getNumElements() == 1)
1171 return translate(*CAZ->getElementValue(0u), Reg);
1172 std::vector<unsigned> Ops;
1173 for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
1174 Constant &Elt = *CAZ->getElementValue(i);
1175 Ops.push_back(getOrCreateVReg(Elt));
1177 EntryBuilder.buildMerge(Reg, Ops);
1178 } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
1179 // Return the scalar if it is a <1 x Ty> vector.
1180 if (CV->getNumElements() == 1)
1181 return translate(*CV->getElementAsConstant(0), Reg);
1182 std::vector<unsigned> Ops;
1183 for (unsigned i = 0; i < CV->getNumElements(); ++i) {
1184 Constant &Elt = *CV->getElementAsConstant(i);
1185 Ops.push_back(getOrCreateVReg(Elt));
1187 EntryBuilder.buildMerge(Reg, Ops);
1188 } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
1189 switch(CE->getOpcode()) {
1190 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1191 case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
1192 #include "llvm/IR/Instruction.def"
1196 } else if (auto CS = dyn_cast<ConstantStruct>(&C)) {
1197 // Return the element if it is a single element ConstantStruct.
1198 if (CS->getNumOperands() == 1) {
1199 unsigned EltReg = getOrCreateVReg(*CS->getOperand(0));
1200 EntryBuilder.buildCast(Reg, EltReg);
1203 SmallVector<unsigned, 4> Ops;
1204 SmallVector<uint64_t, 4> Indices;
1205 uint64_t Offset = 0;
1206 for (unsigned i = 0; i < CS->getNumOperands(); ++i) {
1207 unsigned OpReg = getOrCreateVReg(*CS->getOperand(i));
1208 Ops.push_back(OpReg);
1209 Indices.push_back(Offset);
1210 Offset += MRI->getType(OpReg).getSizeInBits();
1212 EntryBuilder.buildSequence(Reg, Ops, Indices);
1213 } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
1214 if (CV->getNumOperands() == 1)
1215 return translate(*CV->getOperand(0), Reg);
1216 SmallVector<unsigned, 4> Ops;
1217 for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
1218 Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
1220 EntryBuilder.buildMerge(Reg, Ops);
1227 void IRTranslator::finalizeFunction() {
1228 // Release the memory used by the different maps we
1229 // needed during the translation.
1230 PendingPHIs.clear();
1232 FrameIndices.clear();
1233 MachinePreds.clear();
1234 // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
1235 // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
1236 // destroying it twice (in ~IRTranslator() and ~LLVMContext())
1237 EntryBuilder = MachineIRBuilder();
1238 CurBuilder = MachineIRBuilder();
1241 bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
1243 const Function &F = *MF->getFunction();
1246 CLI = MF->getSubtarget().getCallLowering();
1247 CurBuilder.setMF(*MF);
1248 EntryBuilder.setMF(*MF);
1249 MRI = &MF->getRegInfo();
1250 DL = &F.getParent()->getDataLayout();
1251 TPC = &getAnalysis<TargetPassConfig>();
1252 ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
1254 assert(PendingPHIs.empty() && "stale PHIs");
1256 // Release the per-function state when we return, whether we succeeded or not.
1257 auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
1259 // Setup a separate basic-block for the arguments and constants
1260 MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
1261 MF->push_back(EntryBB);
1262 EntryBuilder.setMBB(*EntryBB);
1264 // Create all blocks, in IR order, to preserve the layout.
1265 for (const BasicBlock &BB: F) {
1266 auto *&MBB = BBToMBB[&BB];
1268 MBB = MF->CreateMachineBasicBlock(&BB);
1271 if (BB.hasAddressTaken())
1272 MBB->setHasAddressTaken();
1275 // Make our arguments/constants entry block fallthrough to the IR entry block.
1276 EntryBB->addSuccessor(&getMBB(F.front()));
1278 // Lower the actual args into this basic block.
1279 SmallVector<unsigned, 8> VRegArgs;
1280 for (const Argument &Arg: F.args()) {
1281 if (DL->getTypeStoreSize(Arg.getType()) == 0)
1282 continue; // Don't handle zero sized types.
1283 VRegArgs.push_back(getOrCreateVReg(Arg));
1285 if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
1286 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1287 MF->getFunction()->getSubprogram(),
1288 &MF->getFunction()->getEntryBlock());
1289 R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
1290 reportTranslationError(*MF, *TPC, *ORE, R);
1294 // And translate the function!
1295 for (const BasicBlock &BB: F) {
1296 MachineBasicBlock &MBB = getMBB(BB);
1297 // Set the insertion point of all the following translations to
1298 // the end of this basic block.
1299 CurBuilder.setMBB(MBB);
1301 for (const Instruction &Inst: BB) {
1302 if (translate(Inst))
1305 OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1306 Inst.getDebugLoc(), &BB);
1307 R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
1309 if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
1310 std::string InstStrStorage;
1311 raw_string_ostream InstStr(InstStrStorage);
1314 R << ": '" << InstStr.str() << "'";
1317 reportTranslationError(*MF, *TPC, *ORE, R);
1322 finishPendingPhis();
1324 // Merge the argument lowering and constants block with its single
1325 // successor, the LLVM-IR entry block. We want the basic block to
1327 assert(EntryBB->succ_size() == 1 &&
1328 "Custom BB used for lowering should have only one successor");
1329 // Get the successor of the current entry block.
1330 MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
1331 assert(NewEntryBB.pred_size() == 1 &&
1332 "LLVM-IR entry block has a predecessor!?");
1333 // Move all the instruction from the current entry block to the
1335 NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
1338 // Update the live-in information for the new entry block.
1339 for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
1340 NewEntryBB.addLiveIn(LiveIn);
1341 NewEntryBB.sortUniqueLiveIns();
1343 // Get rid of the now empty basic block.
1344 EntryBB->removeSuccessor(&NewEntryBB);
1345 MF->remove(EntryBB);
1346 MF->DeleteMachineBasicBlock(EntryBB);
1348 assert(&MF->front() == &NewEntryBB &&
1349 "New entry wasn't next in the list of basic block!");