1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #include "PHIEliminationUtils.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetSubtargetInfo.h"
37 #define DEBUG_TYPE "phi-node-elimination"
40 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
41 cl::Hidden, cl::desc("Disable critical edge splitting "
42 "during PHI elimination"));
45 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
46 cl::Hidden, cl::desc("Split all critical edges during "
49 static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
50 "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
51 cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
54 class PHIElimination : public MachineFunctionPass {
55 MachineRegisterInfo *MRI; // Machine register information
60 static char ID; // Pass identification, replacement for typeid
61 PHIElimination() : MachineFunctionPass(ID) {
62 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
65 bool runOnMachineFunction(MachineFunction &Fn) override;
66 void getAnalysisUsage(AnalysisUsage &AU) const override;
69 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
70 /// in predecessor basic blocks.
72 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
73 void LowerPHINode(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator LastPHIIt);
76 /// analyzePHINodes - Gather information about the PHI nodes in
77 /// here. In particular, we want to map the number of uses of a virtual
78 /// register which is used in a PHI node. We map that to the BB the
79 /// vreg is coming from. This is used later to determine when the vreg
80 /// is killed in the BB.
82 void analyzePHINodes(const MachineFunction& Fn);
84 /// Split critical edges where necessary for good coalescer performance.
85 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
86 MachineLoopInfo *MLI);
88 // These functions are temporary abstractions around LiveVariables and
89 // LiveIntervals, so they can go away when LiveVariables does.
90 bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
91 bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
93 typedef std::pair<unsigned, unsigned> BBVRegPair;
94 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
96 VRegPHIUse VRegPHIUseCount;
98 // Defs of PHI sources which are implicit_def.
99 SmallPtrSet<MachineInstr*, 4> ImpDefs;
101 // Map reusable lowered PHI node -> incoming join register.
102 typedef DenseMap<MachineInstr*, unsigned,
103 MachineInstrExpressionTrait> LoweredPHIMap;
104 LoweredPHIMap LoweredPHIs;
108 STATISTIC(NumLowered, "Number of phis lowered");
109 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
110 STATISTIC(NumReused, "Number of reused lowered phis");
112 char PHIElimination::ID = 0;
113 char& llvm::PHIEliminationID = PHIElimination::ID;
115 INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
116 "Eliminate PHI nodes for register allocation",
118 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
119 INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
120 "Eliminate PHI nodes for register allocation", false, false)
122 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
123 AU.addUsedIfAvailable<LiveVariables>();
124 AU.addPreserved<LiveVariables>();
125 AU.addPreserved<SlotIndexes>();
126 AU.addPreserved<LiveIntervals>();
127 AU.addPreserved<MachineDominatorTree>();
128 AU.addPreserved<MachineLoopInfo>();
129 MachineFunctionPass::getAnalysisUsage(AU);
132 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
133 MRI = &MF.getRegInfo();
134 LV = getAnalysisIfAvailable<LiveVariables>();
135 LIS = getAnalysisIfAvailable<LiveIntervals>();
137 bool Changed = false;
139 // This pass takes the function out of SSA form.
142 // Split critical edges to help the coalescer. This does not yet support
143 // updating LiveIntervals, so we disable it.
144 if (!DisableEdgeSplitting && (LV || LIS)) {
145 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
147 Changed |= SplitPHIEdges(MF, MBB, MLI);
150 // Populate VRegPHIUseCount
153 // Eliminate PHI instructions by inserting copies into predecessor blocks.
155 Changed |= EliminatePHINodes(MF, MBB);
157 // Remove dead IMPLICIT_DEF instructions.
158 for (MachineInstr *DefMI : ImpDefs) {
159 unsigned DefReg = DefMI->getOperand(0).getReg();
160 if (MRI->use_nodbg_empty(DefReg)) {
162 LIS->RemoveMachineInstrFromMaps(*DefMI);
163 DefMI->eraseFromParent();
167 // Clean up the lowered PHI instructions.
168 for (auto &I : LoweredPHIs) {
170 LIS->RemoveMachineInstrFromMaps(*I.first);
171 MF.DeleteMachineInstr(I.first);
176 VRegPHIUseCount.clear();
178 MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
183 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
184 /// predecessor basic blocks.
186 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
187 MachineBasicBlock &MBB) {
188 if (MBB.empty() || !MBB.front().isPHI())
189 return false; // Quick exit for basic blocks without PHIs.
191 // Get an iterator to the first instruction after the last PHI node (this may
192 // also be the end of the basic block).
193 MachineBasicBlock::iterator LastPHIIt =
194 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
196 while (MBB.front().isPHI())
197 LowerPHINode(MBB, LastPHIIt);
202 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
203 /// This includes registers with no defs.
204 static bool isImplicitlyDefined(unsigned VirtReg,
205 const MachineRegisterInfo *MRI) {
206 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
207 if (!DI.isImplicitDef())
212 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
213 /// are implicit_def's.
214 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
215 const MachineRegisterInfo *MRI) {
216 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
217 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
223 /// LowerPHINode - Lower the PHI node at the top of the specified block,
225 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
226 MachineBasicBlock::iterator LastPHIIt) {
229 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
231 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
232 MachineInstr *MPhi = MBB.remove(&*MBB.begin());
234 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
235 unsigned DestReg = MPhi->getOperand(0).getReg();
236 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
237 bool isDead = MPhi->getOperand(0).isDead();
239 // Create a new register for the incoming PHI arguments.
240 MachineFunction &MF = *MBB.getParent();
241 unsigned IncomingReg = 0;
242 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
244 // Insert a register to register copy at the top of the current block (but
245 // after any remaining phi nodes) which copies the new incoming register
246 // into the phi node destination.
247 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
248 if (isSourceDefinedByImplicitDef(MPhi, MRI))
249 // If all sources of a PHI node are implicit_def, just emit an
250 // implicit_def instead of a copy.
251 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
252 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
254 // Can we reuse an earlier PHI node? This only happens for critical edges,
255 // typically those created by tail duplication.
256 unsigned &entry = LoweredPHIs[MPhi];
258 // An identical PHI node was already lowered. Reuse the incoming register.
260 reusedIncoming = true;
262 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
264 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
265 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
267 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
268 TII->get(TargetOpcode::COPY), DestReg)
269 .addReg(IncomingReg);
272 // Update live variable information if there is any.
274 MachineInstr &PHICopy = *std::prev(AfterPHIsIt);
277 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
279 // Increment use count of the newly created virtual register.
280 LV->setPHIJoin(IncomingReg);
282 // When we are reusing the incoming register, it may already have been
283 // killed in this block. The old kill will also have been inserted at
284 // AfterPHIsIt, so it appears before the current PHICopy.
286 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
287 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
288 LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
292 // Add information to LiveVariables to know that the incoming value is
293 // killed. Note that because the value is defined in several places (once
294 // each for each incoming block), the "def" block and instruction fields
295 // for the VarInfo is not filled in.
296 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
299 // Since we are going to be deleting the PHI node, if it is the last use of
300 // any registers, or if the value itself is dead, we need to move this
301 // information over to the new copy we just inserted.
302 LV->removeVirtualRegistersKilled(*MPhi);
304 // If the result is dead, update LV.
306 LV->addVirtualRegisterDead(DestReg, PHICopy);
307 LV->removeVirtualRegisterDead(DestReg, *MPhi);
311 // Update LiveIntervals for the new copy or implicit def.
313 SlotIndex DestCopyIndex =
314 LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
316 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
318 // Add the region from the beginning of MBB to the copy instruction to
319 // IncomingReg's live interval.
320 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
321 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
323 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
324 LIS->getVNInfoAllocator());
325 IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
326 DestCopyIndex.getRegSlot(),
330 LiveInterval &DestLI = LIS->getInterval(DestReg);
331 assert(DestLI.begin() != DestLI.end() &&
332 "PHIs should have nonempty LiveIntervals.");
333 if (DestLI.endIndex().isDead()) {
334 // A dead PHI's live range begins and ends at the start of the MBB, but
335 // the lowered copy, which will still be dead, needs to begin and end at
336 // the copy instruction.
337 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
338 assert(OrigDestVNI && "PHI destination should be live at block entry.");
339 DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
340 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
341 LIS->getVNInfoAllocator());
342 DestLI.removeValNo(OrigDestVNI);
344 // Otherwise, remove the region from the beginning of MBB to the copy
345 // instruction from DestReg's live interval.
346 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
347 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
348 assert(DestVNI && "PHI destination should be live at its definition.");
349 DestVNI->def = DestCopyIndex.getRegSlot();
353 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
354 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
355 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
356 MPhi->getOperand(i).getReg())];
358 // Now loop over all of the incoming arguments, changing them to copy into the
359 // IncomingReg register in the corresponding predecessor basic block.
360 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
361 for (int i = NumSrcs - 1; i >= 0; --i) {
362 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
363 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
364 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
365 isImplicitlyDefined(SrcReg, MRI);
366 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
367 "Machine PHI Operands must all be virtual registers!");
369 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
371 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
373 // Check to make sure we haven't already emitted the copy for this block.
374 // This can happen because PHI nodes may have multiple entries for the same
376 if (!MBBsInsertedInto.insert(&opBlock).second)
377 continue; // If the copy has already been emitted, we're done.
379 // Find a safe location to insert the copy, this may be the first terminator
380 // in the block (or end()).
381 MachineBasicBlock::iterator InsertPos =
382 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
385 MachineInstr *NewSrcInstr = nullptr;
386 if (!reusedIncoming && IncomingReg) {
388 // The source register is undefined, so there is no need for a real
389 // COPY, but we still need to ensure joint dominance by defs.
390 // Insert an IMPLICIT_DEF instruction.
391 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
392 TII->get(TargetOpcode::IMPLICIT_DEF),
395 // Clean up the old implicit-def, if there even was one.
396 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
397 if (DefMI->isImplicitDef())
398 ImpDefs.insert(DefMI);
400 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
401 TII->get(TargetOpcode::COPY), IncomingReg)
402 .addReg(SrcReg, 0, SrcSubReg);
406 // We only need to update the LiveVariables kill of SrcReg if this was the
407 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
408 // out of the predecessor. We can also ignore undef sources.
409 if (LV && !SrcUndef &&
410 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
411 !LV->isLiveOut(SrcReg, opBlock)) {
412 // We want to be able to insert a kill of the register if this PHI (aka,
413 // the copy we just inserted) is the last use of the source value. Live
414 // variable analysis conservatively handles this by saying that the value
415 // is live until the end of the block the PHI entry lives in. If the value
416 // really is dead at the PHI copy, there will be no successor blocks which
417 // have the value live-in.
419 // Okay, if we now know that the value is not live out of the block, we
420 // can add a kill marker in this block saying that it kills the incoming
423 // In our final twist, we have to decide which instruction kills the
424 // register. In most cases this is the copy, however, terminator
425 // instructions at the end of the block may also use the value. In this
426 // case, we should mark the last such terminator as being the killing
427 // block, not the copy.
428 MachineBasicBlock::iterator KillInst = opBlock.end();
429 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
430 for (MachineBasicBlock::iterator Term = FirstTerm;
431 Term != opBlock.end(); ++Term) {
432 if (Term->readsRegister(SrcReg))
436 if (KillInst == opBlock.end()) {
437 // No terminator uses the register.
439 if (reusedIncoming || !IncomingReg) {
440 // We may have to rewind a bit if we didn't insert a copy this time.
441 KillInst = FirstTerm;
442 while (KillInst != opBlock.begin()) {
444 if (KillInst->isDebugValue())
446 if (KillInst->readsRegister(SrcReg))
450 // We just inserted this copy.
451 KillInst = std::prev(InsertPos);
454 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
456 // Finally, mark it killed.
457 LV->addVirtualRegisterKilled(SrcReg, *KillInst);
459 // This vreg no longer lives all of the way through opBlock.
460 unsigned opBlockNum = opBlock.getNumber();
461 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
466 LIS->InsertMachineInstrInMaps(*NewSrcInstr);
467 LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
471 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
472 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
474 bool isLiveOut = false;
475 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
476 SE = opBlock.succ_end(); SI != SE; ++SI) {
477 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
478 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
480 // Definitions by other PHIs are not truly live-in for our purposes.
481 if (VNI && VNI->def != startIdx) {
488 MachineBasicBlock::iterator KillInst = opBlock.end();
489 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
490 for (MachineBasicBlock::iterator Term = FirstTerm;
491 Term != opBlock.end(); ++Term) {
492 if (Term->readsRegister(SrcReg))
496 if (KillInst == opBlock.end()) {
497 // No terminator uses the register.
499 if (reusedIncoming || !IncomingReg) {
500 // We may have to rewind a bit if we didn't just insert a copy.
501 KillInst = FirstTerm;
502 while (KillInst != opBlock.begin()) {
504 if (KillInst->isDebugValue())
506 if (KillInst->readsRegister(SrcReg))
510 // We just inserted this copy.
511 KillInst = std::prev(InsertPos);
514 assert(KillInst->readsRegister(SrcReg) &&
515 "Cannot find kill instruction");
517 SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
518 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
519 LIS->getMBBEndIdx(&opBlock));
525 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
526 if (reusedIncoming || !IncomingReg) {
528 LIS->RemoveMachineInstrFromMaps(*MPhi);
529 MF.DeleteMachineInstr(MPhi);
533 /// analyzePHINodes - Gather information about the PHI nodes in here. In
534 /// particular, we want to map the number of uses of a virtual register which is
535 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
536 /// used later to determine when the vreg is killed in the BB.
538 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
539 for (const auto &MBB : MF)
540 for (const auto &BBI : MBB) {
543 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
544 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
545 BBI.getOperand(i).getReg())];
549 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
550 MachineBasicBlock &MBB,
551 MachineLoopInfo *MLI) {
552 if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
553 return false; // Quick exit for basic blocks without PHIs.
555 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
556 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
558 bool Changed = false;
559 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
560 BBI != BBE && BBI->isPHI(); ++BBI) {
561 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
562 unsigned Reg = BBI->getOperand(i).getReg();
563 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
564 // Is there a critical edge from PreMBB to MBB?
565 if (PreMBB->succ_size() == 1)
568 // Avoid splitting backedges of loops. It would introduce small
569 // out-of-line blocks into the loop which is very bad for code placement.
570 if (PreMBB == &MBB && !SplitAllCriticalEdges)
572 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
573 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
576 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
577 // when the source register is live-out for some other reason than a phi
578 // use. That means the copy we will insert in PreMBB won't be a kill, and
579 // there is a risk it may not be coalesced away.
581 // If the copy would be a kill, there is no need to split the edge.
582 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
583 if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
586 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
587 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
591 // If Reg is not live-in to MBB, it means it must be live-in to some
592 // other PreMBB successor, and we can avoid the interference by splitting
595 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
596 // is likely to be left after coalescing. If we are looking at a loop
597 // exiting edge, split it so we won't insert code in the loop, otherwise
599 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
601 // Check for a loop exiting edge.
602 if (!ShouldSplit && CurLoop != PreLoop) {
604 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
605 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
606 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
608 // This edge could be entering a loop, exiting a loop, or it could be
609 // both: Jumping directly form one loop to the header of a sibling
611 // Split unless this edge is entering CurLoop from an outer loop.
612 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
614 if (!ShouldSplit && !SplitAllCriticalEdges)
616 if (!PreMBB->SplitCriticalEdge(&MBB, *this)) {
617 DEBUG(dbgs() << "Failed to split critical edge.\n");
621 ++NumCriticalEdgesSplit;
627 bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
628 assert((LV || LIS) &&
629 "isLiveIn() requires either LiveVariables or LiveIntervals");
631 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
633 return LV->isLiveIn(Reg, *MBB);
636 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
637 const MachineBasicBlock *MBB) {
638 assert((LV || LIS) &&
639 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
640 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
641 // so that a register used only in a PHI is not live out of the block. In
642 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
643 // in the predecessor basic block, so that a register used only in a PHI is live
646 const LiveInterval &LI = LIS->getInterval(Reg);
647 for (const MachineBasicBlock *SI : MBB->successors())
648 if (LI.liveAt(LIS->getMBBStartIdx(SI)))
652 return LV->isLiveOut(Reg, *MBB);