1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
62 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
63 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
64 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
65 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
66 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
67 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
68 case ISD::ANY_EXTEND_VECTOR_INREG:
69 case ISD::SIGN_EXTEND_VECTOR_INREG:
70 case ISD::ZERO_EXTEND_VECTOR_INREG:
71 R = ScalarizeVecRes_VecInregOp(N);
77 case ISD::CTLZ_ZERO_UNDEF:
80 case ISD::CTTZ_ZERO_UNDEF:
100 case ISD::SIGN_EXTEND:
101 case ISD::SINT_TO_FP:
103 case ISD::UINT_TO_FP:
104 case ISD::ZERO_EXTEND:
105 case ISD::FCANONICALIZE:
106 R = ScalarizeVecRes_UnaryOp(N);
138 R = ScalarizeVecRes_BinOp(N);
141 R = ScalarizeVecRes_TernaryOp(N);
145 // If R is null, the sub-method took care of registering the result.
147 SetScalarizedVector(SDValue(N, ResNo), R);
150 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
151 SDValue LHS = GetScalarizedVector(N->getOperand(0));
152 SDValue RHS = GetScalarizedVector(N->getOperand(1));
153 return DAG.getNode(N->getOpcode(), SDLoc(N),
154 LHS.getValueType(), LHS, RHS, N->getFlags());
157 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
158 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
159 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
160 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
161 return DAG.getNode(N->getOpcode(), SDLoc(N),
162 Op0.getValueType(), Op0, Op1, Op2);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
167 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
168 return GetScalarizedVector(Op);
171 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
172 EVT NewVT = N->getValueType(0).getVectorElementType();
173 return DAG.getNode(ISD::BITCAST, SDLoc(N),
174 NewVT, N->getOperand(0));
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
178 EVT EltVT = N->getValueType(0).getVectorElementType();
179 SDValue InOp = N->getOperand(0);
180 // The BUILD_VECTOR operands may be of wider element types and
181 // we may need to truncate them back to the requested return type.
182 if (EltVT.isInteger())
183 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
187 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
188 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
189 N->getValueType(0).getVectorElementType(),
190 N->getOperand(0), N->getOperand(1));
193 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
194 EVT NewVT = N->getValueType(0).getVectorElementType();
195 SDValue Op = GetScalarizedVector(N->getOperand(0));
196 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
197 NewVT, Op, N->getOperand(1));
200 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
201 SDValue Op = GetScalarizedVector(N->getOperand(0));
202 return DAG.getNode(ISD::FPOWI, SDLoc(N),
203 Op.getValueType(), Op, N->getOperand(1));
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
207 // The value to insert may have a wider type than the vector element type,
208 // so be sure to truncate it to the element type if necessary.
209 SDValue Op = N->getOperand(1);
210 EVT EltVT = N->getValueType(0).getVectorElementType();
211 if (Op.getValueType() != EltVT)
212 // FIXME: Can this happen for floating point types?
213 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
217 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
218 assert(N->isUnindexed() && "Indexed vector load?");
220 SDValue Result = DAG.getLoad(
221 ISD::UNINDEXED, N->getExtensionType(),
222 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
223 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
224 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
225 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
228 // Legalize the chain result - switch anything that used the old chain to
230 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
234 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
235 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
236 EVT DestVT = N->getValueType(0).getVectorElementType();
237 SDValue Op = N->getOperand(0);
238 EVT OpVT = Op.getValueType();
240 // The result needs scalarizing, but it's not a given that the source does.
241 // This is a workaround for targets where it's impossible to scalarize the
242 // result of a conversion, because the source type is legal.
243 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
244 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
245 // legal and was not scalarized.
246 // See the similar logic in ScalarizeVecRes_VSETCC
247 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
248 Op = GetScalarizedVector(Op);
250 EVT VT = OpVT.getVectorElementType();
252 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
253 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
255 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
258 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
259 EVT EltVT = N->getValueType(0).getVectorElementType();
260 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
261 SDValue LHS = GetScalarizedVector(N->getOperand(0));
262 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
263 LHS, DAG.getValueType(ExtVT));
266 SDValue DAGTypeLegalizer::ScalarizeVecRes_VecInregOp(SDNode *N) {
268 SDValue Op = N->getOperand(0);
270 EVT OpVT = Op.getValueType();
271 EVT OpEltVT = OpVT.getVectorElementType();
272 EVT EltVT = N->getValueType(0).getVectorElementType();
274 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
275 Op = GetScalarizedVector(Op);
278 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
279 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
282 switch (N->getOpcode()) {
283 case ISD::ANY_EXTEND_VECTOR_INREG:
284 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
285 case ISD::SIGN_EXTEND_VECTOR_INREG:
286 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
287 case ISD::ZERO_EXTEND_VECTOR_INREG:
288 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
291 llvm_unreachable("Illegal extend_vector_inreg opcode");
294 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
295 // If the operand is wider than the vector element type then it is implicitly
296 // truncated. Make that explicit here.
297 EVT EltVT = N->getValueType(0).getVectorElementType();
298 SDValue InOp = N->getOperand(0);
299 if (InOp.getValueType() != EltVT)
300 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
304 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
305 SDValue Cond = GetScalarizedVector(N->getOperand(0));
306 SDValue LHS = GetScalarizedVector(N->getOperand(1));
307 TargetLowering::BooleanContent ScalarBool =
308 TLI.getBooleanContents(false, false);
309 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
311 // If integer and float booleans have different contents then we can't
312 // reliably optimize in all cases. There is a full explanation for this in
313 // DAGCombiner::visitSELECT() where the same issue affects folding
314 // (select C, 0, 1) to (xor C, 1).
315 if (TLI.getBooleanContents(false, false) !=
316 TLI.getBooleanContents(false, true)) {
317 // At least try the common case where the boolean is generated by a
319 if (Cond->getOpcode() == ISD::SETCC) {
320 EVT OpVT = Cond->getOperand(0)->getValueType(0);
321 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
322 VecBool = TLI.getBooleanContents(OpVT);
324 ScalarBool = TargetLowering::UndefinedBooleanContent;
327 if (ScalarBool != VecBool) {
328 EVT CondVT = Cond.getValueType();
329 switch (ScalarBool) {
330 case TargetLowering::UndefinedBooleanContent:
332 case TargetLowering::ZeroOrOneBooleanContent:
333 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
334 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
335 // Vector read from all ones, scalar expects a single 1 so mask.
336 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
337 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
339 case TargetLowering::ZeroOrNegativeOneBooleanContent:
340 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
341 VecBool == TargetLowering::ZeroOrOneBooleanContent);
342 // Vector reads from a one, scalar from all ones so sign extend.
343 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
344 Cond, DAG.getValueType(MVT::i1));
349 return DAG.getSelect(SDLoc(N),
350 LHS.getValueType(), Cond, LHS,
351 GetScalarizedVector(N->getOperand(2)));
354 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
355 SDValue LHS = GetScalarizedVector(N->getOperand(1));
356 return DAG.getSelect(SDLoc(N),
357 LHS.getValueType(), N->getOperand(0), LHS,
358 GetScalarizedVector(N->getOperand(2)));
361 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
362 SDValue LHS = GetScalarizedVector(N->getOperand(2));
363 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
364 N->getOperand(0), N->getOperand(1),
365 LHS, GetScalarizedVector(N->getOperand(3)),
369 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
370 assert(N->getValueType(0).isVector() ==
371 N->getOperand(0).getValueType().isVector() &&
372 "Scalar/Vector type mismatch");
374 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
376 SDValue LHS = GetScalarizedVector(N->getOperand(0));
377 SDValue RHS = GetScalarizedVector(N->getOperand(1));
380 // Turn it into a scalar SETCC.
381 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
384 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
385 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
388 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
389 // Figure out if the scalar is the LHS or RHS and return it.
390 SDValue Arg = N->getOperand(2).getOperand(0);
392 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
393 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
394 return GetScalarizedVector(N->getOperand(Op));
397 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
398 assert(N->getValueType(0).isVector() &&
399 N->getOperand(0).getValueType().isVector() &&
400 "Operand types must be vectors");
401 SDValue LHS = N->getOperand(0);
402 SDValue RHS = N->getOperand(1);
403 EVT OpVT = LHS.getValueType();
404 EVT NVT = N->getValueType(0).getVectorElementType();
407 // The result needs scalarizing, but it's not a given that the source does.
408 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
409 LHS = GetScalarizedVector(LHS);
410 RHS = GetScalarizedVector(RHS);
412 EVT VT = OpVT.getVectorElementType();
414 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
415 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
417 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
418 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
421 // Turn it into a scalar SETCC.
422 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
424 // Vectors may have a different boolean contents to scalars. Promote the
425 // value appropriately.
426 ISD::NodeType ExtendCode =
427 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
428 return DAG.getNode(ExtendCode, DL, NVT, Res);
432 //===----------------------------------------------------------------------===//
433 // Operand Vector Scalarization <1 x ty> -> ty.
434 //===----------------------------------------------------------------------===//
436 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
437 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
440 SDValue Res = SDValue();
442 if (!Res.getNode()) {
443 switch (N->getOpcode()) {
446 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
450 llvm_unreachable("Do not know how to scalarize this operator's operand!");
452 Res = ScalarizeVecOp_BITCAST(N);
454 case ISD::ANY_EXTEND:
455 case ISD::ZERO_EXTEND:
456 case ISD::SIGN_EXTEND:
458 case ISD::FP_TO_SINT:
459 case ISD::FP_TO_UINT:
460 case ISD::SINT_TO_FP:
461 case ISD::UINT_TO_FP:
462 Res = ScalarizeVecOp_UnaryOp(N);
464 case ISD::CONCAT_VECTORS:
465 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
467 case ISD::EXTRACT_VECTOR_ELT:
468 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
471 Res = ScalarizeVecOp_VSELECT(N);
474 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
477 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
482 // If the result is null, the sub-method took care of registering results etc.
483 if (!Res.getNode()) return false;
485 // If the result is N, the sub-method updated N in place. Tell the legalizer
487 if (Res.getNode() == N)
490 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
491 "Invalid operand expansion");
493 ReplaceValueWith(SDValue(N, 0), Res);
497 /// If the value to convert is a vector that needs to be scalarized, it must be
498 /// <1 x ty>. Convert the element instead.
499 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
500 SDValue Elt = GetScalarizedVector(N->getOperand(0));
501 return DAG.getNode(ISD::BITCAST, SDLoc(N),
502 N->getValueType(0), Elt);
505 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
506 /// Do the operation on the element instead.
507 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
508 assert(N->getValueType(0).getVectorNumElements() == 1 &&
509 "Unexpected vector type!");
510 SDValue Elt = GetScalarizedVector(N->getOperand(0));
511 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
512 N->getValueType(0).getScalarType(), Elt);
513 // Revectorize the result so the types line up with what the uses of this
514 // expression expect.
515 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
518 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
519 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
520 SmallVector<SDValue, 8> Ops(N->getNumOperands());
521 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
522 Ops[i] = GetScalarizedVector(N->getOperand(i));
523 return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
526 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
527 /// so just return the element, ignoring the index.
528 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
529 SDValue Res = GetScalarizedVector(N->getOperand(0));
530 if (Res.getValueType() != N->getValueType(0))
531 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
537 /// If the input condition is a vector that needs to be scalarized, it must be
538 /// <1 x i1>, so just convert to a normal ISD::SELECT
539 /// (still with vector output type since that was acceptable if we got here).
540 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
541 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
542 EVT VT = N->getValueType(0);
544 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
548 /// If the value to store is a vector that needs to be scalarized, it must be
549 /// <1 x ty>. Just store the element.
550 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
551 assert(N->isUnindexed() && "Indexed store of one-element vector?");
552 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
555 if (N->isTruncatingStore())
556 return DAG.getTruncStore(
557 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
558 N->getBasePtr(), N->getPointerInfo(),
559 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
560 N->getMemOperand()->getFlags(), N->getAAInfo());
562 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
563 N->getBasePtr(), N->getPointerInfo(),
564 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
568 /// If the value to round is a vector that needs to be scalarized, it must be
569 /// <1 x ty>. Convert the element instead.
570 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
571 SDValue Elt = GetScalarizedVector(N->getOperand(0));
572 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
573 N->getValueType(0).getVectorElementType(), Elt,
575 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
578 //===----------------------------------------------------------------------===//
579 // Result Vector Splitting
580 //===----------------------------------------------------------------------===//
582 /// This method is called when the specified result of the specified node is
583 /// found to need vector splitting. At this point, the node may also have
584 /// invalid operands or may have other results that need legalization, we just
585 /// know that (at least) one result needs vector splitting.
586 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
587 DEBUG(dbgs() << "Split node result: ";
592 // See if the target wants to custom expand this node.
593 if (CustomLowerNode(N, N->getValueType(ResNo), true))
596 switch (N->getOpcode()) {
599 dbgs() << "SplitVectorResult #" << ResNo << ": ";
603 report_fatal_error("Do not know how to split the result of this "
606 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
608 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
609 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
610 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
611 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
612 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
613 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
614 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
615 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
616 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
617 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
618 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
619 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
620 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
621 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
623 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
626 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
629 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
632 SplitVecRes_SETCC(N, Lo, Hi);
634 case ISD::VECTOR_SHUFFLE:
635 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
638 case ISD::ANY_EXTEND_VECTOR_INREG:
639 case ISD::SIGN_EXTEND_VECTOR_INREG:
640 case ISD::ZERO_EXTEND_VECTOR_INREG:
641 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
644 case ISD::BITREVERSE:
648 case ISD::CTLZ_ZERO_UNDEF:
649 case ISD::CTTZ_ZERO_UNDEF:
660 case ISD::FNEARBYINT:
664 case ISD::FP_TO_SINT:
665 case ISD::FP_TO_UINT:
671 case ISD::SINT_TO_FP:
673 case ISD::UINT_TO_FP:
674 case ISD::FCANONICALIZE:
675 SplitVecRes_UnaryOp(N, Lo, Hi);
678 case ISD::ANY_EXTEND:
679 case ISD::SIGN_EXTEND:
680 case ISD::ZERO_EXTEND:
681 SplitVecRes_ExtendOp(N, Lo, Hi);
713 SplitVecRes_BinOp(N, Lo, Hi);
716 SplitVecRes_TernaryOp(N, Lo, Hi);
720 // If Lo/Hi is null, the sub-method took care of registering results etc.
722 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
725 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
727 SDValue LHSLo, LHSHi;
728 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
729 SDValue RHSLo, RHSHi;
730 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
733 const SDNodeFlags *Flags = N->getFlags();
734 unsigned Opcode = N->getOpcode();
735 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
736 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
739 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
741 SDValue Op0Lo, Op0Hi;
742 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
743 SDValue Op1Lo, Op1Hi;
744 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
745 SDValue Op2Lo, Op2Hi;
746 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
749 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
750 Op0Lo, Op1Lo, Op2Lo);
751 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
752 Op0Hi, Op1Hi, Op2Hi);
755 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
757 // We know the result is a vector. The input may be either a vector or a
760 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
763 SDValue InOp = N->getOperand(0);
764 EVT InVT = InOp.getValueType();
766 // Handle some special cases efficiently.
767 switch (getTypeAction(InVT)) {
768 case TargetLowering::TypeLegal:
769 case TargetLowering::TypePromoteInteger:
770 case TargetLowering::TypePromoteFloat:
771 case TargetLowering::TypeSoftenFloat:
772 case TargetLowering::TypeScalarizeVector:
773 case TargetLowering::TypeWidenVector:
775 case TargetLowering::TypeExpandInteger:
776 case TargetLowering::TypeExpandFloat:
777 // A scalar to vector conversion, where the scalar needs expansion.
778 // If the vector is being split in two then we can just convert the
781 GetExpandedOp(InOp, Lo, Hi);
782 if (DAG.getDataLayout().isBigEndian())
784 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
785 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
789 case TargetLowering::TypeSplitVector:
790 // If the input is a vector that needs to be split, convert each split
791 // piece of the input now.
792 GetSplitVector(InOp, Lo, Hi);
793 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
794 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
798 // In the general case, convert the input to an integer and split it by hand.
799 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
800 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
801 if (DAG.getDataLayout().isBigEndian())
802 std::swap(LoIntVT, HiIntVT);
804 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
806 if (DAG.getDataLayout().isBigEndian())
808 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
809 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
812 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
816 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
817 unsigned LoNumElts = LoVT.getVectorNumElements();
818 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
819 Lo = DAG.getBuildVector(LoVT, dl, LoOps);
821 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
822 Hi = DAG.getBuildVector(HiVT, dl, HiOps);
825 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
827 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
829 unsigned NumSubvectors = N->getNumOperands() / 2;
830 if (NumSubvectors == 1) {
831 Lo = N->getOperand(0);
832 Hi = N->getOperand(1);
837 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
839 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
840 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
842 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
843 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
846 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
848 SDValue Vec = N->getOperand(0);
849 SDValue Idx = N->getOperand(1);
853 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
855 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
856 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
857 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
858 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
859 TLI.getVectorIdxTy(DAG.getDataLayout())));
862 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
864 SDValue Vec = N->getOperand(0);
865 SDValue SubVec = N->getOperand(1);
866 SDValue Idx = N->getOperand(2);
868 GetSplitVector(Vec, Lo, Hi);
870 EVT VecVT = Vec.getValueType();
871 unsigned VecElems = VecVT.getVectorNumElements();
872 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
874 // If we know the index is 0, and we know the subvector doesn't cross the
875 // boundary between the halves, we can avoid spilling the vector, and insert
876 // into the lower half of the split vector directly.
877 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
878 // the index is constant and there is no boundary crossing. But those cases
879 // don't seem to get hit in practice.
880 if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
881 unsigned IdxVal = ConstIdx->getZExtValue();
882 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
884 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
885 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
890 // Spill the vector to the stack.
891 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
893 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
895 // Store the new subvector into the specified index.
896 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
897 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
898 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
899 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
901 // Load the Lo part from the stack slot.
903 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
905 // Increment the pointer to the other part.
906 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
908 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
909 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
911 // Load the Hi part from the stack slot.
912 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
913 MinAlign(Alignment, IncrementSize));
916 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
919 GetSplitVector(N->getOperand(0), Lo, Hi);
920 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
921 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
924 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
926 SDValue LHSLo, LHSHi;
927 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
930 SDValue RHSLo, RHSHi;
931 SDValue RHS = N->getOperand(1);
932 EVT RHSVT = RHS.getValueType();
933 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
934 GetSplitVector(RHS, RHSLo, RHSHi);
936 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
939 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
940 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
943 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
945 SDValue LHSLo, LHSHi;
946 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
950 std::tie(LoVT, HiVT) =
951 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
953 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
954 DAG.getValueType(LoVT));
955 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
956 DAG.getValueType(HiVT));
959 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
961 unsigned Opcode = N->getOpcode();
962 SDValue N0 = N->getOperand(0);
967 if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
968 GetSplitVector(N0, InLo, InHi);
970 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
972 EVT InLoVT = InLo.getValueType();
973 unsigned InNumElements = InLoVT.getVectorNumElements();
975 EVT OutLoVT, OutHiVT;
976 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
977 unsigned OutNumElements = OutLoVT.getVectorNumElements();
978 assert((2 * OutNumElements) <= InNumElements &&
979 "Illegal extend vector in reg split");
981 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
982 // input vector (i.e. we only use InLo):
983 // OutLo will extend the first OutNumElements from InLo.
984 // OutHi will extend the next OutNumElements from InLo.
986 // Shuffle the elements from InLo for OutHi into the bottom elements to
987 // create a 'fake' InHi.
988 SmallVector<int, 8> SplitHi(InNumElements, -1);
989 for (unsigned i = 0; i != OutNumElements; ++i)
990 SplitHi[i] = i + OutNumElements;
991 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
993 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
994 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
997 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
999 SDValue Vec = N->getOperand(0);
1000 SDValue Elt = N->getOperand(1);
1001 SDValue Idx = N->getOperand(2);
1003 GetSplitVector(Vec, Lo, Hi);
1005 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
1006 unsigned IdxVal = CIdx->getZExtValue();
1007 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1008 if (IdxVal < LoNumElts)
1009 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1010 Lo.getValueType(), Lo, Elt, Idx);
1013 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1014 DAG.getConstant(IdxVal - LoNumElts, dl,
1015 TLI.getVectorIdxTy(DAG.getDataLayout())));
1019 // See if the target wants to custom expand this node.
1020 if (CustomLowerNode(N, N->getValueType(0), true))
1023 // Spill the vector to the stack.
1024 EVT VecVT = Vec.getValueType();
1025 EVT EltVT = VecVT.getVectorElementType();
1026 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1028 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1030 // Store the new element. This may be larger than the vector element type,
1031 // so use a truncating store.
1032 SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1033 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1034 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1036 DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT);
1038 // Load the Lo part from the stack slot.
1040 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
1042 // Increment the pointer to the other part.
1043 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
1044 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1045 DAG.getConstant(IncrementSize, dl,
1046 StackPtr.getValueType()));
1048 // Load the Hi part from the stack slot.
1049 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1050 MinAlign(Alignment, IncrementSize));
1053 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1057 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1058 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1059 Hi = DAG.getUNDEF(HiVT);
1062 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1064 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1067 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1069 ISD::LoadExtType ExtType = LD->getExtensionType();
1070 SDValue Ch = LD->getChain();
1071 SDValue Ptr = LD->getBasePtr();
1072 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1073 EVT MemoryVT = LD->getMemoryVT();
1074 unsigned Alignment = LD->getOriginalAlignment();
1075 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1076 AAMDNodes AAInfo = LD->getAAInfo();
1078 EVT LoMemVT, HiMemVT;
1079 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1081 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1082 LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1084 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1085 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1086 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1087 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1088 LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1089 Alignment, MMOFlags, AAInfo);
1091 // Build a factor node to remember that this load is independent of the
1093 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1096 // Legalize the chain result - switch anything that used the old chain to
1098 ReplaceValueWith(SDValue(LD, 1), Ch);
1101 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1102 SDValue &Lo, SDValue &Hi) {
1105 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1107 SDValue Ch = MLD->getChain();
1108 SDValue Ptr = MLD->getBasePtr();
1109 SDValue Mask = MLD->getMask();
1110 SDValue Src0 = MLD->getSrc0();
1111 unsigned Alignment = MLD->getOriginalAlignment();
1112 ISD::LoadExtType ExtType = MLD->getExtensionType();
1114 // if Alignment is equal to the vector size,
1115 // take the half of it for the second part
1116 unsigned SecondHalfAlignment =
1117 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1118 Alignment/2 : Alignment;
1120 // Split Mask operand
1121 SDValue MaskLo, MaskHi;
1122 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1123 GetSplitVector(Mask, MaskLo, MaskHi);
1125 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1127 EVT MemoryVT = MLD->getMemoryVT();
1128 EVT LoMemVT, HiMemVT;
1129 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1131 SDValue Src0Lo, Src0Hi;
1132 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1133 GetSplitVector(Src0, Src0Lo, Src0Hi);
1135 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1137 MachineMemOperand *MMO = DAG.getMachineFunction().
1138 getMachineMemOperand(MLD->getPointerInfo(),
1139 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1140 Alignment, MLD->getAAInfo(), MLD->getRanges());
1142 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1143 ExtType, MLD->isExpandingLoad());
1145 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1146 MLD->isExpandingLoad());
1148 MMO = DAG.getMachineFunction().
1149 getMachineMemOperand(MLD->getPointerInfo(),
1150 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1151 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1153 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1154 ExtType, MLD->isExpandingLoad());
1157 // Build a factor node to remember that this load is independent of the
1159 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1162 // Legalize the chain result - switch anything that used the old chain to
1164 ReplaceValueWith(SDValue(MLD, 1), Ch);
1168 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1169 SDValue &Lo, SDValue &Hi) {
1172 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1174 SDValue Ch = MGT->getChain();
1175 SDValue Ptr = MGT->getBasePtr();
1176 SDValue Mask = MGT->getMask();
1177 SDValue Src0 = MGT->getValue();
1178 SDValue Index = MGT->getIndex();
1179 unsigned Alignment = MGT->getOriginalAlignment();
1181 // Split Mask operand
1182 SDValue MaskLo, MaskHi;
1183 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1184 GetSplitVector(Mask, MaskLo, MaskHi);
1186 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1188 EVT MemoryVT = MGT->getMemoryVT();
1189 EVT LoMemVT, HiMemVT;
1191 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1193 SDValue Src0Lo, Src0Hi;
1194 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1195 GetSplitVector(Src0, Src0Lo, Src0Hi);
1197 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1199 SDValue IndexHi, IndexLo;
1200 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1201 GetSplitVector(Index, IndexLo, IndexHi);
1203 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1205 MachineMemOperand *MMO = DAG.getMachineFunction().
1206 getMachineMemOperand(MGT->getPointerInfo(),
1207 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1208 Alignment, MGT->getAAInfo(), MGT->getRanges());
1210 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1211 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1214 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1215 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1218 // Build a factor node to remember that this load is independent of the
1220 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1223 // Legalize the chain result - switch anything that used the old chain to
1225 ReplaceValueWith(SDValue(MGT, 1), Ch);
1229 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1230 assert(N->getValueType(0).isVector() &&
1231 N->getOperand(0).getValueType().isVector() &&
1232 "Operand types must be vectors");
1236 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1239 SDValue LL, LH, RL, RH;
1240 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1241 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1243 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1244 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1247 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1249 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1252 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1254 // If the input also splits, handle it directly for a compile time speedup.
1255 // Otherwise split it by hand.
1256 EVT InVT = N->getOperand(0).getValueType();
1257 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1258 GetSplitVector(N->getOperand(0), Lo, Hi);
1260 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1262 if (N->getOpcode() == ISD::FP_ROUND) {
1263 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1264 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1266 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1267 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1271 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1274 EVT SrcVT = N->getOperand(0).getValueType();
1275 EVT DestVT = N->getValueType(0);
1277 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1279 // We can do better than a generic split operation if the extend is doing
1280 // more than just doubling the width of the elements and the following are
1282 // - The number of vector elements is even,
1283 // - the source type is legal,
1284 // - the type of a split source is illegal,
1285 // - the type of an extended (by doubling element size) source is legal, and
1286 // - the type of that extended source when split is legal.
1288 // This won't necessarily completely legalize the operation, but it will
1289 // more effectively move in the right direction and prevent falling down
1290 // to scalarization in many cases due to the input vector being split too
1292 unsigned NumElements = SrcVT.getVectorNumElements();
1293 if ((NumElements & 1) == 0 &&
1294 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1295 LLVMContext &Ctx = *DAG.getContext();
1296 EVT NewSrcVT = EVT::getVectorVT(
1297 Ctx, EVT::getIntegerVT(
1298 Ctx, SrcVT.getScalarSizeInBits() * 2),
1301 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1302 EVT SplitLoVT, SplitHiVT;
1303 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1304 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1305 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1306 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1307 N->dump(&DAG); dbgs() << "\n");
1308 // Extend the source vector by one step.
1310 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1311 // Get the low and high halves of the new, extended one step, vector.
1312 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1313 // Extend those vector halves the rest of the way.
1314 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1315 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1319 // Fall back to the generic unary operator splitting otherwise.
1320 SplitVecRes_UnaryOp(N, Lo, Hi);
1323 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1324 SDValue &Lo, SDValue &Hi) {
1325 // The low and high parts of the original input give four input vectors.
1328 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1329 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1330 EVT NewVT = Inputs[0].getValueType();
1331 unsigned NewElts = NewVT.getVectorNumElements();
1333 // If Lo or Hi uses elements from at most two of the four input vectors, then
1334 // express it as a vector shuffle of those two inputs. Otherwise extract the
1335 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1336 SmallVector<int, 16> Ops;
1337 for (unsigned High = 0; High < 2; ++High) {
1338 SDValue &Output = High ? Hi : Lo;
1340 // Build a shuffle mask for the output, discovering on the fly which
1341 // input vectors to use as shuffle operands (recorded in InputUsed).
1342 // If building a suitable shuffle vector proves too hard, then bail
1343 // out with useBuildVector set.
1344 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1345 unsigned FirstMaskIdx = High * NewElts;
1346 bool useBuildVector = false;
1347 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1348 // The mask element. This indexes into the input.
1349 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1351 // The input vector this mask element indexes into.
1352 unsigned Input = (unsigned)Idx / NewElts;
1354 if (Input >= array_lengthof(Inputs)) {
1355 // The mask element does not index into any input vector.
1360 // Turn the index into an offset from the start of the input vector.
1361 Idx -= Input * NewElts;
1363 // Find or create a shuffle vector operand to hold this input.
1365 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1366 if (InputUsed[OpNo] == Input) {
1367 // This input vector is already an operand.
1369 } else if (InputUsed[OpNo] == -1U) {
1370 // Create a new operand for this input vector.
1371 InputUsed[OpNo] = Input;
1376 if (OpNo >= array_lengthof(InputUsed)) {
1377 // More than two input vectors used! Give up on trying to create a
1378 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1379 useBuildVector = true;
1383 // Add the mask index for the new shuffle vector.
1384 Ops.push_back(Idx + OpNo * NewElts);
1387 if (useBuildVector) {
1388 EVT EltVT = NewVT.getVectorElementType();
1389 SmallVector<SDValue, 16> SVOps;
1391 // Extract the input elements by hand.
1392 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1393 // The mask element. This indexes into the input.
1394 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1396 // The input vector this mask element indexes into.
1397 unsigned Input = (unsigned)Idx / NewElts;
1399 if (Input >= array_lengthof(Inputs)) {
1400 // The mask element is "undef" or indexes off the end of the input.
1401 SVOps.push_back(DAG.getUNDEF(EltVT));
1405 // Turn the index into an offset from the start of the input vector.
1406 Idx -= Input * NewElts;
1408 // Extract the vector element by hand.
1409 SVOps.push_back(DAG.getNode(
1410 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1411 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1414 // Construct the Lo/Hi output using a BUILD_VECTOR.
1415 Output = DAG.getBuildVector(NewVT, dl, SVOps);
1416 } else if (InputUsed[0] == -1U) {
1417 // No input vectors were used! The result is undefined.
1418 Output = DAG.getUNDEF(NewVT);
1420 SDValue Op0 = Inputs[InputUsed[0]];
1421 // If only one input was used, use an undefined vector for the other.
1422 SDValue Op1 = InputUsed[1] == -1U ?
1423 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1424 // At least one input vector was used. Create a new shuffle vector.
1425 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1433 //===----------------------------------------------------------------------===//
1434 // Operand Vector Splitting
1435 //===----------------------------------------------------------------------===//
1437 /// This method is called when the specified operand of the specified node is
1438 /// found to need vector splitting. At this point, all of the result types of
1439 /// the node are known to be legal, but other operands of the node may need
1440 /// legalization as well as the specified one.
1441 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1442 DEBUG(dbgs() << "Split node operand: ";
1445 SDValue Res = SDValue();
1447 // See if the target wants to custom split this node.
1448 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1451 if (!Res.getNode()) {
1452 switch (N->getOpcode()) {
1455 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1459 report_fatal_error("Do not know how to split this operator's "
1462 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1463 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1464 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1465 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1466 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1468 Res = SplitVecOp_TruncateHelper(N);
1470 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1471 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1473 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1476 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1479 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1482 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1485 Res = SplitVecOp_VSELECT(N, OpNo);
1487 case ISD::FP_TO_SINT:
1488 case ISD::FP_TO_UINT:
1489 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1490 Res = SplitVecOp_TruncateHelper(N);
1492 Res = SplitVecOp_UnaryOp(N);
1494 case ISD::SINT_TO_FP:
1495 case ISD::UINT_TO_FP:
1496 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1497 Res = SplitVecOp_TruncateHelper(N);
1499 Res = SplitVecOp_UnaryOp(N);
1504 case ISD::FP_EXTEND:
1505 case ISD::SIGN_EXTEND:
1506 case ISD::ZERO_EXTEND:
1507 case ISD::ANY_EXTEND:
1509 case ISD::FCANONICALIZE:
1510 Res = SplitVecOp_UnaryOp(N);
1515 // If the result is null, the sub-method took care of registering results etc.
1516 if (!Res.getNode()) return false;
1518 // If the result is N, the sub-method updated N in place. Tell the legalizer
1520 if (Res.getNode() == N)
1523 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1524 "Invalid operand expansion");
1526 ReplaceValueWith(SDValue(N, 0), Res);
1530 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1531 // The only possibility for an illegal operand is the mask, since result type
1532 // legalization would have handled this node already otherwise.
1533 assert(OpNo == 0 && "Illegal operand must be mask");
1535 SDValue Mask = N->getOperand(0);
1536 SDValue Src0 = N->getOperand(1);
1537 SDValue Src1 = N->getOperand(2);
1538 EVT Src0VT = Src0.getValueType();
1540 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1543 GetSplitVector(N->getOperand(0), Lo, Hi);
1544 assert(Lo.getValueType() == Hi.getValueType() &&
1545 "Lo and Hi have differing types");
1548 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1549 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1551 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1552 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1553 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1554 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1557 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1559 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1561 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1564 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1565 // The result has a legal vector type, but the input needs splitting.
1566 EVT ResVT = N->getValueType(0);
1569 GetSplitVector(N->getOperand(0), Lo, Hi);
1570 EVT InVT = Lo.getValueType();
1572 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1573 InVT.getVectorNumElements());
1575 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1576 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1578 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1581 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1582 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1583 // end up being split all the way down to individual components. Convert the
1584 // split pieces into integers and reassemble.
1586 GetSplitVector(N->getOperand(0), Lo, Hi);
1587 Lo = BitConvertToInteger(Lo);
1588 Hi = BitConvertToInteger(Hi);
1590 if (DAG.getDataLayout().isBigEndian())
1593 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1594 JoinIntegers(Lo, Hi));
1597 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1598 // We know that the extracted result type is legal.
1599 EVT SubVT = N->getValueType(0);
1600 SDValue Idx = N->getOperand(1);
1603 GetSplitVector(N->getOperand(0), Lo, Hi);
1605 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1606 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1608 if (IdxVal < LoElts) {
1609 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1610 "Extracted subvector crosses vector split!");
1611 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1613 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1614 DAG.getConstant(IdxVal - LoElts, dl,
1615 Idx.getValueType()));
1619 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1620 SDValue Vec = N->getOperand(0);
1621 SDValue Idx = N->getOperand(1);
1622 EVT VecVT = Vec.getValueType();
1624 if (isa<ConstantSDNode>(Idx)) {
1625 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1626 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1629 GetSplitVector(Vec, Lo, Hi);
1631 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1633 if (IdxVal < LoElts)
1634 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1635 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1636 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1637 Idx.getValueType())), 0);
1640 // See if the target wants to custom expand this node.
1641 if (CustomLowerNode(N, N->getValueType(0), true))
1644 // Make the vector elements byte-addressable if they aren't already.
1646 EVT EltVT = VecVT.getVectorElementType();
1647 if (EltVT.getSizeInBits() < 8) {
1648 SmallVector<SDValue, 4> ElementOps;
1649 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1650 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1651 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1652 DAG.getConstant(i, dl, MVT::i8)),
1657 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1658 VecVT.getVectorNumElements());
1659 Vec = DAG.getBuildVector(VecVT, dl, ElementOps);
1662 // Store the vector to the stack.
1663 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1665 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1667 // Load back the required element.
1668 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1669 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1670 MachinePointerInfo(), EltVT);
1673 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1677 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1679 SDValue Ch = MGT->getChain();
1680 SDValue Ptr = MGT->getBasePtr();
1681 SDValue Index = MGT->getIndex();
1682 SDValue Mask = MGT->getMask();
1683 SDValue Src0 = MGT->getValue();
1684 unsigned Alignment = MGT->getOriginalAlignment();
1686 SDValue MaskLo, MaskHi;
1687 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1688 // Split Mask operand
1689 GetSplitVector(Mask, MaskLo, MaskHi);
1691 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1693 EVT MemoryVT = MGT->getMemoryVT();
1694 EVT LoMemVT, HiMemVT;
1695 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1697 SDValue Src0Lo, Src0Hi;
1698 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1699 GetSplitVector(Src0, Src0Lo, Src0Hi);
1701 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1703 SDValue IndexHi, IndexLo;
1704 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1705 GetSplitVector(Index, IndexLo, IndexHi);
1707 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1709 MachineMemOperand *MMO = DAG.getMachineFunction().
1710 getMachineMemOperand(MGT->getPointerInfo(),
1711 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1712 Alignment, MGT->getAAInfo(), MGT->getRanges());
1714 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1715 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1718 MMO = DAG.getMachineFunction().
1719 getMachineMemOperand(MGT->getPointerInfo(),
1720 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1721 Alignment, MGT->getAAInfo(),
1724 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1725 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1728 // Build a factor node to remember that this load is independent of the
1730 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1733 // Legalize the chain result - switch anything that used the old chain to
1735 ReplaceValueWith(SDValue(MGT, 1), Ch);
1737 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1739 ReplaceValueWith(SDValue(MGT, 0), Res);
1743 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1745 SDValue Ch = N->getChain();
1746 SDValue Ptr = N->getBasePtr();
1747 SDValue Mask = N->getMask();
1748 SDValue Data = N->getValue();
1749 EVT MemoryVT = N->getMemoryVT();
1750 unsigned Alignment = N->getOriginalAlignment();
1753 EVT LoMemVT, HiMemVT;
1754 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1756 SDValue DataLo, DataHi;
1757 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1758 // Split Data operand
1759 GetSplitVector(Data, DataLo, DataHi);
1761 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1763 SDValue MaskLo, MaskHi;
1764 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1765 // Split Mask operand
1766 GetSplitVector(Mask, MaskLo, MaskHi);
1768 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1770 MaskLo = PromoteTargetBoolean(MaskLo, DataLo.getValueType());
1771 MaskHi = PromoteTargetBoolean(MaskHi, DataHi.getValueType());
1773 // if Alignment is equal to the vector size,
1774 // take the half of it for the second part
1775 unsigned SecondHalfAlignment =
1776 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1777 Alignment/2 : Alignment;
1780 MachineMemOperand *MMO = DAG.getMachineFunction().
1781 getMachineMemOperand(N->getPointerInfo(),
1782 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1783 Alignment, N->getAAInfo(), N->getRanges());
1785 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1786 N->isTruncatingStore(),
1787 N->isCompressingStore());
1789 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
1790 N->isCompressingStore());
1791 MMO = DAG.getMachineFunction().
1792 getMachineMemOperand(N->getPointerInfo(),
1793 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1794 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1796 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1797 N->isTruncatingStore(), N->isCompressingStore());
1799 // Build a factor node to remember that this store is independent of the
1801 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1804 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1806 SDValue Ch = N->getChain();
1807 SDValue Ptr = N->getBasePtr();
1808 SDValue Mask = N->getMask();
1809 SDValue Index = N->getIndex();
1810 SDValue Data = N->getValue();
1811 EVT MemoryVT = N->getMemoryVT();
1812 unsigned Alignment = N->getOriginalAlignment();
1815 // Split all operands
1816 EVT LoMemVT, HiMemVT;
1817 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1819 SDValue DataLo, DataHi;
1820 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1821 // Split Data operand
1822 GetSplitVector(Data, DataLo, DataHi);
1824 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1826 SDValue MaskLo, MaskHi;
1827 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1828 // Split Mask operand
1829 GetSplitVector(Mask, MaskLo, MaskHi);
1831 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1833 SDValue IndexHi, IndexLo;
1834 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1835 GetSplitVector(Index, IndexLo, IndexHi);
1837 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1840 MachineMemOperand *MMO = DAG.getMachineFunction().
1841 getMachineMemOperand(N->getPointerInfo(),
1842 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1843 Alignment, N->getAAInfo(), N->getRanges());
1845 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo};
1846 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1849 MMO = DAG.getMachineFunction().
1850 getMachineMemOperand(N->getPointerInfo(),
1851 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1852 Alignment, N->getAAInfo(), N->getRanges());
1854 SDValue OpsHi[] = {Ch, DataHi, MaskHi, Ptr, IndexHi};
1855 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1858 // Build a factor node to remember that this store is independent of the
1860 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1863 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1864 assert(N->isUnindexed() && "Indexed store of vector?");
1865 assert(OpNo == 1 && "Can only split the stored value");
1868 bool isTruncating = N->isTruncatingStore();
1869 SDValue Ch = N->getChain();
1870 SDValue Ptr = N->getBasePtr();
1871 EVT MemoryVT = N->getMemoryVT();
1872 unsigned Alignment = N->getOriginalAlignment();
1873 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
1874 AAMDNodes AAInfo = N->getAAInfo();
1876 GetSplitVector(N->getOperand(1), Lo, Hi);
1878 EVT LoMemVT, HiMemVT;
1879 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1881 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1884 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
1885 Alignment, MMOFlags, AAInfo);
1887 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
1890 // Increment the pointer to the other half.
1891 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1892 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1895 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1896 N->getPointerInfo().getWithOffset(IncrementSize),
1897 HiMemVT, Alignment, MMOFlags, AAInfo);
1899 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1900 N->getPointerInfo().getWithOffset(IncrementSize),
1901 Alignment, MMOFlags, AAInfo);
1903 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1906 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1909 // The input operands all must have the same type, and we know the result
1910 // type is valid. Convert this to a buildvector which extracts all the
1912 // TODO: If the input elements are power-two vectors, we could convert this to
1913 // a new CONCAT_VECTORS node with elements that are half-wide.
1914 SmallVector<SDValue, 32> Elts;
1915 EVT EltVT = N->getValueType(0).getVectorElementType();
1916 for (const SDValue &Op : N->op_values()) {
1917 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1919 Elts.push_back(DAG.getNode(
1920 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1921 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1925 return DAG.getBuildVector(N->getValueType(0), DL, Elts);
1928 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1929 // The result type is legal, but the input type is illegal. If splitting
1930 // ends up with the result type of each half still being legal, just
1931 // do that. If, however, that would result in an illegal result type,
1932 // we can try to get more clever with power-two vectors. Specifically,
1933 // split the input type, but also widen the result element size, then
1934 // concatenate the halves and truncate again. For example, consider a target
1935 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1936 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1937 // %inlo = v4i32 extract_subvector %in, 0
1938 // %inhi = v4i32 extract_subvector %in, 4
1939 // %lo16 = v4i16 trunc v4i32 %inlo
1940 // %hi16 = v4i16 trunc v4i32 %inhi
1941 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1942 // %res = v8i8 trunc v8i16 %in16
1944 // Without this transform, the original truncate would end up being
1945 // scalarized, which is pretty much always a last resort.
1946 SDValue InVec = N->getOperand(0);
1947 EVT InVT = InVec->getValueType(0);
1948 EVT OutVT = N->getValueType(0);
1949 unsigned NumElements = OutVT.getVectorNumElements();
1950 bool IsFloat = OutVT.isFloatingPoint();
1952 // Widening should have already made sure this is a power-two vector
1953 // if we're trying to split it at all. assert() that's true, just in case.
1954 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1956 unsigned InElementSize = InVT.getScalarSizeInBits();
1957 unsigned OutElementSize = OutVT.getScalarSizeInBits();
1959 // If the input elements are only 1/2 the width of the result elements,
1960 // just use the normal splitting. Our trick only work if there's room
1961 // to split more than once.
1962 if (InElementSize <= OutElementSize * 2)
1963 return SplitVecOp_UnaryOp(N);
1966 // Extract the halves of the input via extract_subvector.
1967 SDValue InLoVec, InHiVec;
1968 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1969 // Truncate them to 1/2 the element size.
1970 EVT HalfElementVT = IsFloat ?
1971 EVT::getFloatingPointVT(InElementSize/2) :
1972 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1973 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1975 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1976 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1977 // Concatenate them to get the full intermediate truncation result.
1978 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1979 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1981 // Now finish up by truncating all the way down to the original result
1982 // type. This should normally be something that ends up being legal directly,
1983 // but in theory if a target has very wide vectors and an annoyingly
1984 // restricted set of legal types, this split can chain to build things up.
1986 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1987 DAG.getTargetConstant(
1988 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1989 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1992 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1993 assert(N->getValueType(0).isVector() &&
1994 N->getOperand(0).getValueType().isVector() &&
1995 "Operand types must be vectors");
1996 // The result has a legal vector type, but the input needs splitting.
1997 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1999 GetSplitVector(N->getOperand(0), Lo0, Hi0);
2000 GetSplitVector(N->getOperand(1), Lo1, Hi1);
2001 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
2002 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
2003 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
2005 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2006 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2007 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2008 return PromoteTargetBoolean(Con, N->getValueType(0));
2012 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2013 // The result has a legal vector type, but the input needs splitting.
2014 EVT ResVT = N->getValueType(0);
2017 GetSplitVector(N->getOperand(0), Lo, Hi);
2018 EVT InVT = Lo.getValueType();
2020 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2021 InVT.getVectorNumElements());
2023 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2024 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2026 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2029 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2030 // The result (and the first input) has a legal vector type, but the second
2031 // input needs splitting.
2032 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2036 //===----------------------------------------------------------------------===//
2037 // Result Vector Widening
2038 //===----------------------------------------------------------------------===//
2040 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2041 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
2045 // See if the target wants to custom widen this node.
2046 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2049 SDValue Res = SDValue();
2050 switch (N->getOpcode()) {
2053 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2057 llvm_unreachable("Do not know how to widen the result of this operator!");
2059 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2060 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2061 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2062 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2063 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2064 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2065 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2066 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2067 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2068 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2070 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2071 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2072 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2073 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2074 case ISD::VECTOR_SHUFFLE:
2075 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2078 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2081 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2100 Res = WidenVecRes_Binary(N);
2113 Res = WidenVecRes_BinaryCanTrap(N);
2116 case ISD::FCOPYSIGN:
2117 Res = WidenVecRes_FCOPYSIGN(N);
2121 Res = WidenVecRes_POWI(N);
2127 Res = WidenVecRes_Shift(N);
2130 case ISD::ANY_EXTEND_VECTOR_INREG:
2131 case ISD::SIGN_EXTEND_VECTOR_INREG:
2132 case ISD::ZERO_EXTEND_VECTOR_INREG:
2133 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2136 case ISD::ANY_EXTEND:
2137 case ISD::FP_EXTEND:
2139 case ISD::FP_TO_SINT:
2140 case ISD::FP_TO_UINT:
2141 case ISD::SIGN_EXTEND:
2142 case ISD::SINT_TO_FP:
2144 case ISD::UINT_TO_FP:
2145 case ISD::ZERO_EXTEND:
2146 Res = WidenVecRes_Convert(N);
2149 case ISD::BITREVERSE:
2163 case ISD::FNEARBYINT:
2170 Res = WidenVecRes_Unary(N);
2173 Res = WidenVecRes_Ternary(N);
2177 // If Res is null, the sub-method took care of registering the result.
2179 SetWidenedVector(SDValue(N, ResNo), Res);
2182 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2183 // Ternary op widening.
2185 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2186 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2187 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2188 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2189 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2192 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2193 // Binary op widening.
2195 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2196 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2197 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2198 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2201 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2202 // Binary op widening for operations that can trap.
2203 unsigned Opcode = N->getOpcode();
2205 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2206 EVT WidenEltVT = WidenVT.getVectorElementType();
2208 unsigned NumElts = VT.getVectorNumElements();
2209 const SDNodeFlags *Flags = N->getFlags();
2210 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2211 NumElts = NumElts / 2;
2212 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2215 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2216 // Operation doesn't trap so just widen as normal.
2217 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2218 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2219 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2222 // No legal vector version so unroll the vector operation and then widen.
2224 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2226 // Since the operation can trap, apply operation on the original vector.
2228 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2229 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2230 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2232 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2233 unsigned ConcatEnd = 0; // Current ConcatOps index.
2234 int Idx = 0; // Current Idx into input vectors.
2236 // NumElts := greatest legal vector size (at most WidenVT)
2237 // while (orig. vector has unhandled elements) {
2238 // take munches of size NumElts from the beginning and add to ConcatOps
2239 // NumElts := next smaller supported vector size or 1
2241 while (CurNumElts != 0) {
2242 while (CurNumElts >= NumElts) {
2243 SDValue EOp1 = DAG.getNode(
2244 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2245 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2246 SDValue EOp2 = DAG.getNode(
2247 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2248 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2249 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2251 CurNumElts -= NumElts;
2254 NumElts = NumElts / 2;
2255 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2256 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2259 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2260 SDValue EOp1 = DAG.getNode(
2261 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2262 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2263 SDValue EOp2 = DAG.getNode(
2264 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2265 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2266 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2273 // Check to see if we have a single operation with the widen type.
2274 if (ConcatEnd == 1) {
2275 VT = ConcatOps[0].getValueType();
2277 return ConcatOps[0];
2280 // while (Some element of ConcatOps is not of type MaxVT) {
2281 // From the end of ConcatOps, collect elements of the same type and put
2282 // them into an op of the next larger supported type
2284 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2285 Idx = ConcatEnd - 1;
2286 VT = ConcatOps[Idx--].getValueType();
2287 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2290 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2294 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2295 } while (!TLI.isTypeLegal(NextVT));
2297 if (!VT.isVector()) {
2298 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2299 SDValue VecOp = DAG.getUNDEF(NextVT);
2300 unsigned NumToInsert = ConcatEnd - Idx - 1;
2301 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2302 VecOp = DAG.getNode(
2303 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2304 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2306 ConcatOps[Idx+1] = VecOp;
2307 ConcatEnd = Idx + 2;
2309 // Vector type, create a CONCAT_VECTORS of type NextVT
2310 SDValue undefVec = DAG.getUNDEF(VT);
2311 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2312 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2313 unsigned RealVals = ConcatEnd - Idx - 1;
2314 unsigned SubConcatEnd = 0;
2315 unsigned SubConcatIdx = Idx + 1;
2316 while (SubConcatEnd < RealVals)
2317 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2318 while (SubConcatEnd < OpsToConcat)
2319 SubConcatOps[SubConcatEnd++] = undefVec;
2320 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2321 NextVT, SubConcatOps);
2322 ConcatEnd = SubConcatIdx + 1;
2326 // Check to see if we have a single operation with the widen type.
2327 if (ConcatEnd == 1) {
2328 VT = ConcatOps[0].getValueType();
2330 return ConcatOps[0];
2333 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2334 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2335 if (NumOps != ConcatEnd ) {
2336 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2337 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2338 ConcatOps[j] = UndefVal;
2340 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2341 makeArrayRef(ConcatOps.data(), NumOps));
2344 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2345 SDValue InOp = N->getOperand(0);
2348 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2349 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2351 EVT InVT = InOp.getValueType();
2352 EVT InEltVT = InVT.getVectorElementType();
2353 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2355 unsigned Opcode = N->getOpcode();
2356 unsigned InVTNumElts = InVT.getVectorNumElements();
2357 const SDNodeFlags *Flags = N->getFlags();
2358 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2359 InOp = GetWidenedVector(N->getOperand(0));
2360 InVT = InOp.getValueType();
2361 InVTNumElts = InVT.getVectorNumElements();
2362 if (InVTNumElts == WidenNumElts) {
2363 if (N->getNumOperands() == 1)
2364 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2365 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2367 if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
2368 // If both input and result vector types are of same width, extend
2369 // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
2370 // accepts fewer elements in the result than in the input.
2371 if (Opcode == ISD::SIGN_EXTEND)
2372 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2373 if (Opcode == ISD::ZERO_EXTEND)
2374 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2378 if (TLI.isTypeLegal(InWidenVT)) {
2379 // Because the result and the input are different vector types, widening
2380 // the result could create a legal type but widening the input might make
2381 // it an illegal type that might lead to repeatedly splitting the input
2382 // and then widening it. To avoid this, we widen the input only if
2383 // it results in a legal type.
2384 if (WidenNumElts % InVTNumElts == 0) {
2385 // Widen the input and call convert on the widened input vector.
2386 unsigned NumConcat = WidenNumElts/InVTNumElts;
2387 SmallVector<SDValue, 16> Ops(NumConcat);
2389 SDValue UndefVal = DAG.getUNDEF(InVT);
2390 for (unsigned i = 1; i != NumConcat; ++i)
2392 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2393 if (N->getNumOperands() == 1)
2394 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2395 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2398 if (InVTNumElts % WidenNumElts == 0) {
2399 SDValue InVal = DAG.getNode(
2400 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2401 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2402 // Extract the input and convert the shorten input vector.
2403 if (N->getNumOperands() == 1)
2404 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2405 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2409 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2410 SmallVector<SDValue, 16> Ops(WidenNumElts);
2411 EVT EltVT = WidenVT.getVectorElementType();
2412 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2414 for (i=0; i < MinElts; ++i) {
2415 SDValue Val = DAG.getNode(
2416 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2417 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2418 if (N->getNumOperands() == 1)
2419 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2421 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2424 SDValue UndefVal = DAG.getUNDEF(EltVT);
2425 for (; i < WidenNumElts; ++i)
2428 return DAG.getBuildVector(WidenVT, DL, Ops);
2431 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2432 unsigned Opcode = N->getOpcode();
2433 SDValue InOp = N->getOperand(0);
2436 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2437 EVT WidenSVT = WidenVT.getVectorElementType();
2438 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2440 EVT InVT = InOp.getValueType();
2441 EVT InSVT = InVT.getVectorElementType();
2442 unsigned InVTNumElts = InVT.getVectorNumElements();
2444 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2445 InOp = GetWidenedVector(InOp);
2446 InVT = InOp.getValueType();
2447 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2449 case ISD::ANY_EXTEND_VECTOR_INREG:
2450 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2451 case ISD::SIGN_EXTEND_VECTOR_INREG:
2452 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2453 case ISD::ZERO_EXTEND_VECTOR_INREG:
2454 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2459 // Unroll, extend the scalars and rebuild the vector.
2460 SmallVector<SDValue, 16> Ops;
2461 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2462 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2463 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2465 case ISD::ANY_EXTEND_VECTOR_INREG:
2466 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2468 case ISD::SIGN_EXTEND_VECTOR_INREG:
2469 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2471 case ISD::ZERO_EXTEND_VECTOR_INREG:
2472 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2475 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
2480 while (Ops.size() != WidenNumElts)
2481 Ops.push_back(DAG.getUNDEF(WidenSVT));
2483 return DAG.getBuildVector(WidenVT, DL, Ops);
2486 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2487 // If this is an FCOPYSIGN with same input types, we can treat it as a
2488 // normal (can trap) binary op.
2489 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2490 return WidenVecRes_BinaryCanTrap(N);
2492 // If the types are different, fall back to unrolling.
2493 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2494 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2497 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2498 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2499 SDValue InOp = GetWidenedVector(N->getOperand(0));
2500 SDValue ShOp = N->getOperand(1);
2501 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2504 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2505 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2506 SDValue InOp = GetWidenedVector(N->getOperand(0));
2507 SDValue ShOp = N->getOperand(1);
2509 EVT ShVT = ShOp.getValueType();
2510 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2511 ShOp = GetWidenedVector(ShOp);
2512 ShVT = ShOp.getValueType();
2514 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2515 ShVT.getVectorElementType(),
2516 WidenVT.getVectorNumElements());
2517 if (ShVT != ShWidenVT)
2518 ShOp = ModifyToType(ShOp, ShWidenVT);
2520 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2523 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2524 // Unary op widening.
2525 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2526 SDValue InOp = GetWidenedVector(N->getOperand(0));
2527 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2530 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2531 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2532 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2533 cast<VTSDNode>(N->getOperand(1))->getVT()
2534 .getVectorElementType(),
2535 WidenVT.getVectorNumElements());
2536 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2537 return DAG.getNode(N->getOpcode(), SDLoc(N),
2538 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2541 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2542 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2543 return GetWidenedVector(WidenVec);
2546 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2547 SDValue InOp = N->getOperand(0);
2548 EVT InVT = InOp.getValueType();
2549 EVT VT = N->getValueType(0);
2550 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2553 switch (getTypeAction(InVT)) {
2554 case TargetLowering::TypeLegal:
2556 case TargetLowering::TypePromoteInteger:
2557 // If the incoming type is a vector that is being promoted, then
2558 // we know that the elements are arranged differently and that we
2559 // must perform the conversion using a stack slot.
2560 if (InVT.isVector())
2563 // If the InOp is promoted to the same size, convert it. Otherwise,
2564 // fall out of the switch and widen the promoted input.
2565 InOp = GetPromotedInteger(InOp);
2566 InVT = InOp.getValueType();
2567 if (WidenVT.bitsEq(InVT))
2568 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2570 case TargetLowering::TypeSoftenFloat:
2571 case TargetLowering::TypePromoteFloat:
2572 case TargetLowering::TypeExpandInteger:
2573 case TargetLowering::TypeExpandFloat:
2574 case TargetLowering::TypeScalarizeVector:
2575 case TargetLowering::TypeSplitVector:
2577 case TargetLowering::TypeWidenVector:
2578 // If the InOp is widened to the same size, convert it. Otherwise, fall
2579 // out of the switch and widen the widened input.
2580 InOp = GetWidenedVector(InOp);
2581 InVT = InOp.getValueType();
2582 if (WidenVT.bitsEq(InVT))
2583 // The input widens to the same size. Convert to the widen value.
2584 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2588 unsigned WidenSize = WidenVT.getSizeInBits();
2589 unsigned InSize = InVT.getSizeInBits();
2590 // x86mmx is not an acceptable vector element type, so don't try.
2591 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2592 // Determine new input vector type. The new input vector type will use
2593 // the same element type (if its a vector) or use the input type as a
2594 // vector. It is the same size as the type to widen to.
2596 unsigned NewNumElts = WidenSize / InSize;
2597 if (InVT.isVector()) {
2598 EVT InEltVT = InVT.getVectorElementType();
2599 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2600 WidenSize / InEltVT.getSizeInBits());
2602 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2605 if (TLI.isTypeLegal(NewInVT)) {
2606 // Because the result and the input are different vector types, widening
2607 // the result could create a legal type but widening the input might make
2608 // it an illegal type that might lead to repeatedly splitting the input
2609 // and then widening it. To avoid this, we widen the input only if
2610 // it results in a legal type.
2611 SmallVector<SDValue, 16> Ops(NewNumElts);
2612 SDValue UndefVal = DAG.getUNDEF(InVT);
2614 for (unsigned i = 1; i < NewNumElts; ++i)
2618 if (InVT.isVector())
2619 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2621 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2622 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2626 return CreateStackStoreLoad(InOp, WidenVT);
2629 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2631 // Build a vector with undefined for the new nodes.
2632 EVT VT = N->getValueType(0);
2634 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2635 // type. The UNDEFs need to have the same type as the existing operands.
2636 EVT EltVT = N->getOperand(0).getValueType();
2637 unsigned NumElts = VT.getVectorNumElements();
2639 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2640 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2642 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2643 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2644 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2646 return DAG.getBuildVector(WidenVT, dl, NewOps);
2649 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2650 EVT InVT = N->getOperand(0).getValueType();
2651 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2653 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2654 unsigned NumInElts = InVT.getVectorNumElements();
2655 unsigned NumOperands = N->getNumOperands();
2657 bool InputWidened = false; // Indicates we need to widen the input.
2658 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2659 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2660 // Add undef vectors to widen to correct length.
2661 unsigned NumConcat = WidenVT.getVectorNumElements() /
2662 InVT.getVectorNumElements();
2663 SDValue UndefVal = DAG.getUNDEF(InVT);
2664 SmallVector<SDValue, 16> Ops(NumConcat);
2665 for (unsigned i=0; i < NumOperands; ++i)
2666 Ops[i] = N->getOperand(i);
2667 for (unsigned i = NumOperands; i != NumConcat; ++i)
2669 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2672 InputWidened = true;
2673 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2674 // The inputs and the result are widen to the same value.
2676 for (i=1; i < NumOperands; ++i)
2677 if (!N->getOperand(i).isUndef())
2680 if (i == NumOperands)
2681 // Everything but the first operand is an UNDEF so just return the
2682 // widened first operand.
2683 return GetWidenedVector(N->getOperand(0));
2685 if (NumOperands == 2) {
2686 // Replace concat of two operands with a shuffle.
2687 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2688 for (unsigned i = 0; i < NumInElts; ++i) {
2690 MaskOps[i + NumInElts] = i + WidenNumElts;
2692 return DAG.getVectorShuffle(WidenVT, dl,
2693 GetWidenedVector(N->getOperand(0)),
2694 GetWidenedVector(N->getOperand(1)),
2700 // Fall back to use extracts and build vector.
2701 EVT EltVT = WidenVT.getVectorElementType();
2702 SmallVector<SDValue, 16> Ops(WidenNumElts);
2704 for (unsigned i=0; i < NumOperands; ++i) {
2705 SDValue InOp = N->getOperand(i);
2707 InOp = GetWidenedVector(InOp);
2708 for (unsigned j=0; j < NumInElts; ++j)
2709 Ops[Idx++] = DAG.getNode(
2710 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2711 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2713 SDValue UndefVal = DAG.getUNDEF(EltVT);
2714 for (; Idx < WidenNumElts; ++Idx)
2715 Ops[Idx] = UndefVal;
2716 return DAG.getBuildVector(WidenVT, dl, Ops);
2719 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2720 EVT VT = N->getValueType(0);
2721 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2722 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2723 SDValue InOp = N->getOperand(0);
2724 SDValue Idx = N->getOperand(1);
2727 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2728 InOp = GetWidenedVector(InOp);
2730 EVT InVT = InOp.getValueType();
2732 // Check if we can just return the input vector after widening.
2733 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2734 if (IdxVal == 0 && InVT == WidenVT)
2737 // Check if we can extract from the vector.
2738 unsigned InNumElts = InVT.getVectorNumElements();
2739 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2740 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2742 // We could try widening the input to the right length but for now, extract
2743 // the original elements, fill the rest with undefs and build a vector.
2744 SmallVector<SDValue, 16> Ops(WidenNumElts);
2745 EVT EltVT = VT.getVectorElementType();
2746 unsigned NumElts = VT.getVectorNumElements();
2748 for (i=0; i < NumElts; ++i)
2750 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2751 DAG.getConstant(IdxVal + i, dl,
2752 TLI.getVectorIdxTy(DAG.getDataLayout())));
2754 SDValue UndefVal = DAG.getUNDEF(EltVT);
2755 for (; i < WidenNumElts; ++i)
2757 return DAG.getBuildVector(WidenVT, dl, Ops);
2760 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2761 SDValue InOp = GetWidenedVector(N->getOperand(0));
2762 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2763 InOp.getValueType(), InOp,
2764 N->getOperand(1), N->getOperand(2));
2767 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2768 LoadSDNode *LD = cast<LoadSDNode>(N);
2769 ISD::LoadExtType ExtType = LD->getExtensionType();
2772 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2773 if (ExtType != ISD::NON_EXTLOAD)
2774 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2776 Result = GenWidenVectorLoads(LdChain, LD);
2778 // If we generate a single load, we can use that for the chain. Otherwise,
2779 // build a factor node to remember the multiple loads are independent and
2782 if (LdChain.size() == 1)
2783 NewChain = LdChain[0];
2785 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2787 // Modified the chain - switch anything that used the old chain to use
2789 ReplaceValueWith(SDValue(N, 1), NewChain);
2794 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2796 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2797 SDValue Mask = N->getMask();
2798 EVT MaskVT = Mask.getValueType();
2799 SDValue Src0 = GetWidenedVector(N->getSrc0());
2800 ISD::LoadExtType ExtType = N->getExtensionType();
2803 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2804 Mask = GetWidenedVector(Mask);
2806 EVT BoolVT = getSetCCResultType(WidenVT);
2808 // We can't use ModifyToType() because we should fill the mask with
2810 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2811 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2813 unsigned NumConcat = WidenNumElts / MaskNumElts;
2814 SmallVector<SDValue, 16> Ops(NumConcat);
2815 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2817 for (unsigned i = 1; i != NumConcat; ++i)
2820 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2823 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2824 Mask, Src0, N->getMemoryVT(),
2825 N->getMemOperand(), ExtType,
2826 N->isExpandingLoad());
2827 // Legalize the chain result - switch anything that used the old chain to
2829 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2833 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
2835 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2836 SDValue Mask = N->getMask();
2837 SDValue Src0 = GetWidenedVector(N->getValue());
2838 unsigned NumElts = WideVT.getVectorNumElements();
2841 // The mask should be widened as well
2842 Mask = WidenTargetBoolean(Mask, WideVT, true);
2844 // Widen the Index operand
2845 SDValue Index = N->getIndex();
2846 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
2847 Index.getValueType().getScalarType(),
2849 Index = ModifyToType(Index, WideIndexVT);
2850 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
2851 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
2852 N->getMemoryVT(), dl, Ops,
2853 N->getMemOperand());
2855 // Legalize the chain result - switch anything that used the old chain to
2857 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2861 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2862 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2864 WidenVT, N->getOperand(0));
2867 // Return true if this is a node that could have two SETCCs as operands.
2868 static inline bool isLogicalMaskOp(unsigned Opcode) {
2878 // This is used just for the assert in convertMask(). Check that this either
2879 // a SETCC or a previously handled SETCC by convertMask().
2881 static inline bool isSETCCorConvertedSETCC(SDValue N) {
2882 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
2883 N = N.getOperand(0);
2884 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
2885 for (unsigned i = 1; i < N->getNumOperands(); ++i)
2886 if (!N->getOperand(i)->isUndef())
2888 N = N.getOperand(0);
2891 if (N.getOpcode() == ISD::TRUNCATE)
2892 N = N.getOperand(0);
2893 else if (N.getOpcode() == ISD::SIGN_EXTEND)
2894 N = N.getOperand(0);
2896 return (N.getOpcode() == ISD::SETCC);
2900 // Return a mask of vector type MaskVT to replace InMask. Also adjust MaskVT
2901 // to ToMaskVT if needed with vector extension or truncation.
2902 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
2904 LLVMContext &Ctx = *DAG.getContext();
2906 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
2907 unsigned InMaskOpc = InMask->getOpcode();
2908 assert((InMaskOpc == ISD::SETCC ||
2909 (isLogicalMaskOp(InMaskOpc) &&
2910 isSETCCorConvertedSETCC(InMask->getOperand(0)) &&
2911 isSETCCorConvertedSETCC(InMask->getOperand(1)))) &&
2912 "Unexpected mask argument.");
2914 // Make a new Mask node, with a legal result VT.
2915 SmallVector<SDValue, 4> Ops;
2916 for (unsigned i = 0; i < InMask->getNumOperands(); ++i)
2917 Ops.push_back(InMask->getOperand(i));
2918 SDValue Mask = DAG.getNode(InMaskOpc, SDLoc(InMask), MaskVT, Ops);
2920 // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
2921 // extend or truncate is needed.
2922 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
2923 unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
2924 if (MaskScalarBits < ToMaskScalBits) {
2925 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
2926 MaskVT.getVectorNumElements());
2927 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
2928 } else if (MaskScalarBits > ToMaskScalBits) {
2929 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
2930 MaskVT.getVectorNumElements());
2931 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask);
2934 assert(Mask->getValueType(0).getScalarSizeInBits() ==
2935 ToMaskVT.getScalarSizeInBits() &&
2936 "Mask should have the right element size by now.");
2938 // Adjust Mask to the right number of elements.
2939 unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
2940 if (CurrMaskNumEls > ToMaskVT.getVectorNumElements()) {
2941 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
2942 SDValue ZeroIdx = DAG.getConstant(0, SDLoc(Mask), IdxTy);
2943 Mask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Mask), ToMaskVT, Mask,
2945 } else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
2946 unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
2947 EVT SubVT = Mask->getValueType(0);
2948 SmallVector<SDValue, 16> SubConcatOps(NumSubVecs);
2949 SubConcatOps[0] = Mask;
2950 for (unsigned i = 1; i < NumSubVecs; ++i)
2951 SubConcatOps[i] = DAG.getUNDEF(SubVT);
2953 DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubConcatOps);
2956 assert((Mask->getValueType(0) == ToMaskVT) &&
2957 "A mask of ToMaskVT should have been produced by now.");
2962 // Get the target mask VT, and widen if needed.
2963 EVT DAGTypeLegalizer::getSETCCWidenedResultTy(SDValue SetCC) {
2964 assert(SetCC->getOpcode() == ISD::SETCC);
2965 LLVMContext &Ctx = *DAG.getContext();
2966 EVT MaskVT = getSetCCResultType(SetCC->getOperand(0).getValueType());
2967 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2968 MaskVT = TLI.getTypeToTransformTo(Ctx, MaskVT);
2972 // This method tries to handle VSELECT and its mask by legalizing operands
2973 // (which may require widening) and if needed adjusting the mask vector type
2974 // to match that of the VSELECT. Without it, many cases end up with
2975 // scalarization of the SETCC, with many unnecessary instructions.
2976 SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
2977 LLVMContext &Ctx = *DAG.getContext();
2978 SDValue Cond = N->getOperand(0);
2980 if (N->getOpcode() != ISD::VSELECT)
2983 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
2986 // If this is a splitted VSELECT that was previously already handled, do
2988 if (Cond->getValueType(0).getScalarSizeInBits() != 1)
2991 EVT VSelVT = N->getValueType(0);
2992 // Only handle vector types which are a power of 2.
2993 if (!isPowerOf2_64(VSelVT.getSizeInBits()))
2996 // Don't touch if this will be scalarized.
2997 EVT FinalVT = VSelVT;
2998 while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
2999 FinalVT = EVT::getVectorVT(Ctx, FinalVT.getVectorElementType(),
3000 FinalVT.getVectorNumElements() / 2);
3001 if (FinalVT.getVectorNumElements() == 1)
3004 // If there is support for an i1 vector mask, don't touch.
3005 if (Cond.getOpcode() == ISD::SETCC) {
3006 EVT SetCCOpVT = Cond->getOperand(0).getValueType();
3007 while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
3008 SetCCOpVT = TLI.getTypeToTransformTo(Ctx, SetCCOpVT);
3009 EVT SetCCResVT = getSetCCResultType(SetCCOpVT);
3010 if (SetCCResVT.getScalarSizeInBits() == 1)
3014 // Get the VT and operands for VSELECT, and widen if needed.
3015 SDValue VSelOp1 = N->getOperand(1);
3016 SDValue VSelOp2 = N->getOperand(2);
3017 if (getTypeAction(VSelVT) == TargetLowering::TypeWidenVector) {
3018 VSelVT = TLI.getTypeToTransformTo(Ctx, VSelVT);
3019 VSelOp1 = GetWidenedVector(VSelOp1);
3020 VSelOp2 = GetWidenedVector(VSelOp2);
3023 // The mask of the VSELECT should have integer elements.
3024 EVT ToMaskVT = VSelVT;
3025 if (!ToMaskVT.getScalarType().isInteger())
3026 ToMaskVT = ToMaskVT.changeVectorElementTypeToInteger();
3029 if (Cond->getOpcode() == ISD::SETCC) {
3030 EVT MaskVT = getSETCCWidenedResultTy(Cond);
3031 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3032 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3033 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3034 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3035 // Cond is (AND/OR/XOR (SETCC, SETCC))
3036 SDValue SETCC0 = Cond->getOperand(0);
3037 SDValue SETCC1 = Cond->getOperand(1);
3038 EVT VT0 = getSETCCWidenedResultTy(SETCC0);
3039 EVT VT1 = getSETCCWidenedResultTy(SETCC1);
3040 unsigned ScalarBits0 = VT0.getScalarSizeInBits();
3041 unsigned ScalarBits1 = VT1.getScalarSizeInBits();
3042 unsigned ScalarBits_ToMask = ToMaskVT.getScalarSizeInBits();
3044 // If the two SETCCs have different VTs, either extend/truncate one of
3045 // them to the other "towards" ToMaskVT, or truncate one and extend the
3046 // other to ToMaskVT.
3047 if (ScalarBits0 != ScalarBits1) {
3048 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1);
3049 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
3050 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
3052 else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits())
3057 // If the two SETCCs have the same VT, don't change it.
3060 // Make new SETCCs and logical nodes.
3061 SETCC0 = convertMask(SETCC0, VT0, MaskVT);
3062 SETCC1 = convertMask(SETCC1, VT1, MaskVT);
3063 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
3065 // Convert the logical op for VSELECT if needed.
3066 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3070 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
3073 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
3074 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3075 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3077 SDValue Cond1 = N->getOperand(0);
3078 EVT CondVT = Cond1.getValueType();
3079 if (CondVT.isVector()) {
3080 if (SDValue Res = WidenVSELECTAndMask(N))
3083 EVT CondEltVT = CondVT.getVectorElementType();
3084 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
3085 CondEltVT, WidenNumElts);
3086 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
3087 Cond1 = GetWidenedVector(Cond1);
3089 // If we have to split the condition there is no point in widening the
3090 // select. This would result in an cycle of widening the select ->
3091 // widening the condition operand -> splitting the condition operand ->
3092 // splitting the select -> widening the select. Instead split this select
3093 // further and widen the resulting type.
3094 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
3095 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
3096 SDValue Res = ModifyToType(SplitSelect, WidenVT);
3100 if (Cond1.getValueType() != CondWidenVT)
3101 Cond1 = ModifyToType(Cond1, CondWidenVT);
3104 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3105 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
3106 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
3107 return DAG.getNode(N->getOpcode(), SDLoc(N),
3108 WidenVT, Cond1, InOp1, InOp2);
3111 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
3112 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
3113 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
3114 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
3115 InOp1.getValueType(), N->getOperand(0),
3116 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
3119 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
3120 assert(N->getValueType(0).isVector() ==
3121 N->getOperand(0).getValueType().isVector() &&
3122 "Scalar/Vector type mismatch");
3123 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
3125 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3126 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3127 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3128 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
3129 InOp1, InOp2, N->getOperand(2));
3132 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
3133 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3134 return DAG.getUNDEF(WidenVT);
3137 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
3138 EVT VT = N->getValueType(0);
3141 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3142 unsigned NumElts = VT.getVectorNumElements();
3143 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3145 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3146 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3148 // Adjust mask based on new input vector length.
3149 SmallVector<int, 16> NewMask;
3150 for (unsigned i = 0; i != NumElts; ++i) {
3151 int Idx = N->getMaskElt(i);
3152 if (Idx < (int)NumElts)
3153 NewMask.push_back(Idx);
3155 NewMask.push_back(Idx - NumElts + WidenNumElts);
3157 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3158 NewMask.push_back(-1);
3159 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3162 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
3163 assert(N->getValueType(0).isVector() &&
3164 N->getOperand(0).getValueType().isVector() &&
3165 "Operands must be vectors");
3166 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3167 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3169 SDValue InOp1 = N->getOperand(0);
3170 EVT InVT = InOp1.getValueType();
3171 assert(InVT.isVector() && "can not widen non-vector type");
3172 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3173 InVT.getVectorElementType(), WidenNumElts);
3175 // The input and output types often differ here, and it could be that while
3176 // we'd prefer to widen the result type, the input operands have been split.
3177 // In this case, we also need to split the result of this node as well.
3178 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3179 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3180 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3184 InOp1 = GetWidenedVector(InOp1);
3185 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3187 // Assume that the input and output will be widen appropriately. If not,
3188 // we will have to unroll it at some point.
3189 assert(InOp1.getValueType() == WidenInVT &&
3190 InOp2.getValueType() == WidenInVT &&
3191 "Input not widened to expected type!");
3193 return DAG.getNode(ISD::SETCC, SDLoc(N),
3194 WidenVT, InOp1, InOp2, N->getOperand(2));
3198 //===----------------------------------------------------------------------===//
3199 // Widen Vector Operand
3200 //===----------------------------------------------------------------------===//
3201 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3202 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
3205 SDValue Res = SDValue();
3207 // See if the target wants to custom widen this node.
3208 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3211 switch (N->getOpcode()) {
3214 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3218 llvm_unreachable("Do not know how to widen this operator's operand!");
3220 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3221 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3222 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3223 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3224 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3225 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
3226 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3227 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3228 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3230 case ISD::ANY_EXTEND:
3231 case ISD::SIGN_EXTEND:
3232 case ISD::ZERO_EXTEND:
3233 Res = WidenVecOp_EXTEND(N);
3236 case ISD::FP_EXTEND:
3237 case ISD::FP_TO_SINT:
3238 case ISD::FP_TO_UINT:
3239 case ISD::SINT_TO_FP:
3240 case ISD::UINT_TO_FP:
3242 Res = WidenVecOp_Convert(N);
3246 // If Res is null, the sub-method took care of registering the result.
3247 if (!Res.getNode()) return false;
3249 // If the result is N, the sub-method updated N in place. Tell the legalizer
3251 if (Res.getNode() == N)
3255 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3256 "Invalid operand expansion");
3258 ReplaceValueWith(SDValue(N, 0), Res);
3262 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3264 EVT VT = N->getValueType(0);
3266 SDValue InOp = N->getOperand(0);
3267 // If some legalization strategy other than widening is used on the operand,
3268 // we can't safely assume that just extending the low lanes is the correct
3270 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
3271 return WidenVecOp_Convert(N);
3272 InOp = GetWidenedVector(InOp);
3273 assert(VT.getVectorNumElements() <
3274 InOp.getValueType().getVectorNumElements() &&
3275 "Input wasn't widened!");
3277 // We may need to further widen the operand until it has the same total
3278 // vector size as the result.
3279 EVT InVT = InOp.getValueType();
3280 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3281 EVT InEltVT = InVT.getVectorElementType();
3282 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3283 EVT FixedVT = (MVT::SimpleValueType)i;
3284 EVT FixedEltVT = FixedVT.getVectorElementType();
3285 if (TLI.isTypeLegal(FixedVT) &&
3286 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3287 FixedEltVT == InEltVT) {
3288 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
3289 "Not enough elements in the fixed type for the operand!");
3290 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
3291 "We can't have the same type as we started with!");
3292 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3294 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3295 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3298 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3299 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3303 InVT = InOp.getValueType();
3304 if (InVT.getSizeInBits() != VT.getSizeInBits())
3305 // We couldn't find a legal vector type that was a widening of the input
3306 // and could be extended in-register to the result type, so we have to
3308 return WidenVecOp_Convert(N);
3311 // Use special DAG nodes to represent the operation of extending the
3313 switch (N->getOpcode()) {
3315 llvm_unreachable("Extend legalization on on extend operation!");
3316 case ISD::ANY_EXTEND:
3317 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3318 case ISD::SIGN_EXTEND:
3319 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3320 case ISD::ZERO_EXTEND:
3321 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3325 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3326 // The result (and first input) is legal, but the second input is illegal.
3327 // We can't do much to fix that, so just unroll and let the extracts off of
3328 // the second input be widened as needed later.
3329 return DAG.UnrollVectorOp(N);
3332 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3333 // Since the result is legal and the input is illegal, it is unlikely that we
3334 // can fix the input to a legal type so unroll the convert into some scalar
3335 // code and create a nasty build vector.
3336 EVT VT = N->getValueType(0);
3337 EVT EltVT = VT.getVectorElementType();
3339 unsigned NumElts = VT.getVectorNumElements();
3340 SDValue InOp = N->getOperand(0);
3341 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3342 InOp = GetWidenedVector(InOp);
3343 EVT InVT = InOp.getValueType();
3344 EVT InEltVT = InVT.getVectorElementType();
3346 unsigned Opcode = N->getOpcode();
3347 SmallVector<SDValue, 16> Ops(NumElts);
3348 for (unsigned i=0; i < NumElts; ++i)
3349 Ops[i] = DAG.getNode(
3352 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3353 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3355 return DAG.getBuildVector(VT, dl, Ops);
3358 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3359 EVT VT = N->getValueType(0);
3360 SDValue InOp = GetWidenedVector(N->getOperand(0));
3361 EVT InWidenVT = InOp.getValueType();
3364 // Check if we can convert between two legal vector types and extract.
3365 unsigned InWidenSize = InWidenVT.getSizeInBits();
3366 unsigned Size = VT.getSizeInBits();
3367 // x86mmx is not an acceptable vector element type, so don't try.
3368 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3369 unsigned NewNumElts = InWidenSize / Size;
3370 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3371 if (TLI.isTypeLegal(NewVT)) {
3372 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3374 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3375 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3379 return CreateStackStoreLoad(InOp, VT);
3382 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3383 // If the input vector is not legal, it is likely that we will not find a
3384 // legal vector of the same size. Replace the concatenate vector with a
3385 // nasty build vector.
3386 EVT VT = N->getValueType(0);
3387 EVT EltVT = VT.getVectorElementType();
3389 unsigned NumElts = VT.getVectorNumElements();
3390 SmallVector<SDValue, 16> Ops(NumElts);
3392 EVT InVT = N->getOperand(0).getValueType();
3393 unsigned NumInElts = InVT.getVectorNumElements();
3396 unsigned NumOperands = N->getNumOperands();
3397 for (unsigned i=0; i < NumOperands; ++i) {
3398 SDValue InOp = N->getOperand(i);
3399 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3400 InOp = GetWidenedVector(InOp);
3401 for (unsigned j=0; j < NumInElts; ++j)
3402 Ops[Idx++] = DAG.getNode(
3403 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3404 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3406 return DAG.getBuildVector(VT, dl, Ops);
3409 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3410 SDValue InOp = GetWidenedVector(N->getOperand(0));
3411 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3412 N->getValueType(0), InOp, N->getOperand(1));
3415 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3416 SDValue InOp = GetWidenedVector(N->getOperand(0));
3417 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3418 N->getValueType(0), InOp, N->getOperand(1));
3421 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3422 // We have to widen the value, but we want only to store the original
3424 StoreSDNode *ST = cast<StoreSDNode>(N);
3426 SmallVector<SDValue, 16> StChain;
3427 if (ST->isTruncatingStore())
3428 GenWidenVectorTruncStores(StChain, ST);
3430 GenWidenVectorStores(StChain, ST);
3432 if (StChain.size() == 1)
3435 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3438 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3439 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3440 SDValue Mask = MST->getMask();
3441 EVT MaskVT = Mask.getValueType();
3442 SDValue StVal = MST->getValue();
3444 SDValue WideVal = GetWidenedVector(StVal);
3447 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3448 Mask = GetWidenedVector(Mask);
3450 // The mask should be widened as well.
3451 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3452 // We can't use ModifyToType() because we should fill the mask with
3454 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3455 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3457 unsigned NumConcat = WidenNumElts / MaskNumElts;
3458 SmallVector<SDValue, 16> Ops(NumConcat);
3459 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3461 for (unsigned i = 1; i != NumConcat; ++i)
3464 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3466 assert(Mask.getValueType().getVectorNumElements() ==
3467 WideVal.getValueType().getVectorNumElements() &&
3468 "Mask and data vectors should have the same number of elements");
3469 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3470 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3471 false, MST->isCompressingStore());
3474 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3475 assert(OpNo == 1 && "Can widen only data operand of mscatter");
3476 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3477 SDValue DataOp = MSC->getValue();
3478 SDValue Mask = MSC->getMask();
3481 SDValue WideVal = GetWidenedVector(DataOp);
3482 EVT WideVT = WideVal.getValueType();
3483 unsigned NumElts = WideVal.getValueType().getVectorNumElements();
3486 // The mask should be widened as well.
3487 Mask = WidenTargetBoolean(Mask, WideVT, true);
3490 SDValue Index = MSC->getIndex();
3491 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3492 Index.getValueType().getScalarType(),
3494 Index = ModifyToType(Index, WideIndexVT);
3496 SDValue Ops[] = {MSC->getChain(), WideVal, Mask, MSC->getBasePtr(), Index};
3497 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3498 MSC->getMemoryVT(), dl, Ops,
3499 MSC->getMemOperand());
3502 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3503 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3504 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3507 // WARNING: In this code we widen the compare instruction with garbage.
3508 // This garbage may contain denormal floats which may be slow. Is this a real
3509 // concern ? Should we zero the unused lanes if this is a float compare ?
3511 // Get a new SETCC node to compare the newly widened operands.
3512 // Only some of the compared elements are legal.
3513 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3514 InOp0.getValueType());
3515 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3516 SVT, InOp0, InOp1, N->getOperand(2));
3518 // Extract the needed results from the result vector.
3519 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3520 SVT.getVectorElementType(),
3521 N->getValueType(0).getVectorNumElements());
3522 SDValue CC = DAG.getNode(
3523 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3524 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3526 return PromoteTargetBoolean(CC, N->getValueType(0));
3530 //===----------------------------------------------------------------------===//
3531 // Vector Widening Utilities
3532 //===----------------------------------------------------------------------===//
3534 // Utility function to find the type to chop up a widen vector for load/store
3535 // TLI: Target lowering used to determine legal types.
3536 // Width: Width left need to load/store.
3537 // WidenVT: The widen vector type to load to/store from
3538 // Align: If 0, don't allow use of a wider type
3539 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3541 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3542 unsigned Width, EVT WidenVT,
3543 unsigned Align = 0, unsigned WidenEx = 0) {
3544 EVT WidenEltVT = WidenVT.getVectorElementType();
3545 unsigned WidenWidth = WidenVT.getSizeInBits();
3546 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3547 unsigned AlignInBits = Align*8;
3549 // If we have one element to load/store, return it.
3550 EVT RetVT = WidenEltVT;
3551 if (Width == WidenEltWidth)
3554 // See if there is larger legal integer than the element type to load/store.
3556 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3557 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3558 EVT MemVT((MVT::SimpleValueType) VT);
3559 unsigned MemVTWidth = MemVT.getSizeInBits();
3560 if (MemVT.getSizeInBits() <= WidenEltWidth)
3562 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3563 if ((Action == TargetLowering::TypeLegal ||
3564 Action == TargetLowering::TypePromoteInteger) &&
3565 (WidenWidth % MemVTWidth) == 0 &&
3566 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3567 (MemVTWidth <= Width ||
3568 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3574 // See if there is a larger vector type to load/store that has the same vector
3575 // element type and is evenly divisible with the WidenVT.
3576 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3577 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3578 EVT MemVT = (MVT::SimpleValueType) VT;
3579 unsigned MemVTWidth = MemVT.getSizeInBits();
3580 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3581 (WidenWidth % MemVTWidth) == 0 &&
3582 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3583 (MemVTWidth <= Width ||
3584 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3585 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3593 // Builds a vector type from scalar loads
3594 // VecTy: Resulting Vector type
3595 // LDOps: Load operators to build a vector type
3596 // [Start,End) the list of loads to use.
3597 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3598 SmallVectorImpl<SDValue> &LdOps,
3599 unsigned Start, unsigned End) {
3600 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3601 SDLoc dl(LdOps[Start]);
3602 EVT LdTy = LdOps[Start].getValueType();
3603 unsigned Width = VecTy.getSizeInBits();
3604 unsigned NumElts = Width / LdTy.getSizeInBits();
3605 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3608 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3610 for (unsigned i = Start + 1; i != End; ++i) {
3611 EVT NewLdTy = LdOps[i].getValueType();
3612 if (NewLdTy != LdTy) {
3613 NumElts = Width / NewLdTy.getSizeInBits();
3614 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3615 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3616 // Readjust position and vector position based on new load type.
3617 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3620 VecOp = DAG.getNode(
3621 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3622 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3624 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3627 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3629 // The strategy assumes that we can efficiently load power-of-two widths.
3630 // The routine chops the vector into the largest vector loads with the same
3631 // element type or scalar loads and then recombines it to the widen vector
3633 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3634 unsigned WidenWidth = WidenVT.getSizeInBits();
3635 EVT LdVT = LD->getMemoryVT();
3637 assert(LdVT.isVector() && WidenVT.isVector());
3638 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3641 SDValue Chain = LD->getChain();
3642 SDValue BasePtr = LD->getBasePtr();
3643 unsigned Align = LD->getAlignment();
3644 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3645 AAMDNodes AAInfo = LD->getAAInfo();
3647 int LdWidth = LdVT.getSizeInBits();
3648 int WidthDiff = WidenWidth - LdWidth;
3649 unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
3651 // Find the vector type that can load from.
3652 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3653 int NewVTWidth = NewVT.getSizeInBits();
3654 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3655 Align, MMOFlags, AAInfo);
3656 LdChain.push_back(LdOp.getValue(1));
3658 // Check if we can load the element with one instruction.
3659 if (LdWidth <= NewVTWidth) {
3660 if (!NewVT.isVector()) {
3661 unsigned NumElts = WidenWidth / NewVTWidth;
3662 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3663 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3664 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3666 if (NewVT == WidenVT)
3669 assert(WidenWidth % NewVTWidth == 0);
3670 unsigned NumConcat = WidenWidth / NewVTWidth;
3671 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3672 SDValue UndefVal = DAG.getUNDEF(NewVT);
3673 ConcatOps[0] = LdOp;
3674 for (unsigned i = 1; i != NumConcat; ++i)
3675 ConcatOps[i] = UndefVal;
3676 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3679 // Load vector by using multiple loads from largest vector to scalar.
3680 SmallVector<SDValue, 16> LdOps;
3681 LdOps.push_back(LdOp);
3683 LdWidth -= NewVTWidth;
3684 unsigned Offset = 0;
3686 while (LdWidth > 0) {
3687 unsigned Increment = NewVTWidth / 8;
3688 Offset += Increment;
3689 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3690 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3693 if (LdWidth < NewVTWidth) {
3694 // The current type we are using is too large. Find a better size.
3695 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3696 NewVTWidth = NewVT.getSizeInBits();
3697 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3698 LD->getPointerInfo().getWithOffset(Offset),
3699 MinAlign(Align, Increment), MMOFlags, AAInfo);
3700 LdChain.push_back(L.getValue(1));
3701 if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
3702 // Later code assumes the vector loads produced will be mergeable, so we
3703 // must pad the final entry up to the previous width. Scalars are
3704 // combined separately.
3705 SmallVector<SDValue, 16> Loads;
3707 unsigned size = L->getValueSizeInBits(0);
3708 while (size < LdOp->getValueSizeInBits(0)) {
3709 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3710 size += L->getValueSizeInBits(0);
3712 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3715 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3716 LD->getPointerInfo().getWithOffset(Offset),
3717 MinAlign(Align, Increment), MMOFlags, AAInfo);
3718 LdChain.push_back(L.getValue(1));
3724 LdWidth -= NewVTWidth;
3727 // Build the vector from the load operations.
3728 unsigned End = LdOps.size();
3729 if (!LdOps[0].getValueType().isVector())
3730 // All the loads are scalar loads.
3731 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3733 // If the load contains vectors, build the vector using concat vector.
3734 // All of the vectors used to load are power-of-2, and the scalar loads can be
3735 // combined to make a power-of-2 vector.
3736 SmallVector<SDValue, 16> ConcatOps(End);
3739 EVT LdTy = LdOps[i].getValueType();
3740 // First, combine the scalar loads to a vector.
3741 if (!LdTy.isVector()) {
3742 for (--i; i >= 0; --i) {
3743 LdTy = LdOps[i].getValueType();
3744 if (LdTy.isVector())
3747 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
3749 ConcatOps[--Idx] = LdOps[i];
3750 for (--i; i >= 0; --i) {
3751 EVT NewLdTy = LdOps[i].getValueType();
3752 if (NewLdTy != LdTy) {
3753 // Create a larger vector.
3754 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3755 makeArrayRef(&ConcatOps[Idx], End - Idx));
3759 ConcatOps[--Idx] = LdOps[i];
3762 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
3763 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3764 makeArrayRef(&ConcatOps[Idx], End - Idx));
3766 // We need to fill the rest with undefs to build the vector.
3767 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3768 SmallVector<SDValue, 16> WidenOps(NumOps);
3769 SDValue UndefVal = DAG.getUNDEF(LdTy);
3772 for (; i != End-Idx; ++i)
3773 WidenOps[i] = ConcatOps[Idx+i];
3774 for (; i != NumOps; ++i)
3775 WidenOps[i] = UndefVal;
3777 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3781 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3783 ISD::LoadExtType ExtType) {
3784 // For extension loads, it may not be more efficient to chop up the vector
3785 // and then extend it. Instead, we unroll the load and build a new vector.
3786 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3787 EVT LdVT = LD->getMemoryVT();
3789 assert(LdVT.isVector() && WidenVT.isVector());
3792 SDValue Chain = LD->getChain();
3793 SDValue BasePtr = LD->getBasePtr();
3794 unsigned Align = LD->getAlignment();
3795 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3796 AAMDNodes AAInfo = LD->getAAInfo();
3798 EVT EltVT = WidenVT.getVectorElementType();
3799 EVT LdEltVT = LdVT.getVectorElementType();
3800 unsigned NumElts = LdVT.getVectorNumElements();
3802 // Load each element and widen.
3803 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3804 SmallVector<SDValue, 16> Ops(WidenNumElts);
3805 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3807 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
3808 LdEltVT, Align, MMOFlags, AAInfo);
3809 LdChain.push_back(Ops[0].getValue(1));
3810 unsigned i = 0, Offset = Increment;
3811 for (i=1; i < NumElts; ++i, Offset += Increment) {
3812 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3814 DAG.getConstant(Offset, dl,
3815 BasePtr.getValueType()));
3816 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3817 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3818 Align, MMOFlags, AAInfo);
3819 LdChain.push_back(Ops[i].getValue(1));
3822 // Fill the rest with undefs.
3823 SDValue UndefVal = DAG.getUNDEF(EltVT);
3824 for (; i != WidenNumElts; ++i)
3827 return DAG.getBuildVector(WidenVT, dl, Ops);
3830 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3832 // The strategy assumes that we can efficiently store power-of-two widths.
3833 // The routine chops the vector into the largest vector stores with the same
3834 // element type or scalar stores.
3835 SDValue Chain = ST->getChain();
3836 SDValue BasePtr = ST->getBasePtr();
3837 unsigned Align = ST->getAlignment();
3838 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3839 AAMDNodes AAInfo = ST->getAAInfo();
3840 SDValue ValOp = GetWidenedVector(ST->getValue());
3843 EVT StVT = ST->getMemoryVT();
3844 unsigned StWidth = StVT.getSizeInBits();
3845 EVT ValVT = ValOp.getValueType();
3846 unsigned ValWidth = ValVT.getSizeInBits();
3847 EVT ValEltVT = ValVT.getVectorElementType();
3848 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3849 assert(StVT.getVectorElementType() == ValEltVT);
3851 int Idx = 0; // current index to store
3852 unsigned Offset = 0; // offset from base to store
3853 while (StWidth != 0) {
3854 // Find the largest vector type we can store with.
3855 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3856 unsigned NewVTWidth = NewVT.getSizeInBits();
3857 unsigned Increment = NewVTWidth / 8;
3858 if (NewVT.isVector()) {
3859 unsigned NumVTElts = NewVT.getVectorNumElements();
3861 SDValue EOp = DAG.getNode(
3862 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3863 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3864 StChain.push_back(DAG.getStore(
3865 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3866 MinAlign(Align, Offset), MMOFlags, AAInfo));
3867 StWidth -= NewVTWidth;
3868 Offset += Increment;
3870 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3871 DAG.getConstant(Increment, dl,
3872 BasePtr.getValueType()));
3873 } while (StWidth != 0 && StWidth >= NewVTWidth);
3875 // Cast the vector to the scalar type we can store.
3876 unsigned NumElts = ValWidth / NewVTWidth;
3877 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3878 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3879 // Readjust index position based on new vector type.
3880 Idx = Idx * ValEltWidth / NewVTWidth;
3882 SDValue EOp = DAG.getNode(
3883 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3884 DAG.getConstant(Idx++, dl,
3885 TLI.getVectorIdxTy(DAG.getDataLayout())));
3886 StChain.push_back(DAG.getStore(
3887 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3888 MinAlign(Align, Offset), MMOFlags, AAInfo));
3889 StWidth -= NewVTWidth;
3890 Offset += Increment;
3891 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3892 DAG.getConstant(Increment, dl,
3893 BasePtr.getValueType()));
3894 } while (StWidth != 0 && StWidth >= NewVTWidth);
3895 // Restore index back to be relative to the original widen element type.
3896 Idx = Idx * NewVTWidth / ValEltWidth;
3902 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3904 // For extension loads, it may not be more efficient to truncate the vector
3905 // and then store it. Instead, we extract each element and then store it.
3906 SDValue Chain = ST->getChain();
3907 SDValue BasePtr = ST->getBasePtr();
3908 unsigned Align = ST->getAlignment();
3909 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3910 AAMDNodes AAInfo = ST->getAAInfo();
3911 SDValue ValOp = GetWidenedVector(ST->getValue());
3914 EVT StVT = ST->getMemoryVT();
3915 EVT ValVT = ValOp.getValueType();
3917 // It must be true that the wide vector type is bigger than where we need to
3919 assert(StVT.isVector() && ValOp.getValueType().isVector());
3920 assert(StVT.bitsLT(ValOp.getValueType()));
3922 // For truncating stores, we can not play the tricks of chopping legal vector
3923 // types and bitcast it to the right type. Instead, we unroll the store.
3924 EVT StEltVT = StVT.getVectorElementType();
3925 EVT ValEltVT = ValVT.getVectorElementType();
3926 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3927 unsigned NumElts = StVT.getVectorNumElements();
3928 SDValue EOp = DAG.getNode(
3929 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3930 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3931 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3932 ST->getPointerInfo(), StEltVT, Align,
3934 unsigned Offset = Increment;
3935 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3936 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3938 DAG.getConstant(Offset, dl,
3939 BasePtr.getValueType()));
3940 SDValue EOp = DAG.getNode(
3941 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3942 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3943 StChain.push_back(DAG.getTruncStore(
3944 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
3945 StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
3949 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3950 /// input vector must have the same element type as NVT.
3951 /// FillWithZeroes specifies that the vector should be widened with zeroes.
3952 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
3953 bool FillWithZeroes) {
3954 // Note that InOp might have been widened so it might already have
3955 // the right width or it might need be narrowed.
3956 EVT InVT = InOp.getValueType();
3957 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3958 "input and widen element type must match");
3961 // Check if InOp already has the right width.
3965 unsigned InNumElts = InVT.getVectorNumElements();
3966 unsigned WidenNumElts = NVT.getVectorNumElements();
3967 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3968 unsigned NumConcat = WidenNumElts / InNumElts;
3969 SmallVector<SDValue, 16> Ops(NumConcat);
3970 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
3973 for (unsigned i = 1; i != NumConcat; ++i)
3976 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3979 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3981 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3982 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3984 // Fall back to extract and build.
3985 SmallVector<SDValue, 16> Ops(WidenNumElts);
3986 EVT EltVT = NVT.getVectorElementType();
3987 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3989 for (Idx = 0; Idx < MinNumElts; ++Idx)
3990 Ops[Idx] = DAG.getNode(
3991 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3992 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3994 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
3995 DAG.getUNDEF(EltVT);
3996 for ( ; Idx < WidenNumElts; ++Idx)
3998 return DAG.getBuildVector(NVT, dl, Ops);