1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
73 case ISD::CTLZ_ZERO_UNDEF:
76 case ISD::CTTZ_ZERO_UNDEF:
96 case ISD::SIGN_EXTEND:
100 case ISD::ZERO_EXTEND:
101 R = ScalarizeVecRes_UnaryOp(N);
133 R = ScalarizeVecRes_BinOp(N);
136 R = ScalarizeVecRes_TernaryOp(N);
140 // If R is null, the sub-method took care of registering the result.
142 SetScalarizedVector(SDValue(N, ResNo), R);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
146 SDValue LHS = GetScalarizedVector(N->getOperand(0));
147 SDValue RHS = GetScalarizedVector(N->getOperand(1));
148 return DAG.getNode(N->getOpcode(), SDLoc(N),
149 LHS.getValueType(), LHS, RHS, N->getFlags());
152 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
153 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
154 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
155 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
156 return DAG.getNode(N->getOpcode(), SDLoc(N),
157 Op0.getValueType(), Op0, Op1, Op2);
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
162 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
163 return GetScalarizedVector(Op);
166 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
167 EVT NewVT = N->getValueType(0).getVectorElementType();
168 return DAG.getNode(ISD::BITCAST, SDLoc(N),
169 NewVT, N->getOperand(0));
172 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
173 EVT EltVT = N->getValueType(0).getVectorElementType();
174 SDValue InOp = N->getOperand(0);
175 // The BUILD_VECTOR operands may be of wider element types and
176 // we may need to truncate them back to the requested return type.
177 if (EltVT.isInteger())
178 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
183 EVT NewVT = N->getValueType(0).getVectorElementType();
184 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
185 return DAG.getConvertRndSat(NewVT, SDLoc(N),
186 Op0, DAG.getValueType(NewVT),
187 DAG.getValueType(Op0.getValueType()),
190 cast<CvtRndSatSDNode>(N)->getCvtCode());
193 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
194 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
195 N->getValueType(0).getVectorElementType(),
196 N->getOperand(0), N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
200 EVT NewVT = N->getValueType(0).getVectorElementType();
201 SDValue Op = GetScalarizedVector(N->getOperand(0));
202 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
203 NewVT, Op, N->getOperand(1));
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
207 SDValue Op = GetScalarizedVector(N->getOperand(0));
208 return DAG.getNode(ISD::FPOWI, SDLoc(N),
209 Op.getValueType(), Op, N->getOperand(1));
212 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
213 // The value to insert may have a wider type than the vector element type,
214 // so be sure to truncate it to the element type if necessary.
215 SDValue Op = N->getOperand(1);
216 EVT EltVT = N->getValueType(0).getVectorElementType();
217 if (Op.getValueType() != EltVT)
218 // FIXME: Can this happen for floating point types?
219 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
224 assert(N->isUnindexed() && "Indexed vector load?");
226 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
227 N->getExtensionType(),
228 N->getValueType(0).getVectorElementType(),
230 N->getChain(), N->getBasePtr(),
231 DAG.getUNDEF(N->getBasePtr().getValueType()),
233 N->getMemoryVT().getVectorElementType(),
234 N->isVolatile(), N->isNonTemporal(),
235 N->isInvariant(), N->getOriginalAlignment(),
238 // Legalize the chain result - switch anything that used the old chain to
240 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
244 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
245 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
246 EVT DestVT = N->getValueType(0).getVectorElementType();
247 SDValue Op = N->getOperand(0);
248 EVT OpVT = Op.getValueType();
250 // The result needs scalarizing, but it's not a given that the source does.
251 // This is a workaround for targets where it's impossible to scalarize the
252 // result of a conversion, because the source type is legal.
253 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
254 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
255 // legal and was not scalarized.
256 // See the similar logic in ScalarizeVecRes_VSETCC
257 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
258 Op = GetScalarizedVector(Op);
260 EVT VT = OpVT.getVectorElementType();
262 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
263 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
265 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
269 EVT EltVT = N->getValueType(0).getVectorElementType();
270 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
271 SDValue LHS = GetScalarizedVector(N->getOperand(0));
272 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
273 LHS, DAG.getValueType(ExtVT));
276 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
277 // If the operand is wider than the vector element type then it is implicitly
278 // truncated. Make that explicit here.
279 EVT EltVT = N->getValueType(0).getVectorElementType();
280 SDValue InOp = N->getOperand(0);
281 if (InOp.getValueType() != EltVT)
282 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
286 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
287 SDValue Cond = GetScalarizedVector(N->getOperand(0));
288 SDValue LHS = GetScalarizedVector(N->getOperand(1));
289 TargetLowering::BooleanContent ScalarBool =
290 TLI.getBooleanContents(false, false);
291 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
293 // If integer and float booleans have different contents then we can't
294 // reliably optimize in all cases. There is a full explanation for this in
295 // DAGCombiner::visitSELECT() where the same issue affects folding
296 // (select C, 0, 1) to (xor C, 1).
297 if (TLI.getBooleanContents(false, false) !=
298 TLI.getBooleanContents(false, true)) {
299 // At least try the common case where the boolean is generated by a
301 if (Cond->getOpcode() == ISD::SETCC) {
302 EVT OpVT = Cond->getOperand(0)->getValueType(0);
303 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
304 VecBool = TLI.getBooleanContents(OpVT);
306 ScalarBool = TargetLowering::UndefinedBooleanContent;
309 if (ScalarBool != VecBool) {
310 EVT CondVT = Cond.getValueType();
311 switch (ScalarBool) {
312 case TargetLowering::UndefinedBooleanContent:
314 case TargetLowering::ZeroOrOneBooleanContent:
315 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
316 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
317 // Vector read from all ones, scalar expects a single 1 so mask.
318 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
319 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
321 case TargetLowering::ZeroOrNegativeOneBooleanContent:
322 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
323 VecBool == TargetLowering::ZeroOrOneBooleanContent);
324 // Vector reads from a one, scalar from all ones so sign extend.
325 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
326 Cond, DAG.getValueType(MVT::i1));
331 return DAG.getSelect(SDLoc(N),
332 LHS.getValueType(), Cond, LHS,
333 GetScalarizedVector(N->getOperand(2)));
336 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
337 SDValue LHS = GetScalarizedVector(N->getOperand(1));
338 return DAG.getSelect(SDLoc(N),
339 LHS.getValueType(), N->getOperand(0), LHS,
340 GetScalarizedVector(N->getOperand(2)));
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
344 SDValue LHS = GetScalarizedVector(N->getOperand(2));
345 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
346 N->getOperand(0), N->getOperand(1),
347 LHS, GetScalarizedVector(N->getOperand(3)),
351 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
352 assert(N->getValueType(0).isVector() ==
353 N->getOperand(0).getValueType().isVector() &&
354 "Scalar/Vector type mismatch");
356 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
358 SDValue LHS = GetScalarizedVector(N->getOperand(0));
359 SDValue RHS = GetScalarizedVector(N->getOperand(1));
362 // Turn it into a scalar SETCC.
363 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
366 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
367 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
370 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
371 // Figure out if the scalar is the LHS or RHS and return it.
372 SDValue Arg = N->getOperand(2).getOperand(0);
374 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
375 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
376 return GetScalarizedVector(N->getOperand(Op));
379 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
380 assert(N->getValueType(0).isVector() &&
381 N->getOperand(0).getValueType().isVector() &&
382 "Operand types must be vectors");
383 SDValue LHS = N->getOperand(0);
384 SDValue RHS = N->getOperand(1);
385 EVT OpVT = LHS.getValueType();
386 EVT NVT = N->getValueType(0).getVectorElementType();
389 // The result needs scalarizing, but it's not a given that the source does.
390 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
391 LHS = GetScalarizedVector(LHS);
392 RHS = GetScalarizedVector(RHS);
394 EVT VT = OpVT.getVectorElementType();
396 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
397 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
399 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
400 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
403 // Turn it into a scalar SETCC.
404 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
406 // Vectors may have a different boolean contents to scalars. Promote the
407 // value appropriately.
408 ISD::NodeType ExtendCode =
409 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
410 return DAG.getNode(ExtendCode, DL, NVT, Res);
414 //===----------------------------------------------------------------------===//
415 // Operand Vector Scalarization <1 x ty> -> ty.
416 //===----------------------------------------------------------------------===//
418 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
419 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
422 SDValue Res = SDValue();
424 if (!Res.getNode()) {
425 switch (N->getOpcode()) {
428 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
432 llvm_unreachable("Do not know how to scalarize this operator's operand!");
434 Res = ScalarizeVecOp_BITCAST(N);
436 case ISD::ANY_EXTEND:
437 case ISD::ZERO_EXTEND:
438 case ISD::SIGN_EXTEND:
440 case ISD::FP_TO_SINT:
441 case ISD::FP_TO_UINT:
442 case ISD::SINT_TO_FP:
443 case ISD::UINT_TO_FP:
444 Res = ScalarizeVecOp_UnaryOp(N);
446 case ISD::CONCAT_VECTORS:
447 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
449 case ISD::EXTRACT_VECTOR_ELT:
450 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
453 Res = ScalarizeVecOp_VSELECT(N);
456 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
459 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
464 // If the result is null, the sub-method took care of registering results etc.
465 if (!Res.getNode()) return false;
467 // If the result is N, the sub-method updated N in place. Tell the legalizer
469 if (Res.getNode() == N)
472 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
473 "Invalid operand expansion");
475 ReplaceValueWith(SDValue(N, 0), Res);
479 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
480 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
481 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 return DAG.getNode(ISD::BITCAST, SDLoc(N),
484 N->getValueType(0), Elt);
487 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
488 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
489 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
490 assert(N->getValueType(0).getVectorNumElements() == 1 &&
491 "Unexpected vector type!");
492 SDValue Elt = GetScalarizedVector(N->getOperand(0));
493 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
494 N->getValueType(0).getScalarType(), Elt);
495 // Revectorize the result so the types line up with what the uses of this
496 // expression expect.
497 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
500 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
501 /// use a BUILD_VECTOR instead.
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
503 SmallVector<SDValue, 8> Ops(N->getNumOperands());
504 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
505 Ops[i] = GetScalarizedVector(N->getOperand(i));
506 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
509 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
510 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
512 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
513 SDValue Res = GetScalarizedVector(N->getOperand(0));
514 if (Res.getValueType() != N->getValueType(0))
515 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
521 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
522 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
523 /// (still with vector output type since that was acceptable if we got here).
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
525 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
526 EVT VT = N->getValueType(0);
528 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
532 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
533 /// scalarized, it must be <1 x ty>. Just store the element.
534 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
535 assert(N->isUnindexed() && "Indexed store of one-element vector?");
536 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
539 if (N->isTruncatingStore())
540 return DAG.getTruncStore(N->getChain(), dl,
541 GetScalarizedVector(N->getOperand(1)),
542 N->getBasePtr(), N->getPointerInfo(),
543 N->getMemoryVT().getVectorElementType(),
544 N->isVolatile(), N->isNonTemporal(),
545 N->getAlignment(), N->getAAInfo());
547 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
548 N->getBasePtr(), N->getPointerInfo(),
549 N->isVolatile(), N->isNonTemporal(),
550 N->getOriginalAlignment(), N->getAAInfo());
553 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
554 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
555 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
556 SDValue Elt = GetScalarizedVector(N->getOperand(0));
557 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
558 N->getValueType(0).getVectorElementType(), Elt,
560 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
563 //===----------------------------------------------------------------------===//
564 // Result Vector Splitting
565 //===----------------------------------------------------------------------===//
567 /// SplitVectorResult - This method is called when the specified result of the
568 /// specified node is found to need vector splitting. At this point, the node
569 /// may also have invalid operands or may have other results that need
570 /// legalization, we just know that (at least) one result needs vector
572 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
573 DEBUG(dbgs() << "Split node result: ";
578 // See if the target wants to custom expand this node.
579 if (CustomLowerNode(N, N->getValueType(ResNo), true))
582 switch (N->getOpcode()) {
585 dbgs() << "SplitVectorResult #" << ResNo << ": ";
589 report_fatal_error("Do not know how to split the result of this "
592 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
594 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
595 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
596 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
597 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
598 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
599 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
600 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
601 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
602 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
603 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
604 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
605 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
606 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
607 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
609 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
612 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
615 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
618 SplitVecRes_SETCC(N, Lo, Hi);
620 case ISD::VECTOR_SHUFFLE:
621 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
624 case ISD::ANY_EXTEND_VECTOR_INREG:
625 case ISD::SIGN_EXTEND_VECTOR_INREG:
626 case ISD::ZERO_EXTEND_VECTOR_INREG:
627 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
630 case ISD::BITREVERSE:
632 case ISD::CONVERT_RNDSAT:
635 case ISD::CTLZ_ZERO_UNDEF:
636 case ISD::CTTZ_ZERO_UNDEF:
647 case ISD::FNEARBYINT:
651 case ISD::FP_TO_SINT:
652 case ISD::FP_TO_UINT:
658 case ISD::SINT_TO_FP:
660 case ISD::UINT_TO_FP:
661 SplitVecRes_UnaryOp(N, Lo, Hi);
664 case ISD::ANY_EXTEND:
665 case ISD::SIGN_EXTEND:
666 case ISD::ZERO_EXTEND:
667 SplitVecRes_ExtendOp(N, Lo, Hi);
697 SplitVecRes_BinOp(N, Lo, Hi);
700 SplitVecRes_TernaryOp(N, Lo, Hi);
704 // If Lo/Hi is null, the sub-method took care of registering results etc.
706 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
709 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
711 SDValue LHSLo, LHSHi;
712 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
713 SDValue RHSLo, RHSHi;
714 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
717 const SDNodeFlags *Flags = N->getFlags();
718 unsigned Opcode = N->getOpcode();
719 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
720 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
723 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
725 SDValue Op0Lo, Op0Hi;
726 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
727 SDValue Op1Lo, Op1Hi;
728 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
729 SDValue Op2Lo, Op2Hi;
730 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
733 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
734 Op0Lo, Op1Lo, Op2Lo);
735 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
736 Op0Hi, Op1Hi, Op2Hi);
739 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
741 // We know the result is a vector. The input may be either a vector or a
744 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
747 SDValue InOp = N->getOperand(0);
748 EVT InVT = InOp.getValueType();
750 // Handle some special cases efficiently.
751 switch (getTypeAction(InVT)) {
752 case TargetLowering::TypeLegal:
753 case TargetLowering::TypePromoteInteger:
754 case TargetLowering::TypePromoteFloat:
755 case TargetLowering::TypeSoftenFloat:
756 case TargetLowering::TypeScalarizeVector:
757 case TargetLowering::TypeWidenVector:
759 case TargetLowering::TypeExpandInteger:
760 case TargetLowering::TypeExpandFloat:
761 // A scalar to vector conversion, where the scalar needs expansion.
762 // If the vector is being split in two then we can just convert the
765 GetExpandedOp(InOp, Lo, Hi);
766 if (DAG.getDataLayout().isBigEndian())
768 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
769 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
773 case TargetLowering::TypeSplitVector:
774 // If the input is a vector that needs to be split, convert each split
775 // piece of the input now.
776 GetSplitVector(InOp, Lo, Hi);
777 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
778 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
782 // In the general case, convert the input to an integer and split it by hand.
783 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
784 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
785 if (DAG.getDataLayout().isBigEndian())
786 std::swap(LoIntVT, HiIntVT);
788 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
790 if (DAG.getDataLayout().isBigEndian())
792 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
793 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
796 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
800 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
801 unsigned LoNumElts = LoVT.getVectorNumElements();
802 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
803 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
805 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
806 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
809 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
811 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
813 unsigned NumSubvectors = N->getNumOperands() / 2;
814 if (NumSubvectors == 1) {
815 Lo = N->getOperand(0);
816 Hi = N->getOperand(1);
821 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
823 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
824 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
826 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
827 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
830 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
832 SDValue Vec = N->getOperand(0);
833 SDValue Idx = N->getOperand(1);
837 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
839 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
840 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
841 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
842 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
843 TLI.getVectorIdxTy(DAG.getDataLayout())));
846 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
848 SDValue Vec = N->getOperand(0);
849 SDValue SubVec = N->getOperand(1);
850 SDValue Idx = N->getOperand(2);
852 GetSplitVector(Vec, Lo, Hi);
854 // Spill the vector to the stack.
855 EVT VecVT = Vec.getValueType();
856 EVT SubVecVT = VecVT.getVectorElementType();
857 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
858 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
859 MachinePointerInfo(), false, false, 0);
861 // Store the new subvector into the specified index.
862 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
863 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
864 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
865 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
868 // Load the Lo part from the stack slot.
869 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
870 false, false, false, 0);
872 // Increment the pointer to the other part.
873 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
875 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
876 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
878 // Load the Hi part from the stack slot.
879 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
880 false, false, false, MinAlign(Alignment, IncrementSize));
883 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
886 GetSplitVector(N->getOperand(0), Lo, Hi);
887 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
888 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
891 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
893 SDValue LHSLo, LHSHi;
894 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
897 SDValue RHSLo, RHSHi;
898 SDValue RHS = N->getOperand(1);
899 EVT RHSVT = RHS.getValueType();
900 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
901 GetSplitVector(RHS, RHSLo, RHSHi);
903 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
906 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
907 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
910 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
912 SDValue LHSLo, LHSHi;
913 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
917 std::tie(LoVT, HiVT) =
918 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
920 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
921 DAG.getValueType(LoVT));
922 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
923 DAG.getValueType(HiVT));
926 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
928 unsigned Opcode = N->getOpcode();
929 SDValue N0 = N->getOperand(0);
933 GetSplitVector(N0, InLo, InHi);
934 EVT InLoVT = InLo.getValueType();
935 unsigned InNumElements = InLoVT.getVectorNumElements();
937 EVT OutLoVT, OutHiVT;
938 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
939 unsigned OutNumElements = OutLoVT.getVectorNumElements();
940 assert((2 * OutNumElements) <= InNumElements &&
941 "Illegal extend vector in reg split");
943 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
944 // input vector (i.e. we only use InLo):
945 // OutLo will extend the first OutNumElements from InLo.
946 // OutHi will extend the next OutNumElements from InLo.
948 // Shuffle the elements from InLo for OutHi into the bottom elements to
949 // create a 'fake' InHi.
950 SmallVector<int, 8> SplitHi(InNumElements, -1);
951 for (unsigned i = 0; i != OutNumElements; ++i)
952 SplitHi[i] = i + OutNumElements;
953 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
955 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
956 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
959 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
961 SDValue Vec = N->getOperand(0);
962 SDValue Elt = N->getOperand(1);
963 SDValue Idx = N->getOperand(2);
965 GetSplitVector(Vec, Lo, Hi);
967 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
968 unsigned IdxVal = CIdx->getZExtValue();
969 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
970 if (IdxVal < LoNumElts)
971 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
972 Lo.getValueType(), Lo, Elt, Idx);
975 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
976 DAG.getConstant(IdxVal - LoNumElts, dl,
977 TLI.getVectorIdxTy(DAG.getDataLayout())));
981 // See if the target wants to custom expand this node.
982 if (CustomLowerNode(N, N->getValueType(0), true))
985 // Spill the vector to the stack.
986 EVT VecVT = Vec.getValueType();
987 EVT EltVT = VecVT.getVectorElementType();
988 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
989 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
990 MachinePointerInfo(), false, false, 0);
992 // Store the new element. This may be larger than the vector element type,
993 // so use a truncating store.
994 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
995 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
996 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
997 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
1000 // Load the Lo part from the stack slot.
1001 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1002 false, false, false, 0);
1004 // Increment the pointer to the other part.
1005 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
1006 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1007 DAG.getConstant(IncrementSize, dl,
1008 StackPtr.getValueType()));
1010 // Load the Hi part from the stack slot.
1011 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1012 false, false, false, MinAlign(Alignment, IncrementSize));
1015 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1019 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1020 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1021 Hi = DAG.getUNDEF(HiVT);
1024 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1026 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1029 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1031 ISD::LoadExtType ExtType = LD->getExtensionType();
1032 SDValue Ch = LD->getChain();
1033 SDValue Ptr = LD->getBasePtr();
1034 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1035 EVT MemoryVT = LD->getMemoryVT();
1036 unsigned Alignment = LD->getOriginalAlignment();
1037 bool isVolatile = LD->isVolatile();
1038 bool isNonTemporal = LD->isNonTemporal();
1039 bool isInvariant = LD->isInvariant();
1040 AAMDNodes AAInfo = LD->getAAInfo();
1042 EVT LoMemVT, HiMemVT;
1043 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1045 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1046 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
1047 isInvariant, Alignment, AAInfo);
1049 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1050 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1051 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1052 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1053 LD->getPointerInfo().getWithOffset(IncrementSize),
1054 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
1057 // Build a factor node to remember that this load is independent of the
1059 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1062 // Legalize the chain result - switch anything that used the old chain to
1064 ReplaceValueWith(SDValue(LD, 1), Ch);
1067 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1068 SDValue &Lo, SDValue &Hi) {
1071 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1073 SDValue Ch = MLD->getChain();
1074 SDValue Ptr = MLD->getBasePtr();
1075 SDValue Mask = MLD->getMask();
1076 SDValue Src0 = MLD->getSrc0();
1077 unsigned Alignment = MLD->getOriginalAlignment();
1078 ISD::LoadExtType ExtType = MLD->getExtensionType();
1080 // if Alignment is equal to the vector size,
1081 // take the half of it for the second part
1082 unsigned SecondHalfAlignment =
1083 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1084 Alignment/2 : Alignment;
1086 // Split Mask operand
1087 SDValue MaskLo, MaskHi;
1088 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1089 GetSplitVector(Mask, MaskLo, MaskHi);
1091 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1093 EVT MemoryVT = MLD->getMemoryVT();
1094 EVT LoMemVT, HiMemVT;
1095 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1097 SDValue Src0Lo, Src0Hi;
1098 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1099 GetSplitVector(Src0, Src0Lo, Src0Hi);
1101 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1103 MachineMemOperand *MMO = DAG.getMachineFunction().
1104 getMachineMemOperand(MLD->getPointerInfo(),
1105 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1106 Alignment, MLD->getAAInfo(), MLD->getRanges());
1108 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1111 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1112 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1113 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1115 MMO = DAG.getMachineFunction().
1116 getMachineMemOperand(MLD->getPointerInfo(),
1117 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1118 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1120 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1124 // Build a factor node to remember that this load is independent of the
1126 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1129 // Legalize the chain result - switch anything that used the old chain to
1131 ReplaceValueWith(SDValue(MLD, 1), Ch);
1135 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1136 SDValue &Lo, SDValue &Hi) {
1139 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1141 SDValue Ch = MGT->getChain();
1142 SDValue Ptr = MGT->getBasePtr();
1143 SDValue Mask = MGT->getMask();
1144 SDValue Src0 = MGT->getValue();
1145 SDValue Index = MGT->getIndex();
1146 unsigned Alignment = MGT->getOriginalAlignment();
1148 // Split Mask operand
1149 SDValue MaskLo, MaskHi;
1150 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1151 GetSplitVector(Mask, MaskLo, MaskHi);
1153 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1155 EVT MemoryVT = MGT->getMemoryVT();
1156 EVT LoMemVT, HiMemVT;
1158 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1160 SDValue Src0Lo, Src0Hi;
1161 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1162 GetSplitVector(Src0, Src0Lo, Src0Hi);
1164 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1166 SDValue IndexHi, IndexLo;
1167 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1168 GetSplitVector(Index, IndexLo, IndexHi);
1170 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1172 MachineMemOperand *MMO = DAG.getMachineFunction().
1173 getMachineMemOperand(MGT->getPointerInfo(),
1174 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1175 Alignment, MGT->getAAInfo(), MGT->getRanges());
1177 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1178 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1181 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1182 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1185 // Build a factor node to remember that this load is independent of the
1187 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1190 // Legalize the chain result - switch anything that used the old chain to
1192 ReplaceValueWith(SDValue(MGT, 1), Ch);
1196 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1197 assert(N->getValueType(0).isVector() &&
1198 N->getOperand(0).getValueType().isVector() &&
1199 "Operand types must be vectors");
1203 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1206 SDValue LL, LH, RL, RH;
1207 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1208 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1210 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1211 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1214 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1216 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1219 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1221 // If the input also splits, handle it directly for a compile time speedup.
1222 // Otherwise split it by hand.
1223 EVT InVT = N->getOperand(0).getValueType();
1224 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1225 GetSplitVector(N->getOperand(0), Lo, Hi);
1227 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1229 if (N->getOpcode() == ISD::FP_ROUND) {
1230 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1231 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1232 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1233 SDValue DTyOpLo = DAG.getValueType(LoVT);
1234 SDValue DTyOpHi = DAG.getValueType(HiVT);
1235 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1236 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1237 SDValue RndOp = N->getOperand(3);
1238 SDValue SatOp = N->getOperand(4);
1239 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1240 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1242 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1245 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1246 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1250 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1253 EVT SrcVT = N->getOperand(0).getValueType();
1254 EVT DestVT = N->getValueType(0);
1256 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1258 // We can do better than a generic split operation if the extend is doing
1259 // more than just doubling the width of the elements and the following are
1261 // - The number of vector elements is even,
1262 // - the source type is legal,
1263 // - the type of a split source is illegal,
1264 // - the type of an extended (by doubling element size) source is legal, and
1265 // - the type of that extended source when split is legal.
1267 // This won't necessarily completely legalize the operation, but it will
1268 // more effectively move in the right direction and prevent falling down
1269 // to scalarization in many cases due to the input vector being split too
1271 unsigned NumElements = SrcVT.getVectorNumElements();
1272 if ((NumElements & 1) == 0 &&
1273 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1274 LLVMContext &Ctx = *DAG.getContext();
1275 EVT NewSrcVT = EVT::getVectorVT(
1276 Ctx, EVT::getIntegerVT(
1277 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1280 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1281 EVT SplitLoVT, SplitHiVT;
1282 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1283 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1284 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1285 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1286 N->dump(&DAG); dbgs() << "\n");
1287 // Extend the source vector by one step.
1289 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1290 // Get the low and high halves of the new, extended one step, vector.
1291 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1292 // Extend those vector halves the rest of the way.
1293 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1294 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1298 // Fall back to the generic unary operator splitting otherwise.
1299 SplitVecRes_UnaryOp(N, Lo, Hi);
1302 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1303 SDValue &Lo, SDValue &Hi) {
1304 // The low and high parts of the original input give four input vectors.
1307 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1308 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1309 EVT NewVT = Inputs[0].getValueType();
1310 unsigned NewElts = NewVT.getVectorNumElements();
1312 // If Lo or Hi uses elements from at most two of the four input vectors, then
1313 // express it as a vector shuffle of those two inputs. Otherwise extract the
1314 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1315 SmallVector<int, 16> Ops;
1316 for (unsigned High = 0; High < 2; ++High) {
1317 SDValue &Output = High ? Hi : Lo;
1319 // Build a shuffle mask for the output, discovering on the fly which
1320 // input vectors to use as shuffle operands (recorded in InputUsed).
1321 // If building a suitable shuffle vector proves too hard, then bail
1322 // out with useBuildVector set.
1323 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1324 unsigned FirstMaskIdx = High * NewElts;
1325 bool useBuildVector = false;
1326 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1327 // The mask element. This indexes into the input.
1328 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1330 // The input vector this mask element indexes into.
1331 unsigned Input = (unsigned)Idx / NewElts;
1333 if (Input >= array_lengthof(Inputs)) {
1334 // The mask element does not index into any input vector.
1339 // Turn the index into an offset from the start of the input vector.
1340 Idx -= Input * NewElts;
1342 // Find or create a shuffle vector operand to hold this input.
1344 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1345 if (InputUsed[OpNo] == Input) {
1346 // This input vector is already an operand.
1348 } else if (InputUsed[OpNo] == -1U) {
1349 // Create a new operand for this input vector.
1350 InputUsed[OpNo] = Input;
1355 if (OpNo >= array_lengthof(InputUsed)) {
1356 // More than two input vectors used! Give up on trying to create a
1357 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1358 useBuildVector = true;
1362 // Add the mask index for the new shuffle vector.
1363 Ops.push_back(Idx + OpNo * NewElts);
1366 if (useBuildVector) {
1367 EVT EltVT = NewVT.getVectorElementType();
1368 SmallVector<SDValue, 16> SVOps;
1370 // Extract the input elements by hand.
1371 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1372 // The mask element. This indexes into the input.
1373 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1375 // The input vector this mask element indexes into.
1376 unsigned Input = (unsigned)Idx / NewElts;
1378 if (Input >= array_lengthof(Inputs)) {
1379 // The mask element is "undef" or indexes off the end of the input.
1380 SVOps.push_back(DAG.getUNDEF(EltVT));
1384 // Turn the index into an offset from the start of the input vector.
1385 Idx -= Input * NewElts;
1387 // Extract the vector element by hand.
1388 SVOps.push_back(DAG.getNode(
1389 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1390 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1393 // Construct the Lo/Hi output using a BUILD_VECTOR.
1394 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1395 } else if (InputUsed[0] == -1U) {
1396 // No input vectors were used! The result is undefined.
1397 Output = DAG.getUNDEF(NewVT);
1399 SDValue Op0 = Inputs[InputUsed[0]];
1400 // If only one input was used, use an undefined vector for the other.
1401 SDValue Op1 = InputUsed[1] == -1U ?
1402 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1403 // At least one input vector was used. Create a new shuffle vector.
1404 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1412 //===----------------------------------------------------------------------===//
1413 // Operand Vector Splitting
1414 //===----------------------------------------------------------------------===//
1416 /// SplitVectorOperand - This method is called when the specified operand of the
1417 /// specified node is found to need vector splitting. At this point, all of the
1418 /// result types of the node are known to be legal, but other operands of the
1419 /// node may need legalization as well as the specified one.
1420 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1421 DEBUG(dbgs() << "Split node operand: ";
1424 SDValue Res = SDValue();
1426 // See if the target wants to custom split this node.
1427 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1430 if (!Res.getNode()) {
1431 switch (N->getOpcode()) {
1434 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1438 report_fatal_error("Do not know how to split this operator's "
1441 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1442 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1443 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1444 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1445 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1447 Res = SplitVecOp_TruncateHelper(N);
1449 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1450 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1452 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1455 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1458 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1461 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1464 Res = SplitVecOp_VSELECT(N, OpNo);
1466 case ISD::FP_TO_SINT:
1467 case ISD::FP_TO_UINT:
1468 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1469 Res = SplitVecOp_TruncateHelper(N);
1471 Res = SplitVecOp_UnaryOp(N);
1473 case ISD::SINT_TO_FP:
1474 case ISD::UINT_TO_FP:
1475 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1476 Res = SplitVecOp_TruncateHelper(N);
1478 Res = SplitVecOp_UnaryOp(N);
1483 case ISD::FP_EXTEND:
1484 case ISD::SIGN_EXTEND:
1485 case ISD::ZERO_EXTEND:
1486 case ISD::ANY_EXTEND:
1488 Res = SplitVecOp_UnaryOp(N);
1493 // If the result is null, the sub-method took care of registering results etc.
1494 if (!Res.getNode()) return false;
1496 // If the result is N, the sub-method updated N in place. Tell the legalizer
1498 if (Res.getNode() == N)
1501 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1502 "Invalid operand expansion");
1504 ReplaceValueWith(SDValue(N, 0), Res);
1508 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1509 // The only possibility for an illegal operand is the mask, since result type
1510 // legalization would have handled this node already otherwise.
1511 assert(OpNo == 0 && "Illegal operand must be mask");
1513 SDValue Mask = N->getOperand(0);
1514 SDValue Src0 = N->getOperand(1);
1515 SDValue Src1 = N->getOperand(2);
1516 EVT Src0VT = Src0.getValueType();
1518 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1521 GetSplitVector(N->getOperand(0), Lo, Hi);
1522 assert(Lo.getValueType() == Hi.getValueType() &&
1523 "Lo and Hi have differing types");
1526 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1527 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1529 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1530 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1531 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1532 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1535 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1537 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1539 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1542 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1543 // The result has a legal vector type, but the input needs splitting.
1544 EVT ResVT = N->getValueType(0);
1547 GetSplitVector(N->getOperand(0), Lo, Hi);
1548 EVT InVT = Lo.getValueType();
1550 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1551 InVT.getVectorNumElements());
1553 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1554 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1556 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1559 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1560 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1561 // end up being split all the way down to individual components. Convert the
1562 // split pieces into integers and reassemble.
1564 GetSplitVector(N->getOperand(0), Lo, Hi);
1565 Lo = BitConvertToInteger(Lo);
1566 Hi = BitConvertToInteger(Hi);
1568 if (DAG.getDataLayout().isBigEndian())
1571 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1572 JoinIntegers(Lo, Hi));
1575 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1576 // We know that the extracted result type is legal.
1577 EVT SubVT = N->getValueType(0);
1578 SDValue Idx = N->getOperand(1);
1581 GetSplitVector(N->getOperand(0), Lo, Hi);
1583 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1584 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1586 if (IdxVal < LoElts) {
1587 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1588 "Extracted subvector crosses vector split!");
1589 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1591 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1592 DAG.getConstant(IdxVal - LoElts, dl,
1593 Idx.getValueType()));
1597 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1598 SDValue Vec = N->getOperand(0);
1599 SDValue Idx = N->getOperand(1);
1600 EVT VecVT = Vec.getValueType();
1602 if (isa<ConstantSDNode>(Idx)) {
1603 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1604 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1607 GetSplitVector(Vec, Lo, Hi);
1609 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1611 if (IdxVal < LoElts)
1612 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1613 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1614 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1615 Idx.getValueType())), 0);
1618 // See if the target wants to custom expand this node.
1619 if (CustomLowerNode(N, N->getValueType(0), true))
1622 // Make the vector elements byte-addressable if they aren't already.
1624 EVT EltVT = VecVT.getVectorElementType();
1625 if (EltVT.getSizeInBits() < 8) {
1626 SmallVector<SDValue, 4> ElementOps;
1627 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1628 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1629 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1630 DAG.getConstant(i, dl, MVT::i8)),
1635 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1636 VecVT.getVectorNumElements());
1637 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
1640 // Store the vector to the stack.
1641 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1642 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1643 MachinePointerInfo(), false, false, 0);
1645 // Load back the required element.
1646 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1647 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1648 MachinePointerInfo(), EltVT, false, false, false, 0);
1651 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1655 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1657 SDValue Ch = MGT->getChain();
1658 SDValue Ptr = MGT->getBasePtr();
1659 SDValue Index = MGT->getIndex();
1660 SDValue Mask = MGT->getMask();
1661 SDValue Src0 = MGT->getValue();
1662 unsigned Alignment = MGT->getOriginalAlignment();
1664 SDValue MaskLo, MaskHi;
1665 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1666 // Split Mask operand
1667 GetSplitVector(Mask, MaskLo, MaskHi);
1669 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1671 EVT MemoryVT = MGT->getMemoryVT();
1672 EVT LoMemVT, HiMemVT;
1673 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1675 SDValue Src0Lo, Src0Hi;
1676 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1677 GetSplitVector(Src0, Src0Lo, Src0Hi);
1679 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1681 SDValue IndexHi, IndexLo;
1682 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1683 GetSplitVector(Index, IndexLo, IndexHi);
1685 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1687 MachineMemOperand *MMO = DAG.getMachineFunction().
1688 getMachineMemOperand(MGT->getPointerInfo(),
1689 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1690 Alignment, MGT->getAAInfo(), MGT->getRanges());
1692 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1693 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1696 MMO = DAG.getMachineFunction().
1697 getMachineMemOperand(MGT->getPointerInfo(),
1698 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1699 Alignment, MGT->getAAInfo(),
1702 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1703 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1706 // Build a factor node to remember that this load is independent of the
1708 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1711 // Legalize the chain result - switch anything that used the old chain to
1713 ReplaceValueWith(SDValue(MGT, 1), Ch);
1715 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1717 ReplaceValueWith(SDValue(MGT, 0), Res);
1721 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1723 SDValue Ch = N->getChain();
1724 SDValue Ptr = N->getBasePtr();
1725 SDValue Mask = N->getMask();
1726 SDValue Data = N->getValue();
1727 EVT MemoryVT = N->getMemoryVT();
1728 unsigned Alignment = N->getOriginalAlignment();
1731 EVT LoMemVT, HiMemVT;
1732 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1734 SDValue DataLo, DataHi;
1735 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1736 // Split Data operand
1737 GetSplitVector(Data, DataLo, DataHi);
1739 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1741 SDValue MaskLo, MaskHi;
1742 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1743 // Split Mask operand
1744 GetSplitVector(Mask, MaskLo, MaskHi);
1746 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1748 MaskLo = PromoteTargetBoolean(MaskLo, DataLo.getValueType());
1749 MaskHi = PromoteTargetBoolean(MaskHi, DataHi.getValueType());
1751 // if Alignment is equal to the vector size,
1752 // take the half of it for the second part
1753 unsigned SecondHalfAlignment =
1754 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1755 Alignment/2 : Alignment;
1758 MachineMemOperand *MMO = DAG.getMachineFunction().
1759 getMachineMemOperand(N->getPointerInfo(),
1760 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1761 Alignment, N->getAAInfo(), N->getRanges());
1763 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1764 N->isTruncatingStore());
1766 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1767 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1768 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1770 MMO = DAG.getMachineFunction().
1771 getMachineMemOperand(N->getPointerInfo(),
1772 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1773 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1775 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1776 N->isTruncatingStore());
1778 // Build a factor node to remember that this store is independent of the
1780 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1783 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1785 SDValue Ch = N->getChain();
1786 SDValue Ptr = N->getBasePtr();
1787 SDValue Mask = N->getMask();
1788 SDValue Index = N->getIndex();
1789 SDValue Data = N->getValue();
1790 EVT MemoryVT = N->getMemoryVT();
1791 unsigned Alignment = N->getOriginalAlignment();
1794 // Split all operands
1795 EVT LoMemVT, HiMemVT;
1796 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1798 SDValue DataLo, DataHi;
1799 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1800 // Split Data operand
1801 GetSplitVector(Data, DataLo, DataHi);
1803 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1805 SDValue MaskLo, MaskHi;
1806 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1807 // Split Mask operand
1808 GetSplitVector(Mask, MaskLo, MaskHi);
1810 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1812 SDValue IndexHi, IndexLo;
1813 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1814 GetSplitVector(Index, IndexLo, IndexHi);
1816 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1819 MachineMemOperand *MMO = DAG.getMachineFunction().
1820 getMachineMemOperand(N->getPointerInfo(),
1821 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1822 Alignment, N->getAAInfo(), N->getRanges());
1824 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo};
1825 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1828 MMO = DAG.getMachineFunction().
1829 getMachineMemOperand(N->getPointerInfo(),
1830 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1831 Alignment, N->getAAInfo(), N->getRanges());
1833 SDValue OpsHi[] = {Ch, DataHi, MaskHi, Ptr, IndexHi};
1834 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1837 // Build a factor node to remember that this store is independent of the
1839 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1842 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1843 assert(N->isUnindexed() && "Indexed store of vector?");
1844 assert(OpNo == 1 && "Can only split the stored value");
1847 bool isTruncating = N->isTruncatingStore();
1848 SDValue Ch = N->getChain();
1849 SDValue Ptr = N->getBasePtr();
1850 EVT MemoryVT = N->getMemoryVT();
1851 unsigned Alignment = N->getOriginalAlignment();
1852 bool isVol = N->isVolatile();
1853 bool isNT = N->isNonTemporal();
1854 AAMDNodes AAInfo = N->getAAInfo();
1856 GetSplitVector(N->getOperand(1), Lo, Hi);
1858 EVT LoMemVT, HiMemVT;
1859 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1861 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1864 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1865 LoMemVT, isVol, isNT, Alignment, AAInfo);
1867 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1868 isVol, isNT, Alignment, AAInfo);
1870 // Increment the pointer to the other half.
1871 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1872 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1875 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1876 N->getPointerInfo().getWithOffset(IncrementSize),
1877 HiMemVT, isVol, isNT, Alignment, AAInfo);
1879 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1880 N->getPointerInfo().getWithOffset(IncrementSize),
1881 isVol, isNT, Alignment, AAInfo);
1883 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1886 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1889 // The input operands all must have the same type, and we know the result
1890 // type is valid. Convert this to a buildvector which extracts all the
1892 // TODO: If the input elements are power-two vectors, we could convert this to
1893 // a new CONCAT_VECTORS node with elements that are half-wide.
1894 SmallVector<SDValue, 32> Elts;
1895 EVT EltVT = N->getValueType(0).getVectorElementType();
1896 for (const SDValue &Op : N->op_values()) {
1897 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1899 Elts.push_back(DAG.getNode(
1900 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1901 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1905 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1908 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1909 // The result type is legal, but the input type is illegal. If splitting
1910 // ends up with the result type of each half still being legal, just
1911 // do that. If, however, that would result in an illegal result type,
1912 // we can try to get more clever with power-two vectors. Specifically,
1913 // split the input type, but also widen the result element size, then
1914 // concatenate the halves and truncate again. For example, consider a target
1915 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1916 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1917 // %inlo = v4i32 extract_subvector %in, 0
1918 // %inhi = v4i32 extract_subvector %in, 4
1919 // %lo16 = v4i16 trunc v4i32 %inlo
1920 // %hi16 = v4i16 trunc v4i32 %inhi
1921 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1922 // %res = v8i8 trunc v8i16 %in16
1924 // Without this transform, the original truncate would end up being
1925 // scalarized, which is pretty much always a last resort.
1926 SDValue InVec = N->getOperand(0);
1927 EVT InVT = InVec->getValueType(0);
1928 EVT OutVT = N->getValueType(0);
1929 unsigned NumElements = OutVT.getVectorNumElements();
1930 bool IsFloat = OutVT.isFloatingPoint();
1932 // Widening should have already made sure this is a power-two vector
1933 // if we're trying to split it at all. assert() that's true, just in case.
1934 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1936 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1937 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1939 // If the input elements are only 1/2 the width of the result elements,
1940 // just use the normal splitting. Our trick only work if there's room
1941 // to split more than once.
1942 if (InElementSize <= OutElementSize * 2)
1943 return SplitVecOp_UnaryOp(N);
1946 // Extract the halves of the input via extract_subvector.
1947 SDValue InLoVec, InHiVec;
1948 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1949 // Truncate them to 1/2 the element size.
1950 EVT HalfElementVT = IsFloat ?
1951 EVT::getFloatingPointVT(InElementSize/2) :
1952 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1953 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1955 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1956 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1957 // Concatenate them to get the full intermediate truncation result.
1958 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1959 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1961 // Now finish up by truncating all the way down to the original result
1962 // type. This should normally be something that ends up being legal directly,
1963 // but in theory if a target has very wide vectors and an annoyingly
1964 // restricted set of legal types, this split can chain to build things up.
1966 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1967 DAG.getTargetConstant(
1968 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1969 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1972 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1973 assert(N->getValueType(0).isVector() &&
1974 N->getOperand(0).getValueType().isVector() &&
1975 "Operand types must be vectors");
1976 // The result has a legal vector type, but the input needs splitting.
1977 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1979 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1980 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1981 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1982 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1983 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1985 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1986 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1987 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1988 return PromoteTargetBoolean(Con, N->getValueType(0));
1992 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1993 // The result has a legal vector type, but the input needs splitting.
1994 EVT ResVT = N->getValueType(0);
1997 GetSplitVector(N->getOperand(0), Lo, Hi);
1998 EVT InVT = Lo.getValueType();
2000 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2001 InVT.getVectorNumElements());
2003 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2004 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2006 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2009 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2010 // The result (and the first input) has a legal vector type, but the second
2011 // input needs splitting.
2012 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2016 //===----------------------------------------------------------------------===//
2017 // Result Vector Widening
2018 //===----------------------------------------------------------------------===//
2020 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2021 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
2025 // See if the target wants to custom widen this node.
2026 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2029 SDValue Res = SDValue();
2030 switch (N->getOpcode()) {
2033 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2037 llvm_unreachable("Do not know how to widen the result of this operator!");
2039 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2040 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2041 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2042 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2043 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
2044 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2045 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2046 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2047 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2048 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2049 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2051 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2052 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2053 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2054 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2055 case ISD::VECTOR_SHUFFLE:
2056 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2059 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2062 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2081 Res = WidenVecRes_Binary(N);
2094 Res = WidenVecRes_BinaryCanTrap(N);
2097 case ISD::FCOPYSIGN:
2098 Res = WidenVecRes_FCOPYSIGN(N);
2102 Res = WidenVecRes_POWI(N);
2108 Res = WidenVecRes_Shift(N);
2111 case ISD::ANY_EXTEND_VECTOR_INREG:
2112 case ISD::SIGN_EXTEND_VECTOR_INREG:
2113 case ISD::ZERO_EXTEND_VECTOR_INREG:
2114 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2117 case ISD::ANY_EXTEND:
2118 case ISD::FP_EXTEND:
2120 case ISD::FP_TO_SINT:
2121 case ISD::FP_TO_UINT:
2122 case ISD::SIGN_EXTEND:
2123 case ISD::SINT_TO_FP:
2125 case ISD::UINT_TO_FP:
2126 case ISD::ZERO_EXTEND:
2127 Res = WidenVecRes_Convert(N);
2130 case ISD::BITREVERSE:
2144 case ISD::FNEARBYINT:
2151 Res = WidenVecRes_Unary(N);
2154 Res = WidenVecRes_Ternary(N);
2158 // If Res is null, the sub-method took care of registering the result.
2160 SetWidenedVector(SDValue(N, ResNo), Res);
2163 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2164 // Ternary op widening.
2166 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2167 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2168 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2169 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2170 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2173 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2174 // Binary op widening.
2176 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2177 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2178 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2179 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2182 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2183 // Binary op widening for operations that can trap.
2184 unsigned Opcode = N->getOpcode();
2186 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2187 EVT WidenEltVT = WidenVT.getVectorElementType();
2189 unsigned NumElts = VT.getVectorNumElements();
2190 const SDNodeFlags *Flags = N->getFlags();
2191 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2192 NumElts = NumElts / 2;
2193 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2196 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2197 // Operation doesn't trap so just widen as normal.
2198 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2199 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2200 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2203 // No legal vector version so unroll the vector operation and then widen.
2205 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2207 // Since the operation can trap, apply operation on the original vector.
2209 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2210 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2211 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2213 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2214 unsigned ConcatEnd = 0; // Current ConcatOps index.
2215 int Idx = 0; // Current Idx into input vectors.
2217 // NumElts := greatest legal vector size (at most WidenVT)
2218 // while (orig. vector has unhandled elements) {
2219 // take munches of size NumElts from the beginning and add to ConcatOps
2220 // NumElts := next smaller supported vector size or 1
2222 while (CurNumElts != 0) {
2223 while (CurNumElts >= NumElts) {
2224 SDValue EOp1 = DAG.getNode(
2225 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2226 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2227 SDValue EOp2 = DAG.getNode(
2228 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2229 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2230 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2232 CurNumElts -= NumElts;
2235 NumElts = NumElts / 2;
2236 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2237 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2240 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2241 SDValue EOp1 = DAG.getNode(
2242 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2243 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2244 SDValue EOp2 = DAG.getNode(
2245 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2246 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2247 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2254 // Check to see if we have a single operation with the widen type.
2255 if (ConcatEnd == 1) {
2256 VT = ConcatOps[0].getValueType();
2258 return ConcatOps[0];
2261 // while (Some element of ConcatOps is not of type MaxVT) {
2262 // From the end of ConcatOps, collect elements of the same type and put
2263 // them into an op of the next larger supported type
2265 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2266 Idx = ConcatEnd - 1;
2267 VT = ConcatOps[Idx--].getValueType();
2268 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2271 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2275 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2276 } while (!TLI.isTypeLegal(NextVT));
2278 if (!VT.isVector()) {
2279 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2280 SDValue VecOp = DAG.getUNDEF(NextVT);
2281 unsigned NumToInsert = ConcatEnd - Idx - 1;
2282 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2283 VecOp = DAG.getNode(
2284 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2285 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2287 ConcatOps[Idx+1] = VecOp;
2288 ConcatEnd = Idx + 2;
2290 // Vector type, create a CONCAT_VECTORS of type NextVT
2291 SDValue undefVec = DAG.getUNDEF(VT);
2292 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2293 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2294 unsigned RealVals = ConcatEnd - Idx - 1;
2295 unsigned SubConcatEnd = 0;
2296 unsigned SubConcatIdx = Idx + 1;
2297 while (SubConcatEnd < RealVals)
2298 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2299 while (SubConcatEnd < OpsToConcat)
2300 SubConcatOps[SubConcatEnd++] = undefVec;
2301 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2302 NextVT, SubConcatOps);
2303 ConcatEnd = SubConcatIdx + 1;
2307 // Check to see if we have a single operation with the widen type.
2308 if (ConcatEnd == 1) {
2309 VT = ConcatOps[0].getValueType();
2311 return ConcatOps[0];
2314 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2315 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2316 if (NumOps != ConcatEnd ) {
2317 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2318 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2319 ConcatOps[j] = UndefVal;
2321 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2322 makeArrayRef(ConcatOps.data(), NumOps));
2325 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2326 SDValue InOp = N->getOperand(0);
2329 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2330 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2332 EVT InVT = InOp.getValueType();
2333 EVT InEltVT = InVT.getVectorElementType();
2334 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2336 unsigned Opcode = N->getOpcode();
2337 unsigned InVTNumElts = InVT.getVectorNumElements();
2338 const SDNodeFlags *Flags = N->getFlags();
2339 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2340 InOp = GetWidenedVector(N->getOperand(0));
2341 InVT = InOp.getValueType();
2342 InVTNumElts = InVT.getVectorNumElements();
2343 if (InVTNumElts == WidenNumElts) {
2344 if (N->getNumOperands() == 1)
2345 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2346 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2350 if (TLI.isTypeLegal(InWidenVT)) {
2351 // Because the result and the input are different vector types, widening
2352 // the result could create a legal type but widening the input might make
2353 // it an illegal type that might lead to repeatedly splitting the input
2354 // and then widening it. To avoid this, we widen the input only if
2355 // it results in a legal type.
2356 if (WidenNumElts % InVTNumElts == 0) {
2357 // Widen the input and call convert on the widened input vector.
2358 unsigned NumConcat = WidenNumElts/InVTNumElts;
2359 SmallVector<SDValue, 16> Ops(NumConcat);
2361 SDValue UndefVal = DAG.getUNDEF(InVT);
2362 for (unsigned i = 1; i != NumConcat; ++i)
2364 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2365 if (N->getNumOperands() == 1)
2366 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2367 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2370 if (InVTNumElts % WidenNumElts == 0) {
2371 SDValue InVal = DAG.getNode(
2372 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2373 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2374 // Extract the input and convert the shorten input vector.
2375 if (N->getNumOperands() == 1)
2376 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2377 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2381 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2382 SmallVector<SDValue, 16> Ops(WidenNumElts);
2383 EVT EltVT = WidenVT.getVectorElementType();
2384 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2386 for (i=0; i < MinElts; ++i) {
2387 SDValue Val = DAG.getNode(
2388 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2389 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2390 if (N->getNumOperands() == 1)
2391 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2393 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2396 SDValue UndefVal = DAG.getUNDEF(EltVT);
2397 for (; i < WidenNumElts; ++i)
2400 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2403 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2404 unsigned Opcode = N->getOpcode();
2405 SDValue InOp = N->getOperand(0);
2408 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2409 EVT WidenSVT = WidenVT.getVectorElementType();
2410 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2412 EVT InVT = InOp.getValueType();
2413 EVT InSVT = InVT.getVectorElementType();
2414 unsigned InVTNumElts = InVT.getVectorNumElements();
2416 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2417 InOp = GetWidenedVector(InOp);
2418 InVT = InOp.getValueType();
2419 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2421 case ISD::ANY_EXTEND_VECTOR_INREG:
2422 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2423 case ISD::SIGN_EXTEND_VECTOR_INREG:
2424 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2425 case ISD::ZERO_EXTEND_VECTOR_INREG:
2426 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2431 // Unroll, extend the scalars and rebuild the vector.
2432 SmallVector<SDValue, 16> Ops;
2433 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2434 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2435 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2437 case ISD::ANY_EXTEND_VECTOR_INREG:
2438 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2440 case ISD::SIGN_EXTEND_VECTOR_INREG:
2441 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2443 case ISD::ZERO_EXTEND_VECTOR_INREG:
2444 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2447 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
2452 while (Ops.size() != WidenNumElts)
2453 Ops.push_back(DAG.getUNDEF(WidenSVT));
2455 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2458 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2459 // If this is an FCOPYSIGN with same input types, we can treat it as a
2460 // normal (can trap) binary op.
2461 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2462 return WidenVecRes_BinaryCanTrap(N);
2464 // If the types are different, fall back to unrolling.
2465 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2466 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2469 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2470 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2471 SDValue InOp = GetWidenedVector(N->getOperand(0));
2472 SDValue ShOp = N->getOperand(1);
2473 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2476 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2477 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2478 SDValue InOp = GetWidenedVector(N->getOperand(0));
2479 SDValue ShOp = N->getOperand(1);
2481 EVT ShVT = ShOp.getValueType();
2482 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2483 ShOp = GetWidenedVector(ShOp);
2484 ShVT = ShOp.getValueType();
2486 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2487 ShVT.getVectorElementType(),
2488 WidenVT.getVectorNumElements());
2489 if (ShVT != ShWidenVT)
2490 ShOp = ModifyToType(ShOp, ShWidenVT);
2492 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2495 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2496 // Unary op widening.
2497 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2498 SDValue InOp = GetWidenedVector(N->getOperand(0));
2499 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2502 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2503 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2504 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2505 cast<VTSDNode>(N->getOperand(1))->getVT()
2506 .getVectorElementType(),
2507 WidenVT.getVectorNumElements());
2508 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2509 return DAG.getNode(N->getOpcode(), SDLoc(N),
2510 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2513 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2514 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2515 return GetWidenedVector(WidenVec);
2518 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2519 SDValue InOp = N->getOperand(0);
2520 EVT InVT = InOp.getValueType();
2521 EVT VT = N->getValueType(0);
2522 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2525 switch (getTypeAction(InVT)) {
2526 case TargetLowering::TypeLegal:
2528 case TargetLowering::TypePromoteInteger:
2529 // If the incoming type is a vector that is being promoted, then
2530 // we know that the elements are arranged differently and that we
2531 // must perform the conversion using a stack slot.
2532 if (InVT.isVector())
2535 // If the InOp is promoted to the same size, convert it. Otherwise,
2536 // fall out of the switch and widen the promoted input.
2537 InOp = GetPromotedInteger(InOp);
2538 InVT = InOp.getValueType();
2539 if (WidenVT.bitsEq(InVT))
2540 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2542 case TargetLowering::TypeSoftenFloat:
2543 case TargetLowering::TypePromoteFloat:
2544 case TargetLowering::TypeExpandInteger:
2545 case TargetLowering::TypeExpandFloat:
2546 case TargetLowering::TypeScalarizeVector:
2547 case TargetLowering::TypeSplitVector:
2549 case TargetLowering::TypeWidenVector:
2550 // If the InOp is widened to the same size, convert it. Otherwise, fall
2551 // out of the switch and widen the widened input.
2552 InOp = GetWidenedVector(InOp);
2553 InVT = InOp.getValueType();
2554 if (WidenVT.bitsEq(InVT))
2555 // The input widens to the same size. Convert to the widen value.
2556 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2560 unsigned WidenSize = WidenVT.getSizeInBits();
2561 unsigned InSize = InVT.getSizeInBits();
2562 // x86mmx is not an acceptable vector element type, so don't try.
2563 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2564 // Determine new input vector type. The new input vector type will use
2565 // the same element type (if its a vector) or use the input type as a
2566 // vector. It is the same size as the type to widen to.
2568 unsigned NewNumElts = WidenSize / InSize;
2569 if (InVT.isVector()) {
2570 EVT InEltVT = InVT.getVectorElementType();
2571 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2572 WidenSize / InEltVT.getSizeInBits());
2574 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2577 if (TLI.isTypeLegal(NewInVT)) {
2578 // Because the result and the input are different vector types, widening
2579 // the result could create a legal type but widening the input might make
2580 // it an illegal type that might lead to repeatedly splitting the input
2581 // and then widening it. To avoid this, we widen the input only if
2582 // it results in a legal type.
2583 SmallVector<SDValue, 16> Ops(NewNumElts);
2584 SDValue UndefVal = DAG.getUNDEF(InVT);
2586 for (unsigned i = 1; i < NewNumElts; ++i)
2590 if (InVT.isVector())
2591 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2593 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2594 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2598 return CreateStackStoreLoad(InOp, WidenVT);
2601 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2603 // Build a vector with undefined for the new nodes.
2604 EVT VT = N->getValueType(0);
2606 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2607 // type. The UNDEFs need to have the same type as the existing operands.
2608 EVT EltVT = N->getOperand(0).getValueType();
2609 unsigned NumElts = VT.getVectorNumElements();
2611 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2612 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2614 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2615 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2616 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2618 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2621 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2622 EVT InVT = N->getOperand(0).getValueType();
2623 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2625 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2626 unsigned NumInElts = InVT.getVectorNumElements();
2627 unsigned NumOperands = N->getNumOperands();
2629 bool InputWidened = false; // Indicates we need to widen the input.
2630 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2631 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2632 // Add undef vectors to widen to correct length.
2633 unsigned NumConcat = WidenVT.getVectorNumElements() /
2634 InVT.getVectorNumElements();
2635 SDValue UndefVal = DAG.getUNDEF(InVT);
2636 SmallVector<SDValue, 16> Ops(NumConcat);
2637 for (unsigned i=0; i < NumOperands; ++i)
2638 Ops[i] = N->getOperand(i);
2639 for (unsigned i = NumOperands; i != NumConcat; ++i)
2641 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2644 InputWidened = true;
2645 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2646 // The inputs and the result are widen to the same value.
2648 for (i=1; i < NumOperands; ++i)
2649 if (!N->getOperand(i).isUndef())
2652 if (i == NumOperands)
2653 // Everything but the first operand is an UNDEF so just return the
2654 // widened first operand.
2655 return GetWidenedVector(N->getOperand(0));
2657 if (NumOperands == 2) {
2658 // Replace concat of two operands with a shuffle.
2659 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2660 for (unsigned i = 0; i < NumInElts; ++i) {
2662 MaskOps[i + NumInElts] = i + WidenNumElts;
2664 return DAG.getVectorShuffle(WidenVT, dl,
2665 GetWidenedVector(N->getOperand(0)),
2666 GetWidenedVector(N->getOperand(1)),
2672 // Fall back to use extracts and build vector.
2673 EVT EltVT = WidenVT.getVectorElementType();
2674 SmallVector<SDValue, 16> Ops(WidenNumElts);
2676 for (unsigned i=0; i < NumOperands; ++i) {
2677 SDValue InOp = N->getOperand(i);
2679 InOp = GetWidenedVector(InOp);
2680 for (unsigned j=0; j < NumInElts; ++j)
2681 Ops[Idx++] = DAG.getNode(
2682 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2683 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2685 SDValue UndefVal = DAG.getUNDEF(EltVT);
2686 for (; Idx < WidenNumElts; ++Idx)
2687 Ops[Idx] = UndefVal;
2688 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2691 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2693 SDValue InOp = N->getOperand(0);
2694 SDValue RndOp = N->getOperand(3);
2695 SDValue SatOp = N->getOperand(4);
2697 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2698 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2700 EVT InVT = InOp.getValueType();
2701 EVT InEltVT = InVT.getVectorElementType();
2702 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2704 SDValue DTyOp = DAG.getValueType(WidenVT);
2705 SDValue STyOp = DAG.getValueType(InWidenVT);
2706 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2708 unsigned InVTNumElts = InVT.getVectorNumElements();
2709 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2710 InOp = GetWidenedVector(InOp);
2711 InVT = InOp.getValueType();
2712 InVTNumElts = InVT.getVectorNumElements();
2713 if (InVTNumElts == WidenNumElts)
2714 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2718 if (TLI.isTypeLegal(InWidenVT)) {
2719 // Because the result and the input are different vector types, widening
2720 // the result could create a legal type but widening the input might make
2721 // it an illegal type that might lead to repeatedly splitting the input
2722 // and then widening it. To avoid this, we widen the input only if
2723 // it results in a legal type.
2724 if (WidenNumElts % InVTNumElts == 0) {
2725 // Widen the input and call convert on the widened input vector.
2726 unsigned NumConcat = WidenNumElts/InVTNumElts;
2727 SmallVector<SDValue, 16> Ops(NumConcat);
2729 SDValue UndefVal = DAG.getUNDEF(InVT);
2730 for (unsigned i = 1; i != NumConcat; ++i)
2733 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2734 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2738 if (InVTNumElts % WidenNumElts == 0) {
2739 // Extract the input and convert the shorten input vector.
2741 ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2742 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2743 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2748 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2749 SmallVector<SDValue, 16> Ops(WidenNumElts);
2750 EVT EltVT = WidenVT.getVectorElementType();
2751 DTyOp = DAG.getValueType(EltVT);
2752 STyOp = DAG.getValueType(InEltVT);
2754 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2756 for (i=0; i < MinElts; ++i) {
2757 SDValue ExtVal = DAG.getNode(
2758 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2759 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2760 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2764 SDValue UndefVal = DAG.getUNDEF(EltVT);
2765 for (; i < WidenNumElts; ++i)
2768 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2771 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2772 EVT VT = N->getValueType(0);
2773 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2774 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2775 SDValue InOp = N->getOperand(0);
2776 SDValue Idx = N->getOperand(1);
2779 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2780 InOp = GetWidenedVector(InOp);
2782 EVT InVT = InOp.getValueType();
2784 // Check if we can just return the input vector after widening.
2785 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2786 if (IdxVal == 0 && InVT == WidenVT)
2789 // Check if we can extract from the vector.
2790 unsigned InNumElts = InVT.getVectorNumElements();
2791 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2792 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2794 // We could try widening the input to the right length but for now, extract
2795 // the original elements, fill the rest with undefs and build a vector.
2796 SmallVector<SDValue, 16> Ops(WidenNumElts);
2797 EVT EltVT = VT.getVectorElementType();
2798 unsigned NumElts = VT.getVectorNumElements();
2800 for (i=0; i < NumElts; ++i)
2802 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2803 DAG.getConstant(IdxVal + i, dl,
2804 TLI.getVectorIdxTy(DAG.getDataLayout())));
2806 SDValue UndefVal = DAG.getUNDEF(EltVT);
2807 for (; i < WidenNumElts; ++i)
2809 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2812 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2813 SDValue InOp = GetWidenedVector(N->getOperand(0));
2814 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2815 InOp.getValueType(), InOp,
2816 N->getOperand(1), N->getOperand(2));
2819 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2820 LoadSDNode *LD = cast<LoadSDNode>(N);
2821 ISD::LoadExtType ExtType = LD->getExtensionType();
2824 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2825 if (ExtType != ISD::NON_EXTLOAD)
2826 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2828 Result = GenWidenVectorLoads(LdChain, LD);
2830 // If we generate a single load, we can use that for the chain. Otherwise,
2831 // build a factor node to remember the multiple loads are independent and
2834 if (LdChain.size() == 1)
2835 NewChain = LdChain[0];
2837 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2839 // Modified the chain - switch anything that used the old chain to use
2841 ReplaceValueWith(SDValue(N, 1), NewChain);
2846 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2848 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2849 SDValue Mask = N->getMask();
2850 EVT MaskVT = Mask.getValueType();
2851 SDValue Src0 = GetWidenedVector(N->getSrc0());
2852 ISD::LoadExtType ExtType = N->getExtensionType();
2855 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2856 Mask = GetWidenedVector(Mask);
2858 EVT BoolVT = getSetCCResultType(WidenVT);
2860 // We can't use ModifyToType() because we should fill the mask with
2862 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2863 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2865 unsigned NumConcat = WidenNumElts / MaskNumElts;
2866 SmallVector<SDValue, 16> Ops(NumConcat);
2867 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2869 for (unsigned i = 1; i != NumConcat; ++i)
2872 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2875 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2876 Mask, Src0, N->getMemoryVT(),
2877 N->getMemOperand(), ExtType);
2878 // Legalize the chain result - switch anything that used the old chain to
2880 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2884 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
2886 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2887 SDValue Mask = N->getMask();
2888 SDValue Src0 = GetWidenedVector(N->getValue());
2889 unsigned NumElts = WideVT.getVectorNumElements();
2892 // The mask should be widened as well
2893 Mask = WidenTargetBoolean(Mask, WideVT, true);
2895 // Widen the Index operand
2896 SDValue Index = N->getIndex();
2897 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
2898 Index.getValueType().getScalarType(),
2900 Index = ModifyToType(Index, WideIndexVT);
2901 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
2902 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
2903 N->getMemoryVT(), dl, Ops,
2904 N->getMemOperand());
2906 // Legalize the chain result - switch anything that used the old chain to
2908 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2912 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2913 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2914 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2915 WidenVT, N->getOperand(0));
2918 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2919 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2920 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2922 SDValue Cond1 = N->getOperand(0);
2923 EVT CondVT = Cond1.getValueType();
2924 if (CondVT.isVector()) {
2925 EVT CondEltVT = CondVT.getVectorElementType();
2926 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2927 CondEltVT, WidenNumElts);
2928 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2929 Cond1 = GetWidenedVector(Cond1);
2931 // If we have to split the condition there is no point in widening the
2932 // select. This would result in an cycle of widening the select ->
2933 // widening the condition operand -> splitting the condition operand ->
2934 // splitting the select -> widening the select. Instead split this select
2935 // further and widen the resulting type.
2936 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2937 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2938 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2942 if (Cond1.getValueType() != CondWidenVT)
2943 Cond1 = ModifyToType(Cond1, CondWidenVT);
2946 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2947 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2948 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2949 return DAG.getNode(N->getOpcode(), SDLoc(N),
2950 WidenVT, Cond1, InOp1, InOp2);
2953 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2954 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2955 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2956 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2957 InOp1.getValueType(), N->getOperand(0),
2958 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2961 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2962 assert(N->getValueType(0).isVector() ==
2963 N->getOperand(0).getValueType().isVector() &&
2964 "Scalar/Vector type mismatch");
2965 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2967 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2968 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2969 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2970 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2971 InOp1, InOp2, N->getOperand(2));
2974 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2975 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2976 return DAG.getUNDEF(WidenVT);
2979 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2980 EVT VT = N->getValueType(0);
2983 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2984 unsigned NumElts = VT.getVectorNumElements();
2985 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2987 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2988 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2990 // Adjust mask based on new input vector length.
2991 SmallVector<int, 16> NewMask;
2992 for (unsigned i = 0; i != NumElts; ++i) {
2993 int Idx = N->getMaskElt(i);
2994 if (Idx < (int)NumElts)
2995 NewMask.push_back(Idx);
2997 NewMask.push_back(Idx - NumElts + WidenNumElts);
2999 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3000 NewMask.push_back(-1);
3001 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
3004 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
3005 assert(N->getValueType(0).isVector() &&
3006 N->getOperand(0).getValueType().isVector() &&
3007 "Operands must be vectors");
3008 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3009 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3011 SDValue InOp1 = N->getOperand(0);
3012 EVT InVT = InOp1.getValueType();
3013 assert(InVT.isVector() && "can not widen non-vector type");
3014 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3015 InVT.getVectorElementType(), WidenNumElts);
3017 // The input and output types often differ here, and it could be that while
3018 // we'd prefer to widen the result type, the input operands have been split.
3019 // In this case, we also need to split the result of this node as well.
3020 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3021 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3022 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3026 InOp1 = GetWidenedVector(InOp1);
3027 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3029 // Assume that the input and output will be widen appropriately. If not,
3030 // we will have to unroll it at some point.
3031 assert(InOp1.getValueType() == WidenInVT &&
3032 InOp2.getValueType() == WidenInVT &&
3033 "Input not widened to expected type!");
3035 return DAG.getNode(ISD::SETCC, SDLoc(N),
3036 WidenVT, InOp1, InOp2, N->getOperand(2));
3040 //===----------------------------------------------------------------------===//
3041 // Widen Vector Operand
3042 //===----------------------------------------------------------------------===//
3043 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3044 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
3047 SDValue Res = SDValue();
3049 // See if the target wants to custom widen this node.
3050 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3053 switch (N->getOpcode()) {
3056 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3060 llvm_unreachable("Do not know how to widen this operator's operand!");
3062 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3063 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3064 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3065 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3066 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3067 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
3068 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3069 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3070 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3072 case ISD::ANY_EXTEND:
3073 case ISD::SIGN_EXTEND:
3074 case ISD::ZERO_EXTEND:
3075 Res = WidenVecOp_EXTEND(N);
3078 case ISD::FP_EXTEND:
3079 case ISD::FP_TO_SINT:
3080 case ISD::FP_TO_UINT:
3081 case ISD::SINT_TO_FP:
3082 case ISD::UINT_TO_FP:
3084 Res = WidenVecOp_Convert(N);
3088 // If Res is null, the sub-method took care of registering the result.
3089 if (!Res.getNode()) return false;
3091 // If the result is N, the sub-method updated N in place. Tell the legalizer
3093 if (Res.getNode() == N)
3097 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3098 "Invalid operand expansion");
3100 ReplaceValueWith(SDValue(N, 0), Res);
3104 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3106 EVT VT = N->getValueType(0);
3108 SDValue InOp = N->getOperand(0);
3109 // If some legalization strategy other than widening is used on the operand,
3110 // we can't safely assume that just extending the low lanes is the correct
3112 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
3113 return WidenVecOp_Convert(N);
3114 InOp = GetWidenedVector(InOp);
3115 assert(VT.getVectorNumElements() <
3116 InOp.getValueType().getVectorNumElements() &&
3117 "Input wasn't widened!");
3119 // We may need to further widen the operand until it has the same total
3120 // vector size as the result.
3121 EVT InVT = InOp.getValueType();
3122 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3123 EVT InEltVT = InVT.getVectorElementType();
3124 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3125 EVT FixedVT = (MVT::SimpleValueType)i;
3126 EVT FixedEltVT = FixedVT.getVectorElementType();
3127 if (TLI.isTypeLegal(FixedVT) &&
3128 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3129 FixedEltVT == InEltVT) {
3130 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
3131 "Not enough elements in the fixed type for the operand!");
3132 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
3133 "We can't have the same type as we started with!");
3134 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3136 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3137 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3140 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3141 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3145 InVT = InOp.getValueType();
3146 if (InVT.getSizeInBits() != VT.getSizeInBits())
3147 // We couldn't find a legal vector type that was a widening of the input
3148 // and could be extended in-register to the result type, so we have to
3150 return WidenVecOp_Convert(N);
3153 // Use special DAG nodes to represent the operation of extending the
3155 switch (N->getOpcode()) {
3157 llvm_unreachable("Extend legalization on on extend operation!");
3158 case ISD::ANY_EXTEND:
3159 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3160 case ISD::SIGN_EXTEND:
3161 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3162 case ISD::ZERO_EXTEND:
3163 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3167 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3168 // The result (and first input) is legal, but the second input is illegal.
3169 // We can't do much to fix that, so just unroll and let the extracts off of
3170 // the second input be widened as needed later.
3171 return DAG.UnrollVectorOp(N);
3174 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3175 // Since the result is legal and the input is illegal, it is unlikely
3176 // that we can fix the input to a legal type so unroll the convert
3177 // into some scalar code and create a nasty build vector.
3178 EVT VT = N->getValueType(0);
3179 EVT EltVT = VT.getVectorElementType();
3181 unsigned NumElts = VT.getVectorNumElements();
3182 SDValue InOp = N->getOperand(0);
3183 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3184 InOp = GetWidenedVector(InOp);
3185 EVT InVT = InOp.getValueType();
3186 EVT InEltVT = InVT.getVectorElementType();
3188 unsigned Opcode = N->getOpcode();
3189 SmallVector<SDValue, 16> Ops(NumElts);
3190 for (unsigned i=0; i < NumElts; ++i)
3191 Ops[i] = DAG.getNode(
3194 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3195 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3197 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3200 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3201 EVT VT = N->getValueType(0);
3202 SDValue InOp = GetWidenedVector(N->getOperand(0));
3203 EVT InWidenVT = InOp.getValueType();
3206 // Check if we can convert between two legal vector types and extract.
3207 unsigned InWidenSize = InWidenVT.getSizeInBits();
3208 unsigned Size = VT.getSizeInBits();
3209 // x86mmx is not an acceptable vector element type, so don't try.
3210 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3211 unsigned NewNumElts = InWidenSize / Size;
3212 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3213 if (TLI.isTypeLegal(NewVT)) {
3214 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3216 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3217 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3221 return CreateStackStoreLoad(InOp, VT);
3224 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3225 // If the input vector is not legal, it is likely that we will not find a
3226 // legal vector of the same size. Replace the concatenate vector with a
3227 // nasty build vector.
3228 EVT VT = N->getValueType(0);
3229 EVT EltVT = VT.getVectorElementType();
3231 unsigned NumElts = VT.getVectorNumElements();
3232 SmallVector<SDValue, 16> Ops(NumElts);
3234 EVT InVT = N->getOperand(0).getValueType();
3235 unsigned NumInElts = InVT.getVectorNumElements();
3238 unsigned NumOperands = N->getNumOperands();
3239 for (unsigned i=0; i < NumOperands; ++i) {
3240 SDValue InOp = N->getOperand(i);
3241 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3242 InOp = GetWidenedVector(InOp);
3243 for (unsigned j=0; j < NumInElts; ++j)
3244 Ops[Idx++] = DAG.getNode(
3245 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3246 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3248 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3251 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3252 SDValue InOp = GetWidenedVector(N->getOperand(0));
3253 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3254 N->getValueType(0), InOp, N->getOperand(1));
3257 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3258 SDValue InOp = GetWidenedVector(N->getOperand(0));
3259 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3260 N->getValueType(0), InOp, N->getOperand(1));
3263 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3264 // We have to widen the value but we want only to store the original
3266 StoreSDNode *ST = cast<StoreSDNode>(N);
3268 SmallVector<SDValue, 16> StChain;
3269 if (ST->isTruncatingStore())
3270 GenWidenVectorTruncStores(StChain, ST);
3272 GenWidenVectorStores(StChain, ST);
3274 if (StChain.size() == 1)
3277 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3280 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3281 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3282 SDValue Mask = MST->getMask();
3283 EVT MaskVT = Mask.getValueType();
3284 SDValue StVal = MST->getValue();
3286 SDValue WideVal = GetWidenedVector(StVal);
3289 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3290 Mask = GetWidenedVector(Mask);
3292 // The mask should be widened as well
3293 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3294 // We can't use ModifyToType() because we should fill the mask with
3296 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3297 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3299 unsigned NumConcat = WidenNumElts / MaskNumElts;
3300 SmallVector<SDValue, 16> Ops(NumConcat);
3301 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3303 for (unsigned i = 1; i != NumConcat; ++i)
3306 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3308 assert(Mask.getValueType().getVectorNumElements() ==
3309 WideVal.getValueType().getVectorNumElements() &&
3310 "Mask and data vectors should have the same number of elements");
3311 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3312 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3316 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3317 assert(OpNo == 1 && "Can widen only data operand of mscatter");
3318 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3319 SDValue DataOp = MSC->getValue();
3320 SDValue Mask = MSC->getMask();
3323 SDValue WideVal = GetWidenedVector(DataOp);
3324 EVT WideVT = WideVal.getValueType();
3325 unsigned NumElts = WideVal.getValueType().getVectorNumElements();
3328 // The mask should be widened as well
3329 Mask = WidenTargetBoolean(Mask, WideVT, true);
3332 SDValue Index = MSC->getIndex();
3333 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3334 Index.getValueType().getScalarType(),
3336 Index = ModifyToType(Index, WideIndexVT);
3338 SDValue Ops[] = {MSC->getChain(), WideVal, Mask, MSC->getBasePtr(), Index};
3339 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3340 MSC->getMemoryVT(), dl, Ops,
3341 MSC->getMemOperand());
3344 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3345 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3346 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3349 // WARNING: In this code we widen the compare instruction with garbage.
3350 // This garbage may contain denormal floats which may be slow. Is this a real
3351 // concern ? Should we zero the unused lanes if this is a float compare ?
3353 // Get a new SETCC node to compare the newly widened operands.
3354 // Only some of the compared elements are legal.
3355 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3356 InOp0.getValueType());
3357 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3358 SVT, InOp0, InOp1, N->getOperand(2));
3360 // Extract the needed results from the result vector.
3361 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3362 SVT.getVectorElementType(),
3363 N->getValueType(0).getVectorNumElements());
3364 SDValue CC = DAG.getNode(
3365 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3366 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3368 return PromoteTargetBoolean(CC, N->getValueType(0));
3372 //===----------------------------------------------------------------------===//
3373 // Vector Widening Utilities
3374 //===----------------------------------------------------------------------===//
3376 // Utility function to find the type to chop up a widen vector for load/store
3377 // TLI: Target lowering used to determine legal types.
3378 // Width: Width left need to load/store.
3379 // WidenVT: The widen vector type to load to/store from
3380 // Align: If 0, don't allow use of a wider type
3381 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3383 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3384 unsigned Width, EVT WidenVT,
3385 unsigned Align = 0, unsigned WidenEx = 0) {
3386 EVT WidenEltVT = WidenVT.getVectorElementType();
3387 unsigned WidenWidth = WidenVT.getSizeInBits();
3388 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3389 unsigned AlignInBits = Align*8;
3391 // If we have one element to load/store, return it.
3392 EVT RetVT = WidenEltVT;
3393 if (Width == WidenEltWidth)
3396 // See if there is larger legal integer than the element type to load/store
3398 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3399 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3400 EVT MemVT((MVT::SimpleValueType) VT);
3401 unsigned MemVTWidth = MemVT.getSizeInBits();
3402 if (MemVT.getSizeInBits() <= WidenEltWidth)
3404 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3405 if ((Action == TargetLowering::TypeLegal ||
3406 Action == TargetLowering::TypePromoteInteger) &&
3407 (WidenWidth % MemVTWidth) == 0 &&
3408 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3409 (MemVTWidth <= Width ||
3410 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3416 // See if there is a larger vector type to load/store that has the same vector
3417 // element type and is evenly divisible with the WidenVT.
3418 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3419 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3420 EVT MemVT = (MVT::SimpleValueType) VT;
3421 unsigned MemVTWidth = MemVT.getSizeInBits();
3422 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3423 (WidenWidth % MemVTWidth) == 0 &&
3424 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3425 (MemVTWidth <= Width ||
3426 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3427 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3435 // Builds a vector type from scalar loads
3436 // VecTy: Resulting Vector type
3437 // LDOps: Load operators to build a vector type
3438 // [Start,End) the list of loads to use.
3439 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3440 SmallVectorImpl<SDValue> &LdOps,
3441 unsigned Start, unsigned End) {
3442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3443 SDLoc dl(LdOps[Start]);
3444 EVT LdTy = LdOps[Start].getValueType();
3445 unsigned Width = VecTy.getSizeInBits();
3446 unsigned NumElts = Width / LdTy.getSizeInBits();
3447 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3450 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3452 for (unsigned i = Start + 1; i != End; ++i) {
3453 EVT NewLdTy = LdOps[i].getValueType();
3454 if (NewLdTy != LdTy) {
3455 NumElts = Width / NewLdTy.getSizeInBits();
3456 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3457 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3458 // Readjust position and vector position based on new load type
3459 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3462 VecOp = DAG.getNode(
3463 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3464 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3466 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3469 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3471 // The strategy assumes that we can efficiently load powers of two widths.
3472 // The routines chops the vector into the largest vector loads with the same
3473 // element type or scalar loads and then recombines it to the widen vector
3475 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3476 unsigned WidenWidth = WidenVT.getSizeInBits();
3477 EVT LdVT = LD->getMemoryVT();
3479 assert(LdVT.isVector() && WidenVT.isVector());
3480 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3483 SDValue Chain = LD->getChain();
3484 SDValue BasePtr = LD->getBasePtr();
3485 unsigned Align = LD->getAlignment();
3486 bool isVolatile = LD->isVolatile();
3487 bool isNonTemporal = LD->isNonTemporal();
3488 bool isInvariant = LD->isInvariant();
3489 AAMDNodes AAInfo = LD->getAAInfo();
3491 int LdWidth = LdVT.getSizeInBits();
3492 int WidthDiff = WidenWidth - LdWidth; // Difference
3493 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3495 // Find the vector type that can load from.
3496 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3497 int NewVTWidth = NewVT.getSizeInBits();
3498 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3499 isVolatile, isNonTemporal, isInvariant, Align,
3501 LdChain.push_back(LdOp.getValue(1));
3503 // Check if we can load the element with one instruction
3504 if (LdWidth <= NewVTWidth) {
3505 if (!NewVT.isVector()) {
3506 unsigned NumElts = WidenWidth / NewVTWidth;
3507 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3508 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3509 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3511 if (NewVT == WidenVT)
3514 assert(WidenWidth % NewVTWidth == 0);
3515 unsigned NumConcat = WidenWidth / NewVTWidth;
3516 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3517 SDValue UndefVal = DAG.getUNDEF(NewVT);
3518 ConcatOps[0] = LdOp;
3519 for (unsigned i = 1; i != NumConcat; ++i)
3520 ConcatOps[i] = UndefVal;
3521 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3524 // Load vector by using multiple loads from largest vector to scalar
3525 SmallVector<SDValue, 16> LdOps;
3526 LdOps.push_back(LdOp);
3528 LdWidth -= NewVTWidth;
3529 unsigned Offset = 0;
3531 while (LdWidth > 0) {
3532 unsigned Increment = NewVTWidth / 8;
3533 Offset += Increment;
3534 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3535 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3538 if (LdWidth < NewVTWidth) {
3539 // Our current type we are using is too large, find a better size
3540 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3541 NewVTWidth = NewVT.getSizeInBits();
3542 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3543 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3544 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3546 LdChain.push_back(L.getValue(1));
3547 if (L->getValueType(0).isVector()) {
3548 SmallVector<SDValue, 16> Loads;
3550 unsigned size = L->getValueSizeInBits(0);
3551 while (size < LdOp->getValueSizeInBits(0)) {
3552 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3553 size += L->getValueSizeInBits(0);
3555 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3558 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3559 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3560 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3562 LdChain.push_back(L.getValue(1));
3568 LdWidth -= NewVTWidth;
3571 // Build the vector from the loads operations
3572 unsigned End = LdOps.size();
3573 if (!LdOps[0].getValueType().isVector())
3574 // All the loads are scalar loads.
3575 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3577 // If the load contains vectors, build the vector using concat vector.
3578 // All of the vectors used to loads are power of 2 and the scalars load
3579 // can be combined to make a power of 2 vector.
3580 SmallVector<SDValue, 16> ConcatOps(End);
3583 EVT LdTy = LdOps[i].getValueType();
3584 // First combine the scalar loads to a vector
3585 if (!LdTy.isVector()) {
3586 for (--i; i >= 0; --i) {
3587 LdTy = LdOps[i].getValueType();
3588 if (LdTy.isVector())
3591 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3593 ConcatOps[--Idx] = LdOps[i];
3594 for (--i; i >= 0; --i) {
3595 EVT NewLdTy = LdOps[i].getValueType();
3596 if (NewLdTy != LdTy) {
3597 // Create a larger vector
3598 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3599 makeArrayRef(&ConcatOps[Idx], End - Idx));
3603 ConcatOps[--Idx] = LdOps[i];
3606 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3607 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3608 makeArrayRef(&ConcatOps[Idx], End - Idx));
3610 // We need to fill the rest with undefs to build the vector
3611 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3612 SmallVector<SDValue, 16> WidenOps(NumOps);
3613 SDValue UndefVal = DAG.getUNDEF(LdTy);
3616 for (; i != End-Idx; ++i)
3617 WidenOps[i] = ConcatOps[Idx+i];
3618 for (; i != NumOps; ++i)
3619 WidenOps[i] = UndefVal;
3621 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3625 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3627 ISD::LoadExtType ExtType) {
3628 // For extension loads, it may not be more efficient to chop up the vector
3629 // and then extended it. Instead, we unroll the load and build a new vector.
3630 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3631 EVT LdVT = LD->getMemoryVT();
3633 assert(LdVT.isVector() && WidenVT.isVector());
3636 SDValue Chain = LD->getChain();
3637 SDValue BasePtr = LD->getBasePtr();
3638 unsigned Align = LD->getAlignment();
3639 bool isVolatile = LD->isVolatile();
3640 bool isNonTemporal = LD->isNonTemporal();
3641 bool isInvariant = LD->isInvariant();
3642 AAMDNodes AAInfo = LD->getAAInfo();
3644 EVT EltVT = WidenVT.getVectorElementType();
3645 EVT LdEltVT = LdVT.getVectorElementType();
3646 unsigned NumElts = LdVT.getVectorNumElements();
3648 // Load each element and widen
3649 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3650 SmallVector<SDValue, 16> Ops(WidenNumElts);
3651 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3652 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3653 LD->getPointerInfo(),
3654 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3656 LdChain.push_back(Ops[0].getValue(1));
3657 unsigned i = 0, Offset = Increment;
3658 for (i=1; i < NumElts; ++i, Offset += Increment) {
3659 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3661 DAG.getConstant(Offset, dl,
3662 BasePtr.getValueType()));
3663 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3664 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3665 isVolatile, isNonTemporal, isInvariant, Align,
3667 LdChain.push_back(Ops[i].getValue(1));
3670 // Fill the rest with undefs
3671 SDValue UndefVal = DAG.getUNDEF(EltVT);
3672 for (; i != WidenNumElts; ++i)
3675 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3679 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3681 // The strategy assumes that we can efficiently store powers of two widths.
3682 // The routines chops the vector into the largest vector stores with the same
3683 // element type or scalar stores.
3684 SDValue Chain = ST->getChain();
3685 SDValue BasePtr = ST->getBasePtr();
3686 unsigned Align = ST->getAlignment();
3687 bool isVolatile = ST->isVolatile();
3688 bool isNonTemporal = ST->isNonTemporal();
3689 AAMDNodes AAInfo = ST->getAAInfo();
3690 SDValue ValOp = GetWidenedVector(ST->getValue());
3693 EVT StVT = ST->getMemoryVT();
3694 unsigned StWidth = StVT.getSizeInBits();
3695 EVT ValVT = ValOp.getValueType();
3696 unsigned ValWidth = ValVT.getSizeInBits();
3697 EVT ValEltVT = ValVT.getVectorElementType();
3698 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3699 assert(StVT.getVectorElementType() == ValEltVT);
3701 int Idx = 0; // current index to store
3702 unsigned Offset = 0; // offset from base to store
3703 while (StWidth != 0) {
3704 // Find the largest vector type we can store with
3705 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3706 unsigned NewVTWidth = NewVT.getSizeInBits();
3707 unsigned Increment = NewVTWidth / 8;
3708 if (NewVT.isVector()) {
3709 unsigned NumVTElts = NewVT.getVectorNumElements();
3711 SDValue EOp = DAG.getNode(
3712 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3713 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3714 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3715 ST->getPointerInfo().getWithOffset(Offset),
3716 isVolatile, isNonTemporal,
3717 MinAlign(Align, Offset), AAInfo));
3718 StWidth -= NewVTWidth;
3719 Offset += Increment;
3721 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3722 DAG.getConstant(Increment, dl,
3723 BasePtr.getValueType()));
3724 } while (StWidth != 0 && StWidth >= NewVTWidth);
3726 // Cast the vector to the scalar type we can store
3727 unsigned NumElts = ValWidth / NewVTWidth;
3728 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3729 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3730 // Readjust index position based on new vector type
3731 Idx = Idx * ValEltWidth / NewVTWidth;
3733 SDValue EOp = DAG.getNode(
3734 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3735 DAG.getConstant(Idx++, dl,
3736 TLI.getVectorIdxTy(DAG.getDataLayout())));
3737 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3738 ST->getPointerInfo().getWithOffset(Offset),
3739 isVolatile, isNonTemporal,
3740 MinAlign(Align, Offset), AAInfo));
3741 StWidth -= NewVTWidth;
3742 Offset += Increment;
3743 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3744 DAG.getConstant(Increment, dl,
3745 BasePtr.getValueType()));
3746 } while (StWidth != 0 && StWidth >= NewVTWidth);
3747 // Restore index back to be relative to the original widen element type
3748 Idx = Idx * NewVTWidth / ValEltWidth;
3754 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3756 // For extension loads, it may not be more efficient to truncate the vector
3757 // and then store it. Instead, we extract each element and then store it.
3758 SDValue Chain = ST->getChain();
3759 SDValue BasePtr = ST->getBasePtr();
3760 unsigned Align = ST->getAlignment();
3761 bool isVolatile = ST->isVolatile();
3762 bool isNonTemporal = ST->isNonTemporal();
3763 AAMDNodes AAInfo = ST->getAAInfo();
3764 SDValue ValOp = GetWidenedVector(ST->getValue());
3767 EVT StVT = ST->getMemoryVT();
3768 EVT ValVT = ValOp.getValueType();
3770 // It must be true that we the widen vector type is bigger than where
3771 // we need to store.
3772 assert(StVT.isVector() && ValOp.getValueType().isVector());
3773 assert(StVT.bitsLT(ValOp.getValueType()));
3775 // For truncating stores, we can not play the tricks of chopping legal
3776 // vector types and bit cast it to the right type. Instead, we unroll
3778 EVT StEltVT = StVT.getVectorElementType();
3779 EVT ValEltVT = ValVT.getVectorElementType();
3780 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3781 unsigned NumElts = StVT.getVectorNumElements();
3782 SDValue EOp = DAG.getNode(
3783 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3784 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3785 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3786 ST->getPointerInfo(), StEltVT,
3787 isVolatile, isNonTemporal, Align,
3789 unsigned Offset = Increment;
3790 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3791 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3793 DAG.getConstant(Offset, dl,
3794 BasePtr.getValueType()));
3795 SDValue EOp = DAG.getNode(
3796 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3797 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3798 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3799 ST->getPointerInfo().getWithOffset(Offset),
3800 StEltVT, isVolatile, isNonTemporal,
3801 MinAlign(Align, Offset), AAInfo));
3805 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3806 /// input vector must have the same element type as NVT.
3807 /// FillWithZeroes specifies that the vector should be widened with zeroes.
3808 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
3809 bool FillWithZeroes) {
3810 // Note that InOp might have been widened so it might already have
3811 // the right width or it might need be narrowed.
3812 EVT InVT = InOp.getValueType();
3813 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3814 "input and widen element type must match");
3817 // Check if InOp already has the right width.
3821 unsigned InNumElts = InVT.getVectorNumElements();
3822 unsigned WidenNumElts = NVT.getVectorNumElements();
3823 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3824 unsigned NumConcat = WidenNumElts / InNumElts;
3825 SmallVector<SDValue, 16> Ops(NumConcat);
3826 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
3829 for (unsigned i = 1; i != NumConcat; ++i)
3832 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3835 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3837 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3838 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3840 // Fall back to extract and build.
3841 SmallVector<SDValue, 16> Ops(WidenNumElts);
3842 EVT EltVT = NVT.getVectorElementType();
3843 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3845 for (Idx = 0; Idx < MinNumElts; ++Idx)
3846 Ops[Idx] = DAG.getNode(
3847 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3848 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3850 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
3851 DAG.getUNDEF(EltVT);
3852 for ( ; Idx < WidenNumElts; ++Idx)
3854 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);