1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
133 // If R is null, the sub-method took care of registering the result.
135 SetScalarizedVector(SDValue(N, ResNo), R);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
142 LHS.getValueType(), LHS, RHS);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
149 return DAG.getNode(N->getOpcode(), SDLoc(N),
150 Op0.getValueType(), Op0, Op1, Op2);
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
160 EVT NewVT = N->getValueType(0).getVectorElementType();
161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
162 NewVT, N->getOperand(0));
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
166 EVT EltVT = N->getValueType(0).getVectorElementType();
167 SDValue InOp = N->getOperand(0);
168 // The BUILD_VECTOR operands may be of wider element types and
169 // we may need to truncate them back to the requested return type.
170 if (EltVT.isInteger())
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
179 Op0, DAG.getValueType(NewVT),
180 DAG.getValueType(Op0.getValueType()),
183 cast<CvtRndSatSDNode>(N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
188 N->getValueType(0).getVectorElementType(),
189 N->getOperand(0), N->getOperand(1));
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
193 EVT NewVT = N->getValueType(0).getVectorElementType();
194 SDValue Op = GetScalarizedVector(N->getOperand(0));
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
196 NewVT, Op, N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
200 SDValue Op = GetScalarizedVector(N->getOperand(0));
201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
202 Op.getValueType(), Op, N->getOperand(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
206 // The value to insert may have a wider type than the vector element type,
207 // so be sure to truncate it to the element type if necessary.
208 SDValue Op = N->getOperand(1);
209 EVT EltVT = N->getValueType(0).getVectorElementType();
210 if (Op.getValueType() != EltVT)
211 // FIXME: Can this happen for floating point types?
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
217 assert(N->isUnindexed() && "Indexed vector load?");
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
220 N->getExtensionType(),
221 N->getValueType(0).getVectorElementType(),
223 N->getChain(), N->getBasePtr(),
224 DAG.getUNDEF(N->getBasePtr().getValueType()),
226 N->getMemoryVT().getVectorElementType(),
227 N->isVolatile(), N->isNonTemporal(),
228 N->isInvariant(), N->getOriginalAlignment(),
231 // Legalized the chain result - switch anything that used the old chain to
233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
239 EVT DestVT = N->getValueType(0).getVectorElementType();
240 SDValue Op = N->getOperand(0);
241 EVT OpVT = Op.getValueType();
243 // The result needs scalarizing, but it's not a given that the source does.
244 // This is a workaround for targets where it's impossible to scalarize the
245 // result of a conversion, because the source type is legal.
246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
248 // legal and was not scalarized.
249 // See the similar logic in ScalarizeVecRes_VSETCC
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
251 Op = GetScalarizedVector(Op);
253 EVT VT = OpVT.getVectorElementType();
254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
255 DAG.getConstant(0, TLI.getVectorIdxTy()));
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
261 EVT EltVT = N->getValueType(0).getVectorElementType();
262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
265 LHS, DAG.getValueType(ExtVT));
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
269 // If the operand is wider than the vector element type then it is implicitly
270 // truncated. Make that explicit here.
271 EVT EltVT = N->getValueType(0).getVectorElementType();
272 SDValue InOp = N->getOperand(0);
273 if (InOp.getValueType() != EltVT)
274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
281 TargetLowering::BooleanContent ScalarBool =
282 TLI.getBooleanContents(false, false);
283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
285 // If integer and float booleans have different contents then we can't
286 // reliably optimize in all cases. There is a full explanation for this in
287 // DAGCombiner::visitSELECT() where the same issue affects folding
288 // (select C, 0, 1) to (xor C, 1).
289 if (TLI.getBooleanContents(false, false) !=
290 TLI.getBooleanContents(false, true)) {
291 // At least try the common case where the boolean is generated by a
293 if (Cond->getOpcode() == ISD::SETCC) {
294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
296 VecBool = TLI.getBooleanContents(OpVT);
298 ScalarBool = TargetLowering::UndefinedBooleanContent;
301 if (ScalarBool != VecBool) {
302 EVT CondVT = Cond.getValueType();
303 switch (ScalarBool) {
304 case TargetLowering::UndefinedBooleanContent:
306 case TargetLowering::ZeroOrOneBooleanContent:
307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
309 // Vector read from all ones, scalar expects a single 1 so mask.
310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
311 Cond, DAG.getConstant(1, CondVT));
313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
316 // Vector reads from a one, scalar from all ones so sign extend.
317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 Cond, DAG.getValueType(MVT::i1));
323 return DAG.getSelect(SDLoc(N),
324 LHS.getValueType(), Cond, LHS,
325 GetScalarizedVector(N->getOperand(2)));
328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
330 return DAG.getSelect(SDLoc(N),
331 LHS.getValueType(), N->getOperand(0), LHS,
332 GetScalarizedVector(N->getOperand(2)));
335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
338 N->getOperand(0), N->getOperand(1),
339 LHS, GetScalarizedVector(N->getOperand(3)),
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
344 assert(N->getValueType(0).isVector() ==
345 N->getOperand(0).getValueType().isVector() &&
346 "Scalar/Vector type mismatch");
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
354 // Turn it into a scalar SETCC.
355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
363 // Figure out if the scalar is the LHS or RHS and return it.
364 SDValue Arg = N->getOperand(2).getOperand(0);
365 if (Arg.getOpcode() == ISD::UNDEF)
366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
368 return GetScalarizedVector(N->getOperand(Op));
371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
372 assert(N->getValueType(0).isVector() &&
373 N->getOperand(0).getValueType().isVector() &&
374 "Operand types must be vectors");
375 SDValue LHS = N->getOperand(0);
376 SDValue RHS = N->getOperand(1);
377 EVT OpVT = LHS.getValueType();
378 EVT NVT = N->getValueType(0).getVectorElementType();
381 // The result needs scalarizing, but it's not a given that the source does.
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
383 LHS = GetScalarizedVector(LHS);
384 RHS = GetScalarizedVector(RHS);
386 EVT VT = OpVT.getVectorElementType();
387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
388 DAG.getConstant(0, TLI.getVectorIdxTy()));
389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
390 DAG.getConstant(0, TLI.getVectorIdxTy()));
393 // Turn it into a scalar SETCC.
394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
396 // Vectors may have a different boolean contents to scalars. Promote the
397 // value appropriately.
398 ISD::NodeType ExtendCode =
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
400 return DAG.getNode(ExtendCode, DL, NVT, Res);
404 //===----------------------------------------------------------------------===//
405 // Operand Vector Scalarization <1 x ty> -> ty.
406 //===----------------------------------------------------------------------===//
408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
412 SDValue Res = SDValue();
414 if (!Res.getNode()) {
415 switch (N->getOpcode()) {
418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
424 Res = ScalarizeVecOp_BITCAST(N);
426 case ISD::ANY_EXTEND:
427 case ISD::ZERO_EXTEND:
428 case ISD::SIGN_EXTEND:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
434 Res = ScalarizeVecOp_UnaryOp(N);
436 case ISD::CONCAT_VECTORS:
437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
439 case ISD::EXTRACT_VECTOR_ELT:
440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
443 Res = ScalarizeVecOp_VSELECT(N);
446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
454 // If the result is null, the sub-method took care of registering results etc.
455 if (!Res.getNode()) return false;
457 // If the result is N, the sub-method updated N in place. Tell the legalizer
459 if (Res.getNode() == N)
462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
463 "Invalid operand expansion");
465 ReplaceValueWith(SDValue(N, 0), Res);
469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
474 N->getValueType(0), Elt);
477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
481 "Unexpected vector type!");
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
484 N->getValueType(0).getScalarType(), Elt);
485 // Revectorize the result so the types line up with what the uses of this
486 // expression expect.
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
491 /// use a BUILD_VECTOR instead.
492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
495 Ops[i] = GetScalarizedVector(N->getOperand(i));
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
503 SDValue Res = GetScalarizedVector(N->getOperand(0));
504 if (Res.getValueType() != N->getValueType(0))
505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
513 /// (still with vector output type since that was acceptable if we got here).
514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
516 EVT VT = N->getValueType(0);
518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
523 /// scalarized, it must be <1 x ty>. Just store the element.
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
529 if (N->isTruncatingStore())
530 return DAG.getTruncStore(N->getChain(), dl,
531 GetScalarizedVector(N->getOperand(1)),
532 N->getBasePtr(), N->getPointerInfo(),
533 N->getMemoryVT().getVectorElementType(),
534 N->isVolatile(), N->isNonTemporal(),
535 N->getAlignment(), N->getAAInfo());
537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getOriginalAlignment(), N->getAAInfo());
543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
548 N->getValueType(0).getVectorElementType(), Elt,
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
553 //===----------------------------------------------------------------------===//
554 // Result Vector Splitting
555 //===----------------------------------------------------------------------===//
557 /// SplitVectorResult - This method is called when the specified result of the
558 /// specified node is found to need vector splitting. At this point, the node
559 /// may also have invalid operands or may have other results that need
560 /// legalization, we just know that (at least) one result needs vector
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
563 DEBUG(dbgs() << "Split node result: ";
568 // See if the target wants to custom expand this node.
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
572 switch (N->getOpcode()) {
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
579 report_fatal_error("Do not know how to split the result of this "
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
604 SplitVecRes_SETCC(N, Lo, Hi);
606 case ISD::VECTOR_SHUFFLE:
607 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
611 case ISD::CONVERT_RNDSAT:
614 case ISD::CTLZ_ZERO_UNDEF:
615 case ISD::CTTZ_ZERO_UNDEF:
626 case ISD::FNEARBYINT:
630 case ISD::FP_TO_SINT:
631 case ISD::FP_TO_UINT:
637 case ISD::SINT_TO_FP:
639 case ISD::UINT_TO_FP:
640 SplitVecRes_UnaryOp(N, Lo, Hi);
643 case ISD::ANY_EXTEND:
644 case ISD::SIGN_EXTEND:
645 case ISD::ZERO_EXTEND:
646 SplitVecRes_ExtendOp(N, Lo, Hi);
671 SplitVecRes_BinOp(N, Lo, Hi);
674 SplitVecRes_TernaryOp(N, Lo, Hi);
678 // If Lo/Hi is null, the sub-method took care of registering results etc.
680 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
683 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
685 SDValue LHSLo, LHSHi;
686 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
687 SDValue RHSLo, RHSHi;
688 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
691 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
692 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
695 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
697 SDValue Op0Lo, Op0Hi;
698 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
699 SDValue Op1Lo, Op1Hi;
700 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
701 SDValue Op2Lo, Op2Hi;
702 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
705 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
706 Op0Lo, Op1Lo, Op2Lo);
707 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
708 Op0Hi, Op1Hi, Op2Hi);
711 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
713 // We know the result is a vector. The input may be either a vector or a
716 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
719 SDValue InOp = N->getOperand(0);
720 EVT InVT = InOp.getValueType();
722 // Handle some special cases efficiently.
723 switch (getTypeAction(InVT)) {
724 case TargetLowering::TypeLegal:
725 case TargetLowering::TypePromoteInteger:
726 case TargetLowering::TypeSoftenFloat:
727 case TargetLowering::TypeScalarizeVector:
728 case TargetLowering::TypeWidenVector:
730 case TargetLowering::TypeExpandInteger:
731 case TargetLowering::TypeExpandFloat:
732 // A scalar to vector conversion, where the scalar needs expansion.
733 // If the vector is being split in two then we can just convert the
736 GetExpandedOp(InOp, Lo, Hi);
737 if (TLI.isBigEndian())
739 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
740 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
744 case TargetLowering::TypeSplitVector:
745 // If the input is a vector that needs to be split, convert each split
746 // piece of the input now.
747 GetSplitVector(InOp, Lo, Hi);
748 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
749 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
753 // In the general case, convert the input to an integer and split it by hand.
754 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
755 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
756 if (TLI.isBigEndian())
757 std::swap(LoIntVT, HiIntVT);
759 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
761 if (TLI.isBigEndian())
763 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
764 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
767 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
771 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
772 unsigned LoNumElts = LoVT.getVectorNumElements();
773 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
774 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
776 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
777 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
780 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
782 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
784 unsigned NumSubvectors = N->getNumOperands() / 2;
785 if (NumSubvectors == 1) {
786 Lo = N->getOperand(0);
787 Hi = N->getOperand(1);
792 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
794 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
795 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
797 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
798 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
801 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
803 SDValue Vec = N->getOperand(0);
804 SDValue Idx = N->getOperand(1);
808 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
810 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
811 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
812 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
813 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),
814 TLI.getVectorIdxTy()));
817 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
819 SDValue Vec = N->getOperand(0);
820 SDValue SubVec = N->getOperand(1);
821 SDValue Idx = N->getOperand(2);
823 GetSplitVector(Vec, Lo, Hi);
825 // Spill the vector to the stack.
826 EVT VecVT = Vec.getValueType();
827 EVT SubVecVT = VecVT.getVectorElementType();
828 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
829 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
830 MachinePointerInfo(), false, false, 0);
832 // Store the new subvector into the specified index.
833 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
834 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
835 unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
836 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
839 // Load the Lo part from the stack slot.
840 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
841 false, false, false, 0);
843 // Increment the pointer to the other part.
844 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
846 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
847 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
849 // Load the Hi part from the stack slot.
850 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
851 false, false, false, MinAlign(Alignment, IncrementSize));
854 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
857 GetSplitVector(N->getOperand(0), Lo, Hi);
858 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
859 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
862 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
864 SDValue LHSLo, LHSHi;
865 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
869 std::tie(LoVT, HiVT) =
870 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
872 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
873 DAG.getValueType(LoVT));
874 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
875 DAG.getValueType(HiVT));
878 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
880 SDValue Vec = N->getOperand(0);
881 SDValue Elt = N->getOperand(1);
882 SDValue Idx = N->getOperand(2);
884 GetSplitVector(Vec, Lo, Hi);
886 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
887 unsigned IdxVal = CIdx->getZExtValue();
888 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
889 if (IdxVal < LoNumElts)
890 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
891 Lo.getValueType(), Lo, Elt, Idx);
893 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
894 DAG.getConstant(IdxVal - LoNumElts,
895 TLI.getVectorIdxTy()));
899 // See if the target wants to custom expand this node.
900 if (CustomLowerNode(N, N->getValueType(0), true))
903 // Spill the vector to the stack.
904 EVT VecVT = Vec.getValueType();
905 EVT EltVT = VecVT.getVectorElementType();
906 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
907 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
908 MachinePointerInfo(), false, false, 0);
910 // Store the new element. This may be larger than the vector element type,
911 // so use a truncating store.
912 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
913 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
915 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
916 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
919 // Load the Lo part from the stack slot.
920 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
921 false, false, false, 0);
923 // Increment the pointer to the other part.
924 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
925 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
926 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
928 // Load the Hi part from the stack slot.
929 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
930 false, false, false, MinAlign(Alignment, IncrementSize));
933 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
937 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
938 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
939 Hi = DAG.getUNDEF(HiVT);
942 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
944 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
947 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
949 ISD::LoadExtType ExtType = LD->getExtensionType();
950 SDValue Ch = LD->getChain();
951 SDValue Ptr = LD->getBasePtr();
952 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
953 EVT MemoryVT = LD->getMemoryVT();
954 unsigned Alignment = LD->getOriginalAlignment();
955 bool isVolatile = LD->isVolatile();
956 bool isNonTemporal = LD->isNonTemporal();
957 bool isInvariant = LD->isInvariant();
958 AAMDNodes AAInfo = LD->getAAInfo();
960 EVT LoMemVT, HiMemVT;
961 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
963 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
964 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
965 isInvariant, Alignment, AAInfo);
967 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
968 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
969 DAG.getConstant(IncrementSize, Ptr.getValueType()));
970 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
971 LD->getPointerInfo().getWithOffset(IncrementSize),
972 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
975 // Build a factor node to remember that this load is independent of the
977 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
980 // Legalized the chain result - switch anything that used the old chain to
982 ReplaceValueWith(SDValue(LD, 1), Ch);
985 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
986 SDValue &Lo, SDValue &Hi) {
989 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
991 SDValue Ch = MLD->getChain();
992 SDValue Ptr = MLD->getBasePtr();
993 SDValue Mask = MLD->getMask();
994 unsigned Alignment = MLD->getOriginalAlignment();
996 // if Alignment is equal to the vector size,
997 // take the half of it for the second part
998 unsigned SecondHalfAlignment =
999 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1000 Alignment/2 : Alignment;
1002 SDValue MaskLo, MaskHi;
1003 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1005 EVT MemoryVT = MLD->getMemoryVT();
1006 EVT LoMemVT, HiMemVT;
1007 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1009 SDValue Src0 = MLD->getSrc0();
1010 SDValue Src0Lo, Src0Hi;
1011 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1013 MachineMemOperand *MMO = DAG.getMachineFunction().
1014 getMachineMemOperand(MLD->getPointerInfo(),
1015 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1016 Alignment, MLD->getAAInfo(), MLD->getRanges());
1018 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, MMO);
1020 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1021 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1022 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1024 MMO = DAG.getMachineFunction().
1025 getMachineMemOperand(MLD->getPointerInfo(),
1026 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1027 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1029 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, MMO);
1032 // Build a factor node to remember that this load is independent of the
1034 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1037 // Legalized the chain result - switch anything that used the old chain to
1039 ReplaceValueWith(SDValue(MLD, 1), Ch);
1043 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1044 assert(N->getValueType(0).isVector() &&
1045 N->getOperand(0).getValueType().isVector() &&
1046 "Operand types must be vectors");
1050 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1053 SDValue LL, LH, RL, RH;
1054 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1055 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1057 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1058 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1061 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1063 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1066 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1068 // If the input also splits, handle it directly for a compile time speedup.
1069 // Otherwise split it by hand.
1070 EVT InVT = N->getOperand(0).getValueType();
1071 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1072 GetSplitVector(N->getOperand(0), Lo, Hi);
1074 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1076 if (N->getOpcode() == ISD::FP_ROUND) {
1077 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1078 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1079 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1080 SDValue DTyOpLo = DAG.getValueType(LoVT);
1081 SDValue DTyOpHi = DAG.getValueType(HiVT);
1082 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1083 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1084 SDValue RndOp = N->getOperand(3);
1085 SDValue SatOp = N->getOperand(4);
1086 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1087 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1089 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1092 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1093 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1097 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1100 EVT SrcVT = N->getOperand(0).getValueType();
1101 EVT DestVT = N->getValueType(0);
1103 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1105 // We can do better than a generic split operation if the extend is doing
1106 // more than just doubling the width of the elements and the following are
1108 // - The number of vector elements is even,
1109 // - the source type is legal,
1110 // - the type of a split source is illegal,
1111 // - the type of an extended (by doubling element size) source is legal, and
1112 // - the type of that extended source when split is legal.
1114 // This won't necessarily completely legalize the operation, but it will
1115 // more effectively move in the right direction and prevent falling down
1116 // to scalarization in many cases due to the input vector being split too
1118 unsigned NumElements = SrcVT.getVectorNumElements();
1119 if ((NumElements & 1) == 0 &&
1120 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1121 LLVMContext &Ctx = *DAG.getContext();
1122 EVT NewSrcVT = EVT::getVectorVT(
1123 Ctx, EVT::getIntegerVT(
1124 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1127 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1128 EVT SplitLoVT, SplitHiVT;
1129 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1130 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1131 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1132 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1133 N->dump(&DAG); dbgs() << "\n");
1134 // Extend the source vector by one step.
1136 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1137 // Get the low and high halves of the new, extended one step, vector.
1138 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1139 // Extend those vector halves the rest of the way.
1140 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1141 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1145 // Fall back to the generic unary operator splitting otherwise.
1146 SplitVecRes_UnaryOp(N, Lo, Hi);
1149 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1150 SDValue &Lo, SDValue &Hi) {
1151 // The low and high parts of the original input give four input vectors.
1154 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1155 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1156 EVT NewVT = Inputs[0].getValueType();
1157 unsigned NewElts = NewVT.getVectorNumElements();
1159 // If Lo or Hi uses elements from at most two of the four input vectors, then
1160 // express it as a vector shuffle of those two inputs. Otherwise extract the
1161 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1162 SmallVector<int, 16> Ops;
1163 for (unsigned High = 0; High < 2; ++High) {
1164 SDValue &Output = High ? Hi : Lo;
1166 // Build a shuffle mask for the output, discovering on the fly which
1167 // input vectors to use as shuffle operands (recorded in InputUsed).
1168 // If building a suitable shuffle vector proves too hard, then bail
1169 // out with useBuildVector set.
1170 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1171 unsigned FirstMaskIdx = High * NewElts;
1172 bool useBuildVector = false;
1173 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1174 // The mask element. This indexes into the input.
1175 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1177 // The input vector this mask element indexes into.
1178 unsigned Input = (unsigned)Idx / NewElts;
1180 if (Input >= array_lengthof(Inputs)) {
1181 // The mask element does not index into any input vector.
1186 // Turn the index into an offset from the start of the input vector.
1187 Idx -= Input * NewElts;
1189 // Find or create a shuffle vector operand to hold this input.
1191 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1192 if (InputUsed[OpNo] == Input) {
1193 // This input vector is already an operand.
1195 } else if (InputUsed[OpNo] == -1U) {
1196 // Create a new operand for this input vector.
1197 InputUsed[OpNo] = Input;
1202 if (OpNo >= array_lengthof(InputUsed)) {
1203 // More than two input vectors used! Give up on trying to create a
1204 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1205 useBuildVector = true;
1209 // Add the mask index for the new shuffle vector.
1210 Ops.push_back(Idx + OpNo * NewElts);
1213 if (useBuildVector) {
1214 EVT EltVT = NewVT.getVectorElementType();
1215 SmallVector<SDValue, 16> SVOps;
1217 // Extract the input elements by hand.
1218 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1219 // The mask element. This indexes into the input.
1220 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1222 // The input vector this mask element indexes into.
1223 unsigned Input = (unsigned)Idx / NewElts;
1225 if (Input >= array_lengthof(Inputs)) {
1226 // The mask element is "undef" or indexes off the end of the input.
1227 SVOps.push_back(DAG.getUNDEF(EltVT));
1231 // Turn the index into an offset from the start of the input vector.
1232 Idx -= Input * NewElts;
1234 // Extract the vector element by hand.
1235 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1236 Inputs[Input], DAG.getConstant(Idx,
1237 TLI.getVectorIdxTy())));
1240 // Construct the Lo/Hi output using a BUILD_VECTOR.
1241 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1242 } else if (InputUsed[0] == -1U) {
1243 // No input vectors were used! The result is undefined.
1244 Output = DAG.getUNDEF(NewVT);
1246 SDValue Op0 = Inputs[InputUsed[0]];
1247 // If only one input was used, use an undefined vector for the other.
1248 SDValue Op1 = InputUsed[1] == -1U ?
1249 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1250 // At least one input vector was used. Create a new shuffle vector.
1251 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1259 //===----------------------------------------------------------------------===//
1260 // Operand Vector Splitting
1261 //===----------------------------------------------------------------------===//
1263 /// SplitVectorOperand - This method is called when the specified operand of the
1264 /// specified node is found to need vector splitting. At this point, all of the
1265 /// result types of the node are known to be legal, but other operands of the
1266 /// node may need legalization as well as the specified one.
1267 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1268 DEBUG(dbgs() << "Split node operand: ";
1271 SDValue Res = SDValue();
1273 // See if the target wants to custom split this node.
1274 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1277 if (!Res.getNode()) {
1278 switch (N->getOpcode()) {
1281 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1285 report_fatal_error("Do not know how to split this operator's "
1288 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1289 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1290 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1291 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1292 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1293 case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break;
1294 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1296 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1299 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1302 Res = SplitVecOp_VSELECT(N, OpNo);
1307 case ISD::FP_EXTEND:
1308 case ISD::FP_TO_SINT:
1309 case ISD::FP_TO_UINT:
1310 case ISD::SINT_TO_FP:
1311 case ISD::UINT_TO_FP:
1313 case ISD::SIGN_EXTEND:
1314 case ISD::ZERO_EXTEND:
1315 case ISD::ANY_EXTEND:
1316 Res = SplitVecOp_UnaryOp(N);
1321 // If the result is null, the sub-method took care of registering results etc.
1322 if (!Res.getNode()) return false;
1324 // If the result is N, the sub-method updated N in place. Tell the legalizer
1326 if (Res.getNode() == N)
1329 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1330 "Invalid operand expansion");
1332 ReplaceValueWith(SDValue(N, 0), Res);
1336 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1337 // The only possibility for an illegal operand is the mask, since result type
1338 // legalization would have handled this node already otherwise.
1339 assert(OpNo == 0 && "Illegal operand must be mask");
1341 SDValue Mask = N->getOperand(0);
1342 SDValue Src0 = N->getOperand(1);
1343 SDValue Src1 = N->getOperand(2);
1344 EVT Src0VT = Src0.getValueType();
1346 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1349 GetSplitVector(N->getOperand(0), Lo, Hi);
1350 assert(Lo.getValueType() == Hi.getValueType() &&
1351 "Lo and Hi have differing types");
1354 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1355 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1357 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1358 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1359 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1360 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1363 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1365 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1367 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1370 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1371 // The result has a legal vector type, but the input needs splitting.
1372 EVT ResVT = N->getValueType(0);
1375 GetSplitVector(N->getOperand(0), Lo, Hi);
1376 EVT InVT = Lo.getValueType();
1378 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1379 InVT.getVectorNumElements());
1381 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1382 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1384 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1387 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1388 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1389 // end up being split all the way down to individual components. Convert the
1390 // split pieces into integers and reassemble.
1392 GetSplitVector(N->getOperand(0), Lo, Hi);
1393 Lo = BitConvertToInteger(Lo);
1394 Hi = BitConvertToInteger(Hi);
1396 if (TLI.isBigEndian())
1399 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1400 JoinIntegers(Lo, Hi));
1403 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1404 // We know that the extracted result type is legal.
1405 EVT SubVT = N->getValueType(0);
1406 SDValue Idx = N->getOperand(1);
1409 GetSplitVector(N->getOperand(0), Lo, Hi);
1411 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1412 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1414 if (IdxVal < LoElts) {
1415 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1416 "Extracted subvector crosses vector split!");
1417 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1419 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1420 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1424 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1425 SDValue Vec = N->getOperand(0);
1426 SDValue Idx = N->getOperand(1);
1427 EVT VecVT = Vec.getValueType();
1429 if (isa<ConstantSDNode>(Idx)) {
1430 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1431 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1434 GetSplitVector(Vec, Lo, Hi);
1436 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1438 if (IdxVal < LoElts)
1439 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1440 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1441 DAG.getConstant(IdxVal - LoElts,
1442 Idx.getValueType())), 0);
1445 // See if the target wants to custom expand this node.
1446 if (CustomLowerNode(N, N->getValueType(0), true))
1449 // Store the vector to the stack.
1450 EVT EltVT = VecVT.getVectorElementType();
1452 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1453 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1454 MachinePointerInfo(), false, false, 0);
1456 // Load back the required element.
1457 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1458 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1459 MachinePointerInfo(), EltVT, false, false, false, 0);
1462 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1464 SDValue Ch = N->getChain();
1465 SDValue Ptr = N->getBasePtr();
1466 SDValue Mask = N->getMask();
1467 SDValue Data = N->getData();
1468 EVT MemoryVT = N->getMemoryVT();
1469 unsigned Alignment = N->getOriginalAlignment();
1472 EVT LoMemVT, HiMemVT;
1473 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1475 SDValue DataLo, DataHi;
1476 GetSplitVector(Data, DataLo, DataHi);
1477 SDValue MaskLo, MaskHi;
1478 GetSplitVector(Mask, MaskLo, MaskHi);
1480 // if Alignment is equal to the vector size,
1481 // take the half of it for the second part
1482 unsigned SecondHalfAlignment =
1483 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1484 Alignment/2 : Alignment;
1487 MachineMemOperand *MMO = DAG.getMachineFunction().
1488 getMachineMemOperand(N->getPointerInfo(),
1489 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1490 Alignment, N->getAAInfo(), N->getRanges());
1492 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, MMO);
1494 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1495 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1496 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1498 MMO = DAG.getMachineFunction().
1499 getMachineMemOperand(N->getPointerInfo(),
1500 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1501 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1503 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, MMO);
1506 // Build a factor node to remember that this store is independent of the
1508 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1512 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1513 assert(N->isUnindexed() && "Indexed store of vector?");
1514 assert(OpNo == 1 && "Can only split the stored value");
1517 bool isTruncating = N->isTruncatingStore();
1518 SDValue Ch = N->getChain();
1519 SDValue Ptr = N->getBasePtr();
1520 EVT MemoryVT = N->getMemoryVT();
1521 unsigned Alignment = N->getOriginalAlignment();
1522 bool isVol = N->isVolatile();
1523 bool isNT = N->isNonTemporal();
1524 AAMDNodes AAInfo = N->getAAInfo();
1526 GetSplitVector(N->getOperand(1), Lo, Hi);
1528 EVT LoMemVT, HiMemVT;
1529 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1531 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1534 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1535 LoMemVT, isVol, isNT, Alignment, AAInfo);
1537 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1538 isVol, isNT, Alignment, AAInfo);
1540 // Increment the pointer to the other half.
1541 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1542 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1545 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1546 N->getPointerInfo().getWithOffset(IncrementSize),
1547 HiMemVT, isVol, isNT, Alignment, AAInfo);
1549 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1550 N->getPointerInfo().getWithOffset(IncrementSize),
1551 isVol, isNT, Alignment, AAInfo);
1553 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1556 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1559 // The input operands all must have the same type, and we know the result
1560 // type is valid. Convert this to a buildvector which extracts all the
1562 // TODO: If the input elements are power-two vectors, we could convert this to
1563 // a new CONCAT_VECTORS node with elements that are half-wide.
1564 SmallVector<SDValue, 32> Elts;
1565 EVT EltVT = N->getValueType(0).getVectorElementType();
1566 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1567 SDValue Op = N->getOperand(op);
1568 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1570 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1571 Op, DAG.getConstant(i, TLI.getVectorIdxTy())));
1576 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1579 SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {
1580 // The result type is legal, but the input type is illegal. If splitting
1581 // ends up with the result type of each half still being legal, just
1582 // do that. If, however, that would result in an illegal result type,
1583 // we can try to get more clever with power-two vectors. Specifically,
1584 // split the input type, but also widen the result element size, then
1585 // concatenate the halves and truncate again. For example, consider a target
1586 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1587 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1588 // %inlo = v4i32 extract_subvector %in, 0
1589 // %inhi = v4i32 extract_subvector %in, 4
1590 // %lo16 = v4i16 trunc v4i32 %inlo
1591 // %hi16 = v4i16 trunc v4i32 %inhi
1592 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1593 // %res = v8i8 trunc v8i16 %in16
1595 // Without this transform, the original truncate would end up being
1596 // scalarized, which is pretty much always a last resort.
1597 SDValue InVec = N->getOperand(0);
1598 EVT InVT = InVec->getValueType(0);
1599 EVT OutVT = N->getValueType(0);
1600 unsigned NumElements = OutVT.getVectorNumElements();
1601 // Widening should have already made sure this is a power-two vector
1602 // if we're trying to split it at all. assert() that's true, just in case.
1603 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1605 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1606 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1608 // If the input elements are only 1/2 the width of the result elements,
1609 // just use the normal splitting. Our trick only work if there's room
1610 // to split more than once.
1611 if (InElementSize <= OutElementSize * 2)
1612 return SplitVecOp_UnaryOp(N);
1615 // Extract the halves of the input via extract_subvector.
1616 SDValue InLoVec, InHiVec;
1617 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1618 // Truncate them to 1/2 the element size.
1619 EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1620 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1622 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec);
1623 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);
1624 // Concatenate them to get the full intermediate truncation result.
1625 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1626 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1628 // Now finish up by truncating all the way down to the original result
1629 // type. This should normally be something that ends up being legal directly,
1630 // but in theory if a target has very wide vectors and an annoyingly
1631 // restricted set of legal types, this split can chain to build things up.
1632 return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1635 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1636 assert(N->getValueType(0).isVector() &&
1637 N->getOperand(0).getValueType().isVector() &&
1638 "Operand types must be vectors");
1639 // The result has a legal vector type, but the input needs splitting.
1640 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1642 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1643 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1644 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1645 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1646 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1648 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1649 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1650 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1651 return PromoteTargetBoolean(Con, N->getValueType(0));
1655 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1656 // The result has a legal vector type, but the input needs splitting.
1657 EVT ResVT = N->getValueType(0);
1660 GetSplitVector(N->getOperand(0), Lo, Hi);
1661 EVT InVT = Lo.getValueType();
1663 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1664 InVT.getVectorNumElements());
1666 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1667 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1669 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1674 //===----------------------------------------------------------------------===//
1675 // Result Vector Widening
1676 //===----------------------------------------------------------------------===//
1678 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1679 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1683 // See if the target wants to custom widen this node.
1684 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1687 SDValue Res = SDValue();
1688 switch (N->getOpcode()) {
1691 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1695 llvm_unreachable("Do not know how to widen the result of this operator!");
1697 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1698 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1699 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1700 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1701 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1702 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1703 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1704 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1705 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1706 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1707 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1709 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1710 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1711 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1712 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1713 case ISD::VECTOR_SHUFFLE:
1714 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1727 Res = WidenVecRes_Binary(N);
1731 case ISD::FCOPYSIGN:
1741 Res = WidenVecRes_BinaryCanTrap(N);
1745 Res = WidenVecRes_POWI(N);
1751 Res = WidenVecRes_Shift(N);
1754 case ISD::ANY_EXTEND:
1755 case ISD::FP_EXTEND:
1757 case ISD::FP_TO_SINT:
1758 case ISD::FP_TO_UINT:
1759 case ISD::SIGN_EXTEND:
1760 case ISD::SINT_TO_FP:
1762 case ISD::UINT_TO_FP:
1763 case ISD::ZERO_EXTEND:
1764 Res = WidenVecRes_Convert(N);
1780 case ISD::FNEARBYINT:
1787 Res = WidenVecRes_Unary(N);
1790 Res = WidenVecRes_Ternary(N);
1794 // If Res is null, the sub-method took care of registering the result.
1796 SetWidenedVector(SDValue(N, ResNo), Res);
1799 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
1800 // Ternary op widening.
1802 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1803 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1804 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1805 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
1806 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
1809 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1810 // Binary op widening.
1812 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1813 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1814 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1815 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1818 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
1819 // Binary op widening for operations that can trap.
1820 unsigned Opcode = N->getOpcode();
1822 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1823 EVT WidenEltVT = WidenVT.getVectorElementType();
1825 unsigned NumElts = VT.getVectorNumElements();
1826 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1827 NumElts = NumElts / 2;
1828 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1831 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1832 // Operation doesn't trap so just widen as normal.
1833 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1834 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1835 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1838 // No legal vector version so unroll the vector operation and then widen.
1840 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1842 // Since the operation can trap, apply operation on the original vector.
1844 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1845 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1846 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1848 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1849 unsigned ConcatEnd = 0; // Current ConcatOps index.
1850 int Idx = 0; // Current Idx into input vectors.
1852 // NumElts := greatest legal vector size (at most WidenVT)
1853 // while (orig. vector has unhandled elements) {
1854 // take munches of size NumElts from the beginning and add to ConcatOps
1855 // NumElts := next smaller supported vector size or 1
1857 while (CurNumElts != 0) {
1858 while (CurNumElts >= NumElts) {
1859 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1860 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1861 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1862 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1863 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1865 CurNumElts -= NumElts;
1868 NumElts = NumElts / 2;
1869 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1870 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1873 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1874 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1875 InOp1, DAG.getConstant(Idx,
1876 TLI.getVectorIdxTy()));
1877 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1878 InOp2, DAG.getConstant(Idx,
1879 TLI.getVectorIdxTy()));
1880 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1887 // Check to see if we have a single operation with the widen type.
1888 if (ConcatEnd == 1) {
1889 VT = ConcatOps[0].getValueType();
1891 return ConcatOps[0];
1894 // while (Some element of ConcatOps is not of type MaxVT) {
1895 // From the end of ConcatOps, collect elements of the same type and put
1896 // them into an op of the next larger supported type
1898 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1899 Idx = ConcatEnd - 1;
1900 VT = ConcatOps[Idx--].getValueType();
1901 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1904 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1908 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1909 } while (!TLI.isTypeLegal(NextVT));
1911 if (!VT.isVector()) {
1912 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1913 SDValue VecOp = DAG.getUNDEF(NextVT);
1914 unsigned NumToInsert = ConcatEnd - Idx - 1;
1915 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1916 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1917 ConcatOps[OpIdx], DAG.getConstant(i,
1918 TLI.getVectorIdxTy()));
1920 ConcatOps[Idx+1] = VecOp;
1921 ConcatEnd = Idx + 2;
1923 // Vector type, create a CONCAT_VECTORS of type NextVT
1924 SDValue undefVec = DAG.getUNDEF(VT);
1925 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1926 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1927 unsigned RealVals = ConcatEnd - Idx - 1;
1928 unsigned SubConcatEnd = 0;
1929 unsigned SubConcatIdx = Idx + 1;
1930 while (SubConcatEnd < RealVals)
1931 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1932 while (SubConcatEnd < OpsToConcat)
1933 SubConcatOps[SubConcatEnd++] = undefVec;
1934 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1935 NextVT, SubConcatOps);
1936 ConcatEnd = SubConcatIdx + 1;
1940 // Check to see if we have a single operation with the widen type.
1941 if (ConcatEnd == 1) {
1942 VT = ConcatOps[0].getValueType();
1944 return ConcatOps[0];
1947 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1948 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1949 if (NumOps != ConcatEnd ) {
1950 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1951 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1952 ConcatOps[j] = UndefVal;
1954 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
1955 makeArrayRef(ConcatOps.data(), NumOps));
1958 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1959 SDValue InOp = N->getOperand(0);
1962 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1963 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1965 EVT InVT = InOp.getValueType();
1966 EVT InEltVT = InVT.getVectorElementType();
1967 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1969 unsigned Opcode = N->getOpcode();
1970 unsigned InVTNumElts = InVT.getVectorNumElements();
1972 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1973 InOp = GetWidenedVector(N->getOperand(0));
1974 InVT = InOp.getValueType();
1975 InVTNumElts = InVT.getVectorNumElements();
1976 if (InVTNumElts == WidenNumElts) {
1977 if (N->getNumOperands() == 1)
1978 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1979 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1983 if (TLI.isTypeLegal(InWidenVT)) {
1984 // Because the result and the input are different vector types, widening
1985 // the result could create a legal type but widening the input might make
1986 // it an illegal type that might lead to repeatedly splitting the input
1987 // and then widening it. To avoid this, we widen the input only if
1988 // it results in a legal type.
1989 if (WidenNumElts % InVTNumElts == 0) {
1990 // Widen the input and call convert on the widened input vector.
1991 unsigned NumConcat = WidenNumElts/InVTNumElts;
1992 SmallVector<SDValue, 16> Ops(NumConcat);
1994 SDValue UndefVal = DAG.getUNDEF(InVT);
1995 for (unsigned i = 1; i != NumConcat; ++i)
1997 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
1998 if (N->getNumOperands() == 1)
1999 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2000 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2003 if (InVTNumElts % WidenNumElts == 0) {
2004 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
2005 InOp, DAG.getConstant(0,
2006 TLI.getVectorIdxTy()));
2007 // Extract the input and convert the shorten input vector.
2008 if (N->getNumOperands() == 1)
2009 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2010 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2014 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2015 SmallVector<SDValue, 16> Ops(WidenNumElts);
2016 EVT EltVT = WidenVT.getVectorElementType();
2017 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2019 for (i=0; i < MinElts; ++i) {
2020 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2021 DAG.getConstant(i, TLI.getVectorIdxTy()));
2022 if (N->getNumOperands() == 1)
2023 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2025 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2028 SDValue UndefVal = DAG.getUNDEF(EltVT);
2029 for (; i < WidenNumElts; ++i)
2032 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2035 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2036 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2037 SDValue InOp = GetWidenedVector(N->getOperand(0));
2038 SDValue ShOp = N->getOperand(1);
2039 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2042 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2043 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2044 SDValue InOp = GetWidenedVector(N->getOperand(0));
2045 SDValue ShOp = N->getOperand(1);
2047 EVT ShVT = ShOp.getValueType();
2048 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2049 ShOp = GetWidenedVector(ShOp);
2050 ShVT = ShOp.getValueType();
2052 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2053 ShVT.getVectorElementType(),
2054 WidenVT.getVectorNumElements());
2055 if (ShVT != ShWidenVT)
2056 ShOp = ModifyToType(ShOp, ShWidenVT);
2058 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2061 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2062 // Unary op widening.
2063 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2064 SDValue InOp = GetWidenedVector(N->getOperand(0));
2065 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2068 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2069 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2070 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2071 cast<VTSDNode>(N->getOperand(1))->getVT()
2072 .getVectorElementType(),
2073 WidenVT.getVectorNumElements());
2074 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2075 return DAG.getNode(N->getOpcode(), SDLoc(N),
2076 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2079 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2080 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2081 return GetWidenedVector(WidenVec);
2084 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2085 SDValue InOp = N->getOperand(0);
2086 EVT InVT = InOp.getValueType();
2087 EVT VT = N->getValueType(0);
2088 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2091 switch (getTypeAction(InVT)) {
2092 case TargetLowering::TypeLegal:
2094 case TargetLowering::TypePromoteInteger:
2095 // If the incoming type is a vector that is being promoted, then
2096 // we know that the elements are arranged differently and that we
2097 // must perform the conversion using a stack slot.
2098 if (InVT.isVector())
2101 // If the InOp is promoted to the same size, convert it. Otherwise,
2102 // fall out of the switch and widen the promoted input.
2103 InOp = GetPromotedInteger(InOp);
2104 InVT = InOp.getValueType();
2105 if (WidenVT.bitsEq(InVT))
2106 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2108 case TargetLowering::TypeSoftenFloat:
2109 case TargetLowering::TypeExpandInteger:
2110 case TargetLowering::TypeExpandFloat:
2111 case TargetLowering::TypeScalarizeVector:
2112 case TargetLowering::TypeSplitVector:
2114 case TargetLowering::TypeWidenVector:
2115 // If the InOp is widened to the same size, convert it. Otherwise, fall
2116 // out of the switch and widen the widened input.
2117 InOp = GetWidenedVector(InOp);
2118 InVT = InOp.getValueType();
2119 if (WidenVT.bitsEq(InVT))
2120 // The input widens to the same size. Convert to the widen value.
2121 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2125 unsigned WidenSize = WidenVT.getSizeInBits();
2126 unsigned InSize = InVT.getSizeInBits();
2127 // x86mmx is not an acceptable vector element type, so don't try.
2128 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2129 // Determine new input vector type. The new input vector type will use
2130 // the same element type (if its a vector) or use the input type as a
2131 // vector. It is the same size as the type to widen to.
2133 unsigned NewNumElts = WidenSize / InSize;
2134 if (InVT.isVector()) {
2135 EVT InEltVT = InVT.getVectorElementType();
2136 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2137 WidenSize / InEltVT.getSizeInBits());
2139 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2142 if (TLI.isTypeLegal(NewInVT)) {
2143 // Because the result and the input are different vector types, widening
2144 // the result could create a legal type but widening the input might make
2145 // it an illegal type that might lead to repeatedly splitting the input
2146 // and then widening it. To avoid this, we widen the input only if
2147 // it results in a legal type.
2148 SmallVector<SDValue, 16> Ops(NewNumElts);
2149 SDValue UndefVal = DAG.getUNDEF(InVT);
2151 for (unsigned i = 1; i < NewNumElts; ++i)
2155 if (InVT.isVector())
2156 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2158 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2159 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2163 return CreateStackStoreLoad(InOp, WidenVT);
2166 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2168 // Build a vector with undefined for the new nodes.
2169 EVT VT = N->getValueType(0);
2171 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2172 // type. The UNDEFs need to have the same type as the existing operands.
2173 EVT EltVT = N->getOperand(0).getValueType();
2174 unsigned NumElts = VT.getVectorNumElements();
2176 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2177 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2179 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2180 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2181 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2183 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2186 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2187 EVT InVT = N->getOperand(0).getValueType();
2188 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2190 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2191 unsigned NumInElts = InVT.getVectorNumElements();
2192 unsigned NumOperands = N->getNumOperands();
2194 bool InputWidened = false; // Indicates we need to widen the input.
2195 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2196 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2197 // Add undef vectors to widen to correct length.
2198 unsigned NumConcat = WidenVT.getVectorNumElements() /
2199 InVT.getVectorNumElements();
2200 SDValue UndefVal = DAG.getUNDEF(InVT);
2201 SmallVector<SDValue, 16> Ops(NumConcat);
2202 for (unsigned i=0; i < NumOperands; ++i)
2203 Ops[i] = N->getOperand(i);
2204 for (unsigned i = NumOperands; i != NumConcat; ++i)
2206 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2209 InputWidened = true;
2210 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2211 // The inputs and the result are widen to the same value.
2213 for (i=1; i < NumOperands; ++i)
2214 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2217 if (i == NumOperands)
2218 // Everything but the first operand is an UNDEF so just return the
2219 // widened first operand.
2220 return GetWidenedVector(N->getOperand(0));
2222 if (NumOperands == 2) {
2223 // Replace concat of two operands with a shuffle.
2224 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2225 for (unsigned i = 0; i < NumInElts; ++i) {
2227 MaskOps[i + NumInElts] = i + WidenNumElts;
2229 return DAG.getVectorShuffle(WidenVT, dl,
2230 GetWidenedVector(N->getOperand(0)),
2231 GetWidenedVector(N->getOperand(1)),
2237 // Fall back to use extracts and build vector.
2238 EVT EltVT = WidenVT.getVectorElementType();
2239 SmallVector<SDValue, 16> Ops(WidenNumElts);
2241 for (unsigned i=0; i < NumOperands; ++i) {
2242 SDValue InOp = N->getOperand(i);
2244 InOp = GetWidenedVector(InOp);
2245 for (unsigned j=0; j < NumInElts; ++j)
2246 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2247 DAG.getConstant(j, TLI.getVectorIdxTy()));
2249 SDValue UndefVal = DAG.getUNDEF(EltVT);
2250 for (; Idx < WidenNumElts; ++Idx)
2251 Ops[Idx] = UndefVal;
2252 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2255 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2257 SDValue InOp = N->getOperand(0);
2258 SDValue RndOp = N->getOperand(3);
2259 SDValue SatOp = N->getOperand(4);
2261 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2262 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2264 EVT InVT = InOp.getValueType();
2265 EVT InEltVT = InVT.getVectorElementType();
2266 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2268 SDValue DTyOp = DAG.getValueType(WidenVT);
2269 SDValue STyOp = DAG.getValueType(InWidenVT);
2270 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2272 unsigned InVTNumElts = InVT.getVectorNumElements();
2273 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2274 InOp = GetWidenedVector(InOp);
2275 InVT = InOp.getValueType();
2276 InVTNumElts = InVT.getVectorNumElements();
2277 if (InVTNumElts == WidenNumElts)
2278 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2282 if (TLI.isTypeLegal(InWidenVT)) {
2283 // Because the result and the input are different vector types, widening
2284 // the result could create a legal type but widening the input might make
2285 // it an illegal type that might lead to repeatedly splitting the input
2286 // and then widening it. To avoid this, we widen the input only if
2287 // it results in a legal type.
2288 if (WidenNumElts % InVTNumElts == 0) {
2289 // Widen the input and call convert on the widened input vector.
2290 unsigned NumConcat = WidenNumElts/InVTNumElts;
2291 SmallVector<SDValue, 16> Ops(NumConcat);
2293 SDValue UndefVal = DAG.getUNDEF(InVT);
2294 for (unsigned i = 1; i != NumConcat; ++i)
2297 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2298 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2302 if (InVTNumElts % WidenNumElts == 0) {
2303 // Extract the input and convert the shorten input vector.
2304 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2305 DAG.getConstant(0, TLI.getVectorIdxTy()));
2306 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2311 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2312 SmallVector<SDValue, 16> Ops(WidenNumElts);
2313 EVT EltVT = WidenVT.getVectorElementType();
2314 DTyOp = DAG.getValueType(EltVT);
2315 STyOp = DAG.getValueType(InEltVT);
2317 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2319 for (i=0; i < MinElts; ++i) {
2320 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2321 DAG.getConstant(i, TLI.getVectorIdxTy()));
2322 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2326 SDValue UndefVal = DAG.getUNDEF(EltVT);
2327 for (; i < WidenNumElts; ++i)
2330 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2333 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2334 EVT VT = N->getValueType(0);
2335 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2336 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2337 SDValue InOp = N->getOperand(0);
2338 SDValue Idx = N->getOperand(1);
2341 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2342 InOp = GetWidenedVector(InOp);
2344 EVT InVT = InOp.getValueType();
2346 // Check if we can just return the input vector after widening.
2347 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2348 if (IdxVal == 0 && InVT == WidenVT)
2351 // Check if we can extract from the vector.
2352 unsigned InNumElts = InVT.getVectorNumElements();
2353 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2354 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2356 // We could try widening the input to the right length but for now, extract
2357 // the original elements, fill the rest with undefs and build a vector.
2358 SmallVector<SDValue, 16> Ops(WidenNumElts);
2359 EVT EltVT = VT.getVectorElementType();
2360 unsigned NumElts = VT.getVectorNumElements();
2362 for (i=0; i < NumElts; ++i)
2363 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2364 DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));
2366 SDValue UndefVal = DAG.getUNDEF(EltVT);
2367 for (; i < WidenNumElts; ++i)
2369 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2372 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2373 SDValue InOp = GetWidenedVector(N->getOperand(0));
2374 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2375 InOp.getValueType(), InOp,
2376 N->getOperand(1), N->getOperand(2));
2379 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2380 LoadSDNode *LD = cast<LoadSDNode>(N);
2381 ISD::LoadExtType ExtType = LD->getExtensionType();
2384 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2385 if (ExtType != ISD::NON_EXTLOAD)
2386 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2388 Result = GenWidenVectorLoads(LdChain, LD);
2390 // If we generate a single load, we can use that for the chain. Otherwise,
2391 // build a factor node to remember the multiple loads are independent and
2394 if (LdChain.size() == 1)
2395 NewChain = LdChain[0];
2397 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2399 // Modified the chain - switch anything that used the old chain to use
2401 ReplaceValueWith(SDValue(N, 1), NewChain);
2406 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2407 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2408 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2409 WidenVT, N->getOperand(0));
2412 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2413 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2414 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2416 SDValue Cond1 = N->getOperand(0);
2417 EVT CondVT = Cond1.getValueType();
2418 if (CondVT.isVector()) {
2419 EVT CondEltVT = CondVT.getVectorElementType();
2420 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2421 CondEltVT, WidenNumElts);
2422 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2423 Cond1 = GetWidenedVector(Cond1);
2425 // If we have to split the condition there is no point in widening the
2426 // select. This would result in an cycle of widening the select ->
2427 // widening the condition operand -> splitting the condition operand ->
2428 // splitting the select -> widening the select. Instead split this select
2429 // further and widen the resulting type.
2430 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2431 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2432 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2436 if (Cond1.getValueType() != CondWidenVT)
2437 Cond1 = ModifyToType(Cond1, CondWidenVT);
2440 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2441 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2442 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2443 return DAG.getNode(N->getOpcode(), SDLoc(N),
2444 WidenVT, Cond1, InOp1, InOp2);
2447 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2448 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2449 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2450 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2451 InOp1.getValueType(), N->getOperand(0),
2452 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2455 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2456 assert(N->getValueType(0).isVector() ==
2457 N->getOperand(0).getValueType().isVector() &&
2458 "Scalar/Vector type mismatch");
2459 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2461 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2462 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2463 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2464 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2465 InOp1, InOp2, N->getOperand(2));
2468 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2469 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2470 return DAG.getUNDEF(WidenVT);
2473 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2474 EVT VT = N->getValueType(0);
2477 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2478 unsigned NumElts = VT.getVectorNumElements();
2479 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2481 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2482 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2484 // Adjust mask based on new input vector length.
2485 SmallVector<int, 16> NewMask;
2486 for (unsigned i = 0; i != NumElts; ++i) {
2487 int Idx = N->getMaskElt(i);
2488 if (Idx < (int)NumElts)
2489 NewMask.push_back(Idx);
2491 NewMask.push_back(Idx - NumElts + WidenNumElts);
2493 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2494 NewMask.push_back(-1);
2495 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2498 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2499 assert(N->getValueType(0).isVector() &&
2500 N->getOperand(0).getValueType().isVector() &&
2501 "Operands must be vectors");
2502 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2503 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2505 SDValue InOp1 = N->getOperand(0);
2506 EVT InVT = InOp1.getValueType();
2507 assert(InVT.isVector() && "can not widen non-vector type");
2508 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2509 InVT.getVectorElementType(), WidenNumElts);
2510 InOp1 = GetWidenedVector(InOp1);
2511 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2513 // Assume that the input and output will be widen appropriately. If not,
2514 // we will have to unroll it at some point.
2515 assert(InOp1.getValueType() == WidenInVT &&
2516 InOp2.getValueType() == WidenInVT &&
2517 "Input not widened to expected type!");
2519 return DAG.getNode(ISD::SETCC, SDLoc(N),
2520 WidenVT, InOp1, InOp2, N->getOperand(2));
2524 //===----------------------------------------------------------------------===//
2525 // Widen Vector Operand
2526 //===----------------------------------------------------------------------===//
2527 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2528 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2531 SDValue Res = SDValue();
2533 // See if the target wants to custom widen this node.
2534 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2537 switch (N->getOpcode()) {
2540 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2544 llvm_unreachable("Do not know how to widen this operator's operand!");
2546 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2547 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2548 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2549 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2550 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2551 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2553 case ISD::ANY_EXTEND:
2554 case ISD::SIGN_EXTEND:
2555 case ISD::ZERO_EXTEND:
2556 Res = WidenVecOp_EXTEND(N);
2559 case ISD::FP_EXTEND:
2560 case ISD::FP_TO_SINT:
2561 case ISD::FP_TO_UINT:
2562 case ISD::SINT_TO_FP:
2563 case ISD::UINT_TO_FP:
2565 Res = WidenVecOp_Convert(N);
2569 // If Res is null, the sub-method took care of registering the result.
2570 if (!Res.getNode()) return false;
2572 // If the result is N, the sub-method updated N in place. Tell the legalizer
2574 if (Res.getNode() == N)
2578 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2579 "Invalid operand expansion");
2581 ReplaceValueWith(SDValue(N, 0), Res);
2585 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2587 EVT VT = N->getValueType(0);
2589 SDValue InOp = N->getOperand(0);
2590 // If some legalization strategy other than widening is used on the operand,
2591 // we can't safely assume that just extending the low lanes is the correct
2593 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2594 return WidenVecOp_Convert(N);
2595 InOp = GetWidenedVector(InOp);
2596 assert(VT.getVectorNumElements() <
2597 InOp.getValueType().getVectorNumElements() &&
2598 "Input wasn't widened!");
2600 // We may need to further widen the operand until it has the same total
2601 // vector size as the result.
2602 EVT InVT = InOp.getValueType();
2603 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2604 EVT InEltVT = InVT.getVectorElementType();
2605 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2606 EVT FixedVT = (MVT::SimpleValueType)i;
2607 EVT FixedEltVT = FixedVT.getVectorElementType();
2608 if (TLI.isTypeLegal(FixedVT) &&
2609 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2610 FixedEltVT == InEltVT) {
2611 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2612 "Not enough elements in the fixed type for the operand!");
2613 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2614 "We can't have the same type as we started with!");
2615 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2616 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2617 DAG.getUNDEF(FixedVT), InOp,
2618 DAG.getConstant(0, TLI.getVectorIdxTy()));
2620 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2621 DAG.getConstant(0, TLI.getVectorIdxTy()));
2625 InVT = InOp.getValueType();
2626 if (InVT.getSizeInBits() != VT.getSizeInBits())
2627 // We couldn't find a legal vector type that was a widening of the input
2628 // and could be extended in-register to the result type, so we have to
2630 return WidenVecOp_Convert(N);
2633 // Use special DAG nodes to represent the operation of extending the
2635 switch (N->getOpcode()) {
2637 llvm_unreachable("Extend legalization on on extend operation!");
2638 case ISD::ANY_EXTEND:
2639 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2640 case ISD::SIGN_EXTEND:
2641 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2642 case ISD::ZERO_EXTEND:
2643 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2647 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2648 // Since the result is legal and the input is illegal, it is unlikely
2649 // that we can fix the input to a legal type so unroll the convert
2650 // into some scalar code and create a nasty build vector.
2651 EVT VT = N->getValueType(0);
2652 EVT EltVT = VT.getVectorElementType();
2654 unsigned NumElts = VT.getVectorNumElements();
2655 SDValue InOp = N->getOperand(0);
2656 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2657 InOp = GetWidenedVector(InOp);
2658 EVT InVT = InOp.getValueType();
2659 EVT InEltVT = InVT.getVectorElementType();
2661 unsigned Opcode = N->getOpcode();
2662 SmallVector<SDValue, 16> Ops(NumElts);
2663 for (unsigned i=0; i < NumElts; ++i)
2664 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2665 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2666 DAG.getConstant(i, TLI.getVectorIdxTy())));
2668 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2671 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2672 EVT VT = N->getValueType(0);
2673 SDValue InOp = GetWidenedVector(N->getOperand(0));
2674 EVT InWidenVT = InOp.getValueType();
2677 // Check if we can convert between two legal vector types and extract.
2678 unsigned InWidenSize = InWidenVT.getSizeInBits();
2679 unsigned Size = VT.getSizeInBits();
2680 // x86mmx is not an acceptable vector element type, so don't try.
2681 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2682 unsigned NewNumElts = InWidenSize / Size;
2683 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2684 if (TLI.isTypeLegal(NewVT)) {
2685 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2686 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2687 DAG.getConstant(0, TLI.getVectorIdxTy()));
2691 return CreateStackStoreLoad(InOp, VT);
2694 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2695 // If the input vector is not legal, it is likely that we will not find a
2696 // legal vector of the same size. Replace the concatenate vector with a
2697 // nasty build vector.
2698 EVT VT = N->getValueType(0);
2699 EVT EltVT = VT.getVectorElementType();
2701 unsigned NumElts = VT.getVectorNumElements();
2702 SmallVector<SDValue, 16> Ops(NumElts);
2704 EVT InVT = N->getOperand(0).getValueType();
2705 unsigned NumInElts = InVT.getVectorNumElements();
2708 unsigned NumOperands = N->getNumOperands();
2709 for (unsigned i=0; i < NumOperands; ++i) {
2710 SDValue InOp = N->getOperand(i);
2711 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2712 InOp = GetWidenedVector(InOp);
2713 for (unsigned j=0; j < NumInElts; ++j)
2714 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2715 DAG.getConstant(j, TLI.getVectorIdxTy()));
2717 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2720 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2721 SDValue InOp = GetWidenedVector(N->getOperand(0));
2722 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2723 N->getValueType(0), InOp, N->getOperand(1));
2726 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2727 SDValue InOp = GetWidenedVector(N->getOperand(0));
2728 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2729 N->getValueType(0), InOp, N->getOperand(1));
2732 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2733 // We have to widen the value but we want only to store the original
2735 StoreSDNode *ST = cast<StoreSDNode>(N);
2737 SmallVector<SDValue, 16> StChain;
2738 if (ST->isTruncatingStore())
2739 GenWidenVectorTruncStores(StChain, ST);
2741 GenWidenVectorStores(StChain, ST);
2743 if (StChain.size() == 1)
2746 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
2749 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2750 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2751 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2754 // WARNING: In this code we widen the compare instruction with garbage.
2755 // This garbage may contain denormal floats which may be slow. Is this a real
2756 // concern ? Should we zero the unused lanes if this is a float compare ?
2758 // Get a new SETCC node to compare the newly widened operands.
2759 // Only some of the compared elements are legal.
2760 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
2761 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
2762 SVT, InOp0, InOp1, N->getOperand(2));
2764 // Extract the needed results from the result vector.
2765 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2766 SVT.getVectorElementType(),
2767 N->getValueType(0).getVectorNumElements());
2768 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2769 ResVT, WideSETCC, DAG.getConstant(0,
2770 TLI.getVectorIdxTy()));
2772 return PromoteTargetBoolean(CC, N->getValueType(0));
2776 //===----------------------------------------------------------------------===//
2777 // Vector Widening Utilities
2778 //===----------------------------------------------------------------------===//
2780 // Utility function to find the type to chop up a widen vector for load/store
2781 // TLI: Target lowering used to determine legal types.
2782 // Width: Width left need to load/store.
2783 // WidenVT: The widen vector type to load to/store from
2784 // Align: If 0, don't allow use of a wider type
2785 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2787 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2788 unsigned Width, EVT WidenVT,
2789 unsigned Align = 0, unsigned WidenEx = 0) {
2790 EVT WidenEltVT = WidenVT.getVectorElementType();
2791 unsigned WidenWidth = WidenVT.getSizeInBits();
2792 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2793 unsigned AlignInBits = Align*8;
2795 // If we have one element to load/store, return it.
2796 EVT RetVT = WidenEltVT;
2797 if (Width == WidenEltWidth)
2800 // See if there is larger legal integer than the element type to load/store
2802 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2803 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2804 EVT MemVT((MVT::SimpleValueType) VT);
2805 unsigned MemVTWidth = MemVT.getSizeInBits();
2806 if (MemVT.getSizeInBits() <= WidenEltWidth)
2808 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2809 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2810 (MemVTWidth <= Width ||
2811 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2817 // See if there is a larger vector type to load/store that has the same vector
2818 // element type and is evenly divisible with the WidenVT.
2819 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2820 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2821 EVT MemVT = (MVT::SimpleValueType) VT;
2822 unsigned MemVTWidth = MemVT.getSizeInBits();
2823 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2824 (WidenWidth % MemVTWidth) == 0 &&
2825 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2826 (MemVTWidth <= Width ||
2827 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2828 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2836 // Builds a vector type from scalar loads
2837 // VecTy: Resulting Vector type
2838 // LDOps: Load operators to build a vector type
2839 // [Start,End) the list of loads to use.
2840 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2841 SmallVectorImpl<SDValue> &LdOps,
2842 unsigned Start, unsigned End) {
2843 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2844 SDLoc dl(LdOps[Start]);
2845 EVT LdTy = LdOps[Start].getValueType();
2846 unsigned Width = VecTy.getSizeInBits();
2847 unsigned NumElts = Width / LdTy.getSizeInBits();
2848 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2851 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2853 for (unsigned i = Start + 1; i != End; ++i) {
2854 EVT NewLdTy = LdOps[i].getValueType();
2855 if (NewLdTy != LdTy) {
2856 NumElts = Width / NewLdTy.getSizeInBits();
2857 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2858 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2859 // Readjust position and vector position based on new load type
2860 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2863 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2864 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
2866 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2869 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
2871 // The strategy assumes that we can efficiently load powers of two widths.
2872 // The routines chops the vector into the largest vector loads with the same
2873 // element type or scalar loads and then recombines it to the widen vector
2875 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2876 unsigned WidenWidth = WidenVT.getSizeInBits();
2877 EVT LdVT = LD->getMemoryVT();
2879 assert(LdVT.isVector() && WidenVT.isVector());
2880 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2883 SDValue Chain = LD->getChain();
2884 SDValue BasePtr = LD->getBasePtr();
2885 unsigned Align = LD->getAlignment();
2886 bool isVolatile = LD->isVolatile();
2887 bool isNonTemporal = LD->isNonTemporal();
2888 bool isInvariant = LD->isInvariant();
2889 AAMDNodes AAInfo = LD->getAAInfo();
2891 int LdWidth = LdVT.getSizeInBits();
2892 int WidthDiff = WidenWidth - LdWidth; // Difference
2893 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2895 // Find the vector type that can load from.
2896 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2897 int NewVTWidth = NewVT.getSizeInBits();
2898 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2899 isVolatile, isNonTemporal, isInvariant, Align,
2901 LdChain.push_back(LdOp.getValue(1));
2903 // Check if we can load the element with one instruction
2904 if (LdWidth <= NewVTWidth) {
2905 if (!NewVT.isVector()) {
2906 unsigned NumElts = WidenWidth / NewVTWidth;
2907 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2908 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2909 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2911 if (NewVT == WidenVT)
2914 assert(WidenWidth % NewVTWidth == 0);
2915 unsigned NumConcat = WidenWidth / NewVTWidth;
2916 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2917 SDValue UndefVal = DAG.getUNDEF(NewVT);
2918 ConcatOps[0] = LdOp;
2919 for (unsigned i = 1; i != NumConcat; ++i)
2920 ConcatOps[i] = UndefVal;
2921 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
2924 // Load vector by using multiple loads from largest vector to scalar
2925 SmallVector<SDValue, 16> LdOps;
2926 LdOps.push_back(LdOp);
2928 LdWidth -= NewVTWidth;
2929 unsigned Offset = 0;
2931 while (LdWidth > 0) {
2932 unsigned Increment = NewVTWidth / 8;
2933 Offset += Increment;
2934 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2935 DAG.getConstant(Increment, BasePtr.getValueType()));
2938 if (LdWidth < NewVTWidth) {
2939 // Our current type we are using is too large, find a better size
2940 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2941 NewVTWidth = NewVT.getSizeInBits();
2942 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2943 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2944 isNonTemporal, isInvariant, MinAlign(Align, Increment),
2946 LdChain.push_back(L.getValue(1));
2947 if (L->getValueType(0).isVector()) {
2948 SmallVector<SDValue, 16> Loads;
2950 unsigned size = L->getValueSizeInBits(0);
2951 while (size < LdOp->getValueSizeInBits(0)) {
2952 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
2953 size += L->getValueSizeInBits(0);
2955 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
2958 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2959 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2960 isNonTemporal, isInvariant, MinAlign(Align, Increment),
2962 LdChain.push_back(L.getValue(1));
2968 LdWidth -= NewVTWidth;
2971 // Build the vector from the loads operations
2972 unsigned End = LdOps.size();
2973 if (!LdOps[0].getValueType().isVector())
2974 // All the loads are scalar loads.
2975 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2977 // If the load contains vectors, build the vector using concat vector.
2978 // All of the vectors used to loads are power of 2 and the scalars load
2979 // can be combined to make a power of 2 vector.
2980 SmallVector<SDValue, 16> ConcatOps(End);
2983 EVT LdTy = LdOps[i].getValueType();
2984 // First combine the scalar loads to a vector
2985 if (!LdTy.isVector()) {
2986 for (--i; i >= 0; --i) {
2987 LdTy = LdOps[i].getValueType();
2988 if (LdTy.isVector())
2991 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2993 ConcatOps[--Idx] = LdOps[i];
2994 for (--i; i >= 0; --i) {
2995 EVT NewLdTy = LdOps[i].getValueType();
2996 if (NewLdTy != LdTy) {
2997 // Create a larger vector
2998 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2999 makeArrayRef(&ConcatOps[Idx], End - Idx));
3003 ConcatOps[--Idx] = LdOps[i];
3006 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3007 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3008 makeArrayRef(&ConcatOps[Idx], End - Idx));
3010 // We need to fill the rest with undefs to build the vector
3011 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3012 SmallVector<SDValue, 16> WidenOps(NumOps);
3013 SDValue UndefVal = DAG.getUNDEF(LdTy);
3016 for (; i != End-Idx; ++i)
3017 WidenOps[i] = ConcatOps[Idx+i];
3018 for (; i != NumOps; ++i)
3019 WidenOps[i] = UndefVal;
3021 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3025 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3027 ISD::LoadExtType ExtType) {
3028 // For extension loads, it may not be more efficient to chop up the vector
3029 // and then extended it. Instead, we unroll the load and build a new vector.
3030 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3031 EVT LdVT = LD->getMemoryVT();
3033 assert(LdVT.isVector() && WidenVT.isVector());
3036 SDValue Chain = LD->getChain();
3037 SDValue BasePtr = LD->getBasePtr();
3038 unsigned Align = LD->getAlignment();
3039 bool isVolatile = LD->isVolatile();
3040 bool isNonTemporal = LD->isNonTemporal();
3041 bool isInvariant = LD->isInvariant();
3042 AAMDNodes AAInfo = LD->getAAInfo();
3044 EVT EltVT = WidenVT.getVectorElementType();
3045 EVT LdEltVT = LdVT.getVectorElementType();
3046 unsigned NumElts = LdVT.getVectorNumElements();
3048 // Load each element and widen
3049 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3050 SmallVector<SDValue, 16> Ops(WidenNumElts);
3051 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3052 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3053 LD->getPointerInfo(),
3054 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3056 LdChain.push_back(Ops[0].getValue(1));
3057 unsigned i = 0, Offset = Increment;
3058 for (i=1; i < NumElts; ++i, Offset += Increment) {
3059 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3061 DAG.getConstant(Offset,
3062 BasePtr.getValueType()));
3063 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3064 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3065 isVolatile, isNonTemporal, isInvariant, Align,
3067 LdChain.push_back(Ops[i].getValue(1));
3070 // Fill the rest with undefs
3071 SDValue UndefVal = DAG.getUNDEF(EltVT);
3072 for (; i != WidenNumElts; ++i)
3075 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3079 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3081 // The strategy assumes that we can efficiently store powers of two widths.
3082 // The routines chops the vector into the largest vector stores with the same
3083 // element type or scalar stores.
3084 SDValue Chain = ST->getChain();
3085 SDValue BasePtr = ST->getBasePtr();
3086 unsigned Align = ST->getAlignment();
3087 bool isVolatile = ST->isVolatile();
3088 bool isNonTemporal = ST->isNonTemporal();
3089 AAMDNodes AAInfo = ST->getAAInfo();
3090 SDValue ValOp = GetWidenedVector(ST->getValue());
3093 EVT StVT = ST->getMemoryVT();
3094 unsigned StWidth = StVT.getSizeInBits();
3095 EVT ValVT = ValOp.getValueType();
3096 unsigned ValWidth = ValVT.getSizeInBits();
3097 EVT ValEltVT = ValVT.getVectorElementType();
3098 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3099 assert(StVT.getVectorElementType() == ValEltVT);
3101 int Idx = 0; // current index to store
3102 unsigned Offset = 0; // offset from base to store
3103 while (StWidth != 0) {
3104 // Find the largest vector type we can store with
3105 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3106 unsigned NewVTWidth = NewVT.getSizeInBits();
3107 unsigned Increment = NewVTWidth / 8;
3108 if (NewVT.isVector()) {
3109 unsigned NumVTElts = NewVT.getVectorNumElements();
3111 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3112 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3113 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3114 ST->getPointerInfo().getWithOffset(Offset),
3115 isVolatile, isNonTemporal,
3116 MinAlign(Align, Offset), AAInfo));
3117 StWidth -= NewVTWidth;
3118 Offset += Increment;
3120 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3121 DAG.getConstant(Increment, BasePtr.getValueType()));
3122 } while (StWidth != 0 && StWidth >= NewVTWidth);
3124 // Cast the vector to the scalar type we can store
3125 unsigned NumElts = ValWidth / NewVTWidth;
3126 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3127 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3128 // Readjust index position based on new vector type
3129 Idx = Idx * ValEltWidth / NewVTWidth;
3131 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3132 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
3133 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3134 ST->getPointerInfo().getWithOffset(Offset),
3135 isVolatile, isNonTemporal,
3136 MinAlign(Align, Offset), AAInfo));
3137 StWidth -= NewVTWidth;
3138 Offset += Increment;
3139 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3140 DAG.getConstant(Increment, BasePtr.getValueType()));
3141 } while (StWidth != 0 && StWidth >= NewVTWidth);
3142 // Restore index back to be relative to the original widen element type
3143 Idx = Idx * NewVTWidth / ValEltWidth;
3149 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3151 // For extension loads, it may not be more efficient to truncate the vector
3152 // and then store it. Instead, we extract each element and then store it.
3153 SDValue Chain = ST->getChain();
3154 SDValue BasePtr = ST->getBasePtr();
3155 unsigned Align = ST->getAlignment();
3156 bool isVolatile = ST->isVolatile();
3157 bool isNonTemporal = ST->isNonTemporal();
3158 AAMDNodes AAInfo = ST->getAAInfo();
3159 SDValue ValOp = GetWidenedVector(ST->getValue());
3162 EVT StVT = ST->getMemoryVT();
3163 EVT ValVT = ValOp.getValueType();
3165 // It must be true that we the widen vector type is bigger than where
3166 // we need to store.
3167 assert(StVT.isVector() && ValOp.getValueType().isVector());
3168 assert(StVT.bitsLT(ValOp.getValueType()));
3170 // For truncating stores, we can not play the tricks of chopping legal
3171 // vector types and bit cast it to the right type. Instead, we unroll
3173 EVT StEltVT = StVT.getVectorElementType();
3174 EVT ValEltVT = ValVT.getVectorElementType();
3175 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3176 unsigned NumElts = StVT.getVectorNumElements();
3177 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3178 DAG.getConstant(0, TLI.getVectorIdxTy()));
3179 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3180 ST->getPointerInfo(), StEltVT,
3181 isVolatile, isNonTemporal, Align,
3183 unsigned Offset = Increment;
3184 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3185 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3186 BasePtr, DAG.getConstant(Offset,
3187 BasePtr.getValueType()));
3188 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3189 DAG.getConstant(0, TLI.getVectorIdxTy()));
3190 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3191 ST->getPointerInfo().getWithOffset(Offset),
3192 StEltVT, isVolatile, isNonTemporal,
3193 MinAlign(Align, Offset), AAInfo));
3197 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3198 /// input vector must have the same element type as NVT.
3199 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3200 // Note that InOp might have been widened so it might already have
3201 // the right width or it might need be narrowed.
3202 EVT InVT = InOp.getValueType();
3203 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3204 "input and widen element type must match");
3207 // Check if InOp already has the right width.
3211 unsigned InNumElts = InVT.getVectorNumElements();
3212 unsigned WidenNumElts = NVT.getVectorNumElements();
3213 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3214 unsigned NumConcat = WidenNumElts / InNumElts;
3215 SmallVector<SDValue, 16> Ops(NumConcat);
3216 SDValue UndefVal = DAG.getUNDEF(InVT);
3218 for (unsigned i = 1; i != NumConcat; ++i)
3221 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3224 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3225 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3226 DAG.getConstant(0, TLI.getVectorIdxTy()));
3228 // Fall back to extract and build.
3229 SmallVector<SDValue, 16> Ops(WidenNumElts);
3230 EVT EltVT = NVT.getVectorElementType();
3231 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3233 for (Idx = 0; Idx < MinNumElts; ++Idx)
3234 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3235 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3237 SDValue UndefVal = DAG.getUNDEF(EltVT);
3238 for ( ; Idx < WidenNumElts; ++Idx)
3239 Ops[Idx] = UndefVal;
3240 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);