1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
62 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
63 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
64 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
65 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
66 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
67 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
68 case ISD::ANY_EXTEND_VECTOR_INREG:
69 case ISD::SIGN_EXTEND_VECTOR_INREG:
70 case ISD::ZERO_EXTEND_VECTOR_INREG:
71 R = ScalarizeVecRes_VecInregOp(N);
77 case ISD::CTLZ_ZERO_UNDEF:
80 case ISD::CTTZ_ZERO_UNDEF:
100 case ISD::SIGN_EXTEND:
101 case ISD::SINT_TO_FP:
103 case ISD::UINT_TO_FP:
104 case ISD::ZERO_EXTEND:
105 case ISD::FCANONICALIZE:
106 R = ScalarizeVecRes_UnaryOp(N);
138 R = ScalarizeVecRes_BinOp(N);
141 R = ScalarizeVecRes_TernaryOp(N);
145 // If R is null, the sub-method took care of registering the result.
147 SetScalarizedVector(SDValue(N, ResNo), R);
150 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
151 SDValue LHS = GetScalarizedVector(N->getOperand(0));
152 SDValue RHS = GetScalarizedVector(N->getOperand(1));
153 return DAG.getNode(N->getOpcode(), SDLoc(N),
154 LHS.getValueType(), LHS, RHS, N->getFlags());
157 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
158 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
159 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
160 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
161 return DAG.getNode(N->getOpcode(), SDLoc(N),
162 Op0.getValueType(), Op0, Op1, Op2);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
167 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
168 return GetScalarizedVector(Op);
171 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
172 EVT NewVT = N->getValueType(0).getVectorElementType();
173 return DAG.getNode(ISD::BITCAST, SDLoc(N),
174 NewVT, N->getOperand(0));
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
178 EVT EltVT = N->getValueType(0).getVectorElementType();
179 SDValue InOp = N->getOperand(0);
180 // The BUILD_VECTOR operands may be of wider element types and
181 // we may need to truncate them back to the requested return type.
182 if (EltVT.isInteger())
183 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
187 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
188 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
189 N->getValueType(0).getVectorElementType(),
190 N->getOperand(0), N->getOperand(1));
193 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
194 EVT NewVT = N->getValueType(0).getVectorElementType();
195 SDValue Op = GetScalarizedVector(N->getOperand(0));
196 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
197 NewVT, Op, N->getOperand(1));
200 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
201 SDValue Op = GetScalarizedVector(N->getOperand(0));
202 return DAG.getNode(ISD::FPOWI, SDLoc(N),
203 Op.getValueType(), Op, N->getOperand(1));
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
207 // The value to insert may have a wider type than the vector element type,
208 // so be sure to truncate it to the element type if necessary.
209 SDValue Op = N->getOperand(1);
210 EVT EltVT = N->getValueType(0).getVectorElementType();
211 if (Op.getValueType() != EltVT)
212 // FIXME: Can this happen for floating point types?
213 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
217 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
218 assert(N->isUnindexed() && "Indexed vector load?");
220 SDValue Result = DAG.getLoad(
221 ISD::UNINDEXED, N->getExtensionType(),
222 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
223 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
224 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
225 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
228 // Legalize the chain result - switch anything that used the old chain to
230 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
234 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
235 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
236 EVT DestVT = N->getValueType(0).getVectorElementType();
237 SDValue Op = N->getOperand(0);
238 EVT OpVT = Op.getValueType();
240 // The result needs scalarizing, but it's not a given that the source does.
241 // This is a workaround for targets where it's impossible to scalarize the
242 // result of a conversion, because the source type is legal.
243 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
244 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
245 // legal and was not scalarized.
246 // See the similar logic in ScalarizeVecRes_SETCC
247 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
248 Op = GetScalarizedVector(Op);
250 EVT VT = OpVT.getVectorElementType();
252 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
253 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
255 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
258 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
259 EVT EltVT = N->getValueType(0).getVectorElementType();
260 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
261 SDValue LHS = GetScalarizedVector(N->getOperand(0));
262 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
263 LHS, DAG.getValueType(ExtVT));
266 SDValue DAGTypeLegalizer::ScalarizeVecRes_VecInregOp(SDNode *N) {
268 SDValue Op = N->getOperand(0);
270 EVT OpVT = Op.getValueType();
271 EVT OpEltVT = OpVT.getVectorElementType();
272 EVT EltVT = N->getValueType(0).getVectorElementType();
274 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
275 Op = GetScalarizedVector(Op);
278 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
279 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
282 switch (N->getOpcode()) {
283 case ISD::ANY_EXTEND_VECTOR_INREG:
284 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
285 case ISD::SIGN_EXTEND_VECTOR_INREG:
286 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
287 case ISD::ZERO_EXTEND_VECTOR_INREG:
288 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
291 llvm_unreachable("Illegal extend_vector_inreg opcode");
294 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
295 // If the operand is wider than the vector element type then it is implicitly
296 // truncated. Make that explicit here.
297 EVT EltVT = N->getValueType(0).getVectorElementType();
298 SDValue InOp = N->getOperand(0);
299 if (InOp.getValueType() != EltVT)
300 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
304 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
305 SDValue Cond = N->getOperand(0);
306 EVT OpVT = Cond.getValueType();
308 // The vselect result and true/value operands needs scalarizing, but it's
309 // not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
310 // See the similar logic in ScalarizeVecRes_SETCC
311 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
312 Cond = GetScalarizedVector(Cond);
314 EVT VT = OpVT.getVectorElementType();
316 ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond,
317 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
320 SDValue LHS = GetScalarizedVector(N->getOperand(1));
321 TargetLowering::BooleanContent ScalarBool =
322 TLI.getBooleanContents(false, false);
323 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
325 // If integer and float booleans have different contents then we can't
326 // reliably optimize in all cases. There is a full explanation for this in
327 // DAGCombiner::visitSELECT() where the same issue affects folding
328 // (select C, 0, 1) to (xor C, 1).
329 if (TLI.getBooleanContents(false, false) !=
330 TLI.getBooleanContents(false, true)) {
331 // At least try the common case where the boolean is generated by a
333 if (Cond->getOpcode() == ISD::SETCC) {
334 EVT OpVT = Cond->getOperand(0)->getValueType(0);
335 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
336 VecBool = TLI.getBooleanContents(OpVT);
338 ScalarBool = TargetLowering::UndefinedBooleanContent;
341 if (ScalarBool != VecBool) {
342 EVT CondVT = Cond.getValueType();
343 switch (ScalarBool) {
344 case TargetLowering::UndefinedBooleanContent:
346 case TargetLowering::ZeroOrOneBooleanContent:
347 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
348 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
349 // Vector read from all ones, scalar expects a single 1 so mask.
350 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
351 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
353 case TargetLowering::ZeroOrNegativeOneBooleanContent:
354 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
355 VecBool == TargetLowering::ZeroOrOneBooleanContent);
356 // Vector reads from a one, scalar from all ones so sign extend.
357 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
358 Cond, DAG.getValueType(MVT::i1));
363 return DAG.getSelect(SDLoc(N),
364 LHS.getValueType(), Cond, LHS,
365 GetScalarizedVector(N->getOperand(2)));
368 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
369 SDValue LHS = GetScalarizedVector(N->getOperand(1));
370 return DAG.getSelect(SDLoc(N),
371 LHS.getValueType(), N->getOperand(0), LHS,
372 GetScalarizedVector(N->getOperand(2)));
375 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
376 SDValue LHS = GetScalarizedVector(N->getOperand(2));
377 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
378 N->getOperand(0), N->getOperand(1),
379 LHS, GetScalarizedVector(N->getOperand(3)),
383 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
384 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
387 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
388 // Figure out if the scalar is the LHS or RHS and return it.
389 SDValue Arg = N->getOperand(2).getOperand(0);
391 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
392 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
393 return GetScalarizedVector(N->getOperand(Op));
396 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
397 assert(N->getValueType(0).isVector() &&
398 N->getOperand(0).getValueType().isVector() &&
399 "Operand types must be vectors");
400 SDValue LHS = N->getOperand(0);
401 SDValue RHS = N->getOperand(1);
402 EVT OpVT = LHS.getValueType();
403 EVT NVT = N->getValueType(0).getVectorElementType();
406 // The result needs scalarizing, but it's not a given that the source does.
407 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
408 LHS = GetScalarizedVector(LHS);
409 RHS = GetScalarizedVector(RHS);
411 EVT VT = OpVT.getVectorElementType();
413 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
414 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
416 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
417 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
420 // Turn it into a scalar SETCC.
421 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
423 // Vectors may have a different boolean contents to scalars. Promote the
424 // value appropriately.
425 ISD::NodeType ExtendCode =
426 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
427 return DAG.getNode(ExtendCode, DL, NVT, Res);
431 //===----------------------------------------------------------------------===//
432 // Operand Vector Scalarization <1 x ty> -> ty.
433 //===----------------------------------------------------------------------===//
435 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
436 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
439 SDValue Res = SDValue();
441 if (!Res.getNode()) {
442 switch (N->getOpcode()) {
445 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
449 report_fatal_error("Do not know how to scalarize this operator's "
452 Res = ScalarizeVecOp_BITCAST(N);
454 case ISD::ANY_EXTEND:
455 case ISD::ZERO_EXTEND:
456 case ISD::SIGN_EXTEND:
458 case ISD::FP_TO_SINT:
459 case ISD::FP_TO_UINT:
460 case ISD::SINT_TO_FP:
461 case ISD::UINT_TO_FP:
462 Res = ScalarizeVecOp_UnaryOp(N);
464 case ISD::CONCAT_VECTORS:
465 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
467 case ISD::EXTRACT_VECTOR_ELT:
468 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
471 Res = ScalarizeVecOp_VSELECT(N);
474 Res = ScalarizeVecOp_VSETCC(N);
477 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
480 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
485 // If the result is null, the sub-method took care of registering results etc.
486 if (!Res.getNode()) return false;
488 // If the result is N, the sub-method updated N in place. Tell the legalizer
490 if (Res.getNode() == N)
493 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
494 "Invalid operand expansion");
496 ReplaceValueWith(SDValue(N, 0), Res);
500 /// If the value to convert is a vector that needs to be scalarized, it must be
501 /// <1 x ty>. Convert the element instead.
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
503 SDValue Elt = GetScalarizedVector(N->getOperand(0));
504 return DAG.getNode(ISD::BITCAST, SDLoc(N),
505 N->getValueType(0), Elt);
508 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
509 /// Do the operation on the element instead.
510 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
511 assert(N->getValueType(0).getVectorNumElements() == 1 &&
512 "Unexpected vector type!");
513 SDValue Elt = GetScalarizedVector(N->getOperand(0));
514 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
515 N->getValueType(0).getScalarType(), Elt);
516 // Revectorize the result so the types line up with what the uses of this
517 // expression expect.
518 return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Op);
521 /// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
522 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
523 SmallVector<SDValue, 8> Ops(N->getNumOperands());
524 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
525 Ops[i] = GetScalarizedVector(N->getOperand(i));
526 return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
529 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
530 /// so just return the element, ignoring the index.
531 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
532 EVT VT = N->getValueType(0);
533 SDValue Res = GetScalarizedVector(N->getOperand(0));
534 if (Res.getValueType() != VT)
535 Res = VT.isFloatingPoint()
536 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res)
537 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res);
541 /// If the input condition is a vector that needs to be scalarized, it must be
542 /// <1 x i1>, so just convert to a normal ISD::SELECT
543 /// (still with vector output type since that was acceptable if we got here).
544 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
545 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
546 EVT VT = N->getValueType(0);
548 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
552 /// If the operand is a vector that needs to be scalarized then the
553 /// result must be v1i1, so just convert to a scalar SETCC and wrap
554 /// with a scalar_to_vector since the res type is legal if we got here
555 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSETCC(SDNode *N) {
556 assert(N->getValueType(0).isVector() &&
557 N->getOperand(0).getValueType().isVector() &&
558 "Operand types must be vectors");
559 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type");
561 EVT VT = N->getValueType(0);
562 SDValue LHS = GetScalarizedVector(N->getOperand(0));
563 SDValue RHS = GetScalarizedVector(N->getOperand(1));
565 EVT OpVT = N->getOperand(0).getValueType();
566 EVT NVT = VT.getVectorElementType();
568 // Turn it into a scalar SETCC.
569 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
572 // Vectors may have a different boolean contents to scalars. Promote the
573 // value appropriately.
574 ISD::NodeType ExtendCode =
575 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
577 Res = DAG.getNode(ExtendCode, DL, NVT, Res);
579 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
582 /// If the value to store is a vector that needs to be scalarized, it must be
583 /// <1 x ty>. Just store the element.
584 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
585 assert(N->isUnindexed() && "Indexed store of one-element vector?");
586 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
589 if (N->isTruncatingStore())
590 return DAG.getTruncStore(
591 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
592 N->getBasePtr(), N->getPointerInfo(),
593 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
594 N->getMemOperand()->getFlags(), N->getAAInfo());
596 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
597 N->getBasePtr(), N->getPointerInfo(),
598 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
602 /// If the value to round is a vector that needs to be scalarized, it must be
603 /// <1 x ty>. Convert the element instead.
604 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
605 SDValue Elt = GetScalarizedVector(N->getOperand(0));
606 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
607 N->getValueType(0).getVectorElementType(), Elt,
609 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
612 //===----------------------------------------------------------------------===//
613 // Result Vector Splitting
614 //===----------------------------------------------------------------------===//
616 /// This method is called when the specified result of the specified node is
617 /// found to need vector splitting. At this point, the node may also have
618 /// invalid operands or may have other results that need legalization, we just
619 /// know that (at least) one result needs vector splitting.
620 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
621 DEBUG(dbgs() << "Split node result: ";
626 // See if the target wants to custom expand this node.
627 if (CustomLowerNode(N, N->getValueType(ResNo), true))
630 switch (N->getOpcode()) {
633 dbgs() << "SplitVectorResult #" << ResNo << ": ";
637 report_fatal_error("Do not know how to split the result of this "
640 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
642 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
643 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
644 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
645 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
646 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
647 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
648 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
649 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
650 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
651 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
652 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
653 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
654 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
655 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
657 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
660 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
663 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
666 SplitVecRes_SETCC(N, Lo, Hi);
668 case ISD::VECTOR_SHUFFLE:
669 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
672 case ISD::ANY_EXTEND_VECTOR_INREG:
673 case ISD::SIGN_EXTEND_VECTOR_INREG:
674 case ISD::ZERO_EXTEND_VECTOR_INREG:
675 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
678 case ISD::BITREVERSE:
682 case ISD::CTLZ_ZERO_UNDEF:
683 case ISD::CTTZ_ZERO_UNDEF:
694 case ISD::FNEARBYINT:
698 case ISD::FP_TO_SINT:
699 case ISD::FP_TO_UINT:
705 case ISD::SINT_TO_FP:
707 case ISD::UINT_TO_FP:
708 case ISD::FCANONICALIZE:
709 SplitVecRes_UnaryOp(N, Lo, Hi);
712 case ISD::ANY_EXTEND:
713 case ISD::SIGN_EXTEND:
714 case ISD::ZERO_EXTEND:
715 SplitVecRes_ExtendOp(N, Lo, Hi);
747 SplitVecRes_BinOp(N, Lo, Hi);
750 SplitVecRes_TernaryOp(N, Lo, Hi);
754 // If Lo/Hi is null, the sub-method took care of registering results etc.
756 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
759 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
761 SDValue LHSLo, LHSHi;
762 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
763 SDValue RHSLo, RHSHi;
764 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
767 const SDNodeFlags Flags = N->getFlags();
768 unsigned Opcode = N->getOpcode();
769 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
770 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
773 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
775 SDValue Op0Lo, Op0Hi;
776 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
777 SDValue Op1Lo, Op1Hi;
778 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
779 SDValue Op2Lo, Op2Hi;
780 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
783 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
784 Op0Lo, Op1Lo, Op2Lo);
785 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
786 Op0Hi, Op1Hi, Op2Hi);
789 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
791 // We know the result is a vector. The input may be either a vector or a
794 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
797 SDValue InOp = N->getOperand(0);
798 EVT InVT = InOp.getValueType();
800 // Handle some special cases efficiently.
801 switch (getTypeAction(InVT)) {
802 case TargetLowering::TypeLegal:
803 case TargetLowering::TypePromoteInteger:
804 case TargetLowering::TypePromoteFloat:
805 case TargetLowering::TypeSoftenFloat:
806 case TargetLowering::TypeScalarizeVector:
807 case TargetLowering::TypeWidenVector:
809 case TargetLowering::TypeExpandInteger:
810 case TargetLowering::TypeExpandFloat:
811 // A scalar to vector conversion, where the scalar needs expansion.
812 // If the vector is being split in two then we can just convert the
815 GetExpandedOp(InOp, Lo, Hi);
816 if (DAG.getDataLayout().isBigEndian())
818 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
819 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
823 case TargetLowering::TypeSplitVector:
824 // If the input is a vector that needs to be split, convert each split
825 // piece of the input now.
826 GetSplitVector(InOp, Lo, Hi);
827 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
828 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
832 // In the general case, convert the input to an integer and split it by hand.
833 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
834 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
835 if (DAG.getDataLayout().isBigEndian())
836 std::swap(LoIntVT, HiIntVT);
838 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
840 if (DAG.getDataLayout().isBigEndian())
842 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
843 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
846 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
850 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
851 unsigned LoNumElts = LoVT.getVectorNumElements();
852 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
853 Lo = DAG.getBuildVector(LoVT, dl, LoOps);
855 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
856 Hi = DAG.getBuildVector(HiVT, dl, HiOps);
859 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
861 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
863 unsigned NumSubvectors = N->getNumOperands() / 2;
864 if (NumSubvectors == 1) {
865 Lo = N->getOperand(0);
866 Hi = N->getOperand(1);
871 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
873 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
874 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
876 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
877 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
880 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
882 SDValue Vec = N->getOperand(0);
883 SDValue Idx = N->getOperand(1);
887 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
889 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
890 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
891 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
892 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
893 TLI.getVectorIdxTy(DAG.getDataLayout())));
896 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
898 SDValue Vec = N->getOperand(0);
899 SDValue SubVec = N->getOperand(1);
900 SDValue Idx = N->getOperand(2);
902 GetSplitVector(Vec, Lo, Hi);
904 EVT VecVT = Vec.getValueType();
905 unsigned VecElems = VecVT.getVectorNumElements();
906 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
908 // If we know the index is 0, and we know the subvector doesn't cross the
909 // boundary between the halves, we can avoid spilling the vector, and insert
910 // into the lower half of the split vector directly.
911 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
912 // the index is constant and there is no boundary crossing. But those cases
913 // don't seem to get hit in practice.
914 if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
915 unsigned IdxVal = ConstIdx->getZExtValue();
916 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
918 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
919 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
924 // Spill the vector to the stack.
925 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
927 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
929 // Store the new subvector into the specified index.
930 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
931 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
932 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
933 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
935 // Load the Lo part from the stack slot.
937 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
939 // Increment the pointer to the other part.
940 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
942 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
943 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
945 // Load the Hi part from the stack slot.
946 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
947 MinAlign(Alignment, IncrementSize));
950 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
953 GetSplitVector(N->getOperand(0), Lo, Hi);
954 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
955 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
958 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
960 SDValue LHSLo, LHSHi;
961 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
964 SDValue RHSLo, RHSHi;
965 SDValue RHS = N->getOperand(1);
966 EVT RHSVT = RHS.getValueType();
967 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
968 GetSplitVector(RHS, RHSLo, RHSHi);
970 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
973 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
974 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
977 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
979 SDValue LHSLo, LHSHi;
980 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
984 std::tie(LoVT, HiVT) =
985 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
987 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
988 DAG.getValueType(LoVT));
989 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
990 DAG.getValueType(HiVT));
993 void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
995 unsigned Opcode = N->getOpcode();
996 SDValue N0 = N->getOperand(0);
1001 if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
1002 GetSplitVector(N0, InLo, InHi);
1004 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
1006 EVT InLoVT = InLo.getValueType();
1007 unsigned InNumElements = InLoVT.getVectorNumElements();
1009 EVT OutLoVT, OutHiVT;
1010 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1011 unsigned OutNumElements = OutLoVT.getVectorNumElements();
1012 assert((2 * OutNumElements) <= InNumElements &&
1013 "Illegal extend vector in reg split");
1015 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
1016 // input vector (i.e. we only use InLo):
1017 // OutLo will extend the first OutNumElements from InLo.
1018 // OutHi will extend the next OutNumElements from InLo.
1020 // Shuffle the elements from InLo for OutHi into the bottom elements to
1021 // create a 'fake' InHi.
1022 SmallVector<int, 8> SplitHi(InNumElements, -1);
1023 for (unsigned i = 0; i != OutNumElements; ++i)
1024 SplitHi[i] = i + OutNumElements;
1025 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
1027 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
1028 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
1031 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
1033 SDValue Vec = N->getOperand(0);
1034 SDValue Elt = N->getOperand(1);
1035 SDValue Idx = N->getOperand(2);
1037 GetSplitVector(Vec, Lo, Hi);
1039 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
1040 unsigned IdxVal = CIdx->getZExtValue();
1041 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1042 if (IdxVal < LoNumElts)
1043 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1044 Lo.getValueType(), Lo, Elt, Idx);
1047 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1048 DAG.getConstant(IdxVal - LoNumElts, dl,
1049 TLI.getVectorIdxTy(DAG.getDataLayout())));
1053 // See if the target wants to custom expand this node.
1054 if (CustomLowerNode(N, N->getValueType(0), true))
1057 // Spill the vector to the stack.
1058 EVT VecVT = Vec.getValueType();
1059 EVT EltVT = VecVT.getVectorElementType();
1060 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1061 auto &MF = DAG.getMachineFunction();
1062 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1063 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1064 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1066 // Store the new element. This may be larger than the vector element type,
1067 // so use a truncating store.
1068 SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1069 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1070 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1071 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr,
1072 MachinePointerInfo::getUnknownStack(MF), EltVT);
1074 // Load the Lo part from the stack slot.
1075 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, PtrInfo);
1077 // Increment the pointer to the other part.
1078 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
1079 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1080 DAG.getConstant(IncrementSize, dl,
1081 StackPtr.getValueType()));
1083 // Load the Hi part from the stack slot.
1084 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr,
1085 PtrInfo.getWithOffset(IncrementSize),
1086 MinAlign(Alignment, IncrementSize));
1089 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1093 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1094 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1095 Hi = DAG.getUNDEF(HiVT);
1098 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1100 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
1103 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1105 ISD::LoadExtType ExtType = LD->getExtensionType();
1106 SDValue Ch = LD->getChain();
1107 SDValue Ptr = LD->getBasePtr();
1108 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1109 EVT MemoryVT = LD->getMemoryVT();
1110 unsigned Alignment = LD->getOriginalAlignment();
1111 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1112 AAMDNodes AAInfo = LD->getAAInfo();
1114 EVT LoMemVT, HiMemVT;
1115 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1117 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1118 LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1120 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1121 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
1122 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1123 LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1124 Alignment, MMOFlags, AAInfo);
1126 // Build a factor node to remember that this load is independent of the
1128 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1131 // Legalize the chain result - switch anything that used the old chain to
1133 ReplaceValueWith(SDValue(LD, 1), Ch);
1136 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1137 SDValue &Lo, SDValue &Hi) {
1140 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1142 SDValue Ch = MLD->getChain();
1143 SDValue Ptr = MLD->getBasePtr();
1144 SDValue Mask = MLD->getMask();
1145 SDValue Src0 = MLD->getSrc0();
1146 unsigned Alignment = MLD->getOriginalAlignment();
1147 ISD::LoadExtType ExtType = MLD->getExtensionType();
1149 // if Alignment is equal to the vector size,
1150 // take the half of it for the second part
1151 unsigned SecondHalfAlignment =
1152 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1153 Alignment/2 : Alignment;
1155 // Split Mask operand
1156 SDValue MaskLo, MaskHi;
1157 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1158 GetSplitVector(Mask, MaskLo, MaskHi);
1160 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1162 EVT MemoryVT = MLD->getMemoryVT();
1163 EVT LoMemVT, HiMemVT;
1164 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1166 SDValue Src0Lo, Src0Hi;
1167 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1168 GetSplitVector(Src0, Src0Lo, Src0Hi);
1170 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1172 MachineMemOperand *MMO = DAG.getMachineFunction().
1173 getMachineMemOperand(MLD->getPointerInfo(),
1174 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1175 Alignment, MLD->getAAInfo(), MLD->getRanges());
1177 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1178 ExtType, MLD->isExpandingLoad());
1180 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1181 MLD->isExpandingLoad());
1183 MMO = DAG.getMachineFunction().
1184 getMachineMemOperand(MLD->getPointerInfo(),
1185 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1186 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1188 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1189 ExtType, MLD->isExpandingLoad());
1192 // Build a factor node to remember that this load is independent of the
1194 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1197 // Legalize the chain result - switch anything that used the old chain to
1199 ReplaceValueWith(SDValue(MLD, 1), Ch);
1203 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1204 SDValue &Lo, SDValue &Hi) {
1207 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1209 SDValue Ch = MGT->getChain();
1210 SDValue Ptr = MGT->getBasePtr();
1211 SDValue Mask = MGT->getMask();
1212 SDValue Src0 = MGT->getValue();
1213 SDValue Index = MGT->getIndex();
1214 unsigned Alignment = MGT->getOriginalAlignment();
1216 // Split Mask operand
1217 SDValue MaskLo, MaskHi;
1218 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1219 GetSplitVector(Mask, MaskLo, MaskHi);
1221 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1223 EVT MemoryVT = MGT->getMemoryVT();
1224 EVT LoMemVT, HiMemVT;
1226 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1228 SDValue Src0Lo, Src0Hi;
1229 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1230 GetSplitVector(Src0, Src0Lo, Src0Hi);
1232 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1234 SDValue IndexHi, IndexLo;
1235 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1236 GetSplitVector(Index, IndexLo, IndexHi);
1238 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1240 MachineMemOperand *MMO = DAG.getMachineFunction().
1241 getMachineMemOperand(MGT->getPointerInfo(),
1242 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1243 Alignment, MGT->getAAInfo(), MGT->getRanges());
1245 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1246 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1249 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1250 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1253 // Build a factor node to remember that this load is independent of the
1255 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1258 // Legalize the chain result - switch anything that used the old chain to
1260 ReplaceValueWith(SDValue(MGT, 1), Ch);
1264 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1265 assert(N->getValueType(0).isVector() &&
1266 N->getOperand(0).getValueType().isVector() &&
1267 "Operand types must be vectors");
1271 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1273 // If the input also splits, handle it directly. Otherwise split it by hand.
1274 SDValue LL, LH, RL, RH;
1275 if (getTypeAction(N->getOperand(0).getValueType()) ==
1276 TargetLowering::TypeSplitVector)
1277 GetSplitVector(N->getOperand(0), LL, LH);
1279 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1281 if (getTypeAction(N->getOperand(1).getValueType()) ==
1282 TargetLowering::TypeSplitVector)
1283 GetSplitVector(N->getOperand(1), RL, RH);
1285 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1287 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1288 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1291 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1293 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1296 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1298 // If the input also splits, handle it directly for a compile time speedup.
1299 // Otherwise split it by hand.
1300 EVT InVT = N->getOperand(0).getValueType();
1301 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1302 GetSplitVector(N->getOperand(0), Lo, Hi);
1304 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1306 if (N->getOpcode() == ISD::FP_ROUND) {
1307 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1308 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1310 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1311 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1315 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1318 EVT SrcVT = N->getOperand(0).getValueType();
1319 EVT DestVT = N->getValueType(0);
1321 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1323 // We can do better than a generic split operation if the extend is doing
1324 // more than just doubling the width of the elements and the following are
1326 // - The number of vector elements is even,
1327 // - the source type is legal,
1328 // - the type of a split source is illegal,
1329 // - the type of an extended (by doubling element size) source is legal, and
1330 // - the type of that extended source when split is legal.
1332 // This won't necessarily completely legalize the operation, but it will
1333 // more effectively move in the right direction and prevent falling down
1334 // to scalarization in many cases due to the input vector being split too
1336 unsigned NumElements = SrcVT.getVectorNumElements();
1337 if ((NumElements & 1) == 0 &&
1338 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1339 LLVMContext &Ctx = *DAG.getContext();
1340 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
1341 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
1343 EVT SplitLoVT, SplitHiVT;
1344 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1345 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1346 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1347 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1348 N->dump(&DAG); dbgs() << "\n");
1349 // Extend the source vector by one step.
1351 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1352 // Get the low and high halves of the new, extended one step, vector.
1353 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1354 // Extend those vector halves the rest of the way.
1355 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1356 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1360 // Fall back to the generic unary operator splitting otherwise.
1361 SplitVecRes_UnaryOp(N, Lo, Hi);
1364 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1365 SDValue &Lo, SDValue &Hi) {
1366 // The low and high parts of the original input give four input vectors.
1369 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1370 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1371 EVT NewVT = Inputs[0].getValueType();
1372 unsigned NewElts = NewVT.getVectorNumElements();
1374 // If Lo or Hi uses elements from at most two of the four input vectors, then
1375 // express it as a vector shuffle of those two inputs. Otherwise extract the
1376 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1377 SmallVector<int, 16> Ops;
1378 for (unsigned High = 0; High < 2; ++High) {
1379 SDValue &Output = High ? Hi : Lo;
1381 // Build a shuffle mask for the output, discovering on the fly which
1382 // input vectors to use as shuffle operands (recorded in InputUsed).
1383 // If building a suitable shuffle vector proves too hard, then bail
1384 // out with useBuildVector set.
1385 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1386 unsigned FirstMaskIdx = High * NewElts;
1387 bool useBuildVector = false;
1388 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1389 // The mask element. This indexes into the input.
1390 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1392 // The input vector this mask element indexes into.
1393 unsigned Input = (unsigned)Idx / NewElts;
1395 if (Input >= array_lengthof(Inputs)) {
1396 // The mask element does not index into any input vector.
1401 // Turn the index into an offset from the start of the input vector.
1402 Idx -= Input * NewElts;
1404 // Find or create a shuffle vector operand to hold this input.
1406 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1407 if (InputUsed[OpNo] == Input) {
1408 // This input vector is already an operand.
1410 } else if (InputUsed[OpNo] == -1U) {
1411 // Create a new operand for this input vector.
1412 InputUsed[OpNo] = Input;
1417 if (OpNo >= array_lengthof(InputUsed)) {
1418 // More than two input vectors used! Give up on trying to create a
1419 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1420 useBuildVector = true;
1424 // Add the mask index for the new shuffle vector.
1425 Ops.push_back(Idx + OpNo * NewElts);
1428 if (useBuildVector) {
1429 EVT EltVT = NewVT.getVectorElementType();
1430 SmallVector<SDValue, 16> SVOps;
1432 // Extract the input elements by hand.
1433 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1434 // The mask element. This indexes into the input.
1435 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1437 // The input vector this mask element indexes into.
1438 unsigned Input = (unsigned)Idx / NewElts;
1440 if (Input >= array_lengthof(Inputs)) {
1441 // The mask element is "undef" or indexes off the end of the input.
1442 SVOps.push_back(DAG.getUNDEF(EltVT));
1446 // Turn the index into an offset from the start of the input vector.
1447 Idx -= Input * NewElts;
1449 // Extract the vector element by hand.
1450 SVOps.push_back(DAG.getNode(
1451 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1452 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1455 // Construct the Lo/Hi output using a BUILD_VECTOR.
1456 Output = DAG.getBuildVector(NewVT, dl, SVOps);
1457 } else if (InputUsed[0] == -1U) {
1458 // No input vectors were used! The result is undefined.
1459 Output = DAG.getUNDEF(NewVT);
1461 SDValue Op0 = Inputs[InputUsed[0]];
1462 // If only one input was used, use an undefined vector for the other.
1463 SDValue Op1 = InputUsed[1] == -1U ?
1464 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1465 // At least one input vector was used. Create a new shuffle vector.
1466 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1474 //===----------------------------------------------------------------------===//
1475 // Operand Vector Splitting
1476 //===----------------------------------------------------------------------===//
1478 /// This method is called when the specified operand of the specified node is
1479 /// found to need vector splitting. At this point, all of the result types of
1480 /// the node are known to be legal, but other operands of the node may need
1481 /// legalization as well as the specified one.
1482 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1483 DEBUG(dbgs() << "Split node operand: ";
1486 SDValue Res = SDValue();
1488 // See if the target wants to custom split this node.
1489 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1492 if (!Res.getNode()) {
1493 switch (N->getOpcode()) {
1496 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1500 report_fatal_error("Do not know how to split this operator's "
1503 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1504 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1505 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1506 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1507 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1509 Res = SplitVecOp_TruncateHelper(N);
1511 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1512 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1514 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1517 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1520 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1523 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1526 Res = SplitVecOp_VSELECT(N, OpNo);
1528 case ISD::FP_TO_SINT:
1529 case ISD::FP_TO_UINT:
1530 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1531 Res = SplitVecOp_TruncateHelper(N);
1533 Res = SplitVecOp_UnaryOp(N);
1535 case ISD::SINT_TO_FP:
1536 case ISD::UINT_TO_FP:
1537 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1538 Res = SplitVecOp_TruncateHelper(N);
1540 Res = SplitVecOp_UnaryOp(N);
1545 case ISD::FP_EXTEND:
1546 case ISD::SIGN_EXTEND:
1547 case ISD::ZERO_EXTEND:
1548 case ISD::ANY_EXTEND:
1550 case ISD::FCANONICALIZE:
1551 Res = SplitVecOp_UnaryOp(N);
1554 case ISD::ANY_EXTEND_VECTOR_INREG:
1555 case ISD::SIGN_EXTEND_VECTOR_INREG:
1556 case ISD::ZERO_EXTEND_VECTOR_INREG:
1557 Res = SplitVecOp_ExtVecInRegOp(N);
1560 case ISD::VECREDUCE_FADD:
1561 case ISD::VECREDUCE_FMUL:
1562 case ISD::VECREDUCE_ADD:
1563 case ISD::VECREDUCE_MUL:
1564 case ISD::VECREDUCE_AND:
1565 case ISD::VECREDUCE_OR:
1566 case ISD::VECREDUCE_XOR:
1567 case ISD::VECREDUCE_SMAX:
1568 case ISD::VECREDUCE_SMIN:
1569 case ISD::VECREDUCE_UMAX:
1570 case ISD::VECREDUCE_UMIN:
1571 case ISD::VECREDUCE_FMAX:
1572 case ISD::VECREDUCE_FMIN:
1573 Res = SplitVecOp_VECREDUCE(N, OpNo);
1578 // If the result is null, the sub-method took care of registering results etc.
1579 if (!Res.getNode()) return false;
1581 // If the result is N, the sub-method updated N in place. Tell the legalizer
1583 if (Res.getNode() == N)
1586 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1587 "Invalid operand expansion");
1589 ReplaceValueWith(SDValue(N, 0), Res);
1593 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1594 // The only possibility for an illegal operand is the mask, since result type
1595 // legalization would have handled this node already otherwise.
1596 assert(OpNo == 0 && "Illegal operand must be mask");
1598 SDValue Mask = N->getOperand(0);
1599 SDValue Src0 = N->getOperand(1);
1600 SDValue Src1 = N->getOperand(2);
1601 EVT Src0VT = Src0.getValueType();
1603 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1606 GetSplitVector(N->getOperand(0), Lo, Hi);
1607 assert(Lo.getValueType() == Hi.getValueType() &&
1608 "Lo and Hi have differing types");
1611 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1612 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1614 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1615 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1616 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1617 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1620 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1622 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1624 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1627 SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo) {
1628 EVT ResVT = N->getValueType(0);
1632 SDValue VecOp = N->getOperand(OpNo);
1633 EVT VecVT = VecOp.getValueType();
1634 assert(VecVT.isVector() && "Can only split reduce vector operand");
1635 GetSplitVector(VecOp, Lo, Hi);
1637 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
1639 bool NoNaN = N->getFlags().hasNoNaNs();
1640 unsigned CombineOpc = 0;
1641 switch (N->getOpcode()) {
1642 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
1643 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
1644 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
1645 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
1646 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
1647 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
1648 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break;
1649 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
1650 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
1651 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
1652 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
1653 case ISD::VECREDUCE_FMAX:
1654 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXNAN;
1656 case ISD::VECREDUCE_FMIN:
1657 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN;
1660 llvm_unreachable("Unexpected reduce ISD node");
1663 // Use the appropriate scalar instruction on the split subvectors before
1664 // reducing the now partially reduced smaller vector.
1665 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi);
1666 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial);
1669 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1670 // The result has a legal vector type, but the input needs splitting.
1671 EVT ResVT = N->getValueType(0);
1674 GetSplitVector(N->getOperand(0), Lo, Hi);
1675 EVT InVT = Lo.getValueType();
1677 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1678 InVT.getVectorNumElements());
1680 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1681 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1683 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1686 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1687 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1688 // end up being split all the way down to individual components. Convert the
1689 // split pieces into integers and reassemble.
1691 GetSplitVector(N->getOperand(0), Lo, Hi);
1692 Lo = BitConvertToInteger(Lo);
1693 Hi = BitConvertToInteger(Hi);
1695 if (DAG.getDataLayout().isBigEndian())
1698 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1699 JoinIntegers(Lo, Hi));
1702 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1703 // We know that the extracted result type is legal.
1704 EVT SubVT = N->getValueType(0);
1705 SDValue Idx = N->getOperand(1);
1708 GetSplitVector(N->getOperand(0), Lo, Hi);
1710 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1711 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1713 if (IdxVal < LoElts) {
1714 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1715 "Extracted subvector crosses vector split!");
1716 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1718 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1719 DAG.getConstant(IdxVal - LoElts, dl,
1720 Idx.getValueType()));
1724 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1725 SDValue Vec = N->getOperand(0);
1726 SDValue Idx = N->getOperand(1);
1727 EVT VecVT = Vec.getValueType();
1729 if (isa<ConstantSDNode>(Idx)) {
1730 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1731 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1734 GetSplitVector(Vec, Lo, Hi);
1736 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1738 if (IdxVal < LoElts)
1739 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1740 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1741 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1742 Idx.getValueType())), 0);
1745 // See if the target wants to custom expand this node.
1746 if (CustomLowerNode(N, N->getValueType(0), true))
1749 // Make the vector elements byte-addressable if they aren't already.
1751 EVT EltVT = VecVT.getVectorElementType();
1752 if (EltVT.getSizeInBits() < 8) {
1753 SmallVector<SDValue, 4> ElementOps;
1754 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1755 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1756 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1757 DAG.getConstant(i, dl, MVT::i8)),
1762 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1763 VecVT.getVectorNumElements());
1764 Vec = DAG.getBuildVector(VecVT, dl, ElementOps);
1767 // Store the vector to the stack.
1768 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1769 auto &MF = DAG.getMachineFunction();
1770 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1771 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1772 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1774 // Load back the required element.
1775 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1776 return DAG.getExtLoad(
1777 ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1778 MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT);
1781 SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
1784 // *_EXTEND_VECTOR_INREG only reference the lower half of the input, so
1785 // splitting the result has the same effect as splitting the input operand.
1786 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
1788 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
1791 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1795 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1797 SDValue Ch = MGT->getChain();
1798 SDValue Ptr = MGT->getBasePtr();
1799 SDValue Index = MGT->getIndex();
1800 SDValue Mask = MGT->getMask();
1801 SDValue Src0 = MGT->getValue();
1802 unsigned Alignment = MGT->getOriginalAlignment();
1804 SDValue MaskLo, MaskHi;
1805 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1806 // Split Mask operand
1807 GetSplitVector(Mask, MaskLo, MaskHi);
1809 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1811 EVT MemoryVT = MGT->getMemoryVT();
1812 EVT LoMemVT, HiMemVT;
1813 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1815 SDValue Src0Lo, Src0Hi;
1816 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1817 GetSplitVector(Src0, Src0Lo, Src0Hi);
1819 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1821 SDValue IndexHi, IndexLo;
1822 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1823 GetSplitVector(Index, IndexLo, IndexHi);
1825 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1827 MachineMemOperand *MMO = DAG.getMachineFunction().
1828 getMachineMemOperand(MGT->getPointerInfo(),
1829 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1830 Alignment, MGT->getAAInfo(), MGT->getRanges());
1832 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1833 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1836 MMO = DAG.getMachineFunction().
1837 getMachineMemOperand(MGT->getPointerInfo(),
1838 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1839 Alignment, MGT->getAAInfo(),
1842 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1843 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1846 // Build a factor node to remember that this load is independent of the
1848 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1851 // Legalize the chain result - switch anything that used the old chain to
1853 ReplaceValueWith(SDValue(MGT, 1), Ch);
1855 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1857 ReplaceValueWith(SDValue(MGT, 0), Res);
1861 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1863 SDValue Ch = N->getChain();
1864 SDValue Ptr = N->getBasePtr();
1865 SDValue Mask = N->getMask();
1866 SDValue Data = N->getValue();
1867 EVT MemoryVT = N->getMemoryVT();
1868 unsigned Alignment = N->getOriginalAlignment();
1871 EVT LoMemVT, HiMemVT;
1872 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1874 SDValue DataLo, DataHi;
1875 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1876 // Split Data operand
1877 GetSplitVector(Data, DataLo, DataHi);
1879 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1881 SDValue MaskLo, MaskHi;
1882 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1883 // Split Mask operand
1884 GetSplitVector(Mask, MaskLo, MaskHi);
1886 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1888 // if Alignment is equal to the vector size,
1889 // take the half of it for the second part
1890 unsigned SecondHalfAlignment =
1891 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1892 Alignment/2 : Alignment;
1895 MachineMemOperand *MMO = DAG.getMachineFunction().
1896 getMachineMemOperand(N->getPointerInfo(),
1897 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1898 Alignment, N->getAAInfo(), N->getRanges());
1900 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1901 N->isTruncatingStore(),
1902 N->isCompressingStore());
1904 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
1905 N->isCompressingStore());
1906 MMO = DAG.getMachineFunction().
1907 getMachineMemOperand(N->getPointerInfo(),
1908 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1909 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1911 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1912 N->isTruncatingStore(), N->isCompressingStore());
1914 // Build a factor node to remember that this store is independent of the
1916 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1919 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1921 SDValue Ch = N->getChain();
1922 SDValue Ptr = N->getBasePtr();
1923 SDValue Mask = N->getMask();
1924 SDValue Index = N->getIndex();
1925 SDValue Data = N->getValue();
1926 EVT MemoryVT = N->getMemoryVT();
1927 unsigned Alignment = N->getOriginalAlignment();
1930 // Split all operands
1931 EVT LoMemVT, HiMemVT;
1932 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1934 SDValue DataLo, DataHi;
1935 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1936 // Split Data operand
1937 GetSplitVector(Data, DataLo, DataHi);
1939 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1941 SDValue MaskLo, MaskHi;
1942 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1943 // Split Mask operand
1944 GetSplitVector(Mask, MaskLo, MaskHi);
1946 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1948 SDValue IndexHi, IndexLo;
1949 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1950 GetSplitVector(Index, IndexLo, IndexHi);
1952 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1955 MachineMemOperand *MMO = DAG.getMachineFunction().
1956 getMachineMemOperand(N->getPointerInfo(),
1957 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1958 Alignment, N->getAAInfo(), N->getRanges());
1960 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo};
1961 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1964 MMO = DAG.getMachineFunction().
1965 getMachineMemOperand(N->getPointerInfo(),
1966 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1967 Alignment, N->getAAInfo(), N->getRanges());
1969 // The order of the Scatter operation after split is well defined. The "Hi"
1970 // part comes after the "Lo". So these two operations should be chained one
1972 SDValue OpsHi[] = {Lo, DataHi, MaskHi, Ptr, IndexHi};
1973 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1977 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1978 assert(N->isUnindexed() && "Indexed store of vector?");
1979 assert(OpNo == 1 && "Can only split the stored value");
1982 bool isTruncating = N->isTruncatingStore();
1983 SDValue Ch = N->getChain();
1984 SDValue Ptr = N->getBasePtr();
1985 EVT MemoryVT = N->getMemoryVT();
1986 unsigned Alignment = N->getOriginalAlignment();
1987 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
1988 AAMDNodes AAInfo = N->getAAInfo();
1990 GetSplitVector(N->getOperand(1), Lo, Hi);
1992 EVT LoMemVT, HiMemVT;
1993 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1995 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1998 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
1999 Alignment, MMOFlags, AAInfo);
2001 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2004 // Increment the pointer to the other half.
2005 Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize);
2008 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
2009 N->getPointerInfo().getWithOffset(IncrementSize),
2010 HiMemVT, Alignment, MMOFlags, AAInfo);
2012 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
2013 N->getPointerInfo().getWithOffset(IncrementSize),
2014 Alignment, MMOFlags, AAInfo);
2016 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2019 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
2022 // The input operands all must have the same type, and we know the result
2023 // type is valid. Convert this to a buildvector which extracts all the
2025 // TODO: If the input elements are power-two vectors, we could convert this to
2026 // a new CONCAT_VECTORS node with elements that are half-wide.
2027 SmallVector<SDValue, 32> Elts;
2028 EVT EltVT = N->getValueType(0).getVectorElementType();
2029 for (const SDValue &Op : N->op_values()) {
2030 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
2032 Elts.push_back(DAG.getNode(
2033 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
2034 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
2038 return DAG.getBuildVector(N->getValueType(0), DL, Elts);
2041 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
2042 // The result type is legal, but the input type is illegal. If splitting
2043 // ends up with the result type of each half still being legal, just
2044 // do that. If, however, that would result in an illegal result type,
2045 // we can try to get more clever with power-two vectors. Specifically,
2046 // split the input type, but also widen the result element size, then
2047 // concatenate the halves and truncate again. For example, consider a target
2048 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
2049 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
2050 // %inlo = v4i32 extract_subvector %in, 0
2051 // %inhi = v4i32 extract_subvector %in, 4
2052 // %lo16 = v4i16 trunc v4i32 %inlo
2053 // %hi16 = v4i16 trunc v4i32 %inhi
2054 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
2055 // %res = v8i8 trunc v8i16 %in16
2057 // Without this transform, the original truncate would end up being
2058 // scalarized, which is pretty much always a last resort.
2059 SDValue InVec = N->getOperand(0);
2060 EVT InVT = InVec->getValueType(0);
2061 EVT OutVT = N->getValueType(0);
2062 unsigned NumElements = OutVT.getVectorNumElements();
2063 bool IsFloat = OutVT.isFloatingPoint();
2065 // Widening should have already made sure this is a power-two vector
2066 // if we're trying to split it at all. assert() that's true, just in case.
2067 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
2069 unsigned InElementSize = InVT.getScalarSizeInBits();
2070 unsigned OutElementSize = OutVT.getScalarSizeInBits();
2072 // If the input elements are only 1/2 the width of the result elements,
2073 // just use the normal splitting. Our trick only work if there's room
2074 // to split more than once.
2075 if (InElementSize <= OutElementSize * 2)
2076 return SplitVecOp_UnaryOp(N);
2079 // Extract the halves of the input via extract_subvector.
2080 SDValue InLoVec, InHiVec;
2081 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
2082 // Truncate them to 1/2 the element size.
2083 EVT HalfElementVT = IsFloat ?
2084 EVT::getFloatingPointVT(InElementSize/2) :
2085 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
2086 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
2088 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
2089 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
2090 // Concatenate them to get the full intermediate truncation result.
2091 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
2092 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
2094 // Now finish up by truncating all the way down to the original result
2095 // type. This should normally be something that ends up being legal directly,
2096 // but in theory if a target has very wide vectors and an annoyingly
2097 // restricted set of legal types, this split can chain to build things up.
2099 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2100 DAG.getTargetConstant(
2101 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
2102 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
2105 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
2106 assert(N->getValueType(0).isVector() &&
2107 N->getOperand(0).getValueType().isVector() &&
2108 "Operand types must be vectors");
2109 // The result has a legal vector type, but the input needs splitting.
2110 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
2112 GetSplitVector(N->getOperand(0), Lo0, Hi0);
2113 GetSplitVector(N->getOperand(1), Lo1, Hi1);
2114 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
2115 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
2116 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
2118 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2119 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2120 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2121 return PromoteTargetBoolean(Con, N->getValueType(0));
2125 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2126 // The result has a legal vector type, but the input needs splitting.
2127 EVT ResVT = N->getValueType(0);
2130 GetSplitVector(N->getOperand(0), Lo, Hi);
2131 EVT InVT = Lo.getValueType();
2133 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2134 InVT.getVectorNumElements());
2136 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2137 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2139 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2142 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2143 // The result (and the first input) has a legal vector type, but the second
2144 // input needs splitting.
2145 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2149 //===----------------------------------------------------------------------===//
2150 // Result Vector Widening
2151 //===----------------------------------------------------------------------===//
2153 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2154 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
2158 // See if the target wants to custom widen this node.
2159 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2162 SDValue Res = SDValue();
2163 switch (N->getOpcode()) {
2166 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2170 llvm_unreachable("Do not know how to widen the result of this operator!");
2172 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2173 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2174 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2175 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2176 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2177 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2178 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2179 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2180 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2181 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2183 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2184 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2185 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2186 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2187 case ISD::VECTOR_SHUFFLE:
2188 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2191 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2194 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2213 Res = WidenVecRes_Binary(N);
2226 Res = WidenVecRes_BinaryCanTrap(N);
2229 case ISD::FCOPYSIGN:
2230 Res = WidenVecRes_FCOPYSIGN(N);
2234 Res = WidenVecRes_POWI(N);
2240 Res = WidenVecRes_Shift(N);
2243 case ISD::ANY_EXTEND_VECTOR_INREG:
2244 case ISD::SIGN_EXTEND_VECTOR_INREG:
2245 case ISD::ZERO_EXTEND_VECTOR_INREG:
2246 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2249 case ISD::ANY_EXTEND:
2250 case ISD::FP_EXTEND:
2252 case ISD::FP_TO_SINT:
2253 case ISD::FP_TO_UINT:
2254 case ISD::SIGN_EXTEND:
2255 case ISD::SINT_TO_FP:
2257 case ISD::UINT_TO_FP:
2258 case ISD::ZERO_EXTEND:
2259 Res = WidenVecRes_Convert(N);
2262 case ISD::BITREVERSE:
2276 case ISD::FNEARBYINT:
2283 Res = WidenVecRes_Unary(N);
2286 Res = WidenVecRes_Ternary(N);
2290 // If Res is null, the sub-method took care of registering the result.
2292 SetWidenedVector(SDValue(N, ResNo), Res);
2295 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2296 // Ternary op widening.
2298 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2299 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2300 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2301 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2302 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2305 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2306 // Binary op widening.
2308 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2309 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2310 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2311 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2314 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2315 // Binary op widening for operations that can trap.
2316 unsigned Opcode = N->getOpcode();
2318 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2319 EVT WidenEltVT = WidenVT.getVectorElementType();
2321 unsigned NumElts = VT.getVectorNumElements();
2322 const SDNodeFlags Flags = N->getFlags();
2323 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2324 NumElts = NumElts / 2;
2325 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2328 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2329 // Operation doesn't trap so just widen as normal.
2330 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2331 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2332 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2335 // No legal vector version so unroll the vector operation and then widen.
2337 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2339 // Since the operation can trap, apply operation on the original vector.
2341 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2342 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2343 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2345 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2346 unsigned ConcatEnd = 0; // Current ConcatOps index.
2347 int Idx = 0; // Current Idx into input vectors.
2349 // NumElts := greatest legal vector size (at most WidenVT)
2350 // while (orig. vector has unhandled elements) {
2351 // take munches of size NumElts from the beginning and add to ConcatOps
2352 // NumElts := next smaller supported vector size or 1
2354 while (CurNumElts != 0) {
2355 while (CurNumElts >= NumElts) {
2356 SDValue EOp1 = DAG.getNode(
2357 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2358 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2359 SDValue EOp2 = DAG.getNode(
2360 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2361 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2362 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2364 CurNumElts -= NumElts;
2367 NumElts = NumElts / 2;
2368 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2369 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2372 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2373 SDValue EOp1 = DAG.getNode(
2374 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2375 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2376 SDValue EOp2 = DAG.getNode(
2377 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2378 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2379 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2386 // Check to see if we have a single operation with the widen type.
2387 if (ConcatEnd == 1) {
2388 VT = ConcatOps[0].getValueType();
2390 return ConcatOps[0];
2393 // while (Some element of ConcatOps is not of type MaxVT) {
2394 // From the end of ConcatOps, collect elements of the same type and put
2395 // them into an op of the next larger supported type
2397 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2398 Idx = ConcatEnd - 1;
2399 VT = ConcatOps[Idx--].getValueType();
2400 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2403 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2407 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2408 } while (!TLI.isTypeLegal(NextVT));
2410 if (!VT.isVector()) {
2411 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2412 SDValue VecOp = DAG.getUNDEF(NextVT);
2413 unsigned NumToInsert = ConcatEnd - Idx - 1;
2414 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2415 VecOp = DAG.getNode(
2416 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2417 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2419 ConcatOps[Idx+1] = VecOp;
2420 ConcatEnd = Idx + 2;
2422 // Vector type, create a CONCAT_VECTORS of type NextVT
2423 SDValue undefVec = DAG.getUNDEF(VT);
2424 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2425 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2426 unsigned RealVals = ConcatEnd - Idx - 1;
2427 unsigned SubConcatEnd = 0;
2428 unsigned SubConcatIdx = Idx + 1;
2429 while (SubConcatEnd < RealVals)
2430 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2431 while (SubConcatEnd < OpsToConcat)
2432 SubConcatOps[SubConcatEnd++] = undefVec;
2433 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2434 NextVT, SubConcatOps);
2435 ConcatEnd = SubConcatIdx + 1;
2439 // Check to see if we have a single operation with the widen type.
2440 if (ConcatEnd == 1) {
2441 VT = ConcatOps[0].getValueType();
2443 return ConcatOps[0];
2446 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2447 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2448 if (NumOps != ConcatEnd ) {
2449 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2450 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2451 ConcatOps[j] = UndefVal;
2453 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2454 makeArrayRef(ConcatOps.data(), NumOps));
2457 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2458 SDValue InOp = N->getOperand(0);
2461 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2462 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2464 EVT InVT = InOp.getValueType();
2465 EVT InEltVT = InVT.getVectorElementType();
2466 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2468 unsigned Opcode = N->getOpcode();
2469 unsigned InVTNumElts = InVT.getVectorNumElements();
2470 const SDNodeFlags Flags = N->getFlags();
2471 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2472 InOp = GetWidenedVector(N->getOperand(0));
2473 InVT = InOp.getValueType();
2474 InVTNumElts = InVT.getVectorNumElements();
2475 if (InVTNumElts == WidenNumElts) {
2476 if (N->getNumOperands() == 1)
2477 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2478 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2480 if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
2481 // If both input and result vector types are of same width, extend
2482 // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
2483 // accepts fewer elements in the result than in the input.
2484 if (Opcode == ISD::SIGN_EXTEND)
2485 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2486 if (Opcode == ISD::ZERO_EXTEND)
2487 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2491 if (TLI.isTypeLegal(InWidenVT)) {
2492 // Because the result and the input are different vector types, widening
2493 // the result could create a legal type but widening the input might make
2494 // it an illegal type that might lead to repeatedly splitting the input
2495 // and then widening it. To avoid this, we widen the input only if
2496 // it results in a legal type.
2497 if (WidenNumElts % InVTNumElts == 0) {
2498 // Widen the input and call convert on the widened input vector.
2499 unsigned NumConcat = WidenNumElts/InVTNumElts;
2500 SmallVector<SDValue, 16> Ops(NumConcat);
2502 SDValue UndefVal = DAG.getUNDEF(InVT);
2503 for (unsigned i = 1; i != NumConcat; ++i)
2505 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2506 if (N->getNumOperands() == 1)
2507 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2508 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2511 if (InVTNumElts % WidenNumElts == 0) {
2512 SDValue InVal = DAG.getNode(
2513 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2514 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2515 // Extract the input and convert the shorten input vector.
2516 if (N->getNumOperands() == 1)
2517 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2518 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2522 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2523 SmallVector<SDValue, 16> Ops(WidenNumElts);
2524 EVT EltVT = WidenVT.getVectorElementType();
2525 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2527 for (i=0; i < MinElts; ++i) {
2528 SDValue Val = DAG.getNode(
2529 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2530 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2531 if (N->getNumOperands() == 1)
2532 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2534 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2537 SDValue UndefVal = DAG.getUNDEF(EltVT);
2538 for (; i < WidenNumElts; ++i)
2541 return DAG.getBuildVector(WidenVT, DL, Ops);
2544 SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2545 unsigned Opcode = N->getOpcode();
2546 SDValue InOp = N->getOperand(0);
2549 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2550 EVT WidenSVT = WidenVT.getVectorElementType();
2551 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2553 EVT InVT = InOp.getValueType();
2554 EVT InSVT = InVT.getVectorElementType();
2555 unsigned InVTNumElts = InVT.getVectorNumElements();
2557 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2558 InOp = GetWidenedVector(InOp);
2559 InVT = InOp.getValueType();
2560 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2562 case ISD::ANY_EXTEND_VECTOR_INREG:
2563 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2564 case ISD::SIGN_EXTEND_VECTOR_INREG:
2565 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2566 case ISD::ZERO_EXTEND_VECTOR_INREG:
2567 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2572 // Unroll, extend the scalars and rebuild the vector.
2573 SmallVector<SDValue, 16> Ops;
2574 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2575 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2576 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2578 case ISD::ANY_EXTEND_VECTOR_INREG:
2579 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2581 case ISD::SIGN_EXTEND_VECTOR_INREG:
2582 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2584 case ISD::ZERO_EXTEND_VECTOR_INREG:
2585 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2588 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected");
2593 while (Ops.size() != WidenNumElts)
2594 Ops.push_back(DAG.getUNDEF(WidenSVT));
2596 return DAG.getBuildVector(WidenVT, DL, Ops);
2599 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2600 // If this is an FCOPYSIGN with same input types, we can treat it as a
2601 // normal (can trap) binary op.
2602 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2603 return WidenVecRes_BinaryCanTrap(N);
2605 // If the types are different, fall back to unrolling.
2606 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2607 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2610 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2611 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2612 SDValue InOp = GetWidenedVector(N->getOperand(0));
2613 SDValue ShOp = N->getOperand(1);
2614 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2617 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2618 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2619 SDValue InOp = GetWidenedVector(N->getOperand(0));
2620 SDValue ShOp = N->getOperand(1);
2622 EVT ShVT = ShOp.getValueType();
2623 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2624 ShOp = GetWidenedVector(ShOp);
2625 ShVT = ShOp.getValueType();
2627 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2628 ShVT.getVectorElementType(),
2629 WidenVT.getVectorNumElements());
2630 if (ShVT != ShWidenVT)
2631 ShOp = ModifyToType(ShOp, ShWidenVT);
2633 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2636 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2637 // Unary op widening.
2638 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2639 SDValue InOp = GetWidenedVector(N->getOperand(0));
2640 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2643 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2644 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2645 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2646 cast<VTSDNode>(N->getOperand(1))->getVT()
2647 .getVectorElementType(),
2648 WidenVT.getVectorNumElements());
2649 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2650 return DAG.getNode(N->getOpcode(), SDLoc(N),
2651 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2654 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2655 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2656 return GetWidenedVector(WidenVec);
2659 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2660 SDValue InOp = N->getOperand(0);
2661 EVT InVT = InOp.getValueType();
2662 EVT VT = N->getValueType(0);
2663 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2666 switch (getTypeAction(InVT)) {
2667 case TargetLowering::TypeLegal:
2669 case TargetLowering::TypePromoteInteger:
2670 // If the incoming type is a vector that is being promoted, then
2671 // we know that the elements are arranged differently and that we
2672 // must perform the conversion using a stack slot.
2673 if (InVT.isVector())
2676 // If the InOp is promoted to the same size, convert it. Otherwise,
2677 // fall out of the switch and widen the promoted input.
2678 InOp = GetPromotedInteger(InOp);
2679 InVT = InOp.getValueType();
2680 if (WidenVT.bitsEq(InVT))
2681 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2683 case TargetLowering::TypeSoftenFloat:
2684 case TargetLowering::TypePromoteFloat:
2685 case TargetLowering::TypeExpandInteger:
2686 case TargetLowering::TypeExpandFloat:
2687 case TargetLowering::TypeScalarizeVector:
2688 case TargetLowering::TypeSplitVector:
2690 case TargetLowering::TypeWidenVector:
2691 // If the InOp is widened to the same size, convert it. Otherwise, fall
2692 // out of the switch and widen the widened input.
2693 InOp = GetWidenedVector(InOp);
2694 InVT = InOp.getValueType();
2695 if (WidenVT.bitsEq(InVT))
2696 // The input widens to the same size. Convert to the widen value.
2697 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2701 unsigned WidenSize = WidenVT.getSizeInBits();
2702 unsigned InSize = InVT.getSizeInBits();
2703 // x86mmx is not an acceptable vector element type, so don't try.
2704 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2705 // Determine new input vector type. The new input vector type will use
2706 // the same element type (if its a vector) or use the input type as a
2707 // vector. It is the same size as the type to widen to.
2709 unsigned NewNumElts = WidenSize / InSize;
2710 if (InVT.isVector()) {
2711 EVT InEltVT = InVT.getVectorElementType();
2712 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2713 WidenSize / InEltVT.getSizeInBits());
2715 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2718 if (TLI.isTypeLegal(NewInVT)) {
2719 // Because the result and the input are different vector types, widening
2720 // the result could create a legal type but widening the input might make
2721 // it an illegal type that might lead to repeatedly splitting the input
2722 // and then widening it. To avoid this, we widen the input only if
2723 // it results in a legal type.
2724 SmallVector<SDValue, 16> Ops(NewNumElts);
2725 SDValue UndefVal = DAG.getUNDEF(InVT);
2727 for (unsigned i = 1; i < NewNumElts; ++i)
2731 if (InVT.isVector())
2732 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2734 NewVec = DAG.getBuildVector(NewInVT, dl, Ops);
2735 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2739 return CreateStackStoreLoad(InOp, WidenVT);
2742 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2744 // Build a vector with undefined for the new nodes.
2745 EVT VT = N->getValueType(0);
2747 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2748 // type. The UNDEFs need to have the same type as the existing operands.
2749 EVT EltVT = N->getOperand(0).getValueType();
2750 unsigned NumElts = VT.getVectorNumElements();
2752 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2753 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2755 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2756 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2757 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2759 return DAG.getBuildVector(WidenVT, dl, NewOps);
2762 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2763 EVT InVT = N->getOperand(0).getValueType();
2764 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2766 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2767 unsigned NumInElts = InVT.getVectorNumElements();
2768 unsigned NumOperands = N->getNumOperands();
2770 bool InputWidened = false; // Indicates we need to widen the input.
2771 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2772 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2773 // Add undef vectors to widen to correct length.
2774 unsigned NumConcat = WidenVT.getVectorNumElements() /
2775 InVT.getVectorNumElements();
2776 SDValue UndefVal = DAG.getUNDEF(InVT);
2777 SmallVector<SDValue, 16> Ops(NumConcat);
2778 for (unsigned i=0; i < NumOperands; ++i)
2779 Ops[i] = N->getOperand(i);
2780 for (unsigned i = NumOperands; i != NumConcat; ++i)
2782 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2785 InputWidened = true;
2786 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2787 // The inputs and the result are widen to the same value.
2789 for (i=1; i < NumOperands; ++i)
2790 if (!N->getOperand(i).isUndef())
2793 if (i == NumOperands)
2794 // Everything but the first operand is an UNDEF so just return the
2795 // widened first operand.
2796 return GetWidenedVector(N->getOperand(0));
2798 if (NumOperands == 2) {
2799 // Replace concat of two operands with a shuffle.
2800 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2801 for (unsigned i = 0; i < NumInElts; ++i) {
2803 MaskOps[i + NumInElts] = i + WidenNumElts;
2805 return DAG.getVectorShuffle(WidenVT, dl,
2806 GetWidenedVector(N->getOperand(0)),
2807 GetWidenedVector(N->getOperand(1)),
2813 // Fall back to use extracts and build vector.
2814 EVT EltVT = WidenVT.getVectorElementType();
2815 SmallVector<SDValue, 16> Ops(WidenNumElts);
2817 for (unsigned i=0; i < NumOperands; ++i) {
2818 SDValue InOp = N->getOperand(i);
2820 InOp = GetWidenedVector(InOp);
2821 for (unsigned j=0; j < NumInElts; ++j)
2822 Ops[Idx++] = DAG.getNode(
2823 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2824 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2826 SDValue UndefVal = DAG.getUNDEF(EltVT);
2827 for (; Idx < WidenNumElts; ++Idx)
2828 Ops[Idx] = UndefVal;
2829 return DAG.getBuildVector(WidenVT, dl, Ops);
2832 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2833 EVT VT = N->getValueType(0);
2834 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2835 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2836 SDValue InOp = N->getOperand(0);
2837 SDValue Idx = N->getOperand(1);
2840 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2841 InOp = GetWidenedVector(InOp);
2843 EVT InVT = InOp.getValueType();
2845 // Check if we can just return the input vector after widening.
2846 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2847 if (IdxVal == 0 && InVT == WidenVT)
2850 // Check if we can extract from the vector.
2851 unsigned InNumElts = InVT.getVectorNumElements();
2852 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2853 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2855 // We could try widening the input to the right length but for now, extract
2856 // the original elements, fill the rest with undefs and build a vector.
2857 SmallVector<SDValue, 16> Ops(WidenNumElts);
2858 EVT EltVT = VT.getVectorElementType();
2859 unsigned NumElts = VT.getVectorNumElements();
2861 for (i=0; i < NumElts; ++i)
2863 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2864 DAG.getConstant(IdxVal + i, dl,
2865 TLI.getVectorIdxTy(DAG.getDataLayout())));
2867 SDValue UndefVal = DAG.getUNDEF(EltVT);
2868 for (; i < WidenNumElts; ++i)
2870 return DAG.getBuildVector(WidenVT, dl, Ops);
2873 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2874 SDValue InOp = GetWidenedVector(N->getOperand(0));
2875 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2876 InOp.getValueType(), InOp,
2877 N->getOperand(1), N->getOperand(2));
2880 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2881 LoadSDNode *LD = cast<LoadSDNode>(N);
2882 ISD::LoadExtType ExtType = LD->getExtensionType();
2885 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2886 if (ExtType != ISD::NON_EXTLOAD)
2887 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2889 Result = GenWidenVectorLoads(LdChain, LD);
2891 // If we generate a single load, we can use that for the chain. Otherwise,
2892 // build a factor node to remember the multiple loads are independent and
2895 if (LdChain.size() == 1)
2896 NewChain = LdChain[0];
2898 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2900 // Modified the chain - switch anything that used the old chain to use
2902 ReplaceValueWith(SDValue(N, 1), NewChain);
2907 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2909 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2910 SDValue Mask = N->getMask();
2911 EVT MaskVT = Mask.getValueType();
2912 SDValue Src0 = GetWidenedVector(N->getSrc0());
2913 ISD::LoadExtType ExtType = N->getExtensionType();
2916 // The mask should be widened as well
2917 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
2918 MaskVT.getVectorElementType(),
2919 WidenVT.getVectorNumElements());
2920 Mask = ModifyToType(Mask, WideMaskVT, true);
2922 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2923 Mask, Src0, N->getMemoryVT(),
2924 N->getMemOperand(), ExtType,
2925 N->isExpandingLoad());
2926 // Legalize the chain result - switch anything that used the old chain to
2928 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2932 SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
2934 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2935 SDValue Mask = N->getMask();
2936 EVT MaskVT = Mask.getValueType();
2937 SDValue Src0 = GetWidenedVector(N->getValue());
2938 unsigned NumElts = WideVT.getVectorNumElements();
2941 // The mask should be widened as well
2942 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
2943 MaskVT.getVectorElementType(),
2944 WideVT.getVectorNumElements());
2945 Mask = ModifyToType(Mask, WideMaskVT, true);
2947 // Widen the Index operand
2948 SDValue Index = N->getIndex();
2949 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
2950 Index.getValueType().getScalarType(),
2952 Index = ModifyToType(Index, WideIndexVT);
2953 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
2954 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
2955 N->getMemoryVT(), dl, Ops,
2956 N->getMemOperand());
2958 // Legalize the chain result - switch anything that used the old chain to
2960 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2964 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2965 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2966 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2967 WidenVT, N->getOperand(0));
2970 // Return true if this is a node that could have two SETCCs as operands.
2971 static inline bool isLogicalMaskOp(unsigned Opcode) {
2981 // This is used just for the assert in convertMask(). Check that this either
2982 // a SETCC or a previously handled SETCC by convertMask().
2984 static inline bool isSETCCorConvertedSETCC(SDValue N) {
2985 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
2986 N = N.getOperand(0);
2987 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
2988 for (unsigned i = 1; i < N->getNumOperands(); ++i)
2989 if (!N->getOperand(i)->isUndef())
2991 N = N.getOperand(0);
2994 if (N.getOpcode() == ISD::TRUNCATE)
2995 N = N.getOperand(0);
2996 else if (N.getOpcode() == ISD::SIGN_EXTEND)
2997 N = N.getOperand(0);
2999 if (isLogicalMaskOp(N.getOpcode()))
3000 return isSETCCorConvertedSETCC(N.getOperand(0)) &&
3001 isSETCCorConvertedSETCC(N.getOperand(1));
3003 return (N.getOpcode() == ISD::SETCC ||
3004 ISD::isBuildVectorOfConstantSDNodes(N.getNode()));
3008 // Return a mask of vector type MaskVT to replace InMask. Also adjust MaskVT
3009 // to ToMaskVT if needed with vector extension or truncation.
3010 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
3012 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
3013 // FIXME: This code seems to be too restrictive, we might consider
3014 // generalizing it or dropping it.
3015 assert(isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument.");
3017 // Make a new Mask node, with a legal result VT.
3018 SmallVector<SDValue, 4> Ops;
3019 for (unsigned i = 0, e = InMask->getNumOperands(); i < e; ++i)
3020 Ops.push_back(InMask->getOperand(i));
3021 SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
3023 // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
3024 // extend or truncate is needed.
3025 LLVMContext &Ctx = *DAG.getContext();
3026 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
3027 unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
3028 if (MaskScalarBits < ToMaskScalBits) {
3029 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3030 MaskVT.getVectorNumElements());
3031 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
3032 } else if (MaskScalarBits > ToMaskScalBits) {
3033 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3034 MaskVT.getVectorNumElements());
3035 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask);
3038 assert(Mask->getValueType(0).getScalarSizeInBits() ==
3039 ToMaskVT.getScalarSizeInBits() &&
3040 "Mask should have the right element size by now.");
3042 // Adjust Mask to the right number of elements.
3043 unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
3044 if (CurrMaskNumEls > ToMaskVT.getVectorNumElements()) {
3045 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
3046 SDValue ZeroIdx = DAG.getConstant(0, SDLoc(Mask), IdxTy);
3047 Mask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Mask), ToMaskVT, Mask,
3049 } else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
3050 unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
3051 EVT SubVT = Mask->getValueType(0);
3052 SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
3054 Mask = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubOps);
3057 assert((Mask->getValueType(0) == ToMaskVT) &&
3058 "A mask of ToMaskVT should have been produced by now.");
3063 // Get the target mask VT, and widen if needed.
3064 EVT DAGTypeLegalizer::getSETCCWidenedResultTy(SDValue SetCC) {
3065 assert(SetCC->getOpcode() == ISD::SETCC);
3066 LLVMContext &Ctx = *DAG.getContext();
3067 EVT MaskVT = getSetCCResultType(SetCC->getOperand(0).getValueType());
3068 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3069 MaskVT = TLI.getTypeToTransformTo(Ctx, MaskVT);
3073 // This method tries to handle VSELECT and its mask by legalizing operands
3074 // (which may require widening) and if needed adjusting the mask vector type
3075 // to match that of the VSELECT. Without it, many cases end up with
3076 // scalarization of the SETCC, with many unnecessary instructions.
3077 SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
3078 LLVMContext &Ctx = *DAG.getContext();
3079 SDValue Cond = N->getOperand(0);
3081 if (N->getOpcode() != ISD::VSELECT)
3084 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3087 // If this is a splitted VSELECT that was previously already handled, do
3089 EVT CondVT = Cond->getValueType(0);
3090 if (CondVT.getScalarSizeInBits() != 1)
3093 EVT VSelVT = N->getValueType(0);
3094 // Only handle vector types which are a power of 2.
3095 if (!isPowerOf2_64(VSelVT.getSizeInBits()))
3098 // Don't touch if this will be scalarized.
3099 EVT FinalVT = VSelVT;
3100 while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
3101 FinalVT = FinalVT.getHalfNumVectorElementsVT(Ctx);
3103 if (FinalVT.getVectorNumElements() == 1)
3106 // If there is support for an i1 vector mask, don't touch.
3107 if (Cond.getOpcode() == ISD::SETCC) {
3108 EVT SetCCOpVT = Cond->getOperand(0).getValueType();
3109 while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
3110 SetCCOpVT = TLI.getTypeToTransformTo(Ctx, SetCCOpVT);
3111 EVT SetCCResVT = getSetCCResultType(SetCCOpVT);
3112 if (SetCCResVT.getScalarSizeInBits() == 1)
3114 } else if (CondVT.getScalarType() == MVT::i1) {
3115 // If there is support for an i1 vector mask (or only scalar i1 conditions),
3117 while (TLI.getTypeAction(Ctx, CondVT) != TargetLowering::TypeLegal)
3118 CondVT = TLI.getTypeToTransformTo(Ctx, CondVT);
3120 if (CondVT.getScalarType() == MVT::i1)
3124 // Get the VT and operands for VSELECT, and widen if needed.
3125 SDValue VSelOp1 = N->getOperand(1);
3126 SDValue VSelOp2 = N->getOperand(2);
3127 if (getTypeAction(VSelVT) == TargetLowering::TypeWidenVector) {
3128 VSelVT = TLI.getTypeToTransformTo(Ctx, VSelVT);
3129 VSelOp1 = GetWidenedVector(VSelOp1);
3130 VSelOp2 = GetWidenedVector(VSelOp2);
3133 // The mask of the VSELECT should have integer elements.
3134 EVT ToMaskVT = VSelVT;
3135 if (!ToMaskVT.getScalarType().isInteger())
3136 ToMaskVT = ToMaskVT.changeVectorElementTypeToInteger();
3139 if (Cond->getOpcode() == ISD::SETCC) {
3140 EVT MaskVT = getSETCCWidenedResultTy(Cond);
3141 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3142 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3143 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3144 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3145 // Cond is (AND/OR/XOR (SETCC, SETCC))
3146 SDValue SETCC0 = Cond->getOperand(0);
3147 SDValue SETCC1 = Cond->getOperand(1);
3148 EVT VT0 = getSETCCWidenedResultTy(SETCC0);
3149 EVT VT1 = getSETCCWidenedResultTy(SETCC1);
3150 unsigned ScalarBits0 = VT0.getScalarSizeInBits();
3151 unsigned ScalarBits1 = VT1.getScalarSizeInBits();
3152 unsigned ScalarBits_ToMask = ToMaskVT.getScalarSizeInBits();
3154 // If the two SETCCs have different VTs, either extend/truncate one of
3155 // them to the other "towards" ToMaskVT, or truncate one and extend the
3156 // other to ToMaskVT.
3157 if (ScalarBits0 != ScalarBits1) {
3158 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1);
3159 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
3160 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
3162 else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits())
3167 // If the two SETCCs have the same VT, don't change it.
3170 // Make new SETCCs and logical nodes.
3171 SETCC0 = convertMask(SETCC0, VT0, MaskVT);
3172 SETCC1 = convertMask(SETCC1, VT1, MaskVT);
3173 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
3175 // Convert the logical op for VSELECT if needed.
3176 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3180 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
3183 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
3184 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3185 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3187 SDValue Cond1 = N->getOperand(0);
3188 EVT CondVT = Cond1.getValueType();
3189 if (CondVT.isVector()) {
3190 if (SDValue Res = WidenVSELECTAndMask(N))
3193 EVT CondEltVT = CondVT.getVectorElementType();
3194 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
3195 CondEltVT, WidenNumElts);
3196 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
3197 Cond1 = GetWidenedVector(Cond1);
3199 // If we have to split the condition there is no point in widening the
3200 // select. This would result in an cycle of widening the select ->
3201 // widening the condition operand -> splitting the condition operand ->
3202 // splitting the select -> widening the select. Instead split this select
3203 // further and widen the resulting type.
3204 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
3205 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
3206 SDValue Res = ModifyToType(SplitSelect, WidenVT);
3210 if (Cond1.getValueType() != CondWidenVT)
3211 Cond1 = ModifyToType(Cond1, CondWidenVT);
3214 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3215 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
3216 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
3217 return DAG.getNode(N->getOpcode(), SDLoc(N),
3218 WidenVT, Cond1, InOp1, InOp2);
3221 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
3222 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
3223 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
3224 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
3225 InOp1.getValueType(), N->getOperand(0),
3226 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
3229 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
3230 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3231 return DAG.getUNDEF(WidenVT);
3234 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
3235 EVT VT = N->getValueType(0);
3238 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3239 unsigned NumElts = VT.getVectorNumElements();
3240 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3242 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3243 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3245 // Adjust mask based on new input vector length.
3246 SmallVector<int, 16> NewMask;
3247 for (unsigned i = 0; i != NumElts; ++i) {
3248 int Idx = N->getMaskElt(i);
3249 if (Idx < (int)NumElts)
3250 NewMask.push_back(Idx);
3252 NewMask.push_back(Idx - NumElts + WidenNumElts);
3254 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3255 NewMask.push_back(-1);
3256 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3259 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
3260 assert(N->getValueType(0).isVector() &&
3261 N->getOperand(0).getValueType().isVector() &&
3262 "Operands must be vectors");
3263 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3264 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3266 SDValue InOp1 = N->getOperand(0);
3267 EVT InVT = InOp1.getValueType();
3268 assert(InVT.isVector() && "can not widen non-vector type");
3269 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3270 InVT.getVectorElementType(), WidenNumElts);
3272 // The input and output types often differ here, and it could be that while
3273 // we'd prefer to widen the result type, the input operands have been split.
3274 // In this case, we also need to split the result of this node as well.
3275 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3276 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3277 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3281 InOp1 = GetWidenedVector(InOp1);
3282 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3284 // Assume that the input and output will be widen appropriately. If not,
3285 // we will have to unroll it at some point.
3286 assert(InOp1.getValueType() == WidenInVT &&
3287 InOp2.getValueType() == WidenInVT &&
3288 "Input not widened to expected type!");
3290 return DAG.getNode(ISD::SETCC, SDLoc(N),
3291 WidenVT, InOp1, InOp2, N->getOperand(2));
3295 //===----------------------------------------------------------------------===//
3296 // Widen Vector Operand
3297 //===----------------------------------------------------------------------===//
3298 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3299 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
3302 SDValue Res = SDValue();
3304 // See if the target wants to custom widen this node.
3305 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3308 switch (N->getOpcode()) {
3311 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3315 llvm_unreachable("Do not know how to widen this operator's operand!");
3317 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3318 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3319 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3320 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3321 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3322 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
3323 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3324 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3325 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3327 case ISD::ANY_EXTEND:
3328 case ISD::SIGN_EXTEND:
3329 case ISD::ZERO_EXTEND:
3330 Res = WidenVecOp_EXTEND(N);
3333 case ISD::FP_EXTEND:
3334 case ISD::FP_TO_SINT:
3335 case ISD::FP_TO_UINT:
3336 case ISD::SINT_TO_FP:
3337 case ISD::UINT_TO_FP:
3339 Res = WidenVecOp_Convert(N);
3343 // If Res is null, the sub-method took care of registering the result.
3344 if (!Res.getNode()) return false;
3346 // If the result is N, the sub-method updated N in place. Tell the legalizer
3348 if (Res.getNode() == N)
3352 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3353 "Invalid operand expansion");
3355 ReplaceValueWith(SDValue(N, 0), Res);
3359 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3361 EVT VT = N->getValueType(0);
3363 SDValue InOp = N->getOperand(0);
3364 // If some legalization strategy other than widening is used on the operand,
3365 // we can't safely assume that just extending the low lanes is the correct
3367 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
3368 return WidenVecOp_Convert(N);
3369 InOp = GetWidenedVector(InOp);
3370 assert(VT.getVectorNumElements() <
3371 InOp.getValueType().getVectorNumElements() &&
3372 "Input wasn't widened!");
3374 // We may need to further widen the operand until it has the same total
3375 // vector size as the result.
3376 EVT InVT = InOp.getValueType();
3377 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3378 EVT InEltVT = InVT.getVectorElementType();
3379 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3380 EVT FixedVT = (MVT::SimpleValueType)i;
3381 EVT FixedEltVT = FixedVT.getVectorElementType();
3382 if (TLI.isTypeLegal(FixedVT) &&
3383 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3384 FixedEltVT == InEltVT) {
3385 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
3386 "Not enough elements in the fixed type for the operand!");
3387 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
3388 "We can't have the same type as we started with!");
3389 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3391 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3392 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3395 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3396 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3400 InVT = InOp.getValueType();
3401 if (InVT.getSizeInBits() != VT.getSizeInBits())
3402 // We couldn't find a legal vector type that was a widening of the input
3403 // and could be extended in-register to the result type, so we have to
3405 return WidenVecOp_Convert(N);
3408 // Use special DAG nodes to represent the operation of extending the
3410 switch (N->getOpcode()) {
3412 llvm_unreachable("Extend legalization on on extend operation!");
3413 case ISD::ANY_EXTEND:
3414 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3415 case ISD::SIGN_EXTEND:
3416 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3417 case ISD::ZERO_EXTEND:
3418 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3422 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3423 // The result (and first input) is legal, but the second input is illegal.
3424 // We can't do much to fix that, so just unroll and let the extracts off of
3425 // the second input be widened as needed later.
3426 return DAG.UnrollVectorOp(N);
3429 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3430 // Since the result is legal and the input is illegal, it is unlikely that we
3431 // can fix the input to a legal type so unroll the convert into some scalar
3432 // code and create a nasty build vector.
3433 EVT VT = N->getValueType(0);
3434 EVT EltVT = VT.getVectorElementType();
3436 unsigned NumElts = VT.getVectorNumElements();
3437 SDValue InOp = N->getOperand(0);
3438 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3439 InOp = GetWidenedVector(InOp);
3440 EVT InVT = InOp.getValueType();
3441 EVT InEltVT = InVT.getVectorElementType();
3443 unsigned Opcode = N->getOpcode();
3444 SmallVector<SDValue, 16> Ops(NumElts);
3445 for (unsigned i=0; i < NumElts; ++i)
3446 Ops[i] = DAG.getNode(
3449 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3450 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3452 return DAG.getBuildVector(VT, dl, Ops);
3455 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3456 EVT VT = N->getValueType(0);
3457 SDValue InOp = GetWidenedVector(N->getOperand(0));
3458 EVT InWidenVT = InOp.getValueType();
3461 // Check if we can convert between two legal vector types and extract.
3462 unsigned InWidenSize = InWidenVT.getSizeInBits();
3463 unsigned Size = VT.getSizeInBits();
3464 // x86mmx is not an acceptable vector element type, so don't try.
3465 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3466 unsigned NewNumElts = InWidenSize / Size;
3467 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3468 if (TLI.isTypeLegal(NewVT)) {
3469 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3471 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3472 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3476 return CreateStackStoreLoad(InOp, VT);
3479 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3480 // If the input vector is not legal, it is likely that we will not find a
3481 // legal vector of the same size. Replace the concatenate vector with a
3482 // nasty build vector.
3483 EVT VT = N->getValueType(0);
3484 EVT EltVT = VT.getVectorElementType();
3486 unsigned NumElts = VT.getVectorNumElements();
3487 SmallVector<SDValue, 16> Ops(NumElts);
3489 EVT InVT = N->getOperand(0).getValueType();
3490 unsigned NumInElts = InVT.getVectorNumElements();
3493 unsigned NumOperands = N->getNumOperands();
3494 for (unsigned i=0; i < NumOperands; ++i) {
3495 SDValue InOp = N->getOperand(i);
3496 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3497 InOp = GetWidenedVector(InOp);
3498 for (unsigned j=0; j < NumInElts; ++j)
3499 Ops[Idx++] = DAG.getNode(
3500 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3501 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3503 return DAG.getBuildVector(VT, dl, Ops);
3506 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3507 SDValue InOp = GetWidenedVector(N->getOperand(0));
3508 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3509 N->getValueType(0), InOp, N->getOperand(1));
3512 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3513 SDValue InOp = GetWidenedVector(N->getOperand(0));
3514 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3515 N->getValueType(0), InOp, N->getOperand(1));
3518 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3519 // We have to widen the value, but we want only to store the original
3521 StoreSDNode *ST = cast<StoreSDNode>(N);
3523 SmallVector<SDValue, 16> StChain;
3524 if (ST->isTruncatingStore())
3525 GenWidenVectorTruncStores(StChain, ST);
3527 GenWidenVectorStores(StChain, ST);
3529 if (StChain.size() == 1)
3532 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3535 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3536 assert(OpNo == 3 && "Can widen only data operand of mstore");
3537 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3538 SDValue Mask = MST->getMask();
3539 SDValue StVal = MST->getValue();
3541 SDValue WideVal = GetWidenedVector(StVal);
3544 // The mask should be widened as well.
3545 Mask = WidenTargetBoolean(Mask, WideVal.getValueType(), true);
3547 assert(Mask.getValueType().getVectorNumElements() ==
3548 WideVal.getValueType().getVectorNumElements() &&
3549 "Mask and data vectors should have the same number of elements");
3550 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3551 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3552 false, MST->isCompressingStore());
3555 SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3556 assert(OpNo == 1 && "Can widen only data operand of mscatter");
3557 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3558 SDValue DataOp = MSC->getValue();
3559 SDValue Mask = MSC->getMask();
3562 SDValue WideVal = GetWidenedVector(DataOp);
3563 EVT WideVT = WideVal.getValueType();
3564 unsigned NumElts = WideVal.getValueType().getVectorNumElements();
3567 // The mask should be widened as well.
3568 Mask = WidenTargetBoolean(Mask, WideVT, true);
3571 SDValue Index = MSC->getIndex();
3572 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3573 Index.getValueType().getScalarType(),
3575 Index = ModifyToType(Index, WideIndexVT);
3577 SDValue Ops[] = {MSC->getChain(), WideVal, Mask, MSC->getBasePtr(), Index};
3578 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3579 MSC->getMemoryVT(), dl, Ops,
3580 MSC->getMemOperand());
3583 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3584 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3585 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3588 // WARNING: In this code we widen the compare instruction with garbage.
3589 // This garbage may contain denormal floats which may be slow. Is this a real
3590 // concern ? Should we zero the unused lanes if this is a float compare ?
3592 // Get a new SETCC node to compare the newly widened operands.
3593 // Only some of the compared elements are legal.
3594 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3595 InOp0.getValueType());
3596 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3597 SVT, InOp0, InOp1, N->getOperand(2));
3599 // Extract the needed results from the result vector.
3600 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3601 SVT.getVectorElementType(),
3602 N->getValueType(0).getVectorNumElements());
3603 SDValue CC = DAG.getNode(
3604 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3605 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3607 return PromoteTargetBoolean(CC, N->getValueType(0));
3611 //===----------------------------------------------------------------------===//
3612 // Vector Widening Utilities
3613 //===----------------------------------------------------------------------===//
3615 // Utility function to find the type to chop up a widen vector for load/store
3616 // TLI: Target lowering used to determine legal types.
3617 // Width: Width left need to load/store.
3618 // WidenVT: The widen vector type to load to/store from
3619 // Align: If 0, don't allow use of a wider type
3620 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3622 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3623 unsigned Width, EVT WidenVT,
3624 unsigned Align = 0, unsigned WidenEx = 0) {
3625 EVT WidenEltVT = WidenVT.getVectorElementType();
3626 unsigned WidenWidth = WidenVT.getSizeInBits();
3627 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3628 unsigned AlignInBits = Align*8;
3630 // If we have one element to load/store, return it.
3631 EVT RetVT = WidenEltVT;
3632 if (Width == WidenEltWidth)
3635 // See if there is larger legal integer than the element type to load/store.
3637 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3638 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3639 EVT MemVT((MVT::SimpleValueType) VT);
3640 unsigned MemVTWidth = MemVT.getSizeInBits();
3641 if (MemVT.getSizeInBits() <= WidenEltWidth)
3643 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3644 if ((Action == TargetLowering::TypeLegal ||
3645 Action == TargetLowering::TypePromoteInteger) &&
3646 (WidenWidth % MemVTWidth) == 0 &&
3647 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3648 (MemVTWidth <= Width ||
3649 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3655 // See if there is a larger vector type to load/store that has the same vector
3656 // element type and is evenly divisible with the WidenVT.
3657 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3658 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3659 EVT MemVT = (MVT::SimpleValueType) VT;
3660 unsigned MemVTWidth = MemVT.getSizeInBits();
3661 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3662 (WidenWidth % MemVTWidth) == 0 &&
3663 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3664 (MemVTWidth <= Width ||
3665 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3666 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3674 // Builds a vector type from scalar loads
3675 // VecTy: Resulting Vector type
3676 // LDOps: Load operators to build a vector type
3677 // [Start,End) the list of loads to use.
3678 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3679 SmallVectorImpl<SDValue> &LdOps,
3680 unsigned Start, unsigned End) {
3681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3682 SDLoc dl(LdOps[Start]);
3683 EVT LdTy = LdOps[Start].getValueType();
3684 unsigned Width = VecTy.getSizeInBits();
3685 unsigned NumElts = Width / LdTy.getSizeInBits();
3686 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3689 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3691 for (unsigned i = Start + 1; i != End; ++i) {
3692 EVT NewLdTy = LdOps[i].getValueType();
3693 if (NewLdTy != LdTy) {
3694 NumElts = Width / NewLdTy.getSizeInBits();
3695 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3696 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3697 // Readjust position and vector position based on new load type.
3698 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3701 VecOp = DAG.getNode(
3702 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3703 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3705 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3708 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3710 // The strategy assumes that we can efficiently load power-of-two widths.
3711 // The routine chops the vector into the largest vector loads with the same
3712 // element type or scalar loads and then recombines it to the widen vector
3714 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3715 unsigned WidenWidth = WidenVT.getSizeInBits();
3716 EVT LdVT = LD->getMemoryVT();
3718 assert(LdVT.isVector() && WidenVT.isVector());
3719 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3722 SDValue Chain = LD->getChain();
3723 SDValue BasePtr = LD->getBasePtr();
3724 unsigned Align = LD->getAlignment();
3725 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3726 AAMDNodes AAInfo = LD->getAAInfo();
3728 int LdWidth = LdVT.getSizeInBits();
3729 int WidthDiff = WidenWidth - LdWidth;
3730 unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
3732 // Find the vector type that can load from.
3733 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3734 int NewVTWidth = NewVT.getSizeInBits();
3735 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3736 Align, MMOFlags, AAInfo);
3737 LdChain.push_back(LdOp.getValue(1));
3739 // Check if we can load the element with one instruction.
3740 if (LdWidth <= NewVTWidth) {
3741 if (!NewVT.isVector()) {
3742 unsigned NumElts = WidenWidth / NewVTWidth;
3743 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3744 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3745 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3747 if (NewVT == WidenVT)
3750 assert(WidenWidth % NewVTWidth == 0);
3751 unsigned NumConcat = WidenWidth / NewVTWidth;
3752 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3753 SDValue UndefVal = DAG.getUNDEF(NewVT);
3754 ConcatOps[0] = LdOp;
3755 for (unsigned i = 1; i != NumConcat; ++i)
3756 ConcatOps[i] = UndefVal;
3757 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3760 // Load vector by using multiple loads from largest vector to scalar.
3761 SmallVector<SDValue, 16> LdOps;
3762 LdOps.push_back(LdOp);
3764 LdWidth -= NewVTWidth;
3765 unsigned Offset = 0;
3767 while (LdWidth > 0) {
3768 unsigned Increment = NewVTWidth / 8;
3769 Offset += Increment;
3770 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
3773 if (LdWidth < NewVTWidth) {
3774 // The current type we are using is too large. Find a better size.
3775 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3776 NewVTWidth = NewVT.getSizeInBits();
3777 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3778 LD->getPointerInfo().getWithOffset(Offset),
3779 MinAlign(Align, Increment), MMOFlags, AAInfo);
3780 LdChain.push_back(L.getValue(1));
3781 if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
3782 // Later code assumes the vector loads produced will be mergeable, so we
3783 // must pad the final entry up to the previous width. Scalars are
3784 // combined separately.
3785 SmallVector<SDValue, 16> Loads;
3787 unsigned size = L->getValueSizeInBits(0);
3788 while (size < LdOp->getValueSizeInBits(0)) {
3789 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3790 size += L->getValueSizeInBits(0);
3792 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3795 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3796 LD->getPointerInfo().getWithOffset(Offset),
3797 MinAlign(Align, Increment), MMOFlags, AAInfo);
3798 LdChain.push_back(L.getValue(1));
3804 LdWidth -= NewVTWidth;
3807 // Build the vector from the load operations.
3808 unsigned End = LdOps.size();
3809 if (!LdOps[0].getValueType().isVector())
3810 // All the loads are scalar loads.
3811 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3813 // If the load contains vectors, build the vector using concat vector.
3814 // All of the vectors used to load are power-of-2, and the scalar loads can be
3815 // combined to make a power-of-2 vector.
3816 SmallVector<SDValue, 16> ConcatOps(End);
3819 EVT LdTy = LdOps[i].getValueType();
3820 // First, combine the scalar loads to a vector.
3821 if (!LdTy.isVector()) {
3822 for (--i; i >= 0; --i) {
3823 LdTy = LdOps[i].getValueType();
3824 if (LdTy.isVector())
3827 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
3829 ConcatOps[--Idx] = LdOps[i];
3830 for (--i; i >= 0; --i) {
3831 EVT NewLdTy = LdOps[i].getValueType();
3832 if (NewLdTy != LdTy) {
3833 // Create a larger vector.
3834 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3835 makeArrayRef(&ConcatOps[Idx], End - Idx));
3839 ConcatOps[--Idx] = LdOps[i];
3842 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
3843 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3844 makeArrayRef(&ConcatOps[Idx], End - Idx));
3846 // We need to fill the rest with undefs to build the vector.
3847 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3848 SmallVector<SDValue, 16> WidenOps(NumOps);
3849 SDValue UndefVal = DAG.getUNDEF(LdTy);
3852 for (; i != End-Idx; ++i)
3853 WidenOps[i] = ConcatOps[Idx+i];
3854 for (; i != NumOps; ++i)
3855 WidenOps[i] = UndefVal;
3857 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3861 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3863 ISD::LoadExtType ExtType) {
3864 // For extension loads, it may not be more efficient to chop up the vector
3865 // and then extend it. Instead, we unroll the load and build a new vector.
3866 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3867 EVT LdVT = LD->getMemoryVT();
3869 assert(LdVT.isVector() && WidenVT.isVector());
3872 SDValue Chain = LD->getChain();
3873 SDValue BasePtr = LD->getBasePtr();
3874 unsigned Align = LD->getAlignment();
3875 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3876 AAMDNodes AAInfo = LD->getAAInfo();
3878 EVT EltVT = WidenVT.getVectorElementType();
3879 EVT LdEltVT = LdVT.getVectorElementType();
3880 unsigned NumElts = LdVT.getVectorNumElements();
3882 // Load each element and widen.
3883 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3884 SmallVector<SDValue, 16> Ops(WidenNumElts);
3885 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3887 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
3888 LdEltVT, Align, MMOFlags, AAInfo);
3889 LdChain.push_back(Ops[0].getValue(1));
3890 unsigned i = 0, Offset = Increment;
3891 for (i=1; i < NumElts; ++i, Offset += Increment) {
3892 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
3893 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3894 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3895 Align, MMOFlags, AAInfo);
3896 LdChain.push_back(Ops[i].getValue(1));
3899 // Fill the rest with undefs.
3900 SDValue UndefVal = DAG.getUNDEF(EltVT);
3901 for (; i != WidenNumElts; ++i)
3904 return DAG.getBuildVector(WidenVT, dl, Ops);
3907 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3909 // The strategy assumes that we can efficiently store power-of-two widths.
3910 // The routine chops the vector into the largest vector stores with the same
3911 // element type or scalar stores.
3912 SDValue Chain = ST->getChain();
3913 SDValue BasePtr = ST->getBasePtr();
3914 unsigned Align = ST->getAlignment();
3915 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3916 AAMDNodes AAInfo = ST->getAAInfo();
3917 SDValue ValOp = GetWidenedVector(ST->getValue());
3920 EVT StVT = ST->getMemoryVT();
3921 unsigned StWidth = StVT.getSizeInBits();
3922 EVT ValVT = ValOp.getValueType();
3923 unsigned ValWidth = ValVT.getSizeInBits();
3924 EVT ValEltVT = ValVT.getVectorElementType();
3925 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3926 assert(StVT.getVectorElementType() == ValEltVT);
3928 int Idx = 0; // current index to store
3929 unsigned Offset = 0; // offset from base to store
3930 while (StWidth != 0) {
3931 // Find the largest vector type we can store with.
3932 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3933 unsigned NewVTWidth = NewVT.getSizeInBits();
3934 unsigned Increment = NewVTWidth / 8;
3935 if (NewVT.isVector()) {
3936 unsigned NumVTElts = NewVT.getVectorNumElements();
3938 SDValue EOp = DAG.getNode(
3939 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3940 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3941 StChain.push_back(DAG.getStore(
3942 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3943 MinAlign(Align, Offset), MMOFlags, AAInfo));
3944 StWidth -= NewVTWidth;
3945 Offset += Increment;
3948 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
3949 } while (StWidth != 0 && StWidth >= NewVTWidth);
3951 // Cast the vector to the scalar type we can store.
3952 unsigned NumElts = ValWidth / NewVTWidth;
3953 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3954 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3955 // Readjust index position based on new vector type.
3956 Idx = Idx * ValEltWidth / NewVTWidth;
3958 SDValue EOp = DAG.getNode(
3959 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3960 DAG.getConstant(Idx++, dl,
3961 TLI.getVectorIdxTy(DAG.getDataLayout())));
3962 StChain.push_back(DAG.getStore(
3963 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
3964 MinAlign(Align, Offset), MMOFlags, AAInfo));
3965 StWidth -= NewVTWidth;
3966 Offset += Increment;
3967 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
3968 } while (StWidth != 0 && StWidth >= NewVTWidth);
3969 // Restore index back to be relative to the original widen element type.
3970 Idx = Idx * NewVTWidth / ValEltWidth;
3976 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3978 // For extension loads, it may not be more efficient to truncate the vector
3979 // and then store it. Instead, we extract each element and then store it.
3980 SDValue Chain = ST->getChain();
3981 SDValue BasePtr = ST->getBasePtr();
3982 unsigned Align = ST->getAlignment();
3983 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
3984 AAMDNodes AAInfo = ST->getAAInfo();
3985 SDValue ValOp = GetWidenedVector(ST->getValue());
3988 EVT StVT = ST->getMemoryVT();
3989 EVT ValVT = ValOp.getValueType();
3991 // It must be true that the wide vector type is bigger than where we need to
3993 assert(StVT.isVector() && ValOp.getValueType().isVector());
3994 assert(StVT.bitsLT(ValOp.getValueType()));
3996 // For truncating stores, we can not play the tricks of chopping legal vector
3997 // types and bitcast it to the right type. Instead, we unroll the store.
3998 EVT StEltVT = StVT.getVectorElementType();
3999 EVT ValEltVT = ValVT.getVectorElementType();
4000 unsigned Increment = ValEltVT.getSizeInBits() / 8;
4001 unsigned NumElts = StVT.getVectorNumElements();
4002 SDValue EOp = DAG.getNode(
4003 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4004 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4005 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
4006 ST->getPointerInfo(), StEltVT, Align,
4008 unsigned Offset = Increment;
4009 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
4010 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
4011 SDValue EOp = DAG.getNode(
4012 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4013 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4014 StChain.push_back(DAG.getTruncStore(
4015 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
4016 StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
4020 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
4021 /// input vector must have the same element type as NVT.
4022 /// FillWithZeroes specifies that the vector should be widened with zeroes.
4023 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
4024 bool FillWithZeroes) {
4025 // Note that InOp might have been widened so it might already have
4026 // the right width or it might need be narrowed.
4027 EVT InVT = InOp.getValueType();
4028 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
4029 "input and widen element type must match");
4032 // Check if InOp already has the right width.
4036 unsigned InNumElts = InVT.getVectorNumElements();
4037 unsigned WidenNumElts = NVT.getVectorNumElements();
4038 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
4039 unsigned NumConcat = WidenNumElts / InNumElts;
4040 SmallVector<SDValue, 16> Ops(NumConcat);
4041 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
4044 for (unsigned i = 1; i != NumConcat; ++i)
4047 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
4050 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
4052 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
4053 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4055 // Fall back to extract and build.
4056 SmallVector<SDValue, 16> Ops(WidenNumElts);
4057 EVT EltVT = NVT.getVectorElementType();
4058 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
4060 for (Idx = 0; Idx < MinNumElts; ++Idx)
4061 Ops[Idx] = DAG.getNode(
4062 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
4063 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4065 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
4066 DAG.getUNDEF(EltVT);
4067 for ( ; Idx < WidenNumElts; ++Idx)
4069 return DAG.getBuildVector(NVT, dl, Ops);