1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines interfaces to access the target independent code
10 // generation passes provided by the LLVM backend.
12 //===---------------------------------------------------------------------===//
14 #include "llvm/CodeGen/TargetPassConfig.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/Analysis/BasicAliasAnalysis.h"
19 #include "llvm/Analysis/CFLAndersAliasAnalysis.h"
20 #include "llvm/Analysis/CFLSteensAliasAnalysis.h"
21 #include "llvm/Analysis/CallGraphSCCPass.h"
22 #include "llvm/Analysis/ScopedNoAliasAA.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
25 #include "llvm/CodeGen/CSEConfigBase.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachinePassRegistry.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/RegAllocRegistry.h"
30 #include "llvm/IR/IRPrintingPasses.h"
31 #include "llvm/IR/LegacyPassManager.h"
32 #include "llvm/IR/Verifier.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCTargetOptions.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/Threading.h"
42 #include "llvm/Support/SaveAndRestore.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Transforms/Scalar.h"
45 #include "llvm/Transforms/Utils.h"
46 #include "llvm/Transforms/Utils/SymbolRewriter.h"
52 cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
53 cl::desc("Enable interprocedural register allocation "
54 "to reduce load/store at procedure calls."));
55 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
56 cl::desc("Disable Post Regalloc Scheduler"));
57 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
58 cl::desc("Disable branch folding"));
59 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
60 cl::desc("Disable tail duplication"));
61 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
62 cl::desc("Disable pre-register allocation tail duplication"));
63 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
64 cl::Hidden, cl::desc("Disable probability-driven block placement"));
65 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
66 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
67 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
68 cl::desc("Disable Stack Slot Coloring"));
69 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
70 cl::desc("Disable Machine Dead Code Elimination"));
71 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
72 cl::desc("Disable Early If-conversion"));
73 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
74 cl::desc("Disable Machine LICM"));
75 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
76 cl::desc("Disable Machine Common Subexpression Elimination"));
77 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
78 "optimize-regalloc", cl::Hidden,
79 cl::desc("Enable optimized register allocation compilation path."));
80 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
82 cl::desc("Disable Machine LICM"));
83 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
84 cl::desc("Disable Machine Sinking"));
85 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
87 cl::desc("Disable PostRA Machine Sinking"));
88 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
89 cl::desc("Disable Loop Strength Reduction Pass"));
90 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
91 cl::Hidden, cl::desc("Disable ConstantHoisting"));
92 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
93 cl::desc("Disable Codegen Prepare"));
94 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
95 cl::desc("Disable Copy Propagation pass"));
96 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
97 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
98 static cl::opt<bool> EnableImplicitNullChecks(
99 "enable-implicit-null-checks",
100 cl::desc("Fold null checks into faulting memory operations"),
101 cl::init(false), cl::Hidden);
102 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
103 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
104 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
105 cl::desc("Print LLVM IR input to isel pass"));
106 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
107 cl::desc("Dump garbage collector data"));
108 static cl::opt<cl::boolOrDefault>
109 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
110 cl::desc("Verify generated machine code"),
112 enum RunOutliner { AlwaysOutline, NeverOutline, TargetDefault };
113 // Enable or disable the MachineOutliner.
114 static cl::opt<RunOutliner> EnableMachineOutliner(
115 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
116 cl::Hidden, cl::ValueOptional, cl::init(TargetDefault),
117 cl::values(clEnumValN(AlwaysOutline, "always",
118 "Run on all functions guaranteed to be beneficial"),
119 clEnumValN(NeverOutline, "never", "Disable all outlining"),
120 // Sentinel value for unspecified option.
121 clEnumValN(AlwaysOutline, "", "")));
122 // Enable or disable FastISel. Both options are needed, because
123 // FastISel is enabled by default with -fast, and we wish to be
124 // able to enable or disable fast-isel independently from -O0.
125 static cl::opt<cl::boolOrDefault>
126 EnableFastISelOption("fast-isel", cl::Hidden,
127 cl::desc("Enable the \"fast\" instruction selector"));
129 static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
130 "global-isel", cl::Hidden,
131 cl::desc("Enable the \"global\" instruction selector"));
133 static cl::opt<std::string> PrintMachineInstrs(
134 "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
135 cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
137 static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
138 "global-isel-abort", cl::Hidden,
139 cl::desc("Enable abort calls when \"global\" instruction selection "
140 "fails to lower/select an instruction"),
142 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
143 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
144 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
145 "Disable the abort but emit a diagnostic on failure")));
147 // Temporary option to allow experimenting with MachineScheduler as a post-RA
148 // scheduler. Targets can "properly" enable this with
149 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
150 // Targets can return true in targetSchedulesPostRAScheduling() and
151 // insert a PostRA scheduling pass wherever it wants.
152 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
153 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
155 // Experimental option to run live interval analysis early.
156 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
157 cl::desc("Run live interval analysis earlier in the pipeline"));
159 // Experimental option to use CFL-AA in codegen
160 enum class CFLAAType { None, Steensgaard, Andersen, Both };
161 static cl::opt<CFLAAType> UseCFLAA(
162 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
163 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
164 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
165 clEnumValN(CFLAAType::Steensgaard, "steens",
166 "Enable unification-based CFL-AA"),
167 clEnumValN(CFLAAType::Andersen, "anders",
168 "Enable inclusion-based CFL-AA"),
169 clEnumValN(CFLAAType::Both, "both",
170 "Enable both variants of CFL-AA")));
172 /// Option names for limiting the codegen pipeline.
173 /// Those are used in error reporting and we didn't want
174 /// to duplicate their names all over the place.
175 const char *StartAfterOptName = "start-after";
176 const char *StartBeforeOptName = "start-before";
177 const char *StopAfterOptName = "stop-after";
178 const char *StopBeforeOptName = "stop-before";
180 static cl::opt<std::string>
181 StartAfterOpt(StringRef(StartAfterOptName),
182 cl::desc("Resume compilation after a specific pass"),
183 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
185 static cl::opt<std::string>
186 StartBeforeOpt(StringRef(StartBeforeOptName),
187 cl::desc("Resume compilation before a specific pass"),
188 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
190 static cl::opt<std::string>
191 StopAfterOpt(StringRef(StopAfterOptName),
192 cl::desc("Stop compilation after a specific pass"),
193 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
195 static cl::opt<std::string>
196 StopBeforeOpt(StringRef(StopBeforeOptName),
197 cl::desc("Stop compilation before a specific pass"),
198 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
200 /// Allow standard passes to be disabled by command line options. This supports
201 /// simple binary flags that either suppress the pass or do nothing.
202 /// i.e. -disable-mypass=false has no effect.
203 /// These should be converted to boolOrDefault in order to use applyOverride.
204 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
207 return IdentifyingPassPtr();
211 /// Allow standard passes to be disabled by the command line, regardless of who
212 /// is adding the pass.
214 /// StandardID is the pass identified in the standard pass pipeline and provided
215 /// to addPass(). It may be a target-specific ID in the case that the target
216 /// directly adds its own pass, but in that case we harmlessly fall through.
218 /// TargetID is the pass that the target has configured to override StandardID.
220 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
221 /// pass to run. This allows multiple options to control a single pass depending
222 /// on where in the pipeline that pass is added.
223 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
224 IdentifyingPassPtr TargetID) {
225 if (StandardID == &PostRASchedulerID)
226 return applyDisable(TargetID, DisablePostRASched);
228 if (StandardID == &BranchFolderPassID)
229 return applyDisable(TargetID, DisableBranchFold);
231 if (StandardID == &TailDuplicateID)
232 return applyDisable(TargetID, DisableTailDuplicate);
234 if (StandardID == &EarlyTailDuplicateID)
235 return applyDisable(TargetID, DisableEarlyTailDup);
237 if (StandardID == &MachineBlockPlacementID)
238 return applyDisable(TargetID, DisableBlockPlacement);
240 if (StandardID == &StackSlotColoringID)
241 return applyDisable(TargetID, DisableSSC);
243 if (StandardID == &DeadMachineInstructionElimID)
244 return applyDisable(TargetID, DisableMachineDCE);
246 if (StandardID == &EarlyIfConverterID)
247 return applyDisable(TargetID, DisableEarlyIfConversion);
249 if (StandardID == &EarlyMachineLICMID)
250 return applyDisable(TargetID, DisableMachineLICM);
252 if (StandardID == &MachineCSEID)
253 return applyDisable(TargetID, DisableMachineCSE);
255 if (StandardID == &MachineLICMID)
256 return applyDisable(TargetID, DisablePostRAMachineLICM);
258 if (StandardID == &MachineSinkingID)
259 return applyDisable(TargetID, DisableMachineSink);
261 if (StandardID == &PostRAMachineSinkingID)
262 return applyDisable(TargetID, DisablePostRAMachineSink);
264 if (StandardID == &MachineCopyPropagationID)
265 return applyDisable(TargetID, DisableCopyProp);
270 //===---------------------------------------------------------------------===//
272 //===---------------------------------------------------------------------===//
274 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
275 "Target Pass Configuration", false, false)
276 char TargetPassConfig::ID = 0;
280 struct InsertedPass {
281 AnalysisID TargetPassID;
282 IdentifyingPassPtr InsertedPassID;
286 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
287 bool VerifyAfter, bool PrintAfter)
288 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
289 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
291 Pass *getInsertedPass() const {
292 assert(InsertedPassID.isValid() && "Illegal Pass ID!");
293 if (InsertedPassID.isInstance())
294 return InsertedPassID.getInstance();
295 Pass *NP = Pass::createPass(InsertedPassID.getID());
296 assert(NP && "Pass ID not registered");
301 } // end anonymous namespace
305 class PassConfigImpl {
307 // List of passes explicitly substituted by this target. Normally this is
308 // empty, but it is a convenient way to suppress or replace specific passes
309 // that are part of a standard pass pipeline without overridding the entire
310 // pipeline. This mechanism allows target options to inherit a standard pass's
311 // user interface. For example, a target may disable a standard pass by
312 // default by substituting a pass ID of zero, and the user may still enable
313 // that standard pass with an explicit command line option.
314 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
316 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
317 /// is inserted after each instance of the first one.
318 SmallVector<InsertedPass, 4> InsertedPasses;
321 } // end namespace llvm
323 // Out of line virtual method.
324 TargetPassConfig::~TargetPassConfig() {
328 static const PassInfo *getPassInfo(StringRef PassName) {
329 if (PassName.empty())
332 const PassRegistry &PR = *PassRegistry::getPassRegistry();
333 const PassInfo *PI = PR.getPassInfo(PassName);
335 report_fatal_error(Twine('\"') + Twine(PassName) +
336 Twine("\" pass is not registered."));
340 static AnalysisID getPassIDFromName(StringRef PassName) {
341 const PassInfo *PI = getPassInfo(PassName);
342 return PI ? PI->getTypeInfo() : nullptr;
345 static std::pair<StringRef, unsigned>
346 getPassNameAndInstanceNum(StringRef PassName) {
347 StringRef Name, InstanceNumStr;
348 std::tie(Name, InstanceNumStr) = PassName.split(',');
350 unsigned InstanceNum = 0;
351 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
352 report_fatal_error("invalid pass instance specifier " + PassName);
354 return std::make_pair(Name, InstanceNum);
357 void TargetPassConfig::setStartStopPasses() {
358 StringRef StartBeforeName;
359 std::tie(StartBeforeName, StartBeforeInstanceNum) =
360 getPassNameAndInstanceNum(StartBeforeOpt);
362 StringRef StartAfterName;
363 std::tie(StartAfterName, StartAfterInstanceNum) =
364 getPassNameAndInstanceNum(StartAfterOpt);
366 StringRef StopBeforeName;
367 std::tie(StopBeforeName, StopBeforeInstanceNum)
368 = getPassNameAndInstanceNum(StopBeforeOpt);
370 StringRef StopAfterName;
371 std::tie(StopAfterName, StopAfterInstanceNum)
372 = getPassNameAndInstanceNum(StopAfterOpt);
374 StartBefore = getPassIDFromName(StartBeforeName);
375 StartAfter = getPassIDFromName(StartAfterName);
376 StopBefore = getPassIDFromName(StopBeforeName);
377 StopAfter = getPassIDFromName(StopAfterName);
378 if (StartBefore && StartAfter)
379 report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
380 Twine(StartAfterOptName) + Twine(" specified!"));
381 if (StopBefore && StopAfter)
382 report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
383 Twine(StopAfterOptName) + Twine(" specified!"));
384 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
387 // Out of line constructor provides default values for pass options and
388 // registers all common codegen passes.
389 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
390 : ImmutablePass(ID), PM(&pm), TM(&TM) {
391 Impl = new PassConfigImpl();
393 // Register all target independent codegen passes to activate their PassIDs,
394 // including this pass itself.
395 initializeCodeGen(*PassRegistry::getPassRegistry());
397 // Also register alias analysis passes required by codegen passes.
398 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
399 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
401 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
402 TM.Options.PrintMachineCode = true;
404 if (EnableIPRA.getNumOccurrences())
405 TM.Options.EnableIPRA = EnableIPRA;
407 // If not explicitly specified, use target default.
408 TM.Options.EnableIPRA |= TM.useIPRA();
411 if (TM.Options.EnableIPRA)
412 setRequiresCodeGenSCCOrder();
414 if (EnableGlobalISelAbort.getNumOccurrences())
415 TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
417 setStartStopPasses();
420 CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
421 return TM->getOptLevel();
424 /// Insert InsertedPassID pass after TargetPassID.
425 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
426 IdentifyingPassPtr InsertedPassID,
427 bool VerifyAfter, bool PrintAfter) {
428 assert(((!InsertedPassID.isInstance() &&
429 TargetPassID != InsertedPassID.getID()) ||
430 (InsertedPassID.isInstance() &&
431 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
432 "Insert a pass after itself!");
433 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
437 /// createPassConfig - Create a pass configuration object to be used by
438 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
440 /// Targets may override this to extend TargetPassConfig.
441 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
442 return new TargetPassConfig(*this, PM);
445 TargetPassConfig::TargetPassConfig()
446 : ImmutablePass(ID) {
447 report_fatal_error("Trying to construct TargetPassConfig without a target "
448 "machine. Scheduling a CodeGen pass without a target "
452 bool TargetPassConfig::willCompleteCodeGenPipeline() {
453 return StopBeforeOpt.empty() && StopAfterOpt.empty();
456 bool TargetPassConfig::hasLimitedCodeGenPipeline() {
457 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
458 !willCompleteCodeGenPipeline();
462 TargetPassConfig::getLimitedCodeGenPipelineReason(const char *Separator) const {
463 if (!hasLimitedCodeGenPipeline())
464 return std::string();
466 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
467 &StopAfterOpt, &StopBeforeOpt};
468 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
469 StopAfterOptName, StopBeforeOptName};
471 for (int Idx = 0; Idx < 4; ++Idx)
472 if (!PassNames[Idx]->empty()) {
476 Res += OptNames[Idx];
481 // Helper to verify the analysis is really immutable.
482 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
483 assert(!Initialized && "PassConfig is immutable");
487 void TargetPassConfig::substitutePass(AnalysisID StandardID,
488 IdentifyingPassPtr TargetID) {
489 Impl->TargetPasses[StandardID] = TargetID;
492 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
493 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
494 I = Impl->TargetPasses.find(ID);
495 if (I == Impl->TargetPasses.end())
500 bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
501 IdentifyingPassPtr TargetID = getPassSubstitution(ID);
502 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
503 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
504 FinalPtr.getID() != ID;
507 /// Add a pass to the PassManager if that pass is supposed to be run. If the
508 /// Started/Stopped flags indicate either that the compilation should start at
509 /// a later pass or that it should stop after an earlier pass, then do not add
510 /// the pass. Finally, compare the current pass against the StartAfter
511 /// and StopAfter options and change the Started/Stopped flags accordingly.
512 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
513 assert(!Initialized && "PassConfig is immutable");
515 // Cache the Pass ID here in case the pass manager finds this pass is
516 // redundant with ones already scheduled / available, and deletes it.
517 // Fundamentally, once we add the pass to the manager, we no longer own it
518 // and shouldn't reference it.
519 AnalysisID PassID = P->getPassID();
521 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
523 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
525 if (Started && !Stopped) {
527 // Construct banner message before PM->add() as that may delete the pass.
528 if (AddingMachinePasses && (printAfter || verifyAfter))
529 Banner = std::string("After ") + std::string(P->getPassName());
531 if (AddingMachinePasses) {
533 addPrintPass(Banner);
535 addVerifyPass(Banner);
538 // Add the passes after the pass P if there is any.
539 for (auto IP : Impl->InsertedPasses) {
540 if (IP.TargetPassID == PassID)
541 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
547 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
550 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
552 if (Stopped && !Started)
553 report_fatal_error("Cannot stop compilation after pass that is not run");
556 /// Add a CodeGen pass at this point in the pipeline after checking for target
557 /// and command line overrides.
559 /// addPass cannot return a pointer to the pass instance because is internal the
560 /// PassManager and the instance we create here may already be freed.
561 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
563 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
564 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
565 if (!FinalPtr.isValid())
569 if (FinalPtr.isInstance())
570 P = FinalPtr.getInstance();
572 P = Pass::createPass(FinalPtr.getID());
574 llvm_unreachable("Pass ID not registered");
576 AnalysisID FinalID = P->getPassID();
577 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
582 void TargetPassConfig::printAndVerify(const std::string &Banner) {
583 addPrintPass(Banner);
584 addVerifyPass(Banner);
587 void TargetPassConfig::addPrintPass(const std::string &Banner) {
588 if (TM->shouldPrintMachineCode())
589 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
592 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
593 bool Verify = VerifyMachineCode == cl::BOU_TRUE;
594 #ifdef EXPENSIVE_CHECKS
595 if (VerifyMachineCode == cl::BOU_UNSET)
596 Verify = TM->isMachineVerifierClean();
599 PM->add(createMachineVerifierPass(Banner));
602 /// Add common target configurable passes that perform LLVM IR to IR transforms
603 /// following machine independent optimization.
604 void TargetPassConfig::addIRPasses() {
606 case CFLAAType::Steensgaard:
607 addPass(createCFLSteensAAWrapperPass());
609 case CFLAAType::Andersen:
610 addPass(createCFLAndersAAWrapperPass());
612 case CFLAAType::Both:
613 addPass(createCFLAndersAAWrapperPass());
614 addPass(createCFLSteensAAWrapperPass());
620 // Basic AliasAnalysis support.
621 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
622 // BasicAliasAnalysis wins if they disagree. This is intended to help
623 // support "obvious" type-punning idioms.
624 addPass(createTypeBasedAAWrapperPass());
625 addPass(createScopedNoAliasAAWrapperPass());
626 addPass(createBasicAAWrapperPass());
628 // Before running any passes, run the verifier to determine if the input
629 // coming from the front-end and/or optimizer is valid.
631 addPass(createVerifierPass());
633 // Run loop strength reduction before anything else.
634 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
635 addPass(createLoopStrengthReducePass());
637 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
640 // Run GC lowering passes for builtin collectors
641 // TODO: add a pass insertion point here
642 addPass(createGCLoweringPass());
643 addPass(createShadowStackGCLoweringPass());
645 // Make sure that no unreachable blocks are instruction selected.
646 addPass(createUnreachableBlockEliminationPass());
648 // Prepare expensive constants for SelectionDAG.
649 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
650 addPass(createConstantHoistingPass());
652 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
653 addPass(createPartiallyInlineLibCallsPass());
655 // Instrument function entry and exit, e.g. with calls to mcount().
656 addPass(createPostInlineEntryExitInstrumenterPass());
658 // Add scalarization of target's unsupported masked memory intrinsics pass.
659 // the unsupported intrinsic will be replaced with a chain of basic blocks,
660 // that stores/loads element one-by-one if the appropriate mask bit is set.
661 addPass(createScalarizeMaskedMemIntrinPass());
663 // Expand reduction intrinsics into shuffle sequences if the target wants to.
664 addPass(createExpandReductionsPass());
667 /// Turn exception handling constructs into something the code generators can
669 void TargetPassConfig::addPassesToHandleExceptions() {
670 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
671 assert(MCAI && "No MCAsmInfo");
672 switch (MCAI->getExceptionHandlingType()) {
673 case ExceptionHandling::SjLj:
674 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
675 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
676 // catch info can get misplaced when a selector ends up more than one block
677 // removed from the parent invoke(s). This could happen when a landing
678 // pad is shared by multiple invokes and is also a target of a normal
679 // edge from elsewhere.
680 addPass(createSjLjEHPreparePass());
682 case ExceptionHandling::DwarfCFI:
683 case ExceptionHandling::ARM:
684 addPass(createDwarfEHPass());
686 case ExceptionHandling::WinEH:
687 // We support using both GCC-style and MSVC-style exceptions on Windows, so
688 // add both preparation passes. Each pass will only actually run if it
689 // recognizes the personality function.
690 addPass(createWinEHPass());
691 addPass(createDwarfEHPass());
693 case ExceptionHandling::Wasm:
694 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
695 // on catchpads and cleanuppads because it does not outline them into
696 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
697 // should remove PHIs there.
698 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
699 addPass(createWasmEHPass());
701 case ExceptionHandling::None:
702 addPass(createLowerInvokePass());
704 // The lower invoke pass may create unreachable code. Remove it.
705 addPass(createUnreachableBlockEliminationPass());
710 /// Add pass to prepare the LLVM IR for code generation. This should be done
711 /// before exception handling preparation passes.
712 void TargetPassConfig::addCodeGenPrepare() {
713 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
714 addPass(createCodeGenPreparePass());
715 addPass(createRewriteSymbolsPass());
718 /// Add common passes that perform LLVM IR to IR transforms in preparation for
719 /// instruction selection.
720 void TargetPassConfig::addISelPrepare() {
723 // Force codegen to run according to the callgraph.
724 if (requiresCodeGenSCCOrder())
725 addPass(new DummyCGSCCPass);
727 // Add both the safe stack and the stack protection passes: each of them will
728 // only protect functions that have corresponding attributes.
729 addPass(createSafeStackPass());
730 addPass(createStackProtectorPass());
733 addPass(createPrintFunctionPass(
734 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
736 // All passes which modify the LLVM IR are now complete; run the verifier
737 // to ensure that the IR is valid.
739 addPass(createVerifierPass());
742 bool TargetPassConfig::addCoreISelPasses() {
743 // Enable FastISel with -fast-isel, but allow that to be overridden.
744 TM->setO0WantsFastISel(EnableFastISelOption != cl::BOU_FALSE);
746 // Determine an instruction selector.
747 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
748 SelectorType Selector;
750 if (EnableFastISelOption == cl::BOU_TRUE)
751 Selector = SelectorType::FastISel;
752 else if (EnableGlobalISelOption == cl::BOU_TRUE ||
753 (TM->Options.EnableGlobalISel &&
754 EnableGlobalISelOption != cl::BOU_FALSE))
755 Selector = SelectorType::GlobalISel;
756 else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
757 Selector = SelectorType::FastISel;
759 Selector = SelectorType::SelectionDAG;
761 // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
762 if (Selector == SelectorType::FastISel) {
763 TM->setFastISel(true);
764 TM->setGlobalISel(false);
765 } else if (Selector == SelectorType::GlobalISel) {
766 TM->setFastISel(false);
767 TM->setGlobalISel(true);
770 // Add instruction selector passes.
771 if (Selector == SelectorType::GlobalISel) {
772 SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
773 if (addIRTranslator())
776 addPreLegalizeMachineIR();
778 if (addLegalizeMachineIR())
781 // Before running the register bank selector, ask the target if it
782 // wants to run some passes.
783 addPreRegBankSelect();
785 if (addRegBankSelect())
788 addPreGlobalInstructionSelect();
790 if (addGlobalInstructionSelect())
793 // Pass to reset the MachineFunction if the ISel failed.
794 addPass(createResetMachineFunctionPass(
795 reportDiagnosticWhenGlobalISelFallback(), isGlobalISelAbortEnabled()));
797 // Provide a fallback path when we do not want to abort on
798 // not-yet-supported input.
799 if (!isGlobalISelAbortEnabled() && addInstSelector())
802 } else if (addInstSelector())
805 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
807 addPass(&FinalizeISelID);
809 // Print the instruction selected machine code...
810 printAndVerify("After Instruction Selection");
815 bool TargetPassConfig::addISelPasses() {
816 if (TM->useEmulatedTLS())
817 addPass(createLowerEmuTLSPass());
819 addPass(createPreISelIntrinsicLoweringPass());
820 addPass(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
823 addPassesToHandleExceptions();
826 return addCoreISelPasses();
829 /// -regalloc=... command line option.
830 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
831 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
832 RegisterPassParser<RegisterRegAlloc>>
833 RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
834 cl::desc("Register allocator to use"));
836 /// Add the complete set of target-independent postISel code generator passes.
838 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
839 /// with nontrivial configuration or multiple passes are broken out below in
840 /// add%Stage routines.
842 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
843 /// addPre/Post methods with empty header implementations allow injecting
844 /// target-specific fixups just before or after major stages. Additionally,
845 /// targets have the flexibility to change pass order within a stage by
846 /// overriding default implementation of add%Stage routines below. Each
847 /// technique has maintainability tradeoffs because alternate pass orders are
848 /// not well supported. addPre/Post works better if the target pass is easily
849 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
850 /// the target should override the stage instead.
852 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
853 /// before/after any target-independent pass. But it's currently overkill.
854 void TargetPassConfig::addMachinePasses() {
855 AddingMachinePasses = true;
857 // Insert a machine instr printer pass after the specified pass.
858 StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
859 if (!PrintMachineInstrsPassName.equals("") &&
860 !PrintMachineInstrsPassName.equals("option-unspecified")) {
861 if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
862 const PassRegistry *PR = PassRegistry::getPassRegistry();
863 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
864 assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
865 const char *TID = (const char *)(TPI->getTypeInfo());
866 const char *IID = (const char *)(IPI->getTypeInfo());
867 insertPass(TID, IID);
871 // Add passes that optimize machine instructions in SSA form.
872 if (getOptLevel() != CodeGenOpt::None) {
873 addMachineSSAOptimization();
875 // If the target requests it, assign local variables to stack slots relative
876 // to one another and simplify frame index references where possible.
877 addPass(&LocalStackSlotAllocationID, false);
880 if (TM->Options.EnableIPRA)
881 addPass(createRegUsageInfoPropPass());
883 // Run pre-ra passes.
886 // Run register allocation and passes that are tightly coupled with it,
887 // including phi elimination and scheduling.
888 if (getOptimizeRegAlloc())
889 addOptimizedRegAlloc();
893 // Run post-ra passes.
896 // Insert prolog/epilog code. Eliminate abstract frame index references...
897 if (getOptLevel() != CodeGenOpt::None) {
898 addPass(&PostRAMachineSinkingID);
899 addPass(&ShrinkWrapID);
902 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
903 // do so if it hasn't been disabled, substituted, or overridden.
904 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
905 addPass(createPrologEpilogInserterPass());
907 /// Add passes that optimize machine instructions after register allocation.
908 if (getOptLevel() != CodeGenOpt::None)
909 addMachineLateOptimization();
911 // Expand pseudo instructions before second scheduling pass.
912 addPass(&ExpandPostRAPseudosID);
914 // Run pre-sched2 passes.
917 if (EnableImplicitNullChecks)
918 addPass(&ImplicitNullChecksID);
920 // Second pass scheduler.
921 // Let Target optionally insert this pass by itself at some other
923 if (getOptLevel() != CodeGenOpt::None &&
924 !TM->targetSchedulesPostRAScheduling()) {
926 addPass(&PostMachineSchedulerID);
928 addPass(&PostRASchedulerID);
934 addPass(createGCInfoPrinter(dbgs()), false, false);
937 // Basic block placement.
938 if (getOptLevel() != CodeGenOpt::None)
943 if (TM->Options.EnableIPRA)
944 // Collect register usage information and produce a register mask of
945 // clobbered registers, to be used to optimize call sites.
946 addPass(createRegUsageInfoCollector());
948 addPass(&FuncletLayoutID, false);
950 addPass(&StackMapLivenessID, false);
951 addPass(&LiveDebugValuesID, false);
953 // Insert before XRay Instrumentation.
954 addPass(&FEntryInserterID, false);
956 addPass(&XRayInstrumentationID, false);
957 addPass(&PatchableFunctionID, false);
959 if (TM->Options.EnableMachineOutliner && getOptLevel() != CodeGenOpt::None &&
960 EnableMachineOutliner != NeverOutline) {
961 bool RunOnAllFunctions = (EnableMachineOutliner == AlwaysOutline);
962 bool AddOutliner = RunOnAllFunctions ||
963 TM->Options.SupportsDefaultOutlining;
965 addPass(createMachineOutlinerPass(RunOnAllFunctions));
968 // Add passes that directly emit MI after all other MI passes.
971 AddingMachinePasses = false;
974 /// Add passes that optimize machine instructions in SSA form.
975 void TargetPassConfig::addMachineSSAOptimization() {
976 // Pre-ra tail duplication.
977 addPass(&EarlyTailDuplicateID);
979 // Optimize PHIs before DCE: removing dead PHI cycles may make more
980 // instructions dead.
981 addPass(&OptimizePHIsID, false);
983 // This pass merges large allocas. StackSlotColoring is a different pass
984 // which merges spill slots.
985 addPass(&StackColoringID, false);
987 // If the target requests it, assign local variables to stack slots relative
988 // to one another and simplify frame index references where possible.
989 addPass(&LocalStackSlotAllocationID, false);
991 // With optimization, dead code should already be eliminated. However
992 // there is one known exception: lowered code for arguments that are only
993 // used by tail calls, where the tail calls reuse the incoming stack
994 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
995 addPass(&DeadMachineInstructionElimID);
997 // Allow targets to insert passes that improve instruction level parallelism,
998 // like if-conversion. Such passes will typically need dominator trees and
999 // loop info, just like LICM and CSE below.
1002 addPass(&EarlyMachineLICMID, false);
1003 addPass(&MachineCSEID, false);
1005 addPass(&MachineSinkingID);
1007 addPass(&PeepholeOptimizerID);
1008 // Clean-up the dead code that may have been generated by peephole
1010 addPass(&DeadMachineInstructionElimID);
1013 //===---------------------------------------------------------------------===//
1014 /// Register Allocation Pass Configuration
1015 //===---------------------------------------------------------------------===//
1017 bool TargetPassConfig::getOptimizeRegAlloc() const {
1018 switch (OptimizeRegAlloc) {
1019 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1020 case cl::BOU_TRUE: return true;
1021 case cl::BOU_FALSE: return false;
1023 llvm_unreachable("Invalid optimize-regalloc state");
1026 /// A dummy default pass factory indicates whether the register allocator is
1027 /// overridden on the command line.
1028 static llvm::once_flag InitializeDefaultRegisterAllocatorFlag;
1030 static RegisterRegAlloc
1031 defaultRegAlloc("default",
1032 "pick register allocator based on -O option",
1033 useDefaultRegisterAllocator);
1035 static void initializeDefaultRegisterAllocatorOnce() {
1036 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1040 RegisterRegAlloc::setDefault(RegAlloc);
1044 /// Instantiate the default register allocator pass for this target for either
1045 /// the optimized or unoptimized allocation path. This will be added to the pass
1046 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1047 /// in the optimized case.
1049 /// A target that uses the standard regalloc pass order for fast or optimized
1050 /// allocation may still override this for per-target regalloc
1051 /// selection. But -regalloc=... always takes precedence.
1052 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
1054 return createGreedyRegisterAllocator();
1056 return createFastRegisterAllocator();
1059 /// Find and instantiate the register allocation pass requested by this target
1060 /// at the current optimization level. Different register allocators are
1061 /// defined as separate passes because they may require different analysis.
1063 /// This helper ensures that the regalloc= option is always available,
1064 /// even for targets that override the default allocator.
1066 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1067 /// this can be folded into addPass.
1068 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
1069 // Initialize the global default.
1070 llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
1071 initializeDefaultRegisterAllocatorOnce);
1073 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
1074 if (Ctor != useDefaultRegisterAllocator)
1077 // With no -regalloc= override, ask the target for a regalloc pass.
1078 return createTargetRegisterAllocator(Optimized);
1081 bool TargetPassConfig::addRegAssignmentFast() {
1082 if (RegAlloc != &useDefaultRegisterAllocator &&
1083 RegAlloc != &createFastRegisterAllocator)
1084 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1086 addPass(createRegAllocPass(false));
1090 bool TargetPassConfig::addRegAssignmentOptimized() {
1091 // Add the selected register allocation pass.
1092 addPass(createRegAllocPass(true));
1094 // Allow targets to change the register assignments before rewriting.
1097 // Finally rewrite virtual registers.
1098 addPass(&VirtRegRewriterID);
1099 // Perform stack slot coloring and post-ra machine LICM.
1101 // FIXME: Re-enable coloring with register when it's capable of adding
1103 addPass(&StackSlotColoringID);
1108 /// Return true if the default global register allocator is in use and
1109 /// has not be overriden on the command line with '-regalloc=...'
1110 bool TargetPassConfig::usingDefaultRegAlloc() const {
1111 return RegAlloc.getNumOccurrences() == 0;
1114 /// Add the minimum set of target-independent passes that are required for
1115 /// register allocation. No coalescing or scheduling.
1116 void TargetPassConfig::addFastRegAlloc() {
1117 addPass(&PHIEliminationID, false);
1118 addPass(&TwoAddressInstructionPassID, false);
1120 addRegAssignmentFast();
1123 /// Add standard target-independent passes that are tightly coupled with
1124 /// optimized register allocation, including coalescing, machine instruction
1125 /// scheduling, and register allocation itself.
1126 void TargetPassConfig::addOptimizedRegAlloc() {
1127 addPass(&DetectDeadLanesID, false);
1129 addPass(&ProcessImplicitDefsID, false);
1131 // LiveVariables currently requires pure SSA form.
1133 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1134 // LiveVariables can be removed completely, and LiveIntervals can be directly
1135 // computed. (We still either need to regenerate kill flags after regalloc, or
1136 // preferably fix the scavenger to not depend on them).
1137 addPass(&LiveVariablesID, false);
1139 // Edge splitting is smarter with machine loop info.
1140 addPass(&MachineLoopInfoID, false);
1141 addPass(&PHIEliminationID, false);
1143 // Eventually, we want to run LiveIntervals before PHI elimination.
1144 if (EarlyLiveIntervals)
1145 addPass(&LiveIntervalsID, false);
1147 addPass(&TwoAddressInstructionPassID, false);
1148 addPass(&RegisterCoalescerID);
1150 // The machine scheduler may accidentally create disconnected components
1151 // when moving subregister definitions around, avoid this by splitting them to
1152 // separate vregs before. Splitting can also improve reg. allocation quality.
1153 addPass(&RenameIndependentSubregsID);
1155 // PreRA instruction scheduling.
1156 addPass(&MachineSchedulerID);
1158 if (addRegAssignmentOptimized()) {
1159 // Allow targets to expand pseudo instructions depending on the choice of
1160 // registers before MachineCopyPropagation.
1163 // Copy propagate to forward register uses and try to eliminate COPYs that
1164 // were not coalesced.
1165 addPass(&MachineCopyPropagationID);
1167 // Run post-ra machine LICM to hoist reloads / remats.
1169 // FIXME: can this move into MachineLateOptimization?
1170 addPass(&MachineLICMID);
1174 //===---------------------------------------------------------------------===//
1175 /// Post RegAlloc Pass Configuration
1176 //===---------------------------------------------------------------------===//
1178 /// Add passes that optimize machine instructions after register allocation.
1179 void TargetPassConfig::addMachineLateOptimization() {
1180 // Branch folding must be run after regalloc and prolog/epilog insertion.
1181 addPass(&BranchFolderPassID);
1183 // Tail duplication.
1184 // Note that duplicating tail just increases code size and degrades
1185 // performance for targets that require Structured Control Flow.
1186 // In addition it can also make CFG irreducible. Thus we disable it.
1187 if (!TM->requiresStructuredCFG())
1188 addPass(&TailDuplicateID);
1190 // Copy propagation.
1191 addPass(&MachineCopyPropagationID);
1194 /// Add standard GC passes.
1195 bool TargetPassConfig::addGCPasses() {
1196 addPass(&GCMachineCodeAnalysisID, false);
1200 /// Add standard basic block placement passes.
1201 void TargetPassConfig::addBlockPlacement() {
1202 if (addPass(&MachineBlockPlacementID)) {
1203 // Run a separate pass to collect block placement statistics.
1204 if (EnableBlockPlacementStats)
1205 addPass(&MachineBlockPlacementStatsID);
1209 //===---------------------------------------------------------------------===//
1210 /// GlobalISel Configuration
1211 //===---------------------------------------------------------------------===//
1212 bool TargetPassConfig::isGlobalISelAbortEnabled() const {
1213 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
1216 bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback() const {
1217 return TM->Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
1220 bool TargetPassConfig::isGISelCSEEnabled() const {
1224 std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1225 return make_unique<CSEConfigBase>();