1 //===- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveInterval.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/LiveStackAnalysis.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SlotIndexes.h"
34 #include "llvm/CodeGen/TargetInstrInfo.h"
35 #include "llvm/CodeGen/TargetOpcodes.h"
36 #include "llvm/CodeGen/TargetRegisterInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/MC/LaneBitmask.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/raw_ostream.h"
49 #define DEBUG_TYPE "regalloc"
51 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
52 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
54 //===----------------------------------------------------------------------===//
55 // VirtRegMap implementation
56 //===----------------------------------------------------------------------===//
58 char VirtRegMap::ID = 0;
60 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
62 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
63 MRI = &mf.getRegInfo();
64 TII = mf.getSubtarget().getInstrInfo();
65 TRI = mf.getSubtarget().getRegisterInfo();
69 Virt2StackSlotMap.clear();
70 Virt2SplitMap.clear();
76 void VirtRegMap::grow() {
77 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
78 Virt2PhysMap.resize(NumRegs);
79 Virt2StackSlotMap.resize(NumRegs);
80 Virt2SplitMap.resize(NumRegs);
83 void VirtRegMap::assignVirt2Phys(unsigned virtReg, MCPhysReg physReg) {
84 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
85 TargetRegisterInfo::isPhysicalRegister(physReg));
86 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
87 "attempt to assign physical register to already mapped "
89 assert(!getRegInfo().isReserved(physReg) &&
90 "Attempt to map virtReg to a reserved physReg");
91 Virt2PhysMap[virtReg] = physReg;
94 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
95 unsigned Size = TRI->getSpillSize(*RC);
96 unsigned Align = TRI->getSpillAlignment(*RC);
97 int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
102 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
103 unsigned Hint = MRI->getSimpleHint(VirtReg);
106 if (TargetRegisterInfo::isVirtualRegister(Hint))
107 Hint = getPhys(Hint);
108 return getPhys(VirtReg) == Hint;
111 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
112 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
113 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
115 if (TargetRegisterInfo::isVirtualRegister(Hint.second))
116 return hasPhys(Hint.second);
120 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
121 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
122 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
123 "attempt to assign stack slot to already spilled register");
124 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
125 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
128 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
129 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
130 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
131 "attempt to assign stack slot to already spilled register");
133 (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
134 "illegal fixed frame index");
135 Virt2StackSlotMap[virtReg] = SS;
138 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
139 OS << "********** REGISTER MAP **********\n";
140 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
141 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
142 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
143 OS << '[' << printReg(Reg, TRI) << " -> "
144 << printReg(Virt2PhysMap[Reg], TRI) << "] "
145 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
149 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
150 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
151 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
152 OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
153 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
159 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
160 LLVM_DUMP_METHOD void VirtRegMap::dump() const {
165 //===----------------------------------------------------------------------===//
167 //===----------------------------------------------------------------------===//
169 // The VirtRegRewriter is the last of the register allocator passes.
170 // It rewrites virtual registers to physical registers as specified in the
171 // VirtRegMap analysis. It also updates live-in information on basic blocks
172 // according to LiveIntervals.
176 class VirtRegRewriter : public MachineFunctionPass {
178 const TargetRegisterInfo *TRI;
179 const TargetInstrInfo *TII;
180 MachineRegisterInfo *MRI;
181 SlotIndexes *Indexes;
186 void addMBBLiveIns();
187 bool readsUndefSubreg(const MachineOperand &MO) const;
188 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
189 void handleIdentityCopy(MachineInstr &MI) const;
190 void expandCopyBundle(MachineInstr &MI) const;
191 bool subRegLiveThrough(const MachineInstr &MI, unsigned SuperPhysReg) const;
196 VirtRegRewriter() : MachineFunctionPass(ID) {}
198 void getAnalysisUsage(AnalysisUsage &AU) const override;
200 bool runOnMachineFunction(MachineFunction&) override;
202 MachineFunctionProperties getSetProperties() const override {
203 return MachineFunctionProperties().set(
204 MachineFunctionProperties::Property::NoVRegs);
208 } // end anonymous namespace
210 char VirtRegRewriter::ID = 0;
212 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
214 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
215 "Virtual Register Rewriter", false, false)
216 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
217 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
218 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
219 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
220 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
221 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
222 "Virtual Register Rewriter", false, false)
224 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
225 AU.setPreservesCFG();
226 AU.addRequired<LiveIntervals>();
227 AU.addRequired<SlotIndexes>();
228 AU.addPreserved<SlotIndexes>();
229 AU.addRequired<LiveDebugVariables>();
230 AU.addRequired<LiveStacks>();
231 AU.addPreserved<LiveStacks>();
232 AU.addRequired<VirtRegMap>();
233 MachineFunctionPass::getAnalysisUsage(AU);
236 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
238 TRI = MF->getSubtarget().getRegisterInfo();
239 TII = MF->getSubtarget().getInstrInfo();
240 MRI = &MF->getRegInfo();
241 Indexes = &getAnalysis<SlotIndexes>();
242 LIS = &getAnalysis<LiveIntervals>();
243 VRM = &getAnalysis<VirtRegMap>();
244 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
245 << "********** Function: "
246 << MF->getName() << '\n');
249 // Add kill flags while we still have virtual registers.
250 LIS->addKillFlags(VRM);
252 // Live-in lists on basic blocks are required for physregs.
255 // Rewrite virtual registers.
258 // Write out new DBG_VALUE instructions.
259 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
261 // All machine operands and other references to virtual registers have been
262 // replaced. Remove the virtual registers and release all the transient data.
264 MRI->clearVirtRegs();
268 void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
269 unsigned PhysReg) const {
271 assert(LI.hasSubRanges());
273 using SubRangeIteratorPair =
274 std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>;
276 SmallVector<SubRangeIteratorPair, 4> SubRanges;
279 for (const LiveInterval::SubRange &SR : LI.subranges()) {
280 SubRanges.push_back(std::make_pair(&SR, SR.begin()));
281 if (!First.isValid() || SR.segments.front().start < First)
282 First = SR.segments.front().start;
283 if (!Last.isValid() || SR.segments.back().end > Last)
284 Last = SR.segments.back().end;
287 // Check all mbb start positions between First and Last while
288 // simulatenously advancing an iterator for each subrange.
289 for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
290 MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
291 SlotIndex MBBBegin = MBBI->first;
292 // Advance all subrange iterators so that their end position is just
293 // behind MBBBegin (or the iterator is at the end).
294 LaneBitmask LaneMask;
295 for (auto &RangeIterPair : SubRanges) {
296 const LiveInterval::SubRange *SR = RangeIterPair.first;
297 LiveInterval::const_iterator &SRI = RangeIterPair.second;
298 while (SRI != SR->end() && SRI->end <= MBBBegin)
300 if (SRI == SR->end())
302 if (SRI->start <= MBBBegin)
303 LaneMask |= SR->LaneMask;
307 MachineBasicBlock *MBB = MBBI->second;
308 MBB->addLiveIn(PhysReg, LaneMask);
312 // Compute MBB live-in lists from virtual register live ranges and their
314 void VirtRegRewriter::addMBBLiveIns() {
315 for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
316 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
317 if (MRI->reg_nodbg_empty(VirtReg))
319 LiveInterval &LI = LIS->getInterval(VirtReg);
320 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
322 // This is a virtual register that is live across basic blocks. Its
323 // assigned PhysReg must be marked as live-in to those blocks.
324 unsigned PhysReg = VRM->getPhys(VirtReg);
325 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
327 if (LI.hasSubRanges()) {
328 addLiveInsForSubRanges(LI, PhysReg);
330 // Go over MBB begin positions and see if we have segments covering them.
331 // The following works because segments and the MBBIndex list are both
332 // sorted by slot indexes.
333 SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
334 for (const auto &Seg : LI) {
335 I = Indexes->advanceMBBIndex(I, Seg.start);
336 for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
337 MachineBasicBlock *MBB = I->second;
338 MBB->addLiveIn(PhysReg);
344 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
345 // each MBB's LiveIns set before calling addLiveIn on them.
346 for (MachineBasicBlock &MBB : *MF)
347 MBB.sortUniqueLiveIns();
350 /// Returns true if the given machine operand \p MO only reads undefined lanes.
351 /// The function only works for use operands with a subregister set.
352 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
353 // Shortcut if the operand is already marked undef.
357 unsigned Reg = MO.getReg();
358 const LiveInterval &LI = LIS->getInterval(Reg);
359 const MachineInstr &MI = *MO.getParent();
360 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
361 // This code is only meant to handle reading undefined subregisters which
362 // we couldn't properly detect before.
363 assert(LI.liveAt(BaseIndex) &&
364 "Reads of completely dead register should be marked undef already");
365 unsigned SubRegIdx = MO.getSubReg();
366 assert(SubRegIdx != 0 && LI.hasSubRanges());
367 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
368 // See if any of the relevant subregister liveranges is defined at this point.
369 for (const LiveInterval::SubRange &SR : LI.subranges()) {
370 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
376 void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
377 if (!MI.isIdentityCopy())
379 DEBUG(dbgs() << "Identity copy: " << MI);
383 // %r0 = COPY %r0<undef>
384 // %al = COPY %al, %eax<imp-def>
385 // give us additional liveness information: The target (super-)register
386 // must not be valid before this point. Replace the COPY with a KILL
387 // instruction to maintain this information.
388 if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
389 MI.setDesc(TII->get(TargetOpcode::KILL));
390 DEBUG(dbgs() << " replace by: " << MI);
395 Indexes->removeSingleMachineInstrFromMaps(MI);
396 MI.eraseFromBundle();
397 DEBUG(dbgs() << " deleted.\n");
400 /// The liverange splitting logic sometimes produces bundles of copies when
401 /// subregisters are involved. Expand these into a sequence of copy instructions
402 /// after processing the last in the bundle. Does not update LiveIntervals
403 /// which we shouldn't need for this instruction anymore.
404 void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
408 if (MI.isBundledWithPred() && !MI.isBundledWithSucc()) {
409 // Only do this when the complete bundle is made out of COPYs.
410 MachineBasicBlock &MBB = *MI.getParent();
411 for (MachineBasicBlock::reverse_instr_iterator I =
412 std::next(MI.getReverseIterator()), E = MBB.instr_rend();
413 I != E && I->isBundledWithSucc(); ++I) {
418 for (MachineBasicBlock::reverse_instr_iterator I = MI.getReverseIterator();
419 I->isBundledWithPred(); ) {
420 MachineInstr &MI = *I;
423 MI.unbundleFromPred();
425 Indexes->insertMachineInstrInMaps(MI);
430 /// Check whether (part of) \p SuperPhysReg is live through \p MI.
431 /// \pre \p MI defines a subregister of a virtual register that
432 /// has been assigned to \p SuperPhysReg.
433 bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
434 unsigned SuperPhysReg) const {
435 SlotIndex MIIndex = LIS->getInstructionIndex(MI);
436 SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
437 SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
438 for (MCRegUnitIterator Unit(SuperPhysReg, TRI); Unit.isValid(); ++Unit) {
439 const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
440 // If the regunit is live both before and after MI,
441 // we assume it is live through.
442 // Generally speaking, this is not true, because something like
443 // "RU = op RU" would match that description.
444 // However, we know that we are trying to assess whether
445 // a def of a virtual reg, vreg, is live at the same time of RU.
446 // If we are in the "RU = op RU" situation, that means that vreg
447 // is defined at the same time as RU (i.e., "vreg, RU = op RU").
448 // Thus, vreg and RU interferes and vreg cannot be assigned to
449 // SuperPhysReg. Therefore, this situation cannot happen.
450 if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses))
456 void VirtRegRewriter::rewrite() {
457 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
458 SmallVector<unsigned, 8> SuperDeads;
459 SmallVector<unsigned, 8> SuperDefs;
460 SmallVector<unsigned, 8> SuperKills;
462 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
463 MBBI != MBBE; ++MBBI) {
464 DEBUG(MBBI->print(dbgs(), Indexes));
465 for (MachineBasicBlock::instr_iterator
466 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
467 MachineInstr *MI = &*MII;
470 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
471 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
472 MachineOperand &MO = *MOI;
474 // Make sure MRI knows about registers clobbered by regmasks.
476 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
478 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
480 unsigned VirtReg = MO.getReg();
481 unsigned PhysReg = VRM->getPhys(VirtReg);
482 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
483 "Instruction uses unmapped VirtReg");
484 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
486 // Preserve semantics of sub-register operands.
487 unsigned SubReg = MO.getSubReg();
489 if (NoSubRegLiveness) {
490 // A virtual register kill refers to the whole register, so we may
491 // have to add <imp-use,kill> operands for the super-register. A
492 // partial redef always kills and redefines the super-register.
493 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
494 (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
495 SuperKills.push_back(PhysReg);
498 // Also add implicit defs for the super-register.
500 SuperDeads.push_back(PhysReg);
502 SuperDefs.push_back(PhysReg);
506 if (readsUndefSubreg(MO))
507 // We need to add an <undef> flag if the subregister is
508 // completely undefined (and we are not adding super-register
511 } else if (!MO.isDead()) {
516 // The <def,undef> and <def,internal> flags only make sense for
517 // sub-register defs, and we are substituting a full physreg. An
518 // <imp-use,kill> operand from the SuperKills list will represent the
519 // partial read of the super-register.
521 MO.setIsUndef(false);
522 MO.setIsInternalRead(false);
525 // PhysReg operands cannot have subregister indexes.
526 PhysReg = TRI->getSubReg(PhysReg, SubReg);
527 assert(PhysReg && "Invalid SubReg for physical register");
530 // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
531 // we need the inlining here.
535 // Add any missing super-register kills after rewriting the whole
537 while (!SuperKills.empty())
538 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
540 while (!SuperDeads.empty())
541 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
543 while (!SuperDefs.empty())
544 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
546 DEBUG(dbgs() << "> " << *MI);
548 expandCopyBundle(*MI);
550 // We can remove identity copies right now.
551 handleIdentityCopy(*MI);