1 //===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
21 "Dump MachineInstrs in the CodeEmitter">;
23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
26 "Dump MachineInstrs in the CodeEmitter">;
28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
29 "EnableIRStructurizer",
31 "Disable IR Structurizer">;
33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
34 "EnablePromoteAlloca",
36 "Enable promote alloca pass">;
40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
43 "Disable the if conversion pass">;
45 def FeatureFP64 : SubtargetFeature<"fp64",
48 "Enable double precision operations">;
50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
53 "Enable double precision denormal handling",
56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
59 "Assuming f32 fma is at least as fast as mul + add",
62 // Some instructions do not support denormals despite this flag. Using
63 // fp32 denormals also causes instructions to run at the double
64 // precision rate for the device.
65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
68 "Enable single precision denormal handling">;
70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
73 "Specify if 64-bit addressing should be used">;
75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
78 "Older version of ALU instructions encoding">;
80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
83 "Specify use of dedicated vertex cache">;
85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
93 "GPU has CF_ALU bug">;
95 // XXX - This should probably be removed once enabled by default
96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
99 "Enable SI load/store optimizer pass">;
101 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
104 "Support flat address space">;
106 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
107 "EnableVGPRSpilling",
109 "Enable spilling of VGPRs to scratch memory">;
111 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
114 "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
116 class SubtargetFeatureFetchLimit <string Value> :
117 SubtargetFeature <"fetch"#Value,
120 "Limit the maximum number of fetches in a clause to "#Value>;
122 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
123 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
125 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
126 "wavefrontsize"#Value,
128 !cast<string>(Value),
129 "The number of threads per wavefront">;
131 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
132 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
133 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
135 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
136 "ldsbankcount"#Value,
138 !cast<string>(Value),
139 "The number of LDS banks per compute unit.">;
141 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
142 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
144 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
145 "localmemorysize"#Value,
147 !cast<string>(Value),
148 "The size of local memory in bytes">;
150 def FeatureGCN : SubtargetFeature<"gcn",
155 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
158 "Encoding format for SI and CI">;
160 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
163 "Encoding format for VI">;
165 def FeatureCIInsts : SubtargetFeature<"ci-insts",
168 "Additional intstructions for CI+">;
170 // Dummy feature used to disable assembler instructions.
171 def FeatureDisable : SubtargetFeature<"",
172 "FeatureDisable","true",
173 "Dummy feature to disable assembler"
176 class SubtargetFeatureGeneration <string Value,
177 list<SubtargetFeature> Implies> :
178 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
179 Value#" GPU generation", Implies>;
181 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
182 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
183 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
185 def FeatureR600 : SubtargetFeatureGeneration<"R600",
186 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
188 def FeatureR700 : SubtargetFeatureGeneration<"R700",
189 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
191 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
192 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
194 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
195 [FeatureFetchLimit16, FeatureWavefrontSize64,
196 FeatureLocalMemorySize32768]
199 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
200 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
201 FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
202 FeatureLDSBankCount32]>;
204 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
205 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
206 FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
207 FeatureGCN1Encoding, FeatureCIInsts]>;
209 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
210 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
211 FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
212 FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
214 //===----------------------------------------------------------------------===//
216 def AMDGPUInstrInfo : InstrInfo {
217 let guessInstructionProperties = 1;
218 let noNamedPositionallyEncodedOperands = 1;
221 def AMDGPUAsmParser : AsmParser {
222 // Some of the R600 registers have the same name, so this crashes.
223 // For example T0_XYZW and T0_XY both have the asm name T0.
224 let ShouldEmitMatchRegisterName = 0;
227 def AMDGPU : Target {
228 // Pull in Instruction Info:
229 let InstructionSet = AMDGPUInstrInfo;
230 let AssemblyParsers = [AMDGPUAsmParser];
233 // Dummy Instruction itineraries for pseudo instructions
234 def ALU_NULL : FuncUnit;
235 def NullALU : InstrItinClass;
237 //===----------------------------------------------------------------------===//
238 // Predicate helper class
239 //===----------------------------------------------------------------------===//
241 def TruePredicate : Predicate<"true">;
242 def isSICI : Predicate<
243 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
244 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
245 >, AssemblerPredicate<"FeatureGCN1Encoding">;
247 class PredicateControl {
248 Predicate SubtargetPredicate;
249 Predicate SIAssemblerPredicate = isSICI;
250 list<Predicate> AssemblerPredicates = [];
251 Predicate AssemblerPredicate = TruePredicate;
252 list<Predicate> OtherPredicates = [];
253 list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
258 // Include AMDGPU TD files
259 include "R600Schedule.td"
260 include "SISchedule.td"
261 include "Processors.td"
262 include "AMDGPUInstrInfo.td"
263 include "AMDGPUIntrinsics.td"
264 include "AMDGPURegisterInfo.td"
265 include "AMDGPUInstructions.td"
266 include "AMDGPUCallingConv.td"