1 //===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
15 #include "SIInstrInfo.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "GCNHazardRecognizer.h"
20 #include "SIDefines.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "SIRegisterInfo.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/iterator_range.h"
30 #include "llvm/Analysis/AliasAnalysis.h"
31 #include "llvm/Analysis/MemoryLocation.h"
32 #include "llvm/Analysis/ValueTracking.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineDominators.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineInstrBundle.h"
40 #include "llvm/CodeGen/MachineMemOperand.h"
41 #include "llvm/CodeGen/MachineOperand.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/RegisterScavenging.h"
44 #include "llvm/CodeGen/ScheduleDAG.h"
45 #include "llvm/CodeGen/SelectionDAGNodes.h"
46 #include "llvm/CodeGen/TargetOpcodes.h"
47 #include "llvm/CodeGen/TargetRegisterInfo.h"
48 #include "llvm/IR/DebugLoc.h"
49 #include "llvm/IR/DiagnosticInfo.h"
50 #include "llvm/IR/Function.h"
51 #include "llvm/IR/InlineAsm.h"
52 #include "llvm/IR/LLVMContext.h"
53 #include "llvm/MC/MCInstrDesc.h"
54 #include "llvm/Support/Casting.h"
55 #include "llvm/Support/CommandLine.h"
56 #include "llvm/Support/Compiler.h"
57 #include "llvm/Support/ErrorHandling.h"
58 #include "llvm/Support/MachineValueType.h"
59 #include "llvm/Support/MathExtras.h"
60 #include "llvm/Target/TargetMachine.h"
68 #define GET_INSTRINFO_CTOR_DTOR
69 #include "AMDGPUGenInstrInfo.inc"
73 #define GET_D16ImageDimIntrinsics_IMPL
74 #define GET_ImageDimIntrinsicTable_IMPL
75 #define GET_RsrcIntrinsics_IMPL
76 #include "AMDGPUGenSearchableTables.inc"
81 // Must be at least 4 to be able to branch over minimum unconditional branch
82 // code. This is only for making it possible to write reasonably small tests for
84 static cl::opt<unsigned>
85 BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
86 cl::desc("Restrict range of branch instructions (DEBUG)"));
88 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
89 : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
92 //===----------------------------------------------------------------------===//
93 // TargetInstrInfo callbacks
94 //===----------------------------------------------------------------------===//
96 static unsigned getNumOperandsNoGlue(SDNode *Node) {
97 unsigned N = Node->getNumOperands();
98 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
103 static SDValue findChainOperand(SDNode *Load) {
104 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
105 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
109 /// Returns true if both nodes have the same value for the given
110 /// operand \p Op, or if both nodes do not have this operand.
111 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
112 unsigned Opc0 = N0->getMachineOpcode();
113 unsigned Opc1 = N1->getMachineOpcode();
115 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
116 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
118 if (Op0Idx == -1 && Op1Idx == -1)
122 if ((Op0Idx == -1 && Op1Idx != -1) ||
123 (Op1Idx == -1 && Op0Idx != -1))
126 // getNamedOperandIdx returns the index for the MachineInstr's operands,
127 // which includes the result as the first operand. We are indexing into the
128 // MachineSDNode's operands, so we need to skip the result operand to get
133 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
136 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
137 AliasAnalysis *AA) const {
138 // TODO: The generic check fails for VALU instructions that should be
139 // rematerializable due to implicit reads of exec. We really want all of the
140 // generic logic for this except for this.
141 switch (MI.getOpcode()) {
142 case AMDGPU::V_MOV_B32_e32:
143 case AMDGPU::V_MOV_B32_e64:
144 case AMDGPU::V_MOV_B64_PSEUDO:
151 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
153 int64_t &Offset1) const {
154 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
157 unsigned Opc0 = Load0->getMachineOpcode();
158 unsigned Opc1 = Load1->getMachineOpcode();
160 // Make sure both are actually loads.
161 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
164 if (isDS(Opc0) && isDS(Opc1)) {
166 // FIXME: Handle this case:
167 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
171 if (Load0->getOperand(1) != Load1->getOperand(1))
175 if (findChainOperand(Load0) != findChainOperand(Load1))
178 // Skip read2 / write2 variants for simplicity.
179 // TODO: We should report true if the used offsets are adjacent (excluded
181 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
182 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
185 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
186 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
190 if (isSMRD(Opc0) && isSMRD(Opc1)) {
191 // Skip time and cache invalidation instructions.
192 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
193 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
196 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
199 if (Load0->getOperand(0) != Load1->getOperand(0))
202 const ConstantSDNode *Load0Offset =
203 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
204 const ConstantSDNode *Load1Offset =
205 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
207 if (!Load0Offset || !Load1Offset)
211 if (findChainOperand(Load0) != findChainOperand(Load1))
214 Offset0 = Load0Offset->getZExtValue();
215 Offset1 = Load1Offset->getZExtValue();
219 // MUBUF and MTBUF can access the same addresses.
220 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
222 // MUBUF and MTBUF have vaddr at different indices.
223 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
224 findChainOperand(Load0) != findChainOperand(Load1) ||
225 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
226 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
229 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
230 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
232 if (OffIdx0 == -1 || OffIdx1 == -1)
235 // getNamedOperandIdx returns the index for MachineInstrs. Since they
236 // inlcude the output in the operand list, but SDNodes don't, we need to
237 // subtract the index by one.
241 SDValue Off0 = Load0->getOperand(OffIdx0);
242 SDValue Off1 = Load1->getOperand(OffIdx1);
244 // The offset might be a FrameIndexSDNode.
245 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
248 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
249 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
256 static bool isStride64(unsigned Opc) {
258 case AMDGPU::DS_READ2ST64_B32:
259 case AMDGPU::DS_READ2ST64_B64:
260 case AMDGPU::DS_WRITE2ST64_B32:
261 case AMDGPU::DS_WRITE2ST64_B64:
268 bool SIInstrInfo::getMemOperandWithOffset(MachineInstr &LdSt,
269 MachineOperand *&BaseOp,
271 const TargetRegisterInfo *TRI) const {
272 unsigned Opc = LdSt.getOpcode();
275 const MachineOperand *OffsetImm =
276 getNamedOperand(LdSt, AMDGPU::OpName::offset);
278 // Normal, single offset LDS instruction.
279 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
280 Offset = OffsetImm->getImm();
281 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
282 "operands of type register.");
286 // The 2 offset instructions use offset0 and offset1 instead. We can treat
287 // these as a load with a single offset if the 2 offsets are consecutive. We
288 // will use this for some partially aligned loads.
289 const MachineOperand *Offset0Imm =
290 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
291 const MachineOperand *Offset1Imm =
292 getNamedOperand(LdSt, AMDGPU::OpName::offset1);
294 uint8_t Offset0 = Offset0Imm->getImm();
295 uint8_t Offset1 = Offset1Imm->getImm();
297 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
298 // Each of these offsets is in element sized units, so we need to convert
299 // to bytes of the individual reads.
303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
305 assert(LdSt.mayStore());
306 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
307 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
313 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
314 Offset = EltSize * Offset0;
315 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
316 "operands of type register.");
323 if (isMUBUF(LdSt) || isMTBUF(LdSt)) {
324 const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset);
325 if (SOffset && SOffset->isReg())
328 MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
332 const MachineOperand *OffsetImm =
333 getNamedOperand(LdSt, AMDGPU::OpName::offset);
335 Offset = OffsetImm->getImm();
337 if (SOffset) // soffset can be an inline immediate.
338 Offset += SOffset->getImm();
340 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
341 "operands of type register.");
346 const MachineOperand *OffsetImm =
347 getNamedOperand(LdSt, AMDGPU::OpName::offset);
351 MachineOperand *SBaseReg = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
353 Offset = OffsetImm->getImm();
354 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
355 "operands of type register.");
360 MachineOperand *VAddr = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
362 // Can't analyze 2 offsets.
363 if (getNamedOperand(LdSt, AMDGPU::OpName::saddr))
368 // scratch instructions have either vaddr or saddr.
369 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr);
372 Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm();
373 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
374 "operands of type register.");
381 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
382 const MachineOperand &BaseOp1,
383 const MachineInstr &MI2,
384 const MachineOperand &BaseOp2) {
385 // Support only base operands with base registers.
386 // Note: this could be extended to support FI operands.
387 if (!BaseOp1.isReg() || !BaseOp2.isReg())
390 if (BaseOp1.isIdenticalTo(BaseOp2))
393 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
396 auto MO1 = *MI1.memoperands_begin();
397 auto MO2 = *MI2.memoperands_begin();
398 if (MO1->getAddrSpace() != MO2->getAddrSpace())
401 auto Base1 = MO1->getValue();
402 auto Base2 = MO2->getValue();
403 if (!Base1 || !Base2)
405 const MachineFunction &MF = *MI1.getParent()->getParent();
406 const DataLayout &DL = MF.getFunction().getParent()->getDataLayout();
407 Base1 = GetUnderlyingObject(Base1, DL);
408 Base2 = GetUnderlyingObject(Base1, DL);
410 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
413 return Base1 == Base2;
416 bool SIInstrInfo::shouldClusterMemOps(MachineOperand &BaseOp1,
417 MachineOperand &BaseOp2,
418 unsigned NumLoads) const {
419 MachineInstr &FirstLdSt = *BaseOp1.getParent();
420 MachineInstr &SecondLdSt = *BaseOp2.getParent();
422 if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOp1, SecondLdSt, BaseOp2))
425 const MachineOperand *FirstDst = nullptr;
426 const MachineOperand *SecondDst = nullptr;
428 if ((isMUBUF(FirstLdSt) && isMUBUF(SecondLdSt)) ||
429 (isMTBUF(FirstLdSt) && isMTBUF(SecondLdSt)) ||
430 (isFLAT(FirstLdSt) && isFLAT(SecondLdSt))) {
431 const unsigned MaxGlobalLoadCluster = 6;
432 if (NumLoads > MaxGlobalLoadCluster)
435 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdata);
437 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst);
438 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdata);
440 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst);
441 } else if (isSMRD(FirstLdSt) && isSMRD(SecondLdSt)) {
442 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::sdst);
443 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::sdst);
444 } else if (isDS(FirstLdSt) && isDS(SecondLdSt)) {
445 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst);
446 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst);
449 if (!FirstDst || !SecondDst)
452 // Try to limit clustering based on the total number of bytes loaded
453 // rather than the number of instructions. This is done to help reduce
454 // register pressure. The method used is somewhat inexact, though,
455 // because it assumes that all loads in the cluster will load the
456 // same number of bytes as FirstLdSt.
458 // The unit of this value is bytes.
459 // FIXME: This needs finer tuning.
460 unsigned LoadClusterThreshold = 16;
462 const MachineRegisterInfo &MRI =
463 FirstLdSt.getParent()->getParent()->getRegInfo();
464 const TargetRegisterClass *DstRC = MRI.getRegClass(FirstDst->getReg());
466 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold;
469 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
470 // the first 16 loads will be interleaved with the stores, and the next 16 will
471 // be clustered as expected. It should really split into 2 16 store batches.
473 // Loads are clustered until this returns false, rather than trying to schedule
474 // groups of stores. This also means we have to deal with saying different
475 // address space loads should be clustered, and ones which might cause bank
478 // This might be deprecated so it might not be worth that much effort to fix.
479 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
480 int64_t Offset0, int64_t Offset1,
481 unsigned NumLoads) const {
482 assert(Offset1 > Offset0 &&
483 "Second offset should be larger than first offset!");
484 // If we have less than 16 loads in a row, and the offsets are within 64
485 // bytes, then schedule together.
487 // A cacheline is 64 bytes (for global memory).
488 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
491 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,
492 MachineBasicBlock::iterator MI,
493 const DebugLoc &DL, unsigned DestReg,
494 unsigned SrcReg, bool KillSrc) {
495 MachineFunction *MF = MBB.getParent();
496 DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(),
497 "illegal SGPR to VGPR copy",
499 LLVMContext &C = MF->getFunction().getContext();
500 C.diagnose(IllegalCopy);
502 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
503 .addReg(SrcReg, getKillRegState(KillSrc));
506 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
507 MachineBasicBlock::iterator MI,
508 const DebugLoc &DL, unsigned DestReg,
509 unsigned SrcReg, bool KillSrc) const {
510 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
512 if (RC == &AMDGPU::VGPR_32RegClass) {
513 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
514 AMDGPU::SReg_32RegClass.contains(SrcReg));
515 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
516 .addReg(SrcReg, getKillRegState(KillSrc));
520 if (RC == &AMDGPU::SReg_32_XM0RegClass ||
521 RC == &AMDGPU::SReg_32RegClass) {
522 if (SrcReg == AMDGPU::SCC) {
523 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
529 if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
530 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
534 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
535 .addReg(SrcReg, getKillRegState(KillSrc));
539 if (RC == &AMDGPU::SReg_64RegClass) {
540 if (DestReg == AMDGPU::VCC) {
541 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
542 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
543 .addReg(SrcReg, getKillRegState(KillSrc));
545 // FIXME: Hack until VReg_1 removed.
546 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
547 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
549 .addReg(SrcReg, getKillRegState(KillSrc));
555 if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
556 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
560 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
561 .addReg(SrcReg, getKillRegState(KillSrc));
565 if (DestReg == AMDGPU::SCC) {
566 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
567 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
568 .addReg(SrcReg, getKillRegState(KillSrc))
573 unsigned EltSize = 4;
574 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
575 if (RI.isSGPRClass(RC)) {
576 if (RI.getRegSizeInBits(*RC) > 32) {
577 Opcode = AMDGPU::S_MOV_B64;
580 Opcode = AMDGPU::S_MOV_B32;
584 if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) {
585 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
590 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
591 bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
593 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
596 SubIdx = SubIndices[Idx];
598 SubIdx = SubIndices[SubIndices.size() - Idx - 1];
600 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
601 get(Opcode), RI.getSubReg(DestReg, SubIdx));
603 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
606 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
608 bool UseKill = KillSrc && Idx == SubIndices.size() - 1;
609 Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
613 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
616 // Try to map original to commuted opcode
617 NewOpc = AMDGPU::getCommuteRev(Opcode);
619 // Check if the commuted (REV) opcode exists on the target.
620 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
622 // Try to map commuted to original opcode
623 NewOpc = AMDGPU::getCommuteOrig(Opcode);
625 // Check if the original (non-REV) opcode exists on the target.
626 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
631 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,
632 MachineBasicBlock::iterator MI,
633 const DebugLoc &DL, unsigned DestReg,
634 int64_t Value) const {
635 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
636 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
637 if (RegClass == &AMDGPU::SReg_32RegClass ||
638 RegClass == &AMDGPU::SGPR_32RegClass ||
639 RegClass == &AMDGPU::SReg_32_XM0RegClass ||
640 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
641 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
646 if (RegClass == &AMDGPU::SReg_64RegClass ||
647 RegClass == &AMDGPU::SGPR_64RegClass ||
648 RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
649 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
654 if (RegClass == &AMDGPU::VGPR_32RegClass) {
655 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
659 if (RegClass == &AMDGPU::VReg_64RegClass) {
660 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
665 unsigned EltSize = 4;
666 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
667 if (RI.isSGPRClass(RegClass)) {
668 if (RI.getRegSizeInBits(*RegClass) > 32) {
669 Opcode = AMDGPU::S_MOV_B64;
672 Opcode = AMDGPU::S_MOV_B32;
677 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
678 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
679 int64_t IdxValue = Idx == 0 ? Value : 0;
681 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
682 get(Opcode), RI.getSubReg(DestReg, Idx));
683 Builder.addImm(IdxValue);
687 const TargetRegisterClass *
688 SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {
689 return &AMDGPU::VGPR_32RegClass;
692 void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
693 MachineBasicBlock::iterator I,
694 const DebugLoc &DL, unsigned DstReg,
695 ArrayRef<MachineOperand> Cond,
697 unsigned FalseReg) const {
698 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
699 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
702 if (Cond.size() == 1) {
703 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
704 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
706 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
710 } else if (Cond.size() == 2) {
711 assert(Cond[0].isImm() && "Cond[0] is not an immediate");
712 switch (Cond[0].getImm()) {
713 case SIInstrInfo::SCC_TRUE: {
714 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
715 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
718 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
724 case SIInstrInfo::SCC_FALSE: {
725 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
726 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
729 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
735 case SIInstrInfo::VCCNZ: {
736 MachineOperand RegOp = Cond[1];
737 RegOp.setImplicit(false);
738 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
739 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
741 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
747 case SIInstrInfo::VCCZ: {
748 MachineOperand RegOp = Cond[1];
749 RegOp.setImplicit(false);
750 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
751 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
753 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
759 case SIInstrInfo::EXECNZ: {
760 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
761 unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
762 BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
764 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
767 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
773 case SIInstrInfo::EXECZ: {
774 unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
775 unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
776 BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
778 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
781 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
785 llvm_unreachable("Unhandled branch predicate EXECZ");
789 llvm_unreachable("invalid branch predicate");
792 llvm_unreachable("Can only handle Cond size 1 or 2");
796 unsigned SIInstrInfo::insertEQ(MachineBasicBlock *MBB,
797 MachineBasicBlock::iterator I,
799 unsigned SrcReg, int Value) const {
800 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
801 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
802 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
809 unsigned SIInstrInfo::insertNE(MachineBasicBlock *MBB,
810 MachineBasicBlock::iterator I,
812 unsigned SrcReg, int Value) const {
813 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
814 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
815 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
822 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
824 if (RI.getRegSizeInBits(*DstRC) == 32) {
825 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
826 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
827 return AMDGPU::S_MOV_B64;
828 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
829 return AMDGPU::V_MOV_B64_PSEUDO;
834 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
837 return AMDGPU::SI_SPILL_S32_SAVE;
839 return AMDGPU::SI_SPILL_S64_SAVE;
841 return AMDGPU::SI_SPILL_S128_SAVE;
843 return AMDGPU::SI_SPILL_S256_SAVE;
845 return AMDGPU::SI_SPILL_S512_SAVE;
847 llvm_unreachable("unknown register size");
851 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
854 return AMDGPU::SI_SPILL_V32_SAVE;
856 return AMDGPU::SI_SPILL_V64_SAVE;
858 return AMDGPU::SI_SPILL_V96_SAVE;
860 return AMDGPU::SI_SPILL_V128_SAVE;
862 return AMDGPU::SI_SPILL_V256_SAVE;
864 return AMDGPU::SI_SPILL_V512_SAVE;
866 llvm_unreachable("unknown register size");
870 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
871 MachineBasicBlock::iterator MI,
872 unsigned SrcReg, bool isKill,
874 const TargetRegisterClass *RC,
875 const TargetRegisterInfo *TRI) const {
876 MachineFunction *MF = MBB.getParent();
877 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
878 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
879 const DebugLoc &DL = MBB.findDebugLoc(MI);
881 unsigned Size = FrameInfo.getObjectSize(FrameIndex);
882 unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
883 MachinePointerInfo PtrInfo
884 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
885 MachineMemOperand *MMO
886 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
888 unsigned SpillSize = TRI->getSpillSize(*RC);
890 if (RI.isSGPRClass(RC)) {
891 MFI->setHasSpilledSGPRs();
893 // We are only allowed to create one new instruction when spilling
894 // registers, so we need to use pseudo instruction for spilling SGPRs.
895 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
897 // The SGPR spill/restore instructions only work on number sgprs, so we need
898 // to make sure we are using the correct register class.
899 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && SpillSize == 4) {
900 MachineRegisterInfo &MRI = MF->getRegInfo();
901 MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
904 MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc)
905 .addReg(SrcReg, getKillRegState(isKill)) // data
906 .addFrameIndex(FrameIndex) // addr
908 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
909 .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
910 // Add the scratch resource registers as implicit uses because we may end up
911 // needing them, and need to ensure that the reserved registers are
912 // correctly handled.
914 FrameInfo.setStackID(FrameIndex, SIStackID::SGPR_SPILL);
915 if (ST.hasScalarStores()) {
916 // m0 is used for offset to scalar stores if used to spill.
917 Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead);
923 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
925 unsigned Opcode = getVGPRSpillSaveOpcode(SpillSize);
926 MFI->setHasSpilledVGPRs();
927 BuildMI(MBB, MI, DL, get(Opcode))
928 .addReg(SrcReg, getKillRegState(isKill)) // data
929 .addFrameIndex(FrameIndex) // addr
930 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
931 .addReg(MFI->getFrameOffsetReg()) // scratch_offset
936 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
939 return AMDGPU::SI_SPILL_S32_RESTORE;
941 return AMDGPU::SI_SPILL_S64_RESTORE;
943 return AMDGPU::SI_SPILL_S128_RESTORE;
945 return AMDGPU::SI_SPILL_S256_RESTORE;
947 return AMDGPU::SI_SPILL_S512_RESTORE;
949 llvm_unreachable("unknown register size");
953 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
956 return AMDGPU::SI_SPILL_V32_RESTORE;
958 return AMDGPU::SI_SPILL_V64_RESTORE;
960 return AMDGPU::SI_SPILL_V96_RESTORE;
962 return AMDGPU::SI_SPILL_V128_RESTORE;
964 return AMDGPU::SI_SPILL_V256_RESTORE;
966 return AMDGPU::SI_SPILL_V512_RESTORE;
968 llvm_unreachable("unknown register size");
972 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
973 MachineBasicBlock::iterator MI,
974 unsigned DestReg, int FrameIndex,
975 const TargetRegisterClass *RC,
976 const TargetRegisterInfo *TRI) const {
977 MachineFunction *MF = MBB.getParent();
978 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
979 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
980 const DebugLoc &DL = MBB.findDebugLoc(MI);
981 unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
982 unsigned Size = FrameInfo.getObjectSize(FrameIndex);
983 unsigned SpillSize = TRI->getSpillSize(*RC);
985 MachinePointerInfo PtrInfo
986 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
988 MachineMemOperand *MMO = MF->getMachineMemOperand(
989 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
991 if (RI.isSGPRClass(RC)) {
992 MFI->setHasSpilledSGPRs();
994 // FIXME: Maybe this should not include a memoperand because it will be
995 // lowered to non-memory instructions.
996 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
997 if (TargetRegisterInfo::isVirtualRegister(DestReg) && SpillSize == 4) {
998 MachineRegisterInfo &MRI = MF->getRegInfo();
999 MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
1002 FrameInfo.setStackID(FrameIndex, SIStackID::SGPR_SPILL);
1003 MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc, DestReg)
1004 .addFrameIndex(FrameIndex) // addr
1006 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
1007 .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
1009 if (ST.hasScalarStores()) {
1010 // m0 is used for offset to scalar stores if used to spill.
1011 Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead);
1017 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
1019 unsigned Opcode = getVGPRSpillRestoreOpcode(SpillSize);
1020 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
1021 .addFrameIndex(FrameIndex) // vaddr
1022 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
1023 .addReg(MFI->getFrameOffsetReg()) // scratch_offset
1024 .addImm(0) // offset
1025 .addMemOperand(MMO);
1028 /// \param @Offset Offset in bytes of the FrameIndex being spilled
1029 unsigned SIInstrInfo::calculateLDSSpillAddress(
1030 MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg,
1031 unsigned FrameOffset, unsigned Size) const {
1032 MachineFunction *MF = MBB.getParent();
1033 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
1034 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
1035 const DebugLoc &DL = MBB.findDebugLoc(MI);
1036 unsigned WorkGroupSize = MFI->getMaxFlatWorkGroupSize();
1037 unsigned WavefrontSize = ST.getWavefrontSize();
1039 unsigned TIDReg = MFI->getTIDReg();
1040 if (!MFI->hasCalculatedTID()) {
1041 MachineBasicBlock &Entry = MBB.getParent()->front();
1042 MachineBasicBlock::iterator Insert = Entry.front();
1043 const DebugLoc &DL = Insert->getDebugLoc();
1045 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
1047 if (TIDReg == AMDGPU::NoRegister)
1050 if (!AMDGPU::isShader(MF->getFunction().getCallingConv()) &&
1051 WorkGroupSize > WavefrontSize) {
1053 = MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
1055 = MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
1057 = MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
1058 unsigned InputPtrReg =
1059 MFI->getPreloadedReg(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1060 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
1061 if (!Entry.isLiveIn(Reg))
1062 Entry.addLiveIn(Reg);
1065 RS->enterBasicBlock(Entry);
1066 // FIXME: Can we scavenge an SReg_64 and access the subregs?
1067 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1068 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1069 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
1070 .addReg(InputPtrReg)
1071 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
1072 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
1073 .addReg(InputPtrReg)
1074 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
1076 // NGROUPS.X * NGROUPS.Y
1077 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
1080 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
1081 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
1084 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
1085 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
1089 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
1090 getAddNoCarry(Entry, Insert, DL, TIDReg)
1095 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
1100 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
1106 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
1110 MFI->setTIDReg(TIDReg);
1113 // Add FrameIndex to LDS offset
1114 unsigned LDSOffset = MFI->getLDSSize() + (FrameOffset * WorkGroupSize);
1115 getAddNoCarry(MBB, MI, DL, TmpReg)
1122 void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,
1123 MachineBasicBlock::iterator MI,
1125 DebugLoc DL = MBB.findDebugLoc(MI);
1133 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP))
1138 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,
1139 MachineBasicBlock::iterator MI) const {
1140 insertWaitStates(MBB, MI, 1);
1143 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {
1144 auto MF = MBB.getParent();
1145 SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
1147 assert(Info->isEntryFunction());
1149 if (MBB.succ_empty()) {
1150 bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
1151 if (HasNoTerminator)
1152 BuildMI(MBB, MBB.end(), DebugLoc(),
1153 get(Info->returnsVoid() ? AMDGPU::S_ENDPGM : AMDGPU::SI_RETURN_TO_EPILOG));
1157 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) const {
1158 switch (MI.getOpcode()) {
1159 default: return 1; // FIXME: Do wait states equal cycles?
1162 return MI.getOperand(0).getImm() + 1;
1166 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1167 MachineBasicBlock &MBB = *MI.getParent();
1168 DebugLoc DL = MBB.findDebugLoc(MI);
1169 switch (MI.getOpcode()) {
1170 default: return TargetInstrInfo::expandPostRAPseudo(MI);
1171 case AMDGPU::S_MOV_B64_term:
1172 // This is only a terminator to get the correct spill code placement during
1173 // register allocation.
1174 MI.setDesc(get(AMDGPU::S_MOV_B64));
1177 case AMDGPU::S_XOR_B64_term:
1178 // This is only a terminator to get the correct spill code placement during
1179 // register allocation.
1180 MI.setDesc(get(AMDGPU::S_XOR_B64));
1183 case AMDGPU::S_ANDN2_B64_term:
1184 // This is only a terminator to get the correct spill code placement during
1185 // register allocation.
1186 MI.setDesc(get(AMDGPU::S_ANDN2_B64));
1189 case AMDGPU::V_MOV_B64_PSEUDO: {
1190 unsigned Dst = MI.getOperand(0).getReg();
1191 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1192 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1194 const MachineOperand &SrcOp = MI.getOperand(1);
1195 // FIXME: Will this work for 64-bit floating point immediates?
1196 assert(!SrcOp.isFPImm());
1197 if (SrcOp.isImm()) {
1198 APInt Imm(64, SrcOp.getImm());
1199 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1200 .addImm(Imm.getLoBits(32).getZExtValue())
1201 .addReg(Dst, RegState::Implicit | RegState::Define);
1202 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1203 .addImm(Imm.getHiBits(32).getZExtValue())
1204 .addReg(Dst, RegState::Implicit | RegState::Define);
1206 assert(SrcOp.isReg());
1207 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1208 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1209 .addReg(Dst, RegState::Implicit | RegState::Define);
1210 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1211 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1212 .addReg(Dst, RegState::Implicit | RegState::Define);
1214 MI.eraseFromParent();
1217 case AMDGPU::V_SET_INACTIVE_B32: {
1218 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1219 .addReg(AMDGPU::EXEC);
1220 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1221 .add(MI.getOperand(2));
1222 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1223 .addReg(AMDGPU::EXEC);
1224 MI.eraseFromParent();
1227 case AMDGPU::V_SET_INACTIVE_B64: {
1228 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1229 .addReg(AMDGPU::EXEC);
1230 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1231 MI.getOperand(0).getReg())
1232 .add(MI.getOperand(2));
1233 expandPostRAPseudo(*Copy);
1234 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC)
1235 .addReg(AMDGPU::EXEC);
1236 MI.eraseFromParent();
1239 case AMDGPU::V_MOVRELD_B32_V1:
1240 case AMDGPU::V_MOVRELD_B32_V2:
1241 case AMDGPU::V_MOVRELD_B32_V4:
1242 case AMDGPU::V_MOVRELD_B32_V8:
1243 case AMDGPU::V_MOVRELD_B32_V16: {
1244 const MCInstrDesc &MovRelDesc = get(AMDGPU::V_MOVRELD_B32_e32);
1245 unsigned VecReg = MI.getOperand(0).getReg();
1246 bool IsUndef = MI.getOperand(1).isUndef();
1247 unsigned SubReg = AMDGPU::sub0 + MI.getOperand(3).getImm();
1248 assert(VecReg == MI.getOperand(1).getReg());
1250 MachineInstr *MovRel =
1251 BuildMI(MBB, MI, DL, MovRelDesc)
1252 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1253 .add(MI.getOperand(2))
1254 .addReg(VecReg, RegState::ImplicitDefine)
1256 RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1258 const int ImpDefIdx =
1259 MovRelDesc.getNumOperands() + MovRelDesc.getNumImplicitUses();
1260 const int ImpUseIdx = ImpDefIdx + 1;
1261 MovRel->tieOperands(ImpDefIdx, ImpUseIdx);
1263 MI.eraseFromParent();
1266 case AMDGPU::SI_PC_ADD_REL_OFFSET: {
1267 MachineFunction &MF = *MBB.getParent();
1268 unsigned Reg = MI.getOperand(0).getReg();
1269 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
1270 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
1272 // Create a bundle so these instructions won't be re-ordered by the
1273 // post-RA scheduler.
1274 MIBundleBuilder Bundler(MBB, MI);
1275 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
1277 // Add 32-bit offset from this instruction to the start of the
1279 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
1281 .add(MI.getOperand(1)));
1283 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
1285 if (MI.getOperand(2).getTargetFlags() == SIInstrInfo::MO_NONE)
1288 MIB.add(MI.getOperand(2));
1290 Bundler.append(MIB);
1291 finalizeBundle(MBB, Bundler.begin());
1293 MI.eraseFromParent();
1296 case AMDGPU::EXIT_WWM: {
1297 // This only gets its own opcode so that SIFixWWMLiveness can tell when WWM
1299 MI.setDesc(get(AMDGPU::S_MOV_B64));
1302 case TargetOpcode::BUNDLE: {
1306 // If it is a load it must be a memory clause
1307 for (MachineBasicBlock::instr_iterator I = MI.getIterator();
1308 I->isBundledWithSucc(); ++I) {
1309 I->unbundleFromSucc();
1310 for (MachineOperand &MO : I->operands())
1312 MO.setIsInternalRead(false);
1315 MI.eraseFromParent();
1322 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,
1323 MachineOperand &Src0,
1324 unsigned Src0OpName,
1325 MachineOperand &Src1,
1326 unsigned Src1OpName) const {
1327 MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
1331 MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
1333 "All commutable instructions have both src0 and src1 modifiers");
1335 int Src0ModsVal = Src0Mods->getImm();
1336 int Src1ModsVal = Src1Mods->getImm();
1338 Src1Mods->setImm(Src0ModsVal);
1339 Src0Mods->setImm(Src1ModsVal);
1343 static MachineInstr *swapRegAndNonRegOperand(MachineInstr &MI,
1344 MachineOperand &RegOp,
1345 MachineOperand &NonRegOp) {
1346 unsigned Reg = RegOp.getReg();
1347 unsigned SubReg = RegOp.getSubReg();
1348 bool IsKill = RegOp.isKill();
1349 bool IsDead = RegOp.isDead();
1350 bool IsUndef = RegOp.isUndef();
1351 bool IsDebug = RegOp.isDebug();
1353 if (NonRegOp.isImm())
1354 RegOp.ChangeToImmediate(NonRegOp.getImm());
1355 else if (NonRegOp.isFI())
1356 RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
1360 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
1361 NonRegOp.setSubReg(SubReg);
1366 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1368 unsigned Src1Idx) const {
1369 assert(!NewMI && "this should never be used");
1371 unsigned Opc = MI.getOpcode();
1372 int CommutedOpcode = commuteOpcode(Opc);
1373 if (CommutedOpcode == -1)
1376 assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==
1377 static_cast<int>(Src0Idx) &&
1378 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==
1379 static_cast<int>(Src1Idx) &&
1380 "inconsistency with findCommutedOpIndices");
1382 MachineOperand &Src0 = MI.getOperand(Src0Idx);
1383 MachineOperand &Src1 = MI.getOperand(Src1Idx);
1385 MachineInstr *CommutedMI = nullptr;
1386 if (Src0.isReg() && Src1.isReg()) {
1387 if (isOperandLegal(MI, Src1Idx, &Src0)) {
1388 // Be sure to copy the source modifiers to the right place.
1390 = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
1393 } else if (Src0.isReg() && !Src1.isReg()) {
1394 // src0 should always be able to support any operand type, so no need to
1395 // check operand legality.
1396 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
1397 } else if (!Src0.isReg() && Src1.isReg()) {
1398 if (isOperandLegal(MI, Src1Idx, &Src0))
1399 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
1401 // FIXME: Found two non registers to commute. This does happen.
1406 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
1407 Src1, AMDGPU::OpName::src1_modifiers);
1409 CommutedMI->setDesc(get(CommutedOpcode));
1415 // This needs to be implemented because the source modifiers may be inserted
1416 // between the true commutable operands, and the base
1417 // TargetInstrInfo::commuteInstruction uses it.
1418 bool SIInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx0,
1419 unsigned &SrcOpIdx1) const {
1420 return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
1423 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
1424 unsigned &SrcOpIdx1) const {
1425 if (!Desc.isCommutable())
1428 unsigned Opc = Desc.getOpcode();
1429 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1433 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1437 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
1440 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
1441 int64_t BrOffset) const {
1442 // BranchRelaxation should never have to check s_setpc_b64 because its dest
1443 // block is unanalyzable.
1444 assert(BranchOp != AMDGPU::S_SETPC_B64);
1446 // Convert to dwords.
1449 // The branch instructions do PC += signext(SIMM16 * 4) + 4, so the offset is
1450 // from the next instruction.
1453 return isIntN(BranchOffsetBits, BrOffset);
1456 MachineBasicBlock *SIInstrInfo::getBranchDestBlock(
1457 const MachineInstr &MI) const {
1458 if (MI.getOpcode() == AMDGPU::S_SETPC_B64) {
1459 // This would be a difficult analysis to perform, but can always be legal so
1460 // there's no need to analyze it.
1464 return MI.getOperand(0).getMBB();
1467 unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
1468 MachineBasicBlock &DestBB,
1471 RegScavenger *RS) const {
1472 assert(RS && "RegScavenger required for long branching");
1473 assert(MBB.empty() &&
1474 "new block should be inserted for expanding unconditional branch");
1475 assert(MBB.pred_size() == 1);
1477 MachineFunction *MF = MBB.getParent();
1478 MachineRegisterInfo &MRI = MF->getRegInfo();
1480 // FIXME: Virtual register workaround for RegScavenger not working with empty
1482 unsigned PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1486 // We need to compute the offset relative to the instruction immediately after
1487 // s_getpc_b64. Insert pc arithmetic code before last terminator.
1488 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
1490 // TODO: Handle > 32-bit block address.
1491 if (BrOffset >= 0) {
1492 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
1493 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1494 .addReg(PCReg, 0, AMDGPU::sub0)
1495 .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_FORWARD);
1496 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
1497 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1498 .addReg(PCReg, 0, AMDGPU::sub1)
1501 // Backwards branch.
1502 BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
1503 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1504 .addReg(PCReg, 0, AMDGPU::sub0)
1505 .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_BACKWARD);
1506 BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
1507 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1508 .addReg(PCReg, 0, AMDGPU::sub1)
1512 // Insert the indirect branch after the other terminator.
1513 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
1516 // FIXME: If spilling is necessary, this will fail because this scavenger has
1517 // no emergency stack slots. It is non-trivial to spill in this situation,
1518 // because the restore code needs to be specially placed after the
1519 // jump. BranchRelaxation then needs to be made aware of the newly inserted
1522 // If a spill is needed for the pc register pair, we need to insert a spill
1523 // restore block right before the destination block, and insert a short branch
1524 // into the old destination block's fallthrough predecessor.
1527 // s_cbranch_scc0 skip_long_branch:
1531 // s_getpc_b64 s[8:9]
1532 // s_add_u32 s8, s8, restore_bb
1533 // s_addc_u32 s9, s9, 0
1534 // s_setpc_b64 s[8:9]
1536 // skip_long_branch:
1541 // dest_bb_fallthrough_predecessor:
1547 // fallthrough dest_bb
1552 RS->enterBasicBlockEnd(MBB);
1553 unsigned Scav = RS->scavengeRegisterBackwards(
1554 AMDGPU::SReg_64RegClass,
1555 MachineBasicBlock::iterator(GetPC), false, 0);
1556 MRI.replaceRegWith(PCReg, Scav);
1557 MRI.clearVirtRegs();
1558 RS->setRegUsed(Scav);
1560 return 4 + 8 + 4 + 4;
1563 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
1565 case SIInstrInfo::SCC_TRUE:
1566 return AMDGPU::S_CBRANCH_SCC1;
1567 case SIInstrInfo::SCC_FALSE:
1568 return AMDGPU::S_CBRANCH_SCC0;
1569 case SIInstrInfo::VCCNZ:
1570 return AMDGPU::S_CBRANCH_VCCNZ;
1571 case SIInstrInfo::VCCZ:
1572 return AMDGPU::S_CBRANCH_VCCZ;
1573 case SIInstrInfo::EXECNZ:
1574 return AMDGPU::S_CBRANCH_EXECNZ;
1575 case SIInstrInfo::EXECZ:
1576 return AMDGPU::S_CBRANCH_EXECZ;
1578 llvm_unreachable("invalid branch predicate");
1582 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
1584 case AMDGPU::S_CBRANCH_SCC0:
1586 case AMDGPU::S_CBRANCH_SCC1:
1588 case AMDGPU::S_CBRANCH_VCCNZ:
1590 case AMDGPU::S_CBRANCH_VCCZ:
1592 case AMDGPU::S_CBRANCH_EXECNZ:
1594 case AMDGPU::S_CBRANCH_EXECZ:
1601 bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,
1602 MachineBasicBlock::iterator I,
1603 MachineBasicBlock *&TBB,
1604 MachineBasicBlock *&FBB,
1605 SmallVectorImpl<MachineOperand> &Cond,
1606 bool AllowModify) const {
1607 if (I->getOpcode() == AMDGPU::S_BRANCH) {
1608 // Unconditional Branch
1609 TBB = I->getOperand(0).getMBB();
1613 MachineBasicBlock *CondBB = nullptr;
1615 if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
1616 CondBB = I->getOperand(1).getMBB();
1617 Cond.push_back(I->getOperand(0));
1619 BranchPredicate Pred = getBranchPredicate(I->getOpcode());
1620 if (Pred == INVALID_BR)
1623 CondBB = I->getOperand(0).getMBB();
1624 Cond.push_back(MachineOperand::CreateImm(Pred));
1625 Cond.push_back(I->getOperand(1)); // Save the branch register.
1629 if (I == MBB.end()) {
1630 // Conditional branch followed by fall-through.
1635 if (I->getOpcode() == AMDGPU::S_BRANCH) {
1637 FBB = I->getOperand(0).getMBB();
1644 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
1645 MachineBasicBlock *&FBB,
1646 SmallVectorImpl<MachineOperand> &Cond,
1647 bool AllowModify) const {
1648 MachineBasicBlock::iterator I = MBB.getFirstTerminator();
1653 // Skip over the instructions that are artificially terminators for special
1655 while (I != E && !I->isBranch() && !I->isReturn() &&
1656 I->getOpcode() != AMDGPU::SI_MASK_BRANCH) {
1657 switch (I->getOpcode()) {
1658 case AMDGPU::SI_MASK_BRANCH:
1659 case AMDGPU::S_MOV_B64_term:
1660 case AMDGPU::S_XOR_B64_term:
1661 case AMDGPU::S_ANDN2_B64_term:
1664 case AMDGPU::SI_ELSE:
1665 case AMDGPU::SI_KILL_I1_TERMINATOR:
1666 case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
1667 // FIXME: It's messy that these need to be considered here at all.
1670 llvm_unreachable("unexpected non-branch terminator inst");
1679 if (I->getOpcode() != AMDGPU::SI_MASK_BRANCH)
1680 return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
1684 // TODO: Should be able to treat as fallthrough?
1688 if (analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify))
1691 MachineBasicBlock *MaskBrDest = I->getOperand(0).getMBB();
1693 // Specifically handle the case where the conditional branch is to the same
1694 // destination as the mask branch. e.g.
1696 // si_mask_branch BB8
1697 // s_cbranch_execz BB8
1700 // This is required to understand divergent loops which may need the branches
1702 if (TBB != MaskBrDest || Cond.empty())
1705 auto Pred = Cond[0].getImm();
1706 return (Pred != EXECZ && Pred != EXECNZ);
1709 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,
1710 int *BytesRemoved) const {
1711 MachineBasicBlock::iterator I = MBB.getFirstTerminator();
1714 unsigned RemovedSize = 0;
1715 while (I != MBB.end()) {
1716 MachineBasicBlock::iterator Next = std::next(I);
1717 if (I->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
1722 RemovedSize += getInstSizeInBytes(*I);
1723 I->eraseFromParent();
1729 *BytesRemoved = RemovedSize;
1734 // Copy the flags onto the implicit condition register operand.
1735 static void preserveCondRegFlags(MachineOperand &CondReg,
1736 const MachineOperand &OrigCond) {
1737 CondReg.setIsUndef(OrigCond.isUndef());
1738 CondReg.setIsKill(OrigCond.isKill());
1741 unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
1742 MachineBasicBlock *TBB,
1743 MachineBasicBlock *FBB,
1744 ArrayRef<MachineOperand> Cond,
1746 int *BytesAdded) const {
1747 if (!FBB && Cond.empty()) {
1748 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
1755 if(Cond.size() == 1 && Cond[0].isReg()) {
1756 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
1762 assert(TBB && Cond[0].isImm());
1765 = getBranchOpcode(static_cast<BranchPredicate>(Cond[0].getImm()));
1769 MachineInstr *CondBr =
1770 BuildMI(&MBB, DL, get(Opcode))
1773 // Copy the flags onto the implicit condition register operand.
1774 preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
1783 MachineInstr *CondBr =
1784 BuildMI(&MBB, DL, get(Opcode))
1786 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
1789 MachineOperand &CondReg = CondBr->getOperand(1);
1790 CondReg.setIsUndef(Cond[1].isUndef());
1791 CondReg.setIsKill(Cond[1].isKill());
1799 bool SIInstrInfo::reverseBranchCondition(
1800 SmallVectorImpl<MachineOperand> &Cond) const {
1801 if (Cond.size() != 2) {
1805 if (Cond[0].isImm()) {
1806 Cond[0].setImm(-Cond[0].getImm());
1813 bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
1814 ArrayRef<MachineOperand> Cond,
1815 unsigned TrueReg, unsigned FalseReg,
1817 int &TrueCycles, int &FalseCycles) const {
1818 switch (Cond[0].getImm()) {
1821 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1822 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
1823 assert(MRI.getRegClass(FalseReg) == RC);
1825 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
1826 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
1828 // Limit to equal cost for branch vs. N v_cndmask_b32s.
1829 return !RI.isSGPRClass(RC) && NumInsts <= 6;
1833 // FIXME: We could insert for VGPRs if we could replace the original compare
1834 // with a vector one.
1835 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1836 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
1837 assert(MRI.getRegClass(FalseReg) == RC);
1839 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
1841 // Multiples of 8 can do s_cselect_b64
1842 if (NumInsts % 2 == 0)
1845 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
1846 return RI.isSGPRClass(RC);
1853 void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
1854 MachineBasicBlock::iterator I, const DebugLoc &DL,
1855 unsigned DstReg, ArrayRef<MachineOperand> Cond,
1856 unsigned TrueReg, unsigned FalseReg) const {
1857 BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
1858 if (Pred == VCCZ || Pred == SCC_FALSE) {
1859 Pred = static_cast<BranchPredicate>(-Pred);
1860 std::swap(TrueReg, FalseReg);
1863 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1864 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
1865 unsigned DstSize = RI.getRegSizeInBits(*DstRC);
1867 if (DstSize == 32) {
1868 unsigned SelOp = Pred == SCC_TRUE ?
1869 AMDGPU::S_CSELECT_B32 : AMDGPU::V_CNDMASK_B32_e32;
1871 // Instruction's operands are backwards from what is expected.
1872 MachineInstr *Select =
1873 BuildMI(MBB, I, DL, get(SelOp), DstReg)
1877 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
1881 if (DstSize == 64 && Pred == SCC_TRUE) {
1882 MachineInstr *Select =
1883 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
1887 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
1891 static const int16_t Sub0_15[] = {
1892 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
1893 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
1894 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
1895 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
1898 static const int16_t Sub0_15_64[] = {
1899 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
1900 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
1901 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
1902 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
1905 unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
1906 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
1907 const int16_t *SubIndices = Sub0_15;
1908 int NElts = DstSize / 32;
1910 // 64-bit select is only avaialble for SALU.
1911 if (Pred == SCC_TRUE) {
1912 SelOp = AMDGPU::S_CSELECT_B64;
1913 EltRC = &AMDGPU::SGPR_64RegClass;
1914 SubIndices = Sub0_15_64;
1916 assert(NElts % 2 == 0);
1920 MachineInstrBuilder MIB = BuildMI(
1921 MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
1923 I = MIB->getIterator();
1925 SmallVector<unsigned, 8> Regs;
1926 for (int Idx = 0; Idx != NElts; ++Idx) {
1927 unsigned DstElt = MRI.createVirtualRegister(EltRC);
1928 Regs.push_back(DstElt);
1930 unsigned SubIdx = SubIndices[Idx];
1932 MachineInstr *Select =
1933 BuildMI(MBB, I, DL, get(SelOp), DstElt)
1934 .addReg(FalseReg, 0, SubIdx)
1935 .addReg(TrueReg, 0, SubIdx);
1936 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
1943 bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) const {
1944 switch (MI.getOpcode()) {
1945 case AMDGPU::V_MOV_B32_e32:
1946 case AMDGPU::V_MOV_B32_e64:
1947 case AMDGPU::V_MOV_B64_PSEUDO: {
1948 // If there are additional implicit register operands, this may be used for
1949 // register indexing so the source register operand isn't simply copied.
1950 unsigned NumOps = MI.getDesc().getNumOperands() +
1951 MI.getDesc().getNumImplicitUses();
1953 return MI.getNumOperands() == NumOps;
1955 case AMDGPU::S_MOV_B32:
1956 case AMDGPU::S_MOV_B64:
1964 unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind(
1965 unsigned Kind) const {
1967 case PseudoSourceValue::Stack:
1968 case PseudoSourceValue::FixedStack:
1969 return AMDGPUAS::PRIVATE_ADDRESS;
1970 case PseudoSourceValue::ConstantPool:
1971 case PseudoSourceValue::GOT:
1972 case PseudoSourceValue::JumpTable:
1973 case PseudoSourceValue::GlobalValueCallEntry:
1974 case PseudoSourceValue::ExternalSymbolCallEntry:
1975 case PseudoSourceValue::TargetCustom:
1976 return AMDGPUAS::CONSTANT_ADDRESS;
1978 return AMDGPUAS::FLAT_ADDRESS;
1981 static void removeModOperands(MachineInstr &MI) {
1982 unsigned Opc = MI.getOpcode();
1983 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1984 AMDGPU::OpName::src0_modifiers);
1985 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1986 AMDGPU::OpName::src1_modifiers);
1987 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1988 AMDGPU::OpName::src2_modifiers);
1990 MI.RemoveOperand(Src2ModIdx);
1991 MI.RemoveOperand(Src1ModIdx);
1992 MI.RemoveOperand(Src0ModIdx);
1995 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1996 unsigned Reg, MachineRegisterInfo *MRI) const {
1997 if (!MRI->hasOneNonDBGUse(Reg))
2000 switch (DefMI.getOpcode()) {
2003 case AMDGPU::S_MOV_B64:
2004 // TODO: We could fold 64-bit immediates, but this get compilicated
2005 // when there are sub-registers.
2008 case AMDGPU::V_MOV_B32_e32:
2009 case AMDGPU::S_MOV_B32:
2013 const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
2015 // FIXME: We could handle FrameIndex values here.
2016 if (!ImmOp->isImm())
2019 unsigned Opc = UseMI.getOpcode();
2020 if (Opc == AMDGPU::COPY) {
2021 bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
2022 unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
2023 UseMI.setDesc(get(NewOpc));
2024 UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
2025 UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
2029 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64 ||
2030 Opc == AMDGPU::V_MAD_F16 || Opc == AMDGPU::V_MAC_F16_e64) {
2031 // Don't fold if we are using source or output modifiers. The new VOP2
2032 // instructions don't have them.
2033 if (hasAnyModifiersSet(UseMI))
2036 // If this is a free constant, there's no reason to do this.
2037 // TODO: We could fold this here instead of letting SIFoldOperands do it
2039 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2041 // Any src operand can be used for the legality check.
2042 if (isInlineConstant(UseMI, *Src0, *ImmOp))
2045 bool IsF32 = Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64;
2046 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
2047 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
2049 // Multiplied part is the constant: Use v_madmk_{f16, f32}.
2050 // We should only expect these to be on src0 due to canonicalizations.
2051 if (Src0->isReg() && Src0->getReg() == Reg) {
2052 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2055 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2058 // We need to swap operands 0 and 1 since madmk constant is at operand 1.
2060 const int64_t Imm = ImmOp->getImm();
2062 // FIXME: This would be a lot easier if we could return a new instruction
2063 // instead of having to modify in place.
2065 // Remove these first since they are at the end.
2066 UseMI.RemoveOperand(
2067 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2068 UseMI.RemoveOperand(
2069 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2071 unsigned Src1Reg = Src1->getReg();
2072 unsigned Src1SubReg = Src1->getSubReg();
2073 Src0->setReg(Src1Reg);
2074 Src0->setSubReg(Src1SubReg);
2075 Src0->setIsKill(Src1->isKill());
2077 if (Opc == AMDGPU::V_MAC_F32_e64 ||
2078 Opc == AMDGPU::V_MAC_F16_e64)
2079 UseMI.untieRegOperand(
2080 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2082 Src1->ChangeToImmediate(Imm);
2084 removeModOperands(UseMI);
2085 UseMI.setDesc(get(IsF32 ? AMDGPU::V_MADMK_F32 : AMDGPU::V_MADMK_F16));
2087 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2089 DefMI.eraseFromParent();
2094 // Added part is the constant: Use v_madak_{f16, f32}.
2095 if (Src2->isReg() && Src2->getReg() == Reg) {
2096 // Not allowed to use constant bus for another operand.
2097 // We can however allow an inline immediate as src0.
2098 bool Src0Inlined = false;
2099 if (Src0->isReg()) {
2100 // Try to inline constant if possible.
2101 // If the Def moves immediate and the use is single
2102 // We are saving VGPR here.
2103 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
2104 if (Def && Def->isMoveImmediate() &&
2105 isInlineConstant(Def->getOperand(1)) &&
2106 MRI->hasOneUse(Src0->getReg())) {
2107 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2109 } else if ((RI.isPhysicalRegister(Src0->getReg()) &&
2110 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg()))) ||
2111 (RI.isVirtualRegister(Src0->getReg()) &&
2112 RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
2114 // VGPR is okay as Src0 - fallthrough
2117 if (Src1->isReg() && !Src0Inlined ) {
2118 // We have one slot for inlinable constant so far - try to fill it
2119 MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
2120 if (Def && Def->isMoveImmediate() &&
2121 isInlineConstant(Def->getOperand(1)) &&
2122 MRI->hasOneUse(Src1->getReg()) &&
2123 commuteInstruction(UseMI)) {
2124 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2125 } else if ((RI.isPhysicalRegister(Src1->getReg()) &&
2126 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
2127 (RI.isVirtualRegister(Src1->getReg()) &&
2128 RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
2130 // VGPR is okay as Src1 - fallthrough
2133 const int64_t Imm = ImmOp->getImm();
2135 // FIXME: This would be a lot easier if we could return a new instruction
2136 // instead of having to modify in place.
2138 // Remove these first since they are at the end.
2139 UseMI.RemoveOperand(
2140 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2141 UseMI.RemoveOperand(
2142 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2144 if (Opc == AMDGPU::V_MAC_F32_e64 ||
2145 Opc == AMDGPU::V_MAC_F16_e64)
2146 UseMI.untieRegOperand(
2147 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2149 // ChangingToImmediate adds Src2 back to the instruction.
2150 Src2->ChangeToImmediate(Imm);
2152 // These come before src2.
2153 removeModOperands(UseMI);
2154 UseMI.setDesc(get(IsF32 ? AMDGPU::V_MADAK_F32 : AMDGPU::V_MADAK_F16));
2156 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2158 DefMI.eraseFromParent();
2167 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
2168 int WidthB, int OffsetB) {
2169 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2170 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2171 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2172 return LowOffset + LowWidth <= HighOffset;
2175 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr &MIa,
2176 MachineInstr &MIb) const {
2177 MachineOperand *BaseOp0, *BaseOp1;
2178 int64_t Offset0, Offset1;
2180 if (getMemOperandWithOffset(MIa, BaseOp0, Offset0, &RI) &&
2181 getMemOperandWithOffset(MIb, BaseOp1, Offset1, &RI)) {
2182 if (!BaseOp0->isIdenticalTo(*BaseOp1))
2185 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
2186 // FIXME: Handle ds_read2 / ds_write2.
2189 unsigned Width0 = (*MIa.memoperands_begin())->getSize();
2190 unsigned Width1 = (*MIb.memoperands_begin())->getSize();
2191 if (offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
2199 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa,
2201 AliasAnalysis *AA) const {
2202 assert((MIa.mayLoad() || MIa.mayStore()) &&
2203 "MIa must load from or modify a memory location");
2204 assert((MIb.mayLoad() || MIb.mayStore()) &&
2205 "MIb must load from or modify a memory location");
2207 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects())
2210 // XXX - Can we relax this between address spaces?
2211 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2214 if (AA && MIa.hasOneMemOperand() && MIb.hasOneMemOperand()) {
2215 const MachineMemOperand *MMOa = *MIa.memoperands_begin();
2216 const MachineMemOperand *MMOb = *MIb.memoperands_begin();
2217 if (MMOa->getValue() && MMOb->getValue()) {
2218 MemoryLocation LocA(MMOa->getValue(), MMOa->getSize(), MMOa->getAAInfo());
2219 MemoryLocation LocB(MMOb->getValue(), MMOb->getSize(), MMOb->getAAInfo());
2220 if (!AA->alias(LocA, LocB))
2225 // TODO: Should we check the address space from the MachineMemOperand? That
2226 // would allow us to distinguish objects we know don't alias based on the
2227 // underlying address space, even if it was lowered to a different one,
2228 // e.g. private accesses lowered to use MUBUF instructions on a scratch
2232 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2234 return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb);
2237 if (isMUBUF(MIa) || isMTBUF(MIa)) {
2238 if (isMUBUF(MIb) || isMTBUF(MIb))
2239 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2241 return !isFLAT(MIb) && !isSMRD(MIb);
2246 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2248 return !isFLAT(MIb) && !isMUBUF(MIa) && !isMTBUF(MIa);
2253 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2261 static int64_t getFoldableImm(const MachineOperand* MO) {
2264 const MachineFunction *MF = MO->getParent()->getParent()->getParent();
2265 const MachineRegisterInfo &MRI = MF->getRegInfo();
2266 auto Def = MRI.getUniqueVRegDef(MO->getReg());
2267 if (Def && Def->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
2268 Def->getOperand(1).isImm())
2269 return Def->getOperand(1).getImm();
2270 return AMDGPU::NoRegister;
2273 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
2275 LiveVariables *LV) const {
2276 unsigned Opc = MI.getOpcode();
2278 bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64;
2283 case AMDGPU::V_MAC_F16_e64:
2286 case AMDGPU::V_MAC_F32_e64:
2287 case AMDGPU::V_FMAC_F32_e64:
2289 case AMDGPU::V_MAC_F16_e32:
2292 case AMDGPU::V_MAC_F32_e32:
2293 case AMDGPU::V_FMAC_F32_e32: {
2294 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
2295 AMDGPU::OpName::src0);
2296 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
2297 if (!Src0->isReg() && !Src0->isImm())
2300 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
2307 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
2308 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
2309 const MachineOperand *Src0Mods =
2310 getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
2311 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2312 const MachineOperand *Src1Mods =
2313 getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
2314 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2315 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
2316 const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
2318 if (!IsFMA && !Src0Mods && !Src1Mods && !Clamp && !Omod &&
2319 // If we have an SGPR input, we will violate the constant bus restriction.
2320 (!Src0->isReg() || !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
2321 if (auto Imm = getFoldableImm(Src2)) {
2322 return BuildMI(*MBB, MI, MI.getDebugLoc(),
2323 get(IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32))
2329 if (auto Imm = getFoldableImm(Src1)) {
2330 return BuildMI(*MBB, MI, MI.getDebugLoc(),
2331 get(IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32))
2337 if (auto Imm = getFoldableImm(Src0)) {
2338 if (isOperandLegal(MI, AMDGPU::getNamedOperandIdx(AMDGPU::V_MADMK_F32,
2339 AMDGPU::OpName::src0), Src1))
2340 return BuildMI(*MBB, MI, MI.getDebugLoc(),
2341 get(IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32))
2349 assert((!IsFMA || !IsF16) && "fmac only expected with f32");
2350 unsigned NewOpc = IsFMA ? AMDGPU::V_FMA_F32 :
2351 (IsF16 ? AMDGPU::V_MAD_F16 : AMDGPU::V_MAD_F32);
2352 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2354 .addImm(Src0Mods ? Src0Mods->getImm() : 0)
2356 .addImm(Src1Mods ? Src1Mods->getImm() : 0)
2358 .addImm(0) // Src mods
2360 .addImm(Clamp ? Clamp->getImm() : 0)
2361 .addImm(Omod ? Omod->getImm() : 0);
2364 // It's not generally safe to move VALU instructions across these since it will
2365 // start using the register as a base index rather than directly.
2366 // XXX - Why isn't hasSideEffects sufficient for these?
2367 static bool changesVGPRIndexingMode(const MachineInstr &MI) {
2368 switch (MI.getOpcode()) {
2369 case AMDGPU::S_SET_GPR_IDX_ON:
2370 case AMDGPU::S_SET_GPR_IDX_MODE:
2371 case AMDGPU::S_SET_GPR_IDX_OFF:
2378 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
2379 const MachineBasicBlock *MBB,
2380 const MachineFunction &MF) const {
2381 // XXX - Do we want the SP check in the base implementation?
2383 // Target-independent instructions do not have an implicit-use of EXEC, even
2384 // when they operate on VGPRs. Treating EXEC modifications as scheduling
2385 // boundaries prevents incorrect movements of such instructions.
2386 return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF) ||
2387 MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
2388 MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
2389 MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
2390 changesVGPRIndexingMode(MI);
2393 bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {
2394 unsigned Opcode = MI.getOpcode();
2396 if (MI.mayStore() && isSMRD(MI))
2397 return true; // scalar store or atomic
2399 // These instructions cause shader I/O that may cause hardware lockups
2400 // when executed with an empty EXEC mask.
2402 // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
2403 // EXEC = 0, but checking for that case here seems not worth it
2404 // given the typical code patterns.
2405 if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
2406 Opcode == AMDGPU::EXP || Opcode == AMDGPU::EXP_DONE)
2409 if (MI.isInlineAsm())
2410 return true; // conservative assumption
2412 // These are like SALU instructions in terms of effects, so it's questionable
2413 // whether we should return true for those.
2415 // However, executing them with EXEC = 0 causes them to operate on undefined
2416 // data, which we avoid by returning true here.
2417 if (Opcode == AMDGPU::V_READFIRSTLANE_B32 || Opcode == AMDGPU::V_READLANE_B32)
2423 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
2424 switch (Imm.getBitWidth()) {
2426 return AMDGPU::isInlinableLiteral32(Imm.getSExtValue(),
2427 ST.hasInv2PiInlineImm());
2429 return AMDGPU::isInlinableLiteral64(Imm.getSExtValue(),
2430 ST.hasInv2PiInlineImm());
2432 return ST.has16BitInsts() &&
2433 AMDGPU::isInlinableLiteral16(Imm.getSExtValue(),
2434 ST.hasInv2PiInlineImm());
2436 llvm_unreachable("invalid bitwidth");
2440 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
2441 uint8_t OperandType) const {
2443 OperandType < AMDGPU::OPERAND_SRC_FIRST ||
2444 OperandType > AMDGPU::OPERAND_SRC_LAST)
2447 // MachineOperand provides no way to tell the true operand size, since it only
2448 // records a 64-bit value. We need to know the size to determine if a 32-bit
2449 // floating point immediate bit pattern is legal for an integer immediate. It
2450 // would be for any 32-bit integer operand, but would not be for a 64-bit one.
2452 int64_t Imm = MO.getImm();
2453 switch (OperandType) {
2454 case AMDGPU::OPERAND_REG_IMM_INT32:
2455 case AMDGPU::OPERAND_REG_IMM_FP32:
2456 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
2457 case AMDGPU::OPERAND_REG_INLINE_C_FP32: {
2458 int32_t Trunc = static_cast<int32_t>(Imm);
2459 return AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm());
2461 case AMDGPU::OPERAND_REG_IMM_INT64:
2462 case AMDGPU::OPERAND_REG_IMM_FP64:
2463 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
2464 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
2465 return AMDGPU::isInlinableLiteral64(MO.getImm(),
2466 ST.hasInv2PiInlineImm());
2467 case AMDGPU::OPERAND_REG_IMM_INT16:
2468 case AMDGPU::OPERAND_REG_IMM_FP16:
2469 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
2470 case AMDGPU::OPERAND_REG_INLINE_C_FP16: {
2471 if (isInt<16>(Imm) || isUInt<16>(Imm)) {
2472 // A few special case instructions have 16-bit operands on subtargets
2473 // where 16-bit instructions are not legal.
2474 // TODO: Do the 32-bit immediates work? We shouldn't really need to handle
2475 // constants in these cases
2476 int16_t Trunc = static_cast<int16_t>(Imm);
2477 return ST.has16BitInsts() &&
2478 AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm());
2483 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
2484 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
2485 if (isUInt<16>(Imm)) {
2486 int16_t Trunc = static_cast<int16_t>(Imm);
2487 return ST.has16BitInsts() &&
2488 AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm());
2490 if (!(Imm & 0xffff)) {
2491 return ST.has16BitInsts() &&
2492 AMDGPU::isInlinableLiteral16(Imm >> 16, ST.hasInv2PiInlineImm());
2494 uint32_t Trunc = static_cast<uint32_t>(Imm);
2495 return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm());
2498 llvm_unreachable("invalid bitwidth");
2502 bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,
2503 const MCOperandInfo &OpInfo) const {
2504 switch (MO.getType()) {
2505 case MachineOperand::MO_Register:
2507 case MachineOperand::MO_Immediate:
2508 return !isInlineConstant(MO, OpInfo);
2509 case MachineOperand::MO_FrameIndex:
2510 case MachineOperand::MO_MachineBasicBlock:
2511 case MachineOperand::MO_ExternalSymbol:
2512 case MachineOperand::MO_GlobalAddress:
2513 case MachineOperand::MO_MCSymbol:
2516 llvm_unreachable("unexpected operand type");
2520 static bool compareMachineOp(const MachineOperand &Op0,
2521 const MachineOperand &Op1) {
2522 if (Op0.getType() != Op1.getType())
2525 switch (Op0.getType()) {
2526 case MachineOperand::MO_Register:
2527 return Op0.getReg() == Op1.getReg();
2528 case MachineOperand::MO_Immediate:
2529 return Op0.getImm() == Op1.getImm();
2531 llvm_unreachable("Didn't expect to be comparing these operand types");
2535 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
2536 const MachineOperand &MO) const {
2537 const MCOperandInfo &OpInfo = get(MI.getOpcode()).OpInfo[OpNo];
2539 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
2541 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
2544 if (OpInfo.RegClass < 0)
2547 if (MO.isImm() && isInlineConstant(MO, OpInfo))
2548 return RI.opCanUseInlineConstant(OpInfo.OperandType);
2550 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
2553 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
2554 int Op32 = AMDGPU::getVOPe32(Opcode);
2558 return pseudoToMCOpcode(Op32) != -1;
2561 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
2562 // The src0_modifier operand is present on all instructions
2563 // that have modifiers.
2565 return AMDGPU::getNamedOperandIdx(Opcode,
2566 AMDGPU::OpName::src0_modifiers) != -1;
2569 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
2570 unsigned OpName) const {
2571 const MachineOperand *Mods = getNamedOperand(MI, OpName);
2572 return Mods && Mods->getImm();
2575 bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {
2576 return hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
2577 hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
2578 hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers) ||
2579 hasModifiersSet(MI, AMDGPU::OpName::clamp) ||
2580 hasModifiersSet(MI, AMDGPU::OpName::omod);
2583 bool SIInstrInfo::canShrink(const MachineInstr &MI,
2584 const MachineRegisterInfo &MRI) const {
2585 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2586 // Can't shrink instruction with three operands.
2587 // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
2588 // a special case for it. It can only be shrunk if the third operand
2589 // is vcc. We should handle this the same way we handle vopc, by addding
2590 // a register allocation hint pre-regalloc and then do the shrinking
2593 switch (MI.getOpcode()) {
2594 default: return false;
2596 case AMDGPU::V_ADDC_U32_e64:
2597 case AMDGPU::V_SUBB_U32_e64:
2598 case AMDGPU::V_SUBBREV_U32_e64: {
2599 const MachineOperand *Src1
2600 = getNamedOperand(MI, AMDGPU::OpName::src1);
2601 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
2603 // Additional verification is needed for sdst/src2.
2606 case AMDGPU::V_MAC_F32_e64:
2607 case AMDGPU::V_MAC_F16_e64:
2608 case AMDGPU::V_FMAC_F32_e64:
2609 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
2610 hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
2614 case AMDGPU::V_CNDMASK_B32_e64:
2619 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2620 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
2621 hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
2624 // We don't need to check src0, all input types are legal, so just make sure
2625 // src0 isn't using any modifiers.
2626 if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
2629 // Can it be shrunk to a valid 32 bit opcode?
2630 if (!hasVALU32BitEncoding(MI.getOpcode()))
2633 // Check output modifiers
2634 return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
2635 !hasModifiersSet(MI, AMDGPU::OpName::clamp);
2638 // Set VCC operand with all flags from \p Orig, except for setting it as
2640 static void copyFlagsToImplicitVCC(MachineInstr &MI,
2641 const MachineOperand &Orig) {
2643 for (MachineOperand &Use : MI.implicit_operands()) {
2644 if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
2645 Use.setIsUndef(Orig.isUndef());
2646 Use.setIsKill(Orig.isKill());
2652 MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,
2653 unsigned Op32) const {
2654 MachineBasicBlock *MBB = MI.getParent();;
2655 MachineInstrBuilder Inst32 =
2656 BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32));
2658 // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
2659 // For VOPC instructions, this is replaced by an implicit def of vcc.
2660 int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
2661 if (Op32DstIdx != -1) {
2663 Inst32.add(MI.getOperand(0));
2665 assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
2669 Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
2671 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2675 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2678 int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
2679 if (Op32Src2Idx != -1) {
2682 // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
2683 // replaced with an implicit read of vcc. This was already added
2684 // during the initial BuildMI, so find it to preserve the flags.
2685 copyFlagsToImplicitVCC(*Inst32, *Src2);
2692 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
2693 const MachineOperand &MO,
2694 const MCOperandInfo &OpInfo) const {
2695 // Literal constants use the constant bus.
2696 //if (isLiteralConstantLike(MO, OpInfo))
2699 return !isInlineConstant(MO, OpInfo);
2702 return true; // Misc other operands like FrameIndex
2707 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
2708 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
2710 // FLAT_SCR is just an SGPR pair.
2711 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
2714 // EXEC register uses the constant bus.
2715 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
2718 // SGPRs use the constant bus
2719 return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 ||
2720 (!MO.isImplicit() &&
2721 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
2722 AMDGPU::SGPR_64RegClass.contains(MO.getReg()))));
2725 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
2726 for (const MachineOperand &MO : MI.implicit_operands()) {
2727 // We only care about reads.
2731 switch (MO.getReg()) {
2734 case AMDGPU::FLAT_SCR:
2742 return AMDGPU::NoRegister;
2745 static bool shouldReadExec(const MachineInstr &MI) {
2746 if (SIInstrInfo::isVALU(MI)) {
2747 switch (MI.getOpcode()) {
2748 case AMDGPU::V_READLANE_B32:
2749 case AMDGPU::V_READLANE_B32_si:
2750 case AMDGPU::V_READLANE_B32_vi:
2751 case AMDGPU::V_WRITELANE_B32:
2752 case AMDGPU::V_WRITELANE_B32_si:
2753 case AMDGPU::V_WRITELANE_B32_vi:
2760 if (SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
2761 SIInstrInfo::isSALU(MI) ||
2762 SIInstrInfo::isSMRD(MI))
2768 static bool isSubRegOf(const SIRegisterInfo &TRI,
2769 const MachineOperand &SuperVec,
2770 const MachineOperand &SubReg) {
2771 if (TargetRegisterInfo::isPhysicalRegister(SubReg.getReg()))
2772 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
2774 return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
2775 SubReg.getReg() == SuperVec.getReg();
2778 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
2779 StringRef &ErrInfo) const {
2780 uint16_t Opcode = MI.getOpcode();
2781 if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
2784 const MachineFunction *MF = MI.getParent()->getParent();
2785 const MachineRegisterInfo &MRI = MF->getRegInfo();
2787 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
2788 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
2789 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
2791 // Make sure the number of operands is correct.
2792 const MCInstrDesc &Desc = get(Opcode);
2793 if (!Desc.isVariadic() &&
2794 Desc.getNumOperands() != MI.getNumExplicitOperands()) {
2795 ErrInfo = "Instruction has wrong number of operands.";
2799 if (MI.isInlineAsm()) {
2800 // Verify register classes for inlineasm constraints.
2801 for (unsigned I = InlineAsm::MIOp_FirstOperand, E = MI.getNumOperands();
2803 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI);
2807 const MachineOperand &Op = MI.getOperand(I);
2811 unsigned Reg = Op.getReg();
2812 if (!TargetRegisterInfo::isVirtualRegister(Reg) && !RC->contains(Reg)) {
2813 ErrInfo = "inlineasm operand has incorrect register class.";
2821 // Make sure the register classes are correct.
2822 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
2823 if (MI.getOperand(i).isFPImm()) {
2824 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
2825 "all fp values to integers.";
2829 int RegClass = Desc.OpInfo[i].RegClass;
2831 switch (Desc.OpInfo[i].OperandType) {
2832 case MCOI::OPERAND_REGISTER:
2833 if (MI.getOperand(i).isImm()) {
2834 ErrInfo = "Illegal immediate value for operand.";
2838 case AMDGPU::OPERAND_REG_IMM_INT32:
2839 case AMDGPU::OPERAND_REG_IMM_FP32:
2841 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
2842 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
2843 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
2844 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
2845 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
2846 case AMDGPU::OPERAND_REG_INLINE_C_FP16: {
2847 const MachineOperand &MO = MI.getOperand(i);
2848 if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
2849 ErrInfo = "Illegal immediate value for operand.";
2854 case MCOI::OPERAND_IMMEDIATE:
2855 case AMDGPU::OPERAND_KIMM32:
2856 // Check if this operand is an immediate.
2857 // FrameIndex operands will be replaced by immediates, so they are
2859 if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
2860 ErrInfo = "Expected immediate, but got non-immediate";
2868 if (!MI.getOperand(i).isReg())
2871 if (RegClass != -1) {
2872 unsigned Reg = MI.getOperand(i).getReg();
2873 if (Reg == AMDGPU::NoRegister ||
2874 TargetRegisterInfo::isVirtualRegister(Reg))
2877 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
2878 if (!RC->contains(Reg)) {
2879 ErrInfo = "Operand has incorrect register class.";
2887 if (!ST.hasSDWA()) {
2888 ErrInfo = "SDWA is not supported on this target";
2892 int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
2894 const int OpIndicies[] = { DstIdx, Src0Idx, Src1Idx, Src2Idx };
2896 for (int OpIdx: OpIndicies) {
2899 const MachineOperand &MO = MI.getOperand(OpIdx);
2901 if (!ST.hasSDWAScalar()) {
2903 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) {
2904 ErrInfo = "Only VGPRs allowed as operands in SDWA instructions on VI";
2908 // No immediates on GFX9
2910 ErrInfo = "Only reg allowed as operands in SDWA instructions on GFX9";
2916 if (!ST.hasSDWAOmod()) {
2917 // No omod allowed on VI
2918 const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
2919 if (OMod != nullptr &&
2920 (!OMod->isImm() || OMod->getImm() != 0)) {
2921 ErrInfo = "OMod not allowed in SDWA instructions on VI";
2926 uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
2927 if (isVOPC(BasicOpcode)) {
2928 if (!ST.hasSDWASdst() && DstIdx != -1) {
2929 // Only vcc allowed as dst on VI for VOPC
2930 const MachineOperand &Dst = MI.getOperand(DstIdx);
2931 if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
2932 ErrInfo = "Only VCC allowed as dst in SDWA instructions on VI";
2935 } else if (!ST.hasSDWAOutModsVOPC()) {
2936 // No clamp allowed on GFX9 for VOPC
2937 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
2938 if (Clamp && (!Clamp->isImm() || Clamp->getImm() != 0)) {
2939 ErrInfo = "Clamp not allowed in VOPC SDWA instructions on VI";
2943 // No omod allowed on GFX9 for VOPC
2944 const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
2945 if (OMod && (!OMod->isImm() || OMod->getImm() != 0)) {
2946 ErrInfo = "OMod not allowed in VOPC SDWA instructions on VI";
2952 const MachineOperand *DstUnused = getNamedOperand(MI, AMDGPU::OpName::dst_unused);
2953 if (DstUnused && DstUnused->isImm() &&
2954 DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) {
2955 const MachineOperand &Dst = MI.getOperand(DstIdx);
2956 if (!Dst.isReg() || !Dst.isTied()) {
2957 ErrInfo = "Dst register should have tied register";
2961 const MachineOperand &TiedMO =
2962 MI.getOperand(MI.findTiedOperandIdx(DstIdx));
2963 if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {
2965 "Dst register should be tied to implicit use of preserved register";
2967 } else if (TargetRegisterInfo::isPhysicalRegister(TiedMO.getReg()) &&
2968 Dst.getReg() != TiedMO.getReg()) {
2969 ErrInfo = "Dst register should use same physical register as preserved";
2976 if (isMIMG(MI.getOpcode()) && !MI.mayStore()) {
2977 // Ensure that the return type used is large enough for all the options
2978 // being used TFE/LWE require an extra result register.
2979 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask);
2981 uint64_t DMaskImm = DMask->getImm();
2983 isGather4(MI.getOpcode()) ? 4 : countPopulation(DMaskImm);
2984 const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe);
2985 const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe);
2986 const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
2988 // Adjust for packed 16 bit values
2989 if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
2992 // Adjust if using LWE or TFE
2993 if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
2996 const uint32_t DstIdx =
2997 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
2998 const MachineOperand &Dst = MI.getOperand(DstIdx);
3000 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
3001 uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
3002 if (RegCount > DstSize) {
3003 ErrInfo = "MIMG instruction returns too many registers for dst "
3011 // Verify VOP*. Ignore multiple sgpr operands on writelane.
3012 if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
3013 && (isVOP1(MI) || isVOP2(MI) || isVOP3(MI) || isVOPC(MI) || isSDWA(MI))) {
3014 // Only look at the true operands. Only a real operand can use the constant
3015 // bus, and we don't want to check pseudo-operands like the source modifier
3017 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
3019 unsigned ConstantBusCount = 0;
3020 unsigned LiteralCount = 0;
3022 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
3025 unsigned SGPRUsed = findImplicitSGPRRead(MI);
3026 if (SGPRUsed != AMDGPU::NoRegister)
3029 for (int OpIdx : OpIndices) {
3032 const MachineOperand &MO = MI.getOperand(OpIdx);
3033 if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3035 if (MO.getReg() != SGPRUsed)
3037 SGPRUsed = MO.getReg();
3044 if (ConstantBusCount > 1) {
3045 ErrInfo = "VOP* instruction uses the constant bus more than once";
3049 if (isVOP3(MI) && LiteralCount) {
3050 ErrInfo = "VOP3 instruction uses literal";
3055 // Verify misc. restrictions on specific instructions.
3056 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
3057 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
3058 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3059 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3060 const MachineOperand &Src2 = MI.getOperand(Src2Idx);
3061 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3062 if (!compareMachineOp(Src0, Src1) &&
3063 !compareMachineOp(Src0, Src2)) {
3064 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
3071 int64_t Imm = getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm();
3072 if (sopkIsZext(MI)) {
3073 if (!isUInt<16>(Imm)) {
3074 ErrInfo = "invalid immediate for SOPK instruction";
3078 if (!isInt<16>(Imm)) {
3079 ErrInfo = "invalid immediate for SOPK instruction";
3085 if (Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e32 ||
3086 Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e64 ||
3087 Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
3088 Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64) {
3089 const bool IsDst = Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
3090 Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64;
3092 const unsigned StaticNumOps = Desc.getNumOperands() +
3093 Desc.getNumImplicitUses();
3094 const unsigned NumImplicitOps = IsDst ? 2 : 1;
3096 // Allow additional implicit operands. This allows a fixup done by the post
3097 // RA scheduler where the main implicit operand is killed and implicit-defs
3098 // are added for sub-registers that remain live after this instruction.
3099 if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
3100 ErrInfo = "missing implicit register operands";
3104 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3106 if (!Dst->isUse()) {
3107 ErrInfo = "v_movreld_b32 vdst should be a use operand";
3112 if (!MI.isRegTiedToUseOperand(StaticNumOps, &UseOpIdx) ||
3113 UseOpIdx != StaticNumOps + 1) {
3114 ErrInfo = "movrel implicit operands should be tied";
3119 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3120 const MachineOperand &ImpUse
3121 = MI.getOperand(StaticNumOps + NumImplicitOps - 1);
3122 if (!ImpUse.isReg() || !ImpUse.isUse() ||
3123 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
3124 ErrInfo = "src0 should be subreg of implicit vector use";
3129 // Make sure we aren't losing exec uses in the td files. This mostly requires
3130 // being careful when using let Uses to try to add other use registers.
3131 if (shouldReadExec(MI)) {
3132 if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
3133 ErrInfo = "VALU instruction does not implicitly read exec mask";
3139 if (MI.mayStore()) {
3140 // The register offset form of scalar stores may only use m0 as the
3141 // soffset register.
3142 const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soff);
3143 if (Soff && Soff->getReg() != AMDGPU::M0) {
3144 ErrInfo = "scalar stores must use m0 as offset register";
3150 if (isFLAT(MI) && !MF->getSubtarget<GCNSubtarget>().hasFlatInstOffsets()) {
3151 const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
3152 if (Offset->getImm() != 0) {
3153 ErrInfo = "subtarget does not support offsets in flat instructions";
3158 const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
3160 using namespace AMDGPU::DPP;
3162 unsigned DC = DppCt->getImm();
3163 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 ||
3164 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST ||
3165 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) ||
3166 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) ||
3167 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) ||
3168 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST)) {
3169 ErrInfo = "Invalid dpp_ctrl value";
3177 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
3178 switch (MI.getOpcode()) {
3179 default: return AMDGPU::INSTRUCTION_LIST_END;
3180 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
3181 case AMDGPU::COPY: return AMDGPU::COPY;
3182 case AMDGPU::PHI: return AMDGPU::PHI;
3183 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
3184 case AMDGPU::WQM: return AMDGPU::WQM;
3185 case AMDGPU::WWM: return AMDGPU::WWM;
3186 case AMDGPU::S_MOV_B32:
3187 return MI.getOperand(1).isReg() ?
3188 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
3189 case AMDGPU::S_ADD_I32:
3190 return ST.hasAddNoCarry() ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_I32_e32;
3191 case AMDGPU::S_ADDC_U32:
3192 return AMDGPU::V_ADDC_U32_e32;
3193 case AMDGPU::S_SUB_I32:
3194 return ST.hasAddNoCarry() ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32;
3195 // FIXME: These are not consistently handled, and selected when the carry is
3197 case AMDGPU::S_ADD_U32:
3198 return AMDGPU::V_ADD_I32_e32;
3199 case AMDGPU::S_SUB_U32:
3200 return AMDGPU::V_SUB_I32_e32;
3201 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
3202 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
3203 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64;
3204 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e64;
3205 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e64;
3206 case AMDGPU::S_XNOR_B32:
3207 return ST.hasDLInsts() ? AMDGPU::V_XNOR_B32_e64 : AMDGPU::INSTRUCTION_LIST_END;
3208 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e64;
3209 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e64;
3210 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e64;
3211 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e64;
3212 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
3213 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
3214 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
3215 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
3216 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
3217 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
3218 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
3219 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
3220 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
3221 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
3222 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
3223 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
3224 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
3225 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
3226 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
3227 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
3228 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
3229 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
3230 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
3231 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
3232 case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e32;
3233 case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e32;
3234 case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e32;
3235 case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32;
3236 case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32;
3237 case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32;
3238 case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e32;
3239 case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e32;
3240 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
3241 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
3242 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
3243 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
3244 case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ;
3245 case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ;
3249 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
3250 unsigned OpNo) const {
3251 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3252 const MCInstrDesc &Desc = get(MI.getOpcode());
3253 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
3254 Desc.OpInfo[OpNo].RegClass == -1) {
3255 unsigned Reg = MI.getOperand(OpNo).getReg();
3257 if (TargetRegisterInfo::isVirtualRegister(Reg))
3258 return MRI.getRegClass(Reg);
3259 return RI.getPhysRegClass(Reg);
3262 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
3263 return RI.getRegClass(RCID);
3266 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
3267 switch (MI.getOpcode()) {
3269 case AMDGPU::REG_SEQUENCE:
3271 case AMDGPU::INSERT_SUBREG:
3272 return RI.hasVGPRs(getOpRegClass(MI, 0));
3274 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
3278 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
3279 MachineBasicBlock::iterator I = MI;
3280 MachineBasicBlock *MBB = MI.getParent();
3281 MachineOperand &MO = MI.getOperand(OpIdx);
3282 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
3283 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
3284 const TargetRegisterClass *RC = RI.getRegClass(RCID);
3285 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
3287 Opcode = AMDGPU::COPY;
3288 else if (RI.isSGPRClass(RC))
3289 Opcode = AMDGPU::S_MOV_B32;
3291 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
3292 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
3293 VRC = &AMDGPU::VReg_64RegClass;
3295 VRC = &AMDGPU::VGPR_32RegClass;
3297 unsigned Reg = MRI.createVirtualRegister(VRC);
3298 DebugLoc DL = MBB->findDebugLoc(I);
3299 BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
3300 MO.ChangeToRegister(Reg, false);
3303 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
3304 MachineRegisterInfo &MRI,
3305 MachineOperand &SuperReg,
3306 const TargetRegisterClass *SuperRC,
3308 const TargetRegisterClass *SubRC)
3310 MachineBasicBlock *MBB = MI->getParent();
3311 DebugLoc DL = MI->getDebugLoc();
3312 unsigned SubReg = MRI.createVirtualRegister(SubRC);
3314 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
3315 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3316 .addReg(SuperReg.getReg(), 0, SubIdx);
3320 // Just in case the super register is itself a sub-register, copy it to a new
3321 // value so we don't need to worry about merging its subreg index with the
3322 // SubIdx passed to this function. The register coalescer should be able to
3323 // eliminate this extra copy.
3324 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
3326 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
3327 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
3329 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3330 .addReg(NewSuperReg, 0, SubIdx);
3335 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
3336 MachineBasicBlock::iterator MII,
3337 MachineRegisterInfo &MRI,
3339 const TargetRegisterClass *SuperRC,
3341 const TargetRegisterClass *SubRC) const {
3343 if (SubIdx == AMDGPU::sub0)
3344 return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
3345 if (SubIdx == AMDGPU::sub1)
3346 return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm() >> 32));
3348 llvm_unreachable("Unhandled register index for immediate");
3351 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
3353 return MachineOperand::CreateReg(SubReg, false);
3356 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
3357 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
3358 assert(Inst.getNumExplicitOperands() == 3);
3359 MachineOperand Op1 = Inst.getOperand(1);
3360 Inst.RemoveOperand(1);
3361 Inst.addOperand(Op1);
3364 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
3365 const MCOperandInfo &OpInfo,
3366 const MachineOperand &MO) const {
3370 unsigned Reg = MO.getReg();
3371 const TargetRegisterClass *RC =
3372 TargetRegisterInfo::isVirtualRegister(Reg) ?
3373 MRI.getRegClass(Reg) :
3374 RI.getPhysRegClass(Reg);
3376 const SIRegisterInfo *TRI =
3377 static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
3378 RC = TRI->getSubRegClass(RC, MO.getSubReg());
3380 // In order to be legal, the common sub-class must be equal to the
3381 // class of the current operand. For example:
3383 // v_mov_b32 s0 ; Operand defined as vsrc_b32
3384 // ; RI.getCommonSubClass(s0,vsrc_b32) = sgpr ; LEGAL
3386 // s_sendmsg 0, s0 ; Operand defined as m0reg
3387 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
3389 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
3392 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
3393 const MCOperandInfo &OpInfo,
3394 const MachineOperand &MO) const {
3396 return isLegalRegOperand(MRI, OpInfo, MO);
3398 // Handle non-register types that are treated like immediates.
3399 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
3403 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
3404 const MachineOperand *MO) const {
3405 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3406 const MCInstrDesc &InstDesc = MI.getDesc();
3407 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
3408 const TargetRegisterClass *DefinedRC =
3409 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
3411 MO = &MI.getOperand(OpIdx);
3413 if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
3415 RegSubRegPair SGPRUsed;
3417 SGPRUsed = RegSubRegPair(MO->getReg(), MO->getSubReg());
3419 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3422 const MachineOperand &Op = MI.getOperand(i);
3424 if ((Op.getReg() != SGPRUsed.Reg || Op.getSubReg() != SGPRUsed.SubReg) &&
3425 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
3428 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
3436 return isLegalRegOperand(MRI, OpInfo, *MO);
3439 // Handle non-register types that are treated like immediates.
3440 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
3443 // This operand expects an immediate.
3447 return isImmOperandLegal(MI, OpIdx, *MO);
3450 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
3451 MachineInstr &MI) const {
3452 unsigned Opc = MI.getOpcode();
3453 const MCInstrDesc &InstrDesc = get(Opc);
3455 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
3456 MachineOperand &Src1 = MI.getOperand(Src1Idx);
3458 // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
3459 // we need to only have one constant bus use.
3461 // Note we do not need to worry about literal constants here. They are
3462 // disabled for the operand type for instructions because they will always
3463 // violate the one constant bus use rule.
3464 bool HasImplicitSGPR = findImplicitSGPRRead(MI) != AMDGPU::NoRegister;
3465 if (HasImplicitSGPR) {
3466 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3467 MachineOperand &Src0 = MI.getOperand(Src0Idx);
3469 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg()))
3470 legalizeOpWithMove(MI, Src0Idx);
3473 // Special case: V_WRITELANE_B32 accepts only immediate or SGPR operands for
3474 // both the value to write (src0) and lane select (src1). Fix up non-SGPR
3475 // src0/src1 with V_READFIRSTLANE.
3476 if (Opc == AMDGPU::V_WRITELANE_B32) {
3477 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3478 MachineOperand &Src0 = MI.getOperand(Src0Idx);
3479 const DebugLoc &DL = MI.getDebugLoc();
3480 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
3481 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3482 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
3484 Src0.ChangeToRegister(Reg, false);
3486 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
3487 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3488 const DebugLoc &DL = MI.getDebugLoc();
3489 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
3491 Src1.ChangeToRegister(Reg, false);
3496 // VOP2 src0 instructions support all operand types, so we don't need to check
3497 // their legality. If src1 is already legal, we don't need to do anything.
3498 if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
3501 // Special case: V_READLANE_B32 accepts only immediate or SGPR operands for
3502 // lane select. Fix up using V_READFIRSTLANE, since we assume that the lane
3503 // select is uniform.
3504 if (Opc == AMDGPU::V_READLANE_B32 && Src1.isReg() &&
3505 RI.isVGPR(MRI, Src1.getReg())) {
3506 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3507 const DebugLoc &DL = MI.getDebugLoc();
3508 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
3510 Src1.ChangeToRegister(Reg, false);
3514 // We do not use commuteInstruction here because it is too aggressive and will
3515 // commute if it is possible. We only want to commute here if it improves
3516 // legality. This can be called a fairly large number of times so don't waste
3517 // compile time pointlessly swapping and checking legality again.
3518 if (HasImplicitSGPR || !MI.isCommutable()) {
3519 legalizeOpWithMove(MI, Src1Idx);
3523 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3524 MachineOperand &Src0 = MI.getOperand(Src0Idx);
3526 // If src0 can be used as src1, commuting will make the operands legal.
3527 // Otherwise we have to give up and insert a move.
3529 // TODO: Other immediate-like operand kinds could be commuted if there was a
3530 // MachineOperand::ChangeTo* for them.
3531 if ((!Src1.isImm() && !Src1.isReg()) ||
3532 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
3533 legalizeOpWithMove(MI, Src1Idx);
3537 int CommutedOpc = commuteOpcode(MI);
3538 if (CommutedOpc == -1) {
3539 legalizeOpWithMove(MI, Src1Idx);
3543 MI.setDesc(get(CommutedOpc));
3545 unsigned Src0Reg = Src0.getReg();
3546 unsigned Src0SubReg = Src0.getSubReg();
3547 bool Src0Kill = Src0.isKill();
3550 Src0.ChangeToImmediate(Src1.getImm());
3551 else if (Src1.isReg()) {
3552 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
3553 Src0.setSubReg(Src1.getSubReg());
3555 llvm_unreachable("Should only have register or immediate operands");
3557 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
3558 Src1.setSubReg(Src0SubReg);
3561 // Legalize VOP3 operands. Because all operand types are supported for any
3562 // operand, and since literal constants are not allowed and should never be
3563 // seen, we only need to worry about inserting copies if we use multiple SGPR
3565 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
3566 MachineInstr &MI) const {
3567 unsigned Opc = MI.getOpcode();
3570 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
3571 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
3572 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
3575 // Find the one SGPR operand we are allowed to use.
3576 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
3578 for (unsigned i = 0; i < 3; ++i) {
3579 int Idx = VOP3Idx[i];
3582 MachineOperand &MO = MI.getOperand(Idx);
3584 // We should never see a VOP3 instruction with an illegal immediate operand.
3588 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
3589 continue; // VGPRs are legal
3591 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
3592 SGPRReg = MO.getReg();
3593 // We can use one SGPR in each VOP3 instruction.
3597 // If we make it this far, then the operand is not legal and we must
3599 legalizeOpWithMove(MI, Idx);
3603 unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
3604 MachineRegisterInfo &MRI) const {
3605 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
3606 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
3607 unsigned DstReg = MRI.createVirtualRegister(SRC);
3608 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
3611 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
3612 get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
3617 SmallVector<unsigned, 8> SRegs;
3618 for (unsigned i = 0; i < SubRegs; ++i) {
3619 unsigned SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3620 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
3621 get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
3622 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
3623 SRegs.push_back(SGPR);
3626 MachineInstrBuilder MIB =
3627 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
3628 get(AMDGPU::REG_SEQUENCE), DstReg);
3629 for (unsigned i = 0; i < SubRegs; ++i) {
3630 MIB.addReg(SRegs[i]);
3631 MIB.addImm(RI.getSubRegFromChannel(i));
3636 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
3637 MachineInstr &MI) const {
3639 // If the pointer is store in VGPRs, then we need to move them to
3640 // SGPRs using v_readfirstlane. This is safe because we only select
3641 // loads with uniform pointers to SMRD instruction so we know the
3642 // pointer value is uniform.
3643 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase);
3644 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
3645 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI);
3646 SBase->setReg(SGPR);
3648 MachineOperand *SOff = getNamedOperand(MI, AMDGPU::OpName::soff);
3649 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
3650 unsigned SGPR = readlaneVGPRToSGPR(SOff->getReg(), MI, MRI);
3655 void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
3656 MachineBasicBlock::iterator I,
3657 const TargetRegisterClass *DstRC,
3659 MachineRegisterInfo &MRI,
3660 const DebugLoc &DL) const {
3661 unsigned OpReg = Op.getReg();
3662 unsigned OpSubReg = Op.getSubReg();
3664 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg(
3665 RI.getRegClassForReg(MRI, OpReg), OpSubReg);
3667 // Check if operand is already the correct register class.
3671 unsigned DstReg = MRI.createVirtualRegister(DstRC);
3672 MachineInstr *Copy =
3673 BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
3678 MachineInstr *Def = MRI.getVRegDef(OpReg);
3682 // Try to eliminate the copy if it is copying an immediate value.
3683 if (Def->isMoveImmediate())
3684 FoldImmediate(*Copy, *Def, OpReg, &MRI);
3687 // Emit the actual waterfall loop, executing the wrapped instruction for each
3688 // unique value of \p Rsrc across all lanes. In the best case we execute 1
3689 // iteration, in the worst case we execute 64 (once per lane).
3691 emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,
3692 MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,
3693 const DebugLoc &DL, MachineOperand &Rsrc) {
3694 MachineBasicBlock::iterator I = LoopBB.begin();
3696 unsigned VRsrc = Rsrc.getReg();
3697 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
3699 unsigned SaveExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3700 unsigned CondReg0 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3701 unsigned CondReg1 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3702 unsigned AndCond = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3703 unsigned SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3704 unsigned SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3705 unsigned SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3706 unsigned SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3707 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
3709 // Beginning of the loop, read the next Rsrc variant.
3710 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
3711 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub0);
3712 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
3713 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub1);
3714 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
3715 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub2);
3716 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)
3717 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub3);
3719 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
3721 .addImm(AMDGPU::sub0)
3723 .addImm(AMDGPU::sub1)
3725 .addImm(AMDGPU::sub2)
3727 .addImm(AMDGPU::sub3);
3729 // Update Rsrc operand to use the SGPR Rsrc.
3731 Rsrc.setIsKill(true);
3733 // Identify all lanes with identical Rsrc operands in their VGPRs.
3734 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0)
3735 .addReg(SRsrc, 0, AMDGPU::sub0_sub1)
3736 .addReg(VRsrc, 0, AMDGPU::sub0_sub1);
3737 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1)
3738 .addReg(SRsrc, 0, AMDGPU::sub2_sub3)
3739 .addReg(VRsrc, 0, AMDGPU::sub2_sub3);
3740 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_B64), AndCond)
3744 MRI.setSimpleHint(SaveExec, AndCond);
3746 // Update EXEC to matching lanes, saving original to SaveExec.
3747 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_SAVEEXEC_B64), SaveExec)
3748 .addReg(AndCond, RegState::Kill);
3750 // The original instruction is here; we insert the terminators after it.
3753 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3754 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_XOR_B64_term), AMDGPU::EXEC)
3755 .addReg(AMDGPU::EXEC)
3757 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
3760 // Build a waterfall loop around \p MI, replacing the VGPR \p Rsrc register
3761 // with SGPRs by iterating over all unique values across all lanes.
3762 static void loadSRsrcFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,
3763 MachineOperand &Rsrc, MachineDominatorTree *MDT) {
3764 MachineBasicBlock &MBB = *MI.getParent();
3765 MachineFunction &MF = *MBB.getParent();
3766 MachineRegisterInfo &MRI = MF.getRegInfo();
3767 MachineBasicBlock::iterator I(&MI);
3768 const DebugLoc &DL = MI.getDebugLoc();
3770 unsigned SaveExec = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
3772 // Save the EXEC mask
3773 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_MOV_B64), SaveExec)
3774 .addReg(AMDGPU::EXEC);
3776 // Killed uses in the instruction we are waterfalling around will be
3777 // incorrect due to the added control-flow.
3778 for (auto &MO : MI.uses()) {
3779 if (MO.isReg() && MO.isUse()) {
3780 MRI.clearKillFlags(MO.getReg());
3784 // To insert the loop we need to split the block. Move everything after this
3785 // point to a new block, and insert a new empty block between the two.
3786 MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock();
3787 MachineBasicBlock *RemainderBB = MF.CreateMachineBasicBlock();
3788 MachineFunction::iterator MBBI(MBB);
3791 MF.insert(MBBI, LoopBB);
3792 MF.insert(MBBI, RemainderBB);
3794 LoopBB->addSuccessor(LoopBB);
3795 LoopBB->addSuccessor(RemainderBB);
3797 // Move MI to the LoopBB, and the remainder of the block to RemainderBB.
3798 MachineBasicBlock::iterator J = I++;
3799 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3800 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3801 LoopBB->splice(LoopBB->begin(), &MBB, J);
3803 MBB.addSuccessor(LoopBB);
3805 // Update dominators. We know that MBB immediately dominates LoopBB, that
3806 // LoopBB immediately dominates RemainderBB, and that RemainderBB immediately
3807 // dominates all of the successors transferred to it from MBB that MBB used
3810 MDT->addNewBlock(LoopBB, &MBB);
3811 MDT->addNewBlock(RemainderBB, LoopBB);
3812 for (auto &Succ : RemainderBB->successors()) {
3813 if (MDT->dominates(&MBB, Succ)) {
3814 MDT->changeImmediateDominator(Succ, RemainderBB);
3819 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc);
3821 // Restore the EXEC mask
3822 MachineBasicBlock::iterator First = RemainderBB->begin();
3823 BuildMI(*RemainderBB, First, DL, TII.get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
3827 // Extract pointer from Rsrc and return a zero-value Rsrc replacement.
3828 static std::tuple<unsigned, unsigned>
3829 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
3830 MachineBasicBlock &MBB = *MI.getParent();
3831 MachineFunction &MF = *MBB.getParent();
3832 MachineRegisterInfo &MRI = MF.getRegInfo();
3834 // Extract the ptr from the resource descriptor.
3836 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass,
3837 AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
3839 // Create an empty resource descriptor
3840 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
3841 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3842 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3843 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
3844 uint64_t RsrcDataFormat = TII.getDefaultRsrcDataFormat();
3847 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64)
3850 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
3851 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo)
3852 .addImm(RsrcDataFormat & 0xFFFFFFFF);
3854 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
3855 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi)
3856 .addImm(RsrcDataFormat >> 32);
3858 // NewSRsrc = {Zero64, SRsrcFormat}
3859 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc)
3861 .addImm(AMDGPU::sub0_sub1)
3862 .addReg(SRsrcFormatLo)
3863 .addImm(AMDGPU::sub2)
3864 .addReg(SRsrcFormatHi)
3865 .addImm(AMDGPU::sub3);
3867 return std::make_tuple(RsrcPtr, NewSRsrc);
3870 void SIInstrInfo::legalizeOperands(MachineInstr &MI,
3871 MachineDominatorTree *MDT) const {
3872 MachineFunction &MF = *MI.getParent()->getParent();
3873 MachineRegisterInfo &MRI = MF.getRegInfo();
3876 if (isVOP2(MI) || isVOPC(MI)) {
3877 legalizeOperandsVOP2(MRI, MI);
3883 legalizeOperandsVOP3(MRI, MI);
3889 legalizeOperandsSMRD(MRI, MI);
3893 // Legalize REG_SEQUENCE and PHI
3894 // The register class of the operands much be the same type as the register
3895 // class of the output.
3896 if (MI.getOpcode() == AMDGPU::PHI) {
3897 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
3898 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
3899 if (!MI.getOperand(i).isReg() ||
3900 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
3902 const TargetRegisterClass *OpRC =
3903 MRI.getRegClass(MI.getOperand(i).getReg());
3904 if (RI.hasVGPRs(OpRC)) {
3911 // If any of the operands are VGPR registers, then they all most be
3912 // otherwise we will create illegal VGPR->SGPR copies when legalizing
3914 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) {
3917 VRC = RI.getEquivalentVGPRClass(SRC);
3924 // Update all the operands so they have the same type.
3925 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3926 MachineOperand &Op = MI.getOperand(I);
3927 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
3930 // MI is a PHI instruction.
3931 MachineBasicBlock *InsertBB = MI.getOperand(I + 1).getMBB();
3932 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
3934 // Avoid creating no-op copies with the same src and dst reg class. These
3935 // confuse some of the machine passes.
3936 legalizeGenericOperand(*InsertBB, Insert, RC, Op, MRI, MI.getDebugLoc());
3940 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
3941 // VGPR dest type and SGPR sources, insert copies so all operands are
3942 // VGPRs. This seems to help operand folding / the register coalescer.
3943 if (MI.getOpcode() == AMDGPU::REG_SEQUENCE) {
3944 MachineBasicBlock *MBB = MI.getParent();
3945 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0);
3946 if (RI.hasVGPRs(DstRC)) {
3947 // Update all the operands so they are VGPR register classes. These may
3948 // not be the same register class because REG_SEQUENCE supports mixing
3949 // subregister index types e.g. sub0_sub1 + sub2 + sub3
3950 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3951 MachineOperand &Op = MI.getOperand(I);
3952 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
3955 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
3956 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
3960 legalizeGenericOperand(*MBB, MI, VRC, Op, MRI, MI.getDebugLoc());
3968 // Legalize INSERT_SUBREG
3969 // src0 must have the same register class as dst
3970 if (MI.getOpcode() == AMDGPU::INSERT_SUBREG) {
3971 unsigned Dst = MI.getOperand(0).getReg();
3972 unsigned Src0 = MI.getOperand(1).getReg();
3973 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
3974 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
3975 if (DstRC != Src0RC) {
3976 MachineBasicBlock *MBB = MI.getParent();
3977 MachineOperand &Op = MI.getOperand(1);
3978 legalizeGenericOperand(*MBB, MI, DstRC, Op, MRI, MI.getDebugLoc());
3983 // Legalize SI_INIT_M0
3984 if (MI.getOpcode() == AMDGPU::SI_INIT_M0) {
3985 MachineOperand &Src = MI.getOperand(0);
3986 if (Src.isReg() && RI.hasVGPRs(MRI.getRegClass(Src.getReg())))
3987 Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI));
3991 // Legalize MIMG and MUBUF/MTBUF for shaders.
3993 // Shaders only generate MUBUF/MTBUF instructions via intrinsics or via
3994 // scratch memory access. In both cases, the legalization never involves
3995 // conversion to the addr64 form.
3997 (AMDGPU::isShader(MF.getFunction().getCallingConv()) &&
3998 (isMUBUF(MI) || isMTBUF(MI)))) {
3999 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
4000 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4001 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
4002 SRsrc->setReg(SGPR);
4005 MachineOperand *SSamp = getNamedOperand(MI, AMDGPU::OpName::ssamp);
4006 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
4007 unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI);
4008 SSamp->setReg(SGPR);
4013 // Legalize MUBUF* instructions.
4015 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
4016 if (RsrcIdx != -1) {
4017 // We have an MUBUF instruction
4018 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
4019 unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
4020 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
4021 RI.getRegClass(RsrcRC))) {
4022 // The operands are legal.
4023 // FIXME: We may need to legalize operands besided srsrc.
4027 // Legalize a VGPR Rsrc.
4029 // If the instruction is _ADDR64, we can avoid a waterfall by extracting
4030 // the base pointer from the VGPR Rsrc, adding it to the VAddr, then using
4031 // a zero-value SRsrc.
4033 // If the instruction is _OFFSET (both idxen and offen disabled), and we
4034 // support ADDR64 instructions, we can convert to ADDR64 and do the same as
4037 // Otherwise we are on non-ADDR64 hardware, and/or we have
4038 // idxen/offen/bothen and we fall back to a waterfall loop.
4040 MachineBasicBlock &MBB = *MI.getParent();
4042 MachineOperand *VAddr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
4043 if (VAddr && AMDGPU::getIfAddr64Inst(MI.getOpcode()) != -1) {
4044 // This is already an ADDR64 instruction so we need to add the pointer
4045 // extracted from the resource descriptor to the current value of VAddr.
4046 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4047 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4048 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4050 unsigned RsrcPtr, NewSRsrc;
4051 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
4053 // NewVaddrLo = RsrcPtr:sub0 + VAddr:sub0
4054 DebugLoc DL = MI.getDebugLoc();
4055 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
4056 .addReg(RsrcPtr, 0, AMDGPU::sub0)
4057 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
4059 // NewVaddrHi = RsrcPtr:sub1 + VAddr:sub1
4060 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
4061 .addReg(RsrcPtr, 0, AMDGPU::sub1)
4062 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
4064 // NewVaddr = {NewVaddrHi, NewVaddrLo}
4065 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
4067 .addImm(AMDGPU::sub0)
4069 .addImm(AMDGPU::sub1);
4071 VAddr->setReg(NewVAddr);
4072 Rsrc->setReg(NewSRsrc);
4073 } else if (!VAddr && ST.hasAddr64()) {
4074 // This instructions is the _OFFSET variant, so we need to convert it to
4076 assert(MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration()
4077 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
4078 "FIXME: Need to emit flat atomics here");
4080 unsigned RsrcPtr, NewSRsrc;
4081 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
4083 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4084 MachineOperand *VData = getNamedOperand(MI, AMDGPU::OpName::vdata);
4085 MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
4086 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset);
4087 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI.getOpcode());
4089 // Atomics rith return have have an additional tied operand and are
4090 // missing some of the special bits.
4091 MachineOperand *VDataIn = getNamedOperand(MI, AMDGPU::OpName::vdata_in);
4092 MachineInstr *Addr64;
4095 // Regular buffer load / store.
4096 MachineInstrBuilder MIB =
4097 BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4104 // Atomics do not have this operand.
4105 if (const MachineOperand *GLC =
4106 getNamedOperand(MI, AMDGPU::OpName::glc)) {
4107 MIB.addImm(GLC->getImm());
4110 MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc));
4112 if (const MachineOperand *TFE =
4113 getNamedOperand(MI, AMDGPU::OpName::tfe)) {
4114 MIB.addImm(TFE->getImm());
4117 MIB.cloneMemRefs(MI);
4120 // Atomics with return.
4121 Addr64 = BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4128 .addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc))
4132 MI.removeFromParent();
4134 // NewVaddr = {NewVaddrHi, NewVaddrLo}
4135 BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
4137 .addReg(RsrcPtr, 0, AMDGPU::sub0)
4138 .addImm(AMDGPU::sub0)
4139 .addReg(RsrcPtr, 0, AMDGPU::sub1)
4140 .addImm(AMDGPU::sub1);
4142 // This is another variant; legalize Rsrc with waterfall loop from VGPRs
4144 loadSRsrcFromVGPR(*this, MI, *Rsrc, MDT);
4149 void SIInstrInfo::moveToVALU(MachineInstr &TopInst,
4150 MachineDominatorTree *MDT) const {
4151 SetVectorType Worklist;
4152 Worklist.insert(&TopInst);
4154 while (!Worklist.empty()) {
4155 MachineInstr &Inst = *Worklist.pop_back_val();
4156 MachineBasicBlock *MBB = Inst.getParent();
4157 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
4159 unsigned Opcode = Inst.getOpcode();
4160 unsigned NewOpcode = getVALUOp(Inst);
4162 // Handle some special cases
4166 case AMDGPU::S_ADD_U64_PSEUDO:
4167 case AMDGPU::S_SUB_U64_PSEUDO:
4168 splitScalar64BitAddSub(Worklist, Inst, MDT);
4169 Inst.eraseFromParent();
4171 case AMDGPU::S_ADD_I32:
4172 case AMDGPU::S_SUB_I32:
4173 // FIXME: The u32 versions currently selected use the carry.
4174 if (moveScalarAddSub(Worklist, Inst, MDT))
4179 case AMDGPU::S_AND_B64:
4180 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32, MDT);
4181 Inst.eraseFromParent();
4184 case AMDGPU::S_OR_B64:
4185 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32, MDT);
4186 Inst.eraseFromParent();
4189 case AMDGPU::S_XOR_B64:
4190 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32, MDT);
4191 Inst.eraseFromParent();
4194 case AMDGPU::S_NAND_B64:
4195 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NAND_B32, MDT);
4196 Inst.eraseFromParent();
4199 case AMDGPU::S_NOR_B64:
4200 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NOR_B32, MDT);
4201 Inst.eraseFromParent();
4204 case AMDGPU::S_XNOR_B64:
4205 if (ST.hasDLInsts())
4206 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XNOR_B32, MDT);
4208 splitScalar64BitXnor(Worklist, Inst, MDT);
4209 Inst.eraseFromParent();
4212 case AMDGPU::S_ANDN2_B64:
4213 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ANDN2_B32, MDT);
4214 Inst.eraseFromParent();
4217 case AMDGPU::S_ORN2_B64:
4218 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ORN2_B32, MDT);
4219 Inst.eraseFromParent();
4222 case AMDGPU::S_NOT_B64:
4223 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
4224 Inst.eraseFromParent();
4227 case AMDGPU::S_BCNT1_I32_B64:
4228 splitScalar64BitBCNT(Worklist, Inst);
4229 Inst.eraseFromParent();
4232 case AMDGPU::S_BFE_I64:
4233 splitScalar64BitBFE(Worklist, Inst);
4234 Inst.eraseFromParent();
4237 case AMDGPU::S_LSHL_B32:
4238 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4239 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
4243 case AMDGPU::S_ASHR_I32:
4244 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4245 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
4249 case AMDGPU::S_LSHR_B32:
4250 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4251 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
4255 case AMDGPU::S_LSHL_B64:
4256 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4257 NewOpcode = AMDGPU::V_LSHLREV_B64;
4261 case AMDGPU::S_ASHR_I64:
4262 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4263 NewOpcode = AMDGPU::V_ASHRREV_I64;
4267 case AMDGPU::S_LSHR_B64:
4268 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
4269 NewOpcode = AMDGPU::V_LSHRREV_B64;
4274 case AMDGPU::S_ABS_I32:
4275 lowerScalarAbs(Worklist, Inst);
4276 Inst.eraseFromParent();
4279 case AMDGPU::S_CBRANCH_SCC0:
4280 case AMDGPU::S_CBRANCH_SCC1:
4281 // Clear unused bits of vcc
4282 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64),
4284 .addReg(AMDGPU::EXEC)
4285 .addReg(AMDGPU::VCC);
4288 case AMDGPU::S_BFE_U64:
4289 case AMDGPU::S_BFM_B64:
4290 llvm_unreachable("Moving this op to VALU not implemented");
4292 case AMDGPU::S_PACK_LL_B32_B16:
4293 case AMDGPU::S_PACK_LH_B32_B16:
4294 case AMDGPU::S_PACK_HH_B32_B16:
4295 movePackToVALU(Worklist, MRI, Inst);
4296 Inst.eraseFromParent();
4299 case AMDGPU::S_XNOR_B32:
4300 lowerScalarXnor(Worklist, Inst);
4301 Inst.eraseFromParent();
4304 case AMDGPU::S_NAND_B32:
4305 splitScalarNotBinop(Worklist, Inst, AMDGPU::S_AND_B32);
4306 Inst.eraseFromParent();
4309 case AMDGPU::S_NOR_B32:
4310 splitScalarNotBinop(Worklist, Inst, AMDGPU::S_OR_B32);
4311 Inst.eraseFromParent();
4314 case AMDGPU::S_ANDN2_B32:
4315 splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_AND_B32);
4316 Inst.eraseFromParent();
4319 case AMDGPU::S_ORN2_B32:
4320 splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_OR_B32);
4321 Inst.eraseFromParent();
4325 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
4326 // We cannot move this instruction to the VALU, so we should try to
4327 // legalize its operands instead.
4328 legalizeOperands(Inst, MDT);
4332 // Use the new VALU Opcode.
4333 const MCInstrDesc &NewDesc = get(NewOpcode);
4334 Inst.setDesc(NewDesc);
4336 // Remove any references to SCC. Vector instructions can't read from it, and
4337 // We're just about to add the implicit use / defs of VCC, and we don't want
4339 for (unsigned i = Inst.getNumOperands() - 1; i > 0; --i) {
4340 MachineOperand &Op = Inst.getOperand(i);
4341 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
4342 Inst.RemoveOperand(i);
4343 addSCCDefUsersToVALUWorklist(Inst, Worklist);
4347 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
4348 // We are converting these to a BFE, so we need to add the missing
4349 // operands for the size and offset.
4350 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
4351 Inst.addOperand(MachineOperand::CreateImm(0));
4352 Inst.addOperand(MachineOperand::CreateImm(Size));
4354 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
4355 // The VALU version adds the second operand to the result, so insert an
4357 Inst.addOperand(MachineOperand::CreateImm(0));
4360 Inst.addImplicitDefUseOperands(*Inst.getParent()->getParent());
4362 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
4363 const MachineOperand &OffsetWidthOp = Inst.getOperand(2);
4364 // If we need to move this to VGPRs, we need to unpack the second operand
4365 // back into the 2 separate ones for bit offset and width.
4366 assert(OffsetWidthOp.isImm() &&
4367 "Scalar BFE is only implemented for constant width and offset");
4368 uint32_t Imm = OffsetWidthOp.getImm();
4370 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
4371 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
4372 Inst.RemoveOperand(2); // Remove old immediate.
4373 Inst.addOperand(MachineOperand::CreateImm(Offset));
4374 Inst.addOperand(MachineOperand::CreateImm(BitWidth));
4377 bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
4378 unsigned NewDstReg = AMDGPU::NoRegister;
4380 unsigned DstReg = Inst.getOperand(0).getReg();
4381 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4384 // Update the destination register class.
4385 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst);
4389 if (Inst.isCopy() &&
4390 TargetRegisterInfo::isVirtualRegister(Inst.getOperand(1).getReg()) &&
4391 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) {
4392 // Instead of creating a copy where src and dst are the same register
4393 // class, we just replace all uses of dst with src. These kinds of
4394 // copies interfere with the heuristics MachineSink uses to decide
4395 // whether or not to split a critical edge. Since the pass assumes
4396 // that copies will end up as machine instructions and not be
4398 addUsersToMoveToVALUWorklist(DstReg, MRI, Worklist);
4399 MRI.replaceRegWith(DstReg, Inst.getOperand(1).getReg());
4400 MRI.clearKillFlags(Inst.getOperand(1).getReg());
4401 Inst.getOperand(0).setReg(DstReg);
4403 // Make sure we don't leave around a dead VGPR->SGPR copy. Normally
4404 // these are deleted later, but at -O0 it would leave a suspicious
4405 // looking illegal copy of an undef register.
4406 for (unsigned I = Inst.getNumOperands() - 1; I != 0; --I)
4407 Inst.RemoveOperand(I);
4408 Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
4412 NewDstReg = MRI.createVirtualRegister(NewDstRC);
4413 MRI.replaceRegWith(DstReg, NewDstReg);
4416 // Legalize the operands
4417 legalizeOperands(Inst, MDT);
4420 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
4424 // Add/sub require special handling to deal with carry outs.
4425 bool SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
4426 MachineDominatorTree *MDT) const {
4427 if (ST.hasAddNoCarry()) {
4428 // Assume there is no user of scc since we don't select this in that case.
4429 // Since scc isn't used, it doesn't really matter if the i32 or u32 variant
4432 MachineBasicBlock &MBB = *Inst.getParent();
4433 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4435 unsigned OldDstReg = Inst.getOperand(0).getReg();
4436 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4438 unsigned Opc = Inst.getOpcode();
4439 assert(Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32);
4441 unsigned NewOpc = Opc == AMDGPU::S_ADD_I32 ?
4442 AMDGPU::V_ADD_U32_e64 : AMDGPU::V_SUB_U32_e64;
4444 assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
4445 Inst.RemoveOperand(3);
4447 Inst.setDesc(get(NewOpc));
4448 Inst.addImplicitDefUseOperands(*MBB.getParent());
4449 MRI.replaceRegWith(OldDstReg, ResultReg);
4450 legalizeOperands(Inst, MDT);
4452 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
4459 void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,
4460 MachineInstr &Inst) const {
4461 MachineBasicBlock &MBB = *Inst.getParent();
4462 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4463 MachineBasicBlock::iterator MII = Inst;
4464 DebugLoc DL = Inst.getDebugLoc();
4466 MachineOperand &Dest = Inst.getOperand(0);
4467 MachineOperand &Src = Inst.getOperand(1);
4468 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4469 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4471 unsigned SubOp = ST.hasAddNoCarry() ?
4472 AMDGPU::V_SUB_U32_e32 : AMDGPU::V_SUB_I32_e32;
4474 BuildMI(MBB, MII, DL, get(SubOp), TmpReg)
4476 .addReg(Src.getReg());
4478 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
4479 .addReg(Src.getReg())
4482 MRI.replaceRegWith(Dest.getReg(), ResultReg);
4483 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
4486 void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,
4487 MachineInstr &Inst) const {
4488 MachineBasicBlock &MBB = *Inst.getParent();
4489 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4490 MachineBasicBlock::iterator MII = Inst;
4491 const DebugLoc &DL = Inst.getDebugLoc();
4493 MachineOperand &Dest = Inst.getOperand(0);
4494 MachineOperand &Src0 = Inst.getOperand(1);
4495 MachineOperand &Src1 = Inst.getOperand(2);
4497 if (ST.hasDLInsts()) {
4498 unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4499 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
4500 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src1, MRI, DL);
4502 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest)
4506 MRI.replaceRegWith(Dest.getReg(), NewDest);
4507 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4509 // Using the identity !(x ^ y) == (!x ^ y) == (x ^ !y), we can
4510 // invert either source and then perform the XOR. If either source is a
4511 // scalar register, then we can leave the inversion on the scalar unit to
4512 // acheive a better distrubution of scalar and vector instructions.
4513 bool Src0IsSGPR = Src0.isReg() &&
4514 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
4515 bool Src1IsSGPR = Src1.isReg() &&
4516 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
4517 MachineInstr *Not = nullptr;
4518 MachineInstr *Xor = nullptr;
4519 unsigned Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4520 unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4522 // Build a pair of scalar instructions and add them to the work list.
4523 // The next iteration over the work list will lower these to the vector
4524 // unit as necessary.
4526 Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp)
4528 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
4531 } else if (Src1IsSGPR) {
4532 Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp)
4534 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
4538 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
4541 Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
4543 Worklist.insert(Not);
4546 MRI.replaceRegWith(Dest.getReg(), NewDest);
4548 Worklist.insert(Xor);
4550 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4554 void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,
4556 unsigned Opcode) const {
4557 MachineBasicBlock &MBB = *Inst.getParent();
4558 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4559 MachineBasicBlock::iterator MII = Inst;
4560 const DebugLoc &DL = Inst.getDebugLoc();
4562 MachineOperand &Dest = Inst.getOperand(0);
4563 MachineOperand &Src0 = Inst.getOperand(1);
4564 MachineOperand &Src1 = Inst.getOperand(2);
4566 unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4567 unsigned Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4569 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)
4573 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
4576 Worklist.insert(&Op);
4577 Worklist.insert(&Not);
4579 MRI.replaceRegWith(Dest.getReg(), NewDest);
4580 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4583 void SIInstrInfo::splitScalarBinOpN2(SetVectorType& Worklist,
4585 unsigned Opcode) const {
4586 MachineBasicBlock &MBB = *Inst.getParent();
4587 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4588 MachineBasicBlock::iterator MII = Inst;
4589 const DebugLoc &DL = Inst.getDebugLoc();
4591 MachineOperand &Dest = Inst.getOperand(0);
4592 MachineOperand &Src0 = Inst.getOperand(1);
4593 MachineOperand &Src1 = Inst.getOperand(2);
4595 unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4596 unsigned Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4598 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm)
4601 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), NewDest)
4605 Worklist.insert(&Not);
4606 Worklist.insert(&Op);
4608 MRI.replaceRegWith(Dest.getReg(), NewDest);
4609 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
4612 void SIInstrInfo::splitScalar64BitUnaryOp(
4613 SetVectorType &Worklist, MachineInstr &Inst,
4614 unsigned Opcode) const {
4615 MachineBasicBlock &MBB = *Inst.getParent();
4616 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4618 MachineOperand &Dest = Inst.getOperand(0);
4619 MachineOperand &Src0 = Inst.getOperand(1);
4620 DebugLoc DL = Inst.getDebugLoc();
4622 MachineBasicBlock::iterator MII = Inst;
4624 const MCInstrDesc &InstDesc = get(Opcode);
4625 const TargetRegisterClass *Src0RC = Src0.isReg() ?
4626 MRI.getRegClass(Src0.getReg()) :
4627 &AMDGPU::SGPR_32RegClass;
4629 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
4631 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4632 AMDGPU::sub0, Src0SubRC);
4634 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
4635 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
4636 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
4638 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
4639 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
4641 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4642 AMDGPU::sub1, Src0SubRC);
4644 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
4645 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
4647 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
4648 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
4650 .addImm(AMDGPU::sub0)
4652 .addImm(AMDGPU::sub1);
4654 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
4656 Worklist.insert(&LoHalf);
4657 Worklist.insert(&HiHalf);
4659 // We don't need to legalizeOperands here because for a single operand, src0
4660 // will support any kind of input.
4662 // Move all users of this moved value.
4663 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
4666 void SIInstrInfo::splitScalar64BitAddSub(SetVectorType &Worklist,
4668 MachineDominatorTree *MDT) const {
4669 bool IsAdd = (Inst.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
4671 MachineBasicBlock &MBB = *Inst.getParent();
4672 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4674 unsigned FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4675 unsigned DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4676 unsigned DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4678 unsigned CarryReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
4679 unsigned DeadCarryReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
4681 MachineOperand &Dest = Inst.getOperand(0);
4682 MachineOperand &Src0 = Inst.getOperand(1);
4683 MachineOperand &Src1 = Inst.getOperand(2);
4684 const DebugLoc &DL = Inst.getDebugLoc();
4685 MachineBasicBlock::iterator MII = Inst;
4687 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
4688 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
4689 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
4690 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
4692 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4693 AMDGPU::sub0, Src0SubRC);
4694 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
4695 AMDGPU::sub0, Src1SubRC);
4698 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4699 AMDGPU::sub1, Src0SubRC);
4700 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
4701 AMDGPU::sub1, Src1SubRC);
4703 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
4704 MachineInstr *LoHalf =
4705 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
4706 .addReg(CarryReg, RegState::Define)
4710 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
4711 MachineInstr *HiHalf =
4712 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
4713 .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
4716 .addReg(CarryReg, RegState::Kill);
4718 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
4720 .addImm(AMDGPU::sub0)
4722 .addImm(AMDGPU::sub1);
4724 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
4726 // Try to legalize the operands in case we need to swap the order to keep it
4728 legalizeOperands(*LoHalf, MDT);
4729 legalizeOperands(*HiHalf, MDT);
4731 // Move all users of this moved vlaue.
4732 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
4735 void SIInstrInfo::splitScalar64BitBinaryOp(SetVectorType &Worklist,
4736 MachineInstr &Inst, unsigned Opcode,
4737 MachineDominatorTree *MDT) const {
4738 MachineBasicBlock &MBB = *Inst.getParent();
4739 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4741 MachineOperand &Dest = Inst.getOperand(0);
4742 MachineOperand &Src0 = Inst.getOperand(1);
4743 MachineOperand &Src1 = Inst.getOperand(2);
4744 DebugLoc DL = Inst.getDebugLoc();
4746 MachineBasicBlock::iterator MII = Inst;
4748 const MCInstrDesc &InstDesc = get(Opcode);
4749 const TargetRegisterClass *Src0RC = Src0.isReg() ?
4750 MRI.getRegClass(Src0.getReg()) :
4751 &AMDGPU::SGPR_32RegClass;
4753 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
4754 const TargetRegisterClass *Src1RC = Src1.isReg() ?
4755 MRI.getRegClass(Src1.getReg()) :
4756 &AMDGPU::SGPR_32RegClass;
4758 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
4760 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4761 AMDGPU::sub0, Src0SubRC);
4762 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
4763 AMDGPU::sub0, Src1SubRC);
4764 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
4765 AMDGPU::sub1, Src0SubRC);
4766 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
4767 AMDGPU::sub1, Src1SubRC);
4769 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
4770 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
4771 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
4773 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
4774 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
4778 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
4779 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
4783 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
4784 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
4786 .addImm(AMDGPU::sub0)
4788 .addImm(AMDGPU::sub1);
4790 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
4792 Worklist.insert(&LoHalf);
4793 Worklist.insert(&HiHalf);
4795 // Move all users of this moved vlaue.
4796 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
4799 void SIInstrInfo::splitScalar64BitXnor(SetVectorType &Worklist,
4801 MachineDominatorTree *MDT) const {
4802 MachineBasicBlock &MBB = *Inst.getParent();
4803 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4805 MachineOperand &Dest = Inst.getOperand(0);
4806 MachineOperand &Src0 = Inst.getOperand(1);
4807 MachineOperand &Src1 = Inst.getOperand(2);
4808 const DebugLoc &DL = Inst.getDebugLoc();
4810 MachineBasicBlock::iterator MII = Inst;
4812 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
4814 unsigned Interm = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
4816 MachineOperand* Op0;
4817 MachineOperand* Op1;
4819 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
4827 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm)
4830 unsigned NewDest = MRI.createVirtualRegister(DestRC);
4832 MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest)
4836 MRI.replaceRegWith(Dest.getReg(), NewDest);
4838 Worklist.insert(&Xor);
4841 void SIInstrInfo::splitScalar64BitBCNT(
4842 SetVectorType &Worklist, MachineInstr &Inst) const {
4843 MachineBasicBlock &MBB = *Inst.getParent();
4844 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4846 MachineBasicBlock::iterator MII = Inst;
4847 const DebugLoc &DL = Inst.getDebugLoc();
4849 MachineOperand &Dest = Inst.getOperand(0);
4850 MachineOperand &Src = Inst.getOperand(1);
4852 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
4853 const TargetRegisterClass *SrcRC = Src.isReg() ?
4854 MRI.getRegClass(Src.getReg()) :
4855 &AMDGPU::SGPR_32RegClass;
4857 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4858 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4860 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
4862 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
4863 AMDGPU::sub0, SrcSubRC);
4864 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
4865 AMDGPU::sub1, SrcSubRC);
4867 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
4869 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
4871 MRI.replaceRegWith(Dest.getReg(), ResultReg);
4873 // We don't need to legalize operands here. src0 for etiher instruction can be
4874 // an SGPR, and the second input is unused or determined here.
4875 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
4878 void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,
4879 MachineInstr &Inst) const {
4880 MachineBasicBlock &MBB = *Inst.getParent();
4881 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4882 MachineBasicBlock::iterator MII = Inst;
4883 const DebugLoc &DL = Inst.getDebugLoc();
4885 MachineOperand &Dest = Inst.getOperand(0);
4886 uint32_t Imm = Inst.getOperand(2).getImm();
4887 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
4888 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
4892 // Only sext_inreg cases handled.
4893 assert(Inst.getOpcode() == AMDGPU::S_BFE_I64 && BitWidth <= 32 &&
4894 Offset == 0 && "Not implemented");
4896 if (BitWidth < 32) {
4897 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4898 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4899 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4901 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
4902 .addReg(Inst.getOperand(1).getReg(), 0, AMDGPU::sub0)
4906 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
4910 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
4912 .addImm(AMDGPU::sub0)
4914 .addImm(AMDGPU::sub1);
4916 MRI.replaceRegWith(Dest.getReg(), ResultReg);
4917 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
4921 MachineOperand &Src = Inst.getOperand(1);
4922 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4923 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4925 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
4927 .addReg(Src.getReg(), 0, AMDGPU::sub0);
4929 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
4930 .addReg(Src.getReg(), 0, AMDGPU::sub0)
4931 .addImm(AMDGPU::sub0)
4933 .addImm(AMDGPU::sub1);
4935 MRI.replaceRegWith(Dest.getReg(), ResultReg);
4936 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
4939 void SIInstrInfo::addUsersToMoveToVALUWorklist(
4941 MachineRegisterInfo &MRI,
4942 SetVectorType &Worklist) const {
4943 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
4944 E = MRI.use_end(); I != E;) {
4945 MachineInstr &UseMI = *I->getParent();
4946 if (!canReadVGPR(UseMI, I.getOperandNo())) {
4947 Worklist.insert(&UseMI);
4951 } while (I != E && I->getParent() == &UseMI);
4958 void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,
4959 MachineRegisterInfo &MRI,
4960 MachineInstr &Inst) const {
4961 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4962 MachineBasicBlock *MBB = Inst.getParent();
4963 MachineOperand &Src0 = Inst.getOperand(1);
4964 MachineOperand &Src1 = Inst.getOperand(2);
4965 const DebugLoc &DL = Inst.getDebugLoc();
4967 switch (Inst.getOpcode()) {
4968 case AMDGPU::S_PACK_LL_B32_B16: {
4969 unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4970 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4972 // FIXME: Can do a lot better if we know the high bits of src0 or src1 are
4974 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
4977 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_B32_e64), TmpReg)
4978 .addReg(ImmReg, RegState::Kill)
4981 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg)
4984 .addReg(TmpReg, RegState::Kill);
4987 case AMDGPU::S_PACK_LH_B32_B16: {
4988 unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4989 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
4991 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg)
4992 .addReg(ImmReg, RegState::Kill)
4997 case AMDGPU::S_PACK_HH_B32_B16: {
4998 unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4999 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5000 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
5003 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5004 .addImm(0xffff0000);
5005 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
5007 .addReg(ImmReg, RegState::Kill)
5008 .addReg(TmpReg, RegState::Kill);
5012 llvm_unreachable("unhandled s_pack_* instruction");
5015 MachineOperand &Dest = Inst.getOperand(0);
5016 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5017 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5020 void SIInstrInfo::addSCCDefUsersToVALUWorklist(
5021 MachineInstr &SCCDefInst, SetVectorType &Worklist) const {
5022 // This assumes that all the users of SCC are in the same block
5024 for (MachineInstr &MI :
5025 make_range(MachineBasicBlock::iterator(SCCDefInst),
5026 SCCDefInst.getParent()->end())) {
5027 // Exit if we find another SCC def.
5028 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
5031 if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1)
5032 Worklist.insert(&MI);
5036 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
5037 const MachineInstr &Inst) const {
5038 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
5040 switch (Inst.getOpcode()) {
5041 // For target instructions, getOpRegClass just returns the virtual register
5042 // class associated with the operand, so we need to find an equivalent VGPR
5043 // register class in order to move the instruction to the VALU.
5046 case AMDGPU::REG_SEQUENCE:
5047 case AMDGPU::INSERT_SUBREG:
5050 if (RI.hasVGPRs(NewDstRC))
5053 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
5062 // Find the one SGPR operand we are allowed to use.
5063 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr &MI,
5064 int OpIndices[3]) const {
5065 const MCInstrDesc &Desc = MI.getDesc();
5067 // Find the one SGPR operand we are allowed to use.
5069 // First we need to consider the instruction's operand requirements before
5070 // legalizing. Some operands are required to be SGPRs, such as implicit uses
5071 // of VCC, but we are still bound by the constant bus requirement to only use
5074 // If the operand's class is an SGPR, we can never move it.
5076 unsigned SGPRReg = findImplicitSGPRRead(MI);
5077 if (SGPRReg != AMDGPU::NoRegister)
5080 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
5081 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
5083 for (unsigned i = 0; i < 3; ++i) {
5084 int Idx = OpIndices[i];
5088 const MachineOperand &MO = MI.getOperand(Idx);
5092 // Is this operand statically required to be an SGPR based on the operand
5094 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
5095 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
5099 // If this could be a VGPR or an SGPR, Check the dynamic register class.
5100 unsigned Reg = MO.getReg();
5101 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
5102 if (RI.isSGPRClass(RegRC))
5106 // We don't have a required SGPR operand, so we have a bit more freedom in
5107 // selecting operands to move.
5109 // Try to select the most used SGPR. If an SGPR is equal to one of the
5110 // others, we choose that.
5113 // V_FMA_F32 v0, s0, s0, s0 -> No moves
5114 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
5116 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
5119 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
5120 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
5121 SGPRReg = UsedSGPRs[0];
5124 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
5125 if (UsedSGPRs[1] == UsedSGPRs[2])
5126 SGPRReg = UsedSGPRs[1];
5132 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
5133 unsigned OperandName) const {
5134 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
5138 return &MI.getOperand(Idx);
5141 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
5142 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
5143 if (ST.isAmdHsaOS()) {
5144 // Set ATC = 1. GFX9 doesn't have this bit.
5145 if (ST.getGeneration() <= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5146 RsrcDataFormat |= (1ULL << 56);
5148 // Set MTYPE = 2 (MTYPE_UC = uncached). GFX9 doesn't have this.
5149 // BTW, it disables TC L2 and therefore decreases performance.
5150 if (ST.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS)
5151 RsrcDataFormat |= (2ULL << 59);
5154 return RsrcDataFormat;
5157 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
5158 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
5159 AMDGPU::RSRC_TID_ENABLE |
5160 0xffffffff; // Size;
5162 // GFX9 doesn't have ELEMENT_SIZE.
5163 if (ST.getGeneration() <= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
5164 uint64_t EltSizeValue = Log2_32(ST.getMaxPrivateElementSize()) - 1;
5165 Rsrc23 |= EltSizeValue << AMDGPU::RSRC_ELEMENT_SIZE_SHIFT;
5168 // IndexStride = 64.
5169 Rsrc23 |= UINT64_C(3) << AMDGPU::RSRC_INDEX_STRIDE_SHIFT;
5171 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
5172 // Clear them unless we want a huge stride.
5173 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5174 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;
5179 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {
5180 unsigned Opc = MI.getOpcode();
5185 bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {
5186 unsigned Opc = MI.getOpcode();
5188 return isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc);
5191 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
5192 int &FrameIndex) const {
5193 const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
5194 if (!Addr || !Addr->isFI())
5195 return AMDGPU::NoRegister;
5197 assert(!MI.memoperands_empty() &&
5198 (*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS);
5200 FrameIndex = Addr->getIndex();
5201 return getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg();
5204 unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
5205 int &FrameIndex) const {
5206 const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::addr);
5207 assert(Addr && Addr->isFI());
5208 FrameIndex = Addr->getIndex();
5209 return getNamedOperand(MI, AMDGPU::OpName::data)->getReg();
5212 unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
5213 int &FrameIndex) const {
5215 return AMDGPU::NoRegister;
5217 if (isMUBUF(MI) || isVGPRSpill(MI))
5218 return isStackAccess(MI, FrameIndex);
5220 if (isSGPRSpill(MI))
5221 return isSGPRStackAccess(MI, FrameIndex);
5223 return AMDGPU::NoRegister;
5226 unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
5227 int &FrameIndex) const {
5229 return AMDGPU::NoRegister;
5231 if (isMUBUF(MI) || isVGPRSpill(MI))
5232 return isStackAccess(MI, FrameIndex);
5234 if (isSGPRSpill(MI))
5235 return isSGPRStackAccess(MI, FrameIndex);
5237 return AMDGPU::NoRegister;
5240 unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {
5242 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
5243 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
5244 while (++I != E && I->isInsideBundle()) {
5245 assert(!I->isBundle() && "No nested bundle!");
5246 Size += getInstSizeInBytes(*I);
5252 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
5253 unsigned Opc = MI.getOpcode();
5254 const MCInstrDesc &Desc = getMCOpcodeFromPseudo(Opc);
5255 unsigned DescSize = Desc.getSize();
5257 // If we have a definitive size, we can use it. Otherwise we need to inspect
5258 // the operands to know the size.
5259 if (isFixedSize(MI))
5262 // 4-byte instructions may have a 32-bit literal encoded after them. Check
5263 // operands that coud ever be literals.
5264 if (isVALU(MI) || isSALU(MI)) {
5265 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
5267 return DescSize; // No operands.
5269 if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
5270 return DescSize + 4;
5272 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
5276 if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
5277 return DescSize + 4;
5279 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
5283 if (isLiteralConstantLike(MI.getOperand(Src2Idx), Desc.OpInfo[Src2Idx]))
5284 return DescSize + 4;
5290 case TargetOpcode::IMPLICIT_DEF:
5291 case TargetOpcode::KILL:
5292 case TargetOpcode::DBG_VALUE:
5293 case TargetOpcode::EH_LABEL:
5295 case TargetOpcode::BUNDLE:
5296 return getInstBundleSize(MI);
5297 case TargetOpcode::INLINEASM: {
5298 const MachineFunction *MF = MI.getParent()->getParent();
5299 const char *AsmStr = MI.getOperand(0).getSymbolName();
5300 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
5307 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {
5311 if (MI.memoperands_empty())
5314 for (const MachineMemOperand *MMO : MI.memoperands()) {
5315 if (MMO->getAddrSpace() == AMDGPUAS::FLAT_ADDRESS)
5321 bool SIInstrInfo::isNonUniformBranchInstr(MachineInstr &Branch) const {
5322 return Branch.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO;
5325 void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
5326 MachineBasicBlock *IfEnd) const {
5327 MachineBasicBlock::iterator TI = IfEntry->getFirstTerminator();
5328 assert(TI != IfEntry->end());
5330 MachineInstr *Branch = &(*TI);
5331 MachineFunction *MF = IfEntry->getParent();
5332 MachineRegisterInfo &MRI = IfEntry->getParent()->getRegInfo();
5334 if (Branch->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
5335 unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5336 MachineInstr *SIIF =
5337 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_IF), DstReg)
5338 .add(Branch->getOperand(0))
5339 .add(Branch->getOperand(1));
5340 MachineInstr *SIEND =
5341 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_END_CF))
5345 IfEntry->insert(IfEntry->end(), SIIF);
5346 IfEnd->insert(IfEnd->getFirstNonPHI(), SIEND);
5350 void SIInstrInfo::convertNonUniformLoopRegion(
5351 MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const {
5352 MachineBasicBlock::iterator TI = LoopEnd->getFirstTerminator();
5353 // We expect 2 terminators, one conditional and one unconditional.
5354 assert(TI != LoopEnd->end());
5356 MachineInstr *Branch = &(*TI);
5357 MachineFunction *MF = LoopEnd->getParent();
5358 MachineRegisterInfo &MRI = LoopEnd->getParent()->getRegInfo();
5360 if (Branch->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
5362 unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5363 unsigned BackEdgeReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5364 MachineInstrBuilder HeaderPHIBuilder =
5365 BuildMI(*(MF), Branch->getDebugLoc(), get(TargetOpcode::PHI), DstReg);
5366 for (MachineBasicBlock::pred_iterator PI = LoopEntry->pred_begin(),
5367 E = LoopEntry->pred_end();
5369 if (*PI == LoopEnd) {
5370 HeaderPHIBuilder.addReg(BackEdgeReg);
5372 MachineBasicBlock *PMBB = *PI;
5373 unsigned ZeroReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5374 materializeImmediate(*PMBB, PMBB->getFirstTerminator(), DebugLoc(),
5376 HeaderPHIBuilder.addReg(ZeroReg);
5378 HeaderPHIBuilder.addMBB(*PI);
5380 MachineInstr *HeaderPhi = HeaderPHIBuilder;
5381 MachineInstr *SIIFBREAK = BuildMI(*(MF), Branch->getDebugLoc(),
5382 get(AMDGPU::SI_IF_BREAK), BackEdgeReg)
5384 .add(Branch->getOperand(0));
5385 MachineInstr *SILOOP =
5386 BuildMI(*(MF), Branch->getDebugLoc(), get(AMDGPU::SI_LOOP))
5387 .addReg(BackEdgeReg)
5390 LoopEntry->insert(LoopEntry->begin(), HeaderPhi);
5392 LoopEnd->insert(LoopEnd->end(), SIIFBREAK);
5393 LoopEnd->insert(LoopEnd->end(), SILOOP);
5397 ArrayRef<std::pair<int, const char *>>
5398 SIInstrInfo::getSerializableTargetIndices() const {
5399 static const std::pair<int, const char *> TargetIndices[] = {
5400 {AMDGPU::TI_CONSTDATA_START, "amdgpu-constdata-start"},
5401 {AMDGPU::TI_SCRATCH_RSRC_DWORD0, "amdgpu-scratch-rsrc-dword0"},
5402 {AMDGPU::TI_SCRATCH_RSRC_DWORD1, "amdgpu-scratch-rsrc-dword1"},
5403 {AMDGPU::TI_SCRATCH_RSRC_DWORD2, "amdgpu-scratch-rsrc-dword2"},
5404 {AMDGPU::TI_SCRATCH_RSRC_DWORD3, "amdgpu-scratch-rsrc-dword3"}};
5405 return makeArrayRef(TargetIndices);
5408 /// This is used by the post-RA scheduler (SchedulePostRAList.cpp). The
5409 /// post-RA version of misched uses CreateTargetMIHazardRecognizer.
5410 ScheduleHazardRecognizer *
5411 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
5412 const ScheduleDAG *DAG) const {
5413 return new GCNHazardRecognizer(DAG->MF);
5416 /// This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer
5418 ScheduleHazardRecognizer *
5419 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
5420 return new GCNHazardRecognizer(MF);
5423 std::pair<unsigned, unsigned>
5424 SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
5425 return std::make_pair(TF & MO_MASK, TF & ~MO_MASK);
5428 ArrayRef<std::pair<unsigned, const char *>>
5429 SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
5430 static const std::pair<unsigned, const char *> TargetFlags[] = {
5431 { MO_GOTPCREL, "amdgpu-gotprel" },
5432 { MO_GOTPCREL32_LO, "amdgpu-gotprel32-lo" },
5433 { MO_GOTPCREL32_HI, "amdgpu-gotprel32-hi" },
5434 { MO_REL32_LO, "amdgpu-rel32-lo" },
5435 { MO_REL32_HI, "amdgpu-rel32-hi" }
5438 return makeArrayRef(TargetFlags);
5441 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {
5442 return !MI.isTerminator() && MI.getOpcode() != AMDGPU::COPY &&
5443 MI.modifiesRegister(AMDGPU::EXEC, &RI);
5447 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,
5448 MachineBasicBlock::iterator I,
5450 unsigned DestReg) const {
5451 if (ST.hasAddNoCarry())
5452 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e64), DestReg);
5454 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5455 unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5456 MRI.setRegAllocationHint(UnusedCarry, 0, AMDGPU::VCC);
5458 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
5459 .addReg(UnusedCarry, RegState::Define | RegState::Dead);
5462 bool SIInstrInfo::isKillTerminator(unsigned Opcode) {
5464 case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
5465 case AMDGPU::SI_KILL_I1_TERMINATOR:
5472 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {
5474 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
5475 return get(AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR);
5476 case AMDGPU::SI_KILL_I1_PSEUDO:
5477 return get(AMDGPU::SI_KILL_I1_TERMINATOR);
5479 llvm_unreachable("invalid opcode, expected SI_KILL_*_PSEUDO");
5483 bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {
5487 // Check that it is using a buffer resource.
5488 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sbase);
5489 if (Idx == -1) // e.g. s_memtime
5492 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;
5493 return RCID == AMDGPU::SReg_128RegClassID;
5496 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
5497 enum SIEncodingFamily {
5506 static SIEncodingFamily subtargetEncodingFamily(const GCNSubtarget &ST) {
5507 switch (ST.getGeneration()) {
5510 case AMDGPUSubtarget::SOUTHERN_ISLANDS:
5511 case AMDGPUSubtarget::SEA_ISLANDS:
5512 return SIEncodingFamily::SI;
5513 case AMDGPUSubtarget::VOLCANIC_ISLANDS:
5514 case AMDGPUSubtarget::GFX9:
5515 return SIEncodingFamily::VI;
5517 llvm_unreachable("Unknown subtarget generation!");
5520 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
5521 SIEncodingFamily Gen = subtargetEncodingFamily(ST);
5523 if ((get(Opcode).TSFlags & SIInstrFlags::renamedInGFX9) != 0 &&
5524 ST.getGeneration() >= AMDGPUSubtarget::GFX9)
5525 Gen = SIEncodingFamily::GFX9;
5527 if (get(Opcode).TSFlags & SIInstrFlags::SDWA)
5528 Gen = ST.getGeneration() == AMDGPUSubtarget::GFX9 ? SIEncodingFamily::SDWA9
5529 : SIEncodingFamily::SDWA;
5530 // Adjust the encoding family to GFX80 for D16 buffer instructions when the
5531 // subtarget has UnpackedD16VMem feature.
5532 // TODO: remove this when we discard GFX80 encoding.
5533 if (ST.hasUnpackedD16VMem() && (get(Opcode).TSFlags & SIInstrFlags::D16Buf))
5534 Gen = SIEncodingFamily::GFX80;
5536 int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
5538 // -1 means that Opcode is already a native instruction.
5542 // (uint16_t)-1 means that Opcode is a pseudo instruction that has
5543 // no encoding in the given subtarget generation.
5544 if (MCOp == (uint16_t)-1)
5551 TargetInstrInfo::RegSubRegPair getRegOrUndef(const MachineOperand &RegOpnd) {
5552 assert(RegOpnd.isReg());
5553 return RegOpnd.isUndef() ? TargetInstrInfo::RegSubRegPair() :
5554 getRegSubRegPair(RegOpnd);
5557 TargetInstrInfo::RegSubRegPair
5558 llvm::getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg) {
5559 assert(MI.isRegSequence());
5560 for (unsigned I = 0, E = (MI.getNumOperands() - 1)/ 2; I < E; ++I)
5561 if (MI.getOperand(1 + 2 * I + 1).getImm() == SubReg) {
5562 auto &RegOp = MI.getOperand(1 + 2 * I);
5563 return getRegOrUndef(RegOp);
5565 return TargetInstrInfo::RegSubRegPair();
5568 // Try to find the definition of reg:subreg in subreg-manipulation pseudos
5569 // Following a subreg of reg:subreg isn't supported
5570 static bool followSubRegDef(MachineInstr &MI,
5571 TargetInstrInfo::RegSubRegPair &RSR) {
5574 switch (MI.getOpcode()) {
5576 case AMDGPU::REG_SEQUENCE:
5577 RSR = getRegSequenceSubReg(MI, RSR.SubReg);
5579 // EXTRACT_SUBREG ins't supported as this would follow a subreg of subreg
5580 case AMDGPU::INSERT_SUBREG:
5581 if (RSR.SubReg == (unsigned)MI.getOperand(3).getImm())
5582 // inserted the subreg we're looking for
5583 RSR = getRegOrUndef(MI.getOperand(2));
5584 else { // the subreg in the rest of the reg
5585 auto R1 = getRegOrUndef(MI.getOperand(1));
5586 if (R1.SubReg) // subreg of subreg isn't supported
5595 MachineInstr *llvm::getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
5596 MachineRegisterInfo &MRI) {
5597 assert(MRI.isSSA());
5598 if (!TargetRegisterInfo::isVirtualRegister(P.Reg))
5602 auto *DefInst = MRI.getVRegDef(RSR.Reg);
5603 while (auto *MI = DefInst) {
5605 switch (MI->getOpcode()) {
5607 case AMDGPU::V_MOV_B32_e32: {
5608 auto &Op1 = MI->getOperand(1);
5610 TargetRegisterInfo::isVirtualRegister(Op1.getReg())) {
5613 RSR = getRegSubRegPair(Op1);
5614 DefInst = MRI.getVRegDef(RSR.Reg);
5619 if (followSubRegDef(*MI, RSR)) {
5622 DefInst = MRI.getVRegDef(RSR.Reg);