1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //===----------------------------------------------------------------------===//
14 #include "ARMAsmPrinter.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "MCTargetDesc/ARMInstPrinter.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
23 #include "TargetInfo/ARMTargetInfo.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Support/ARMBuildAttributes.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/TargetParser.h"
48 #include "llvm/Support/TargetRegistry.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetMachine.h"
53 #define DEBUG_TYPE "asm-printer"
55 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
56 std::unique_ptr<MCStreamer> Streamer)
57 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
58 InConstantPool(false), OptimizationGoals(-1) {}
60 void ARMAsmPrinter::EmitFunctionBodyEnd() {
61 // Make sure to terminate any constant pools that were at the end
65 InConstantPool = false;
66 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
69 void ARMAsmPrinter::EmitFunctionEntryLabel() {
70 if (AFI->isThumbFunction()) {
71 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
72 OutStreamer->EmitThumbFunc(CurrentFnSym);
74 OutStreamer->EmitAssemblerFlag(MCAF_Code32);
76 OutStreamer->EmitLabel(CurrentFnSym);
79 void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
80 uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
81 assert(Size && "C++ constructor pointer had zero size!");
83 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
84 assert(GV && "C++ constructor pointer was not a GlobalValue!");
86 const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
88 (Subtarget->isTargetELF()
89 ? MCSymbolRefExpr::VK_ARM_TARGET1
90 : MCSymbolRefExpr::VK_None),
93 OutStreamer->EmitValue(E, Size);
96 void ARMAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
97 if (PromotedGlobals.count(GV))
98 // The global was promoted into a constant pool. It should not be emitted.
100 AsmPrinter::EmitGlobalVariable(GV);
103 /// runOnMachineFunction - This uses the EmitInstruction()
104 /// method to print assembly for each instruction.
106 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
107 AFI = MF.getInfo<ARMFunctionInfo>();
108 MCP = MF.getConstantPool();
109 Subtarget = &MF.getSubtarget<ARMSubtarget>();
111 SetupMachineFunction(MF);
112 const Function &F = MF.getFunction();
113 const TargetMachine& TM = MF.getTarget();
115 // Collect all globals that had their storage promoted to a constant pool.
116 // Functions are emitted before variables, so this accumulates promoted
117 // globals from all functions in PromotedGlobals.
118 for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
119 PromotedGlobals.insert(GV);
121 // Calculate this function's optimization goal.
122 unsigned OptimizationGoal;
124 // For best debugging illusion, speed and small size sacrificed
125 OptimizationGoal = 6;
126 else if (F.hasMinSize())
127 // Aggressively for small size, speed and debug illusion sacrificed
128 OptimizationGoal = 4;
129 else if (F.hasOptSize())
130 // For small size, but speed and debugging illusion preserved
131 OptimizationGoal = 3;
132 else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
133 // Aggressively for speed, small size and debug illusion sacrificed
134 OptimizationGoal = 2;
135 else if (TM.getOptLevel() > CodeGenOpt::None)
136 // For speed, but small size and good debug illusion preserved
137 OptimizationGoal = 1;
138 else // TM.getOptLevel() == CodeGenOpt::None
139 // For good debugging, but speed and small size preserved
140 OptimizationGoal = 5;
142 // Combine a new optimization goal with existing ones.
143 if (OptimizationGoals == -1) // uninitialized goals
144 OptimizationGoals = OptimizationGoal;
145 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
146 OptimizationGoals = 0;
148 if (Subtarget->isTargetCOFF()) {
149 bool Internal = F.hasInternalLinkage();
150 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
151 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
152 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
154 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
155 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
156 OutStreamer->EmitCOFFSymbolType(Type);
157 OutStreamer->EndCOFFSymbolDef();
160 // Emit the rest of the function body.
163 // Emit the XRay table for this function.
166 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
167 // These are created per function, rather than per TU, since it's
168 // relatively easy to exceed the thumb branch range within a TU.
169 if (! ThumbIndirectPads.empty()) {
170 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
172 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
173 OutStreamer->EmitLabel(TIP.second);
174 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
176 // Add predicate operands.
180 ThumbIndirectPads.clear();
183 // We didn't modify anything.
187 void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
189 assert(MO.isGlobal() && "caller should check MO.isGlobal");
190 unsigned TF = MO.getTargetFlags();
191 if (TF & ARMII::MO_LO16)
193 else if (TF & ARMII::MO_HI16)
195 GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
196 printOffset(MO.getOffset(), O);
199 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
201 const MachineOperand &MO = MI->getOperand(OpNum);
203 switch (MO.getType()) {
204 default: llvm_unreachable("<unknown operand type>");
205 case MachineOperand::MO_Register: {
206 unsigned Reg = MO.getReg();
207 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
208 assert(!MO.getSubReg() && "Subregs should be eliminated!");
209 if(ARM::GPRPairRegClass.contains(Reg)) {
210 const MachineFunction &MF = *MI->getParent()->getParent();
211 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
212 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
214 O << ARMInstPrinter::getRegisterName(Reg);
217 case MachineOperand::MO_Immediate: {
219 unsigned TF = MO.getTargetFlags();
220 if (TF == ARMII::MO_LO16)
222 else if (TF == ARMII::MO_HI16)
227 case MachineOperand::MO_MachineBasicBlock:
228 MO.getMBB()->getSymbol()->print(O, MAI);
230 case MachineOperand::MO_GlobalAddress: {
231 PrintSymbolOperand(MO, O);
234 case MachineOperand::MO_ConstantPoolIndex:
235 if (Subtarget->genExecuteOnly())
236 llvm_unreachable("execute-only should not generate constant pools");
237 GetCPISymbol(MO.getIndex())->print(O, MAI);
242 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
243 // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
244 // indexes in MachineConstantPool, which isn't in sync with indexes used here.
245 const DataLayout &DL = getDataLayout();
246 return OutContext.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
247 "CPI" + Twine(getFunctionNumber()) + "_" +
251 //===--------------------------------------------------------------------===//
253 MCSymbol *ARMAsmPrinter::
254 GetARMJTIPICJumpTableLabel(unsigned uid) const {
255 const DataLayout &DL = getDataLayout();
256 SmallString<60> Name;
257 raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
258 << getFunctionNumber() << '_' << uid;
259 return OutContext.getOrCreateSymbol(Name);
262 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
263 const char *ExtraCode, raw_ostream &O) {
264 // Does this asm operand have a single letter operand modifier?
265 if (ExtraCode && ExtraCode[0]) {
266 if (ExtraCode[1] != 0) return true; // Unknown modifier.
268 switch (ExtraCode[0]) {
270 // See if this is a generic print operand
271 return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
272 case 'P': // Print a VFP double precision register.
273 case 'q': // Print a NEON quad precision register.
274 printOperand(MI, OpNum, O);
276 case 'y': // Print a VFP single precision register as indexed double.
277 if (MI->getOperand(OpNum).isReg()) {
278 unsigned Reg = MI->getOperand(OpNum).getReg();
279 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
280 // Find the 'd' register that has this 's' register as a sub-register,
281 // and determine the lane number.
282 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
283 if (!ARM::DPRRegClass.contains(*SR))
285 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
286 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
291 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
292 if (!MI->getOperand(OpNum).isImm())
294 O << ~(MI->getOperand(OpNum).getImm());
296 case 'L': // The low 16 bits of an immediate constant.
297 if (!MI->getOperand(OpNum).isImm())
299 O << (MI->getOperand(OpNum).getImm() & 0xffff);
301 case 'M': { // A register range suitable for LDM/STM.
302 if (!MI->getOperand(OpNum).isReg())
304 const MachineOperand &MO = MI->getOperand(OpNum);
305 unsigned RegBegin = MO.getReg();
306 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
307 // already got the operands in registers that are operands to the
308 // inline asm statement.
310 if (ARM::GPRPairRegClass.contains(RegBegin)) {
311 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
312 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
313 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
314 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
316 O << ARMInstPrinter::getRegisterName(RegBegin);
318 // FIXME: The register allocator not only may not have given us the
319 // registers in sequence, but may not be in ascending registers. This
320 // will require changes in the register allocator that'll need to be
321 // propagated down here if the operands change.
322 unsigned RegOps = OpNum + 1;
323 while (MI->getOperand(RegOps).isReg()) {
325 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
333 case 'R': // The most significant register of a pair.
334 case 'Q': { // The least significant register of a pair.
337 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
338 if (!FlagsOP.isImm())
340 unsigned Flags = FlagsOP.getImm();
342 // This operand may not be the one that actually provides the register. If
343 // it's tied to a previous one then we should refer instead to that one
344 // for registers and their classes.
346 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
347 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
348 unsigned OpFlags = MI->getOperand(OpNum).getImm();
349 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
351 Flags = MI->getOperand(OpNum).getImm();
353 // Later code expects OpNum to be pointing at the register rather than
358 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
361 const ARMBaseTargetMachine &ATM =
362 static_cast<const ARMBaseTargetMachine &>(TM);
364 // 'Q' should correspond to the low order register and 'R' to the high
365 // order register. Whether this corresponds to the upper or lower half
366 // depends on the endianess mode.
367 if (ExtraCode[0] == 'Q')
368 FirstHalf = ATM.isLittleEndian();
370 // ExtraCode[0] == 'R'.
371 FirstHalf = !ATM.isLittleEndian();
372 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
373 if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
374 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
377 const MachineOperand &MO = MI->getOperand(OpNum);
380 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
381 unsigned Reg = TRI->getSubReg(MO.getReg(), FirstHalf ?
382 ARM::gsub_0 : ARM::gsub_1);
383 O << ARMInstPrinter::getRegisterName(Reg);
388 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
389 if (RegOp >= MI->getNumOperands())
391 const MachineOperand &MO = MI->getOperand(RegOp);
394 unsigned Reg = MO.getReg();
395 O << ARMInstPrinter::getRegisterName(Reg);
399 case 'e': // The low doubleword register of a NEON quad register.
400 case 'f': { // The high doubleword register of a NEON quad register.
401 if (!MI->getOperand(OpNum).isReg())
403 unsigned Reg = MI->getOperand(OpNum).getReg();
404 if (!ARM::QPRRegClass.contains(Reg))
406 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
407 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
408 ARM::dsub_0 : ARM::dsub_1);
409 O << ARMInstPrinter::getRegisterName(SubReg);
413 // This modifier is not yet supported.
414 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
416 case 'H': { // The highest-numbered register of a pair.
417 const MachineOperand &MO = MI->getOperand(OpNum);
420 const MachineFunction &MF = *MI->getParent()->getParent();
421 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
422 unsigned Reg = MO.getReg();
423 if(!ARM::GPRPairRegClass.contains(Reg))
425 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
426 O << ARMInstPrinter::getRegisterName(Reg);
432 printOperand(MI, OpNum, O);
436 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
437 unsigned OpNum, const char *ExtraCode,
439 // Does this asm operand have a single letter operand modifier?
440 if (ExtraCode && ExtraCode[0]) {
441 if (ExtraCode[1] != 0) return true; // Unknown modifier.
443 switch (ExtraCode[0]) {
444 case 'A': // A memory operand for a VLD1/VST1 instruction.
445 default: return true; // Unknown modifier.
446 case 'm': // The base register of a memory operand.
447 if (!MI->getOperand(OpNum).isReg())
449 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
454 const MachineOperand &MO = MI->getOperand(OpNum);
455 assert(MO.isReg() && "unexpected inline asm memory operand");
456 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
460 static bool isThumb(const MCSubtargetInfo& STI) {
461 return STI.getFeatureBits()[ARM::ModeThumb];
464 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
465 const MCSubtargetInfo *EndInfo) const {
466 // If either end mode is unknown (EndInfo == NULL) or different than
467 // the start mode, then restore the start mode.
468 const bool WasThumb = isThumb(StartInfo);
469 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
470 OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
474 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
475 const Triple &TT = TM.getTargetTriple();
476 // Use unified assembler syntax.
477 OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
479 // Emit ARM Build Attributes
480 if (TT.isOSBinFormatELF())
483 // Use the triple's architecture and subarchitecture to determine
484 // if we're thumb for the purposes of the top level code16 assembler
486 if (!M.getModuleInlineAsm().empty() && TT.isThumb())
487 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
491 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
492 MachineModuleInfoImpl::StubValueTy &MCSym) {
494 OutStreamer.EmitLabel(StubLabel);
495 // .indirect_symbol _foo
496 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
499 // External to current translation unit.
500 OutStreamer.EmitIntValue(0, 4/*size*/);
502 // Internal to current translation unit.
504 // When we place the LSDA into the TEXT section, the type info
505 // pointers need to be indirect and pc-rel. We accomplish this by
506 // using NLPs; however, sometimes the types are local to the file.
507 // We need to fill in the value for the NLP in those cases.
508 OutStreamer.EmitValue(
509 MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
514 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
515 const Triple &TT = TM.getTargetTriple();
516 if (TT.isOSBinFormatMachO()) {
517 // All darwin targets use mach-o.
518 const TargetLoweringObjectFileMachO &TLOFMacho =
519 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
520 MachineModuleInfoMachO &MMIMacho =
521 MMI->getObjFileInfo<MachineModuleInfoMachO>();
523 // Output non-lazy-pointers for external and common global variables.
524 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
526 if (!Stubs.empty()) {
527 // Switch with ".non_lazy_symbol_pointer" directive.
528 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
531 for (auto &Stub : Stubs)
532 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
535 OutStreamer->AddBlankLine();
538 Stubs = MMIMacho.GetThreadLocalGVStubList();
539 if (!Stubs.empty()) {
540 // Switch with ".non_lazy_symbol_pointer" directive.
541 OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
544 for (auto &Stub : Stubs)
545 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
548 OutStreamer->AddBlankLine();
551 // Funny Darwin hack: This flag tells the linker that no global symbols
552 // contain code that falls through to other global symbols (e.g. the obvious
553 // implementation of multiple entry points). If this doesn't occur, the
554 // linker can safely perform dead code stripping. Since LLVM never
555 // generates code that does this, it is always safe to set.
556 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
559 // The last attribute to be emitted is ABI_optimization_goals
560 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
561 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
563 if (OptimizationGoals > 0 &&
564 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
565 Subtarget->isTargetMuslAEABI()))
566 ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
567 OptimizationGoals = -1;
569 ATS.finishAttributeSection();
572 //===----------------------------------------------------------------------===//
573 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
575 // The following seem like one-off assembler flags, but they actually need
576 // to appear in the .ARM.attributes section in ELF.
577 // Instead of subclassing the MCELFStreamer, we do the work here.
579 // Returns true if all functions have the same function attribute value.
580 // It also returns true when the module has no functions.
581 static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
583 return !any_of(M, [&](const Function &F) {
584 return F.getFnAttribute(Attr).getValueAsString() != Value;
588 void ARMAsmPrinter::emitAttributes() {
589 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
590 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
592 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
594 ATS.switchVendor("aeabi");
596 // Compute ARM ELF Attributes based on the default subtarget that
597 // we'd have constructed. The existing ARM behavior isn't LTO clean
599 // FIXME: For ifunc related functions we could iterate over and look
600 // for a feature string that doesn't match the default one.
601 const Triple &TT = TM.getTargetTriple();
602 StringRef CPU = TM.getTargetCPU();
603 StringRef FS = TM.getTargetFeatureString();
604 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
607 ArchFS = (Twine(ArchFS) + "," + FS).str();
611 const ARMBaseTargetMachine &ATM =
612 static_cast<const ARMBaseTargetMachine &>(TM);
613 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
615 // Emit build attributes for the available hardware.
616 ATS.emitTargetAttributes(STI);
618 // RW data addressing.
619 if (isPositionIndependent()) {
620 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
621 ARMBuildAttrs::AddressRWPCRel);
622 } else if (STI.isRWPI()) {
623 // RWPI specific attributes.
624 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
625 ARMBuildAttrs::AddressRWSBRel);
628 // RO data addressing.
629 if (isPositionIndependent() || STI.isROPI()) {
630 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
631 ARMBuildAttrs::AddressROPCRel);
635 if (isPositionIndependent()) {
636 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
637 ARMBuildAttrs::AddressGOT);
639 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
640 ARMBuildAttrs::AddressDirect);
644 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
647 TM.Options.FPDenormalMode == FPDenormal::PreserveSign)
648 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
649 ARMBuildAttrs::PreserveFPSign);
650 else if (checkFunctionsAttributeConsistency(*MMI->getModule(),
653 TM.Options.FPDenormalMode == FPDenormal::PositiveZero)
654 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
655 ARMBuildAttrs::PositiveZero);
656 else if (!TM.Options.UnsafeFPMath)
657 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
658 ARMBuildAttrs::IEEEDenormals);
660 if (!STI.hasVFP2Base()) {
661 // When the target doesn't have an FPU (by design or
662 // intention), the assumptions made on the software support
663 // mirror that of the equivalent hardware support *if it
664 // existed*. For v7 and better we indicate that denormals are
665 // flushed preserving sign, and for V6 we indicate that
666 // denormals are flushed to positive zero.
668 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
669 ARMBuildAttrs::PreserveFPSign);
670 } else if (STI.hasVFP3Base()) {
671 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
672 // the sign bit of the zero matches the sign bit of the input or
673 // result that is being flushed to zero.
674 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
675 ARMBuildAttrs::PreserveFPSign);
677 // For VFPv2 implementations it is implementation defined as
678 // to whether denormals are flushed to positive zero or to
679 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
680 // LLVM has chosen to flush this to positive zero (most likely for
681 // GCC compatibility), so that's the chosen value here (the
682 // absence of its emission implies zero).
685 // Set FP exceptions and rounding
686 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
687 "no-trapping-math", "true") ||
688 TM.Options.NoTrappingFPMath)
689 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
690 ARMBuildAttrs::Not_Allowed);
691 else if (!TM.Options.UnsafeFPMath) {
692 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
694 // If the user has permitted this code to choose the IEEE 754
695 // rounding at run-time, emit the rounding attribute.
696 if (TM.Options.HonorSignDependentRoundingFPMathOption)
697 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
700 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
701 // equivalent of GCC's -ffinite-math-only flag.
702 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
703 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
704 ARMBuildAttrs::Allowed);
706 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
707 ARMBuildAttrs::AllowIEEE754);
709 // FIXME: add more flags to ARMBuildAttributes.h
710 // 8-bytes alignment stuff.
711 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
712 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
714 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
715 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
716 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
718 // FIXME: To support emitting this build attribute as GCC does, the
719 // -mfp16-format option and associated plumbing must be
720 // supported. For now the __fp16 type is exposed by default, so this
721 // attribute should be emitted with value 1.
722 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
723 ARMBuildAttrs::FP16FormatIEEE);
726 if (const Module *SourceModule = MMI->getModule()) {
727 // ABI_PCS_wchar_t to indicate wchar_t width
728 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
729 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
730 SourceModule->getModuleFlag("wchar_size"))) {
731 int WCharWidth = WCharWidthValue->getZExtValue();
732 assert((WCharWidth == 2 || WCharWidth == 4) &&
733 "wchar_t width must be 2 or 4 bytes");
734 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
737 // ABI_enum_size to indicate enum width
738 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
739 // (all enums contain a value needing 32 bits to encode).
740 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
741 SourceModule->getModuleFlag("min_enum_size"))) {
742 int EnumWidth = EnumWidthValue->getZExtValue();
743 assert((EnumWidth == 1 || EnumWidth == 4) &&
744 "Minimum enum width must be 1 or 4 bytes");
745 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
746 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
751 // We currently do not support using R9 as the TLS pointer.
753 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
754 ARMBuildAttrs::R9IsSB);
755 else if (STI.isR9Reserved())
756 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
757 ARMBuildAttrs::R9Reserved);
759 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
760 ARMBuildAttrs::R9IsGPR);
763 //===----------------------------------------------------------------------===//
765 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
766 unsigned LabelId, MCContext &Ctx) {
768 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
769 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
773 static MCSymbolRefExpr::VariantKind
774 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
776 case ARMCP::no_modifier:
777 return MCSymbolRefExpr::VK_None;
779 return MCSymbolRefExpr::VK_TLSGD;
781 return MCSymbolRefExpr::VK_TPOFF;
782 case ARMCP::GOTTPOFF:
783 return MCSymbolRefExpr::VK_GOTTPOFF;
785 return MCSymbolRefExpr::VK_ARM_SBREL;
786 case ARMCP::GOT_PREL:
787 return MCSymbolRefExpr::VK_ARM_GOT_PREL;
789 return MCSymbolRefExpr::VK_SECREL;
791 llvm_unreachable("Invalid ARMCPModifier!");
794 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
795 unsigned char TargetFlags) {
796 if (Subtarget->isTargetMachO()) {
798 (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
801 return getSymbol(GV);
803 // FIXME: Remove this when Darwin transition to @GOT like syntax.
804 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
805 MachineModuleInfoMachO &MMIMachO =
806 MMI->getObjFileInfo<MachineModuleInfoMachO>();
807 MachineModuleInfoImpl::StubValueTy &StubSym =
808 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
809 : MMIMachO.getGVStubEntry(MCSym);
811 if (!StubSym.getPointer())
812 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
813 !GV->hasInternalLinkage());
815 } else if (Subtarget->isTargetCOFF()) {
816 assert(Subtarget->isTargetWindows() &&
817 "Windows is the only supported COFF target");
820 (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
822 return getSymbol(GV);
824 SmallString<128> Name;
825 if (TargetFlags & ARMII::MO_DLLIMPORT)
827 else if (TargetFlags & ARMII::MO_COFFSTUB)
829 getNameWithPrefix(Name, GV);
831 MCSymbol *MCSym = OutContext.getOrCreateSymbol(Name);
833 if (TargetFlags & ARMII::MO_COFFSTUB) {
834 MachineModuleInfoCOFF &MMICOFF =
835 MMI->getObjFileInfo<MachineModuleInfoCOFF>();
836 MachineModuleInfoImpl::StubValueTy &StubSym =
837 MMICOFF.getGVStubEntry(MCSym);
839 if (!StubSym.getPointer())
840 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
844 } else if (Subtarget->isTargetELF()) {
845 return getSymbol(GV);
847 llvm_unreachable("unexpected target");
851 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
852 const DataLayout &DL = getDataLayout();
853 int Size = DL.getTypeAllocSize(MCPV->getType());
855 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
857 if (ACPV->isPromotedGlobal()) {
858 // This constant pool entry is actually a global whose storage has been
859 // promoted into the constant pool. This global may be referenced still
860 // by debug information, and due to the way AsmPrinter is set up, the debug
861 // info is immutable by the time we decide to promote globals to constant
862 // pools. Because of this, we need to ensure we emit a symbol for the global
863 // with private linkage (the default) so debug info can refer to it.
865 // However, if this global is promoted into several functions we must ensure
866 // we don't try and emit duplicate symbols!
867 auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
868 for (const auto *GV : ACPC->promotedGlobals()) {
869 if (!EmittedPromotedGlobalLabels.count(GV)) {
870 MCSymbol *GVSym = getSymbol(GV);
871 OutStreamer->EmitLabel(GVSym);
872 EmittedPromotedGlobalLabels.insert(GV);
875 return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
879 if (ACPV->isLSDA()) {
880 MCSym = getCurExceptionSym();
881 } else if (ACPV->isBlockAddress()) {
882 const BlockAddress *BA =
883 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
884 MCSym = GetBlockAddressSymbol(BA);
885 } else if (ACPV->isGlobalValue()) {
886 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
888 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
889 // flag the global as MO_NONLAZY.
890 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
891 MCSym = GetARMGVSymbol(GV, TF);
892 } else if (ACPV->isMachineBasicBlock()) {
893 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
894 MCSym = MBB->getSymbol();
896 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
897 auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
898 MCSym = GetExternalSymbolSymbol(Sym);
901 // Create an MCSymbol for the reference.
903 MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
906 if (ACPV->getPCAdjustment()) {
908 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
909 ACPV->getLabelId(), OutContext);
910 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
912 MCBinaryExpr::createAdd(PCRelExpr,
913 MCConstantExpr::create(ACPV->getPCAdjustment(),
916 if (ACPV->mustAddCurrentAddress()) {
917 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
918 // label, so just emit a local label end reference that instead.
919 MCSymbol *DotSym = OutContext.createTempSymbol();
920 OutStreamer->EmitLabel(DotSym);
921 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
922 PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
924 Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
926 OutStreamer->EmitValue(Expr, Size);
929 void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
930 const MachineOperand &MO1 = MI->getOperand(1);
931 unsigned JTI = MO1.getIndex();
933 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
937 // Emit a label for the jump table.
938 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
939 OutStreamer->EmitLabel(JTISymbol);
941 // Mark the jump table as data-in-code.
942 OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
944 // Emit each entry of the table.
945 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
946 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
947 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
949 for (MachineBasicBlock *MBB : JTBBs) {
950 // Construct an MCExpr for the entry. We want a value of the form:
951 // (BasicBlockAddr - TableBeginAddr)
953 // For example, a table with entries jumping to basic blocks BB0 and BB1
956 // .word (LBB0 - LJTI_0_0)
957 // .word (LBB1 - LJTI_0_0)
958 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
960 if (isPositionIndependent() || Subtarget->isROPI())
961 Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
964 // If we're generating a table of Thumb addresses in static relocation
965 // model, we need to add one to keep interworking correctly.
966 else if (AFI->isThumbFunction())
967 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
969 OutStreamer->EmitValue(Expr, 4);
971 // Mark the end of jump table data-in-code region.
972 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
975 void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
976 const MachineOperand &MO1 = MI->getOperand(1);
977 unsigned JTI = MO1.getIndex();
979 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
983 // Emit a label for the jump table.
984 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
985 OutStreamer->EmitLabel(JTISymbol);
987 // Emit each entry of the table.
988 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
989 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
990 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
992 for (MachineBasicBlock *MBB : JTBBs) {
993 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
995 // If this isn't a TBB or TBH, the entries are direct branch instructions.
996 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
997 .addExpr(MBBSymbolExpr)
1003 void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
1004 unsigned OffsetWidth) {
1005 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1006 const MachineOperand &MO1 = MI->getOperand(1);
1007 unsigned JTI = MO1.getIndex();
1009 if (Subtarget->isThumb1Only())
1012 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1013 OutStreamer->EmitLabel(JTISymbol);
1015 // Emit each entry of the table.
1016 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1017 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1018 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1020 // Mark the jump table as data-in-code.
1021 OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1022 : MCDR_DataRegionJT16);
1024 for (auto MBB : JTBBs) {
1025 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1027 // Otherwise it's an offset from the dispatch instruction. Construct an
1028 // MCExpr for the entry. We want a value of the form:
1029 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1031 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1034 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1035 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1036 // where LCPI0_0 is a label defined just before the TBB instruction using
1038 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1039 const MCExpr *Expr = MCBinaryExpr::createAdd(
1040 MCSymbolRefExpr::create(TBInstPC, OutContext),
1041 MCConstantExpr::create(4, OutContext), OutContext);
1042 Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1043 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
1045 OutStreamer->EmitValue(Expr, OffsetWidth);
1047 // Mark the end of jump table data-in-code region. 32-bit offsets use
1048 // actual branch instructions here, so we don't mark those as a data-region
1050 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1052 // Make sure the next instruction is 2-byte aligned.
1056 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1057 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1058 "Only instruction which are involved into frame setup code are allowed");
1060 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1061 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1062 const MachineFunction &MF = *MI->getParent()->getParent();
1063 const TargetRegisterInfo *TargetRegInfo =
1064 MF.getSubtarget().getRegisterInfo();
1065 const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1066 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1068 unsigned FramePtr = TargetRegInfo->getFrameRegister(MF);
1069 unsigned Opc = MI->getOpcode();
1070 unsigned SrcReg, DstReg;
1072 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1073 // Two special cases:
1074 // 1) tPUSH does not have src/dst regs.
1075 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1076 // load. Yes, this is pretty fragile, but for now I don't see better
1078 SrcReg = DstReg = ARM::SP;
1080 SrcReg = MI->getOperand(1).getReg();
1081 DstReg = MI->getOperand(0).getReg();
1084 // Try to figure out the unwinding opcode out of src / dst regs.
1085 if (MI->mayStore()) {
1087 assert(DstReg == ARM::SP &&
1088 "Only stack pointer as a destination reg is supported");
1090 SmallVector<unsigned, 4> RegList;
1091 // Skip src & dst reg, and pred ops.
1092 unsigned StartOp = 2 + 2;
1093 // Use all the operands.
1094 unsigned NumOffset = 0;
1095 // Amount of SP adjustment folded into a push.
1101 llvm_unreachable("Unsupported opcode for unwinding information");
1103 // Special case here: no src & dst reg, but two extra imp ops.
1104 StartOp = 2; NumOffset = 2;
1106 case ARM::STMDB_UPD:
1107 case ARM::t2STMDB_UPD:
1108 case ARM::VSTMDDB_UPD:
1109 assert(SrcReg == ARM::SP &&
1110 "Only stack pointer as a source reg is supported");
1111 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1113 const MachineOperand &MO = MI->getOperand(i);
1114 // Actually, there should never be any impdef stuff here. Skip it
1115 // temporary to workaround PR11902.
1116 if (MO.isImplicit())
1118 // Registers, pushed as a part of folding an SP update into the
1119 // push instruction are marked as undef and should not be
1120 // restored when unwinding, because the function can modify the
1121 // corresponding stack slots.
1123 assert(RegList.empty() &&
1124 "Pad registers must come before restored ones");
1126 TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1130 RegList.push_back(MO.getReg());
1133 case ARM::STR_PRE_IMM:
1134 case ARM::STR_PRE_REG:
1135 case ARM::t2STR_PRE:
1136 assert(MI->getOperand(2).getReg() == ARM::SP &&
1137 "Only stack pointer as a source reg is supported");
1138 RegList.push_back(SrcReg);
1141 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1142 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1143 // Account for the SP adjustment, folded into the push.
1148 // Changes of stack / frame pointer.
1149 if (SrcReg == ARM::SP) {
1154 llvm_unreachable("Unsupported opcode for unwinding information");
1161 Offset = -MI->getOperand(2).getImm();
1165 Offset = MI->getOperand(2).getImm();
1168 Offset = MI->getOperand(2).getImm()*4;
1172 Offset = -MI->getOperand(2).getImm()*4;
1174 case ARM::tLDRpci: {
1175 // Grab the constpool index and check, whether it corresponds to
1176 // original or cloned constpool entry.
1177 unsigned CPI = MI->getOperand(1).getIndex();
1178 const MachineConstantPool *MCP = MF.getConstantPool();
1179 if (CPI >= MCP->getConstants().size())
1180 CPI = AFI.getOriginalCPIdx(CPI);
1181 assert(CPI != -1U && "Invalid constpool index");
1183 // Derive the actual offset.
1184 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1185 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1186 // FIXME: Check for user, it should be "add" instruction!
1187 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1192 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1193 if (DstReg == FramePtr && FramePtr != ARM::SP)
1194 // Set-up of the frame pointer. Positive values correspond to "add"
1196 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1197 else if (DstReg == ARM::SP) {
1198 // Change of SP by an offset. Positive values correspond to "sub"
1200 ATS.emitPad(Offset);
1202 // Move of SP to a register. Positive values correspond to an "add"
1204 ATS.emitMovSP(DstReg, -Offset);
1207 } else if (DstReg == ARM::SP) {
1209 llvm_unreachable("Unsupported opcode for unwinding information");
1213 llvm_unreachable("Unsupported opcode for unwinding information");
1218 // Simple pseudo-instructions have their lowering (with expansion to real
1219 // instructions) auto-generated.
1220 #include "ARMGenMCPseudoLowering.inc"
1222 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1223 const DataLayout &DL = getDataLayout();
1224 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1225 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1227 const MachineFunction &MF = *MI->getParent()->getParent();
1228 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
1229 unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
1231 // If we just ended a constant pool, mark it as such.
1232 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1233 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1234 InConstantPool = false;
1237 // Emit unwinding stuff for frame-related instructions
1238 if (Subtarget->isTargetEHABICompatible() &&
1239 MI->getFlag(MachineInstr::FrameSetup))
1240 EmitUnwindingInstruction(MI);
1242 // Do any auto-generated pseudo lowerings.
1243 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1246 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1247 "Pseudo flag setting opcode should be expanded early");
1249 // Check for manual lowerings.
1250 unsigned Opc = MI->getOpcode();
1252 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1253 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1255 case ARM::tLEApcrel:
1256 case ARM::t2LEApcrel: {
1257 // FIXME: Need to also handle globals and externals
1258 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1259 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1260 ARM::t2LEApcrel ? ARM::t2ADR
1261 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1263 .addReg(MI->getOperand(0).getReg())
1264 .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1265 // Add predicate operands.
1266 .addImm(MI->getOperand(2).getImm())
1267 .addReg(MI->getOperand(3).getReg()));
1270 case ARM::LEApcrelJT:
1271 case ARM::tLEApcrelJT:
1272 case ARM::t2LEApcrelJT: {
1273 MCSymbol *JTIPICSymbol =
1274 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1275 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1276 ARM::t2LEApcrelJT ? ARM::t2ADR
1277 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1279 .addReg(MI->getOperand(0).getReg())
1280 .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1281 // Add predicate operands.
1282 .addImm(MI->getOperand(2).getImm())
1283 .addReg(MI->getOperand(3).getReg()));
1286 // Darwin call instructions are just normal call instructions with different
1287 // clobber semantics (they clobber R9).
1288 case ARM::BX_CALL: {
1289 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1292 // Add predicate operands.
1295 // Add 's' bit operand (always reg0 for this)
1298 assert(Subtarget->hasV4TOps());
1299 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1300 .addReg(MI->getOperand(0).getReg()));
1303 case ARM::tBX_CALL: {
1304 if (Subtarget->hasV5TOps())
1305 llvm_unreachable("Expected BLX to be selected for v5t+");
1307 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1308 // that the saved lr has its LSB set correctly (the arch doesn't
1310 // So here we generate a bl to a small jump pad that does bx rN.
1311 // The jump pads are emitted after the function body.
1313 unsigned TReg = MI->getOperand(0).getReg();
1314 MCSymbol *TRegSym = nullptr;
1315 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1316 if (TIP.first == TReg) {
1317 TRegSym = TIP.second;
1323 TRegSym = OutContext.createTempSymbol();
1324 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1327 // Create a link-saving branch to the Reg Indirect Jump Pad.
1328 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1329 // Predicate comes first here.
1330 .addImm(ARMCC::AL).addReg(0)
1331 .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1334 case ARM::BMOVPCRX_CALL: {
1335 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1338 // Add predicate operands.
1341 // Add 's' bit operand (always reg0 for this)
1344 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1346 .addReg(MI->getOperand(0).getReg())
1347 // Add predicate operands.
1350 // Add 's' bit operand (always reg0 for this)
1354 case ARM::BMOVPCB_CALL: {
1355 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1358 // Add predicate operands.
1361 // Add 's' bit operand (always reg0 for this)
1364 const MachineOperand &Op = MI->getOperand(0);
1365 const GlobalValue *GV = Op.getGlobal();
1366 const unsigned TF = Op.getTargetFlags();
1367 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1368 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1369 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1371 // Add predicate operands.
1376 case ARM::MOVi16_ga_pcrel:
1377 case ARM::t2MOVi16_ga_pcrel: {
1379 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1380 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1382 unsigned TF = MI->getOperand(1).getTargetFlags();
1383 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1384 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1385 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1387 MCSymbol *LabelSym =
1388 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1389 MI->getOperand(2).getImm(), OutContext);
1390 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1391 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1392 const MCExpr *PCRelExpr =
1393 ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
1394 MCBinaryExpr::createAdd(LabelSymExpr,
1395 MCConstantExpr::create(PCAdj, OutContext),
1396 OutContext), OutContext), OutContext);
1397 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1399 // Add predicate operands.
1400 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1401 TmpInst.addOperand(MCOperand::createReg(0));
1402 // Add 's' bit operand (always reg0 for this)
1403 TmpInst.addOperand(MCOperand::createReg(0));
1404 EmitToStreamer(*OutStreamer, TmpInst);
1407 case ARM::MOVTi16_ga_pcrel:
1408 case ARM::t2MOVTi16_ga_pcrel: {
1410 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1411 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1412 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1413 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1415 unsigned TF = MI->getOperand(2).getTargetFlags();
1416 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1417 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1418 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1420 MCSymbol *LabelSym =
1421 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1422 MI->getOperand(3).getImm(), OutContext);
1423 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1424 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1425 const MCExpr *PCRelExpr =
1426 ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
1427 MCBinaryExpr::createAdd(LabelSymExpr,
1428 MCConstantExpr::create(PCAdj, OutContext),
1429 OutContext), OutContext), OutContext);
1430 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1431 // Add predicate operands.
1432 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1433 TmpInst.addOperand(MCOperand::createReg(0));
1434 // Add 's' bit operand (always reg0 for this)
1435 TmpInst.addOperand(MCOperand::createReg(0));
1436 EmitToStreamer(*OutStreamer, TmpInst);
1439 case ARM::tPICADD: {
1440 // This is a pseudo op for a label + instruction sequence, which looks like:
1443 // This adds the address of LPC0 to r0.
1446 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1447 getFunctionNumber(),
1448 MI->getOperand(2).getImm(), OutContext));
1450 // Form and emit the add.
1451 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1452 .addReg(MI->getOperand(0).getReg())
1453 .addReg(MI->getOperand(0).getReg())
1455 // Add predicate operands.
1461 // This is a pseudo op for a label + instruction sequence, which looks like:
1464 // This adds the address of LPC0 to r0.
1467 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1468 getFunctionNumber(),
1469 MI->getOperand(2).getImm(), OutContext));
1471 // Form and emit the add.
1472 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1473 .addReg(MI->getOperand(0).getReg())
1475 .addReg(MI->getOperand(1).getReg())
1476 // Add predicate operands.
1477 .addImm(MI->getOperand(3).getImm())
1478 .addReg(MI->getOperand(4).getReg())
1479 // Add 's' bit operand (always reg0 for this)
1490 case ARM::PICLDRSH: {
1491 // This is a pseudo op for a label + instruction sequence, which looks like:
1494 // The LCP0 label is referenced by a constant pool entry in order to get
1495 // a PC-relative address at the ldr instruction.
1498 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1499 getFunctionNumber(),
1500 MI->getOperand(2).getImm(), OutContext));
1502 // Form and emit the load
1504 switch (MI->getOpcode()) {
1506 llvm_unreachable("Unexpected opcode!");
1507 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1508 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1509 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1510 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1511 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1512 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1513 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1514 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1516 EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1517 .addReg(MI->getOperand(0).getReg())
1519 .addReg(MI->getOperand(1).getReg())
1521 // Add predicate operands.
1522 .addImm(MI->getOperand(3).getImm())
1523 .addReg(MI->getOperand(4).getReg()));
1527 case ARM::CONSTPOOL_ENTRY: {
1528 if (Subtarget->genExecuteOnly())
1529 llvm_unreachable("execute-only should not generate constant pools");
1531 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1532 /// in the function. The first operand is the ID# for this instruction, the
1533 /// second is the index into the MachineConstantPool that this is, the third
1534 /// is the size in bytes of this constant pool entry.
1535 /// The required alignment is specified on the basic block holding this MI.
1536 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1537 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1539 // If this is the first entry of the pool, mark it.
1540 if (!InConstantPool) {
1541 OutStreamer->EmitDataRegion(MCDR_DataRegion);
1542 InConstantPool = true;
1545 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1547 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1548 if (MCPE.isMachineConstantPoolEntry())
1549 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1551 EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1554 case ARM::JUMPTABLE_ADDRS:
1555 EmitJumpTableAddrs(MI);
1557 case ARM::JUMPTABLE_INSTS:
1558 EmitJumpTableInsts(MI);
1560 case ARM::JUMPTABLE_TBB:
1561 case ARM::JUMPTABLE_TBH:
1562 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1564 case ARM::t2BR_JT: {
1565 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1567 .addReg(MI->getOperand(0).getReg())
1568 // Add predicate operands.
1574 case ARM::t2TBH_JT: {
1575 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1576 // Lower and emit the PC label, then the instruction itself.
1577 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1578 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1579 .addReg(MI->getOperand(0).getReg())
1580 .addReg(MI->getOperand(1).getReg())
1581 // Add predicate operands.
1587 case ARM::tTBH_JT: {
1589 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1590 unsigned Base = MI->getOperand(0).getReg();
1591 unsigned Idx = MI->getOperand(1).getReg();
1592 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1594 // Multiply up idx if necessary.
1596 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1601 // Add predicate operands.
1605 if (Base == ARM::PC) {
1606 // TBB [base, idx] =
1607 // ADDS idx, idx, base
1608 // LDRB idx, [idx, #4] ; or LDRH if TBH
1612 // When using PC as the base, it's important that there is no padding
1613 // between the last ADDS and the start of the jump table. The jump table
1614 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1616 // FIXME: Ideally we could vary the LDRB index based on the padding
1617 // between the sequence and jump table, however that relies on MCExprs
1618 // for load indexes which are currently not supported.
1619 OutStreamer->EmitCodeAlignment(4);
1620 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1624 // Add predicate operands.
1628 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1629 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1632 .addImm(Is8Bit ? 4 : 2)
1633 // Add predicate operands.
1637 // TBB [base, idx] =
1638 // LDRB idx, [base, idx] ; or LDRH if TBH
1642 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1643 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1647 // Add predicate operands.
1652 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1657 // Add predicate operands.
1661 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1662 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1666 // Add predicate operands.
1675 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1676 ARM::MOVr : ARM::tMOVr;
1677 TmpInst.setOpcode(Opc);
1678 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1679 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1680 // Add predicate operands.
1681 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1682 TmpInst.addOperand(MCOperand::createReg(0));
1683 // Add 's' bit operand (always reg0 for this)
1684 if (Opc == ARM::MOVr)
1685 TmpInst.addOperand(MCOperand::createReg(0));
1686 EmitToStreamer(*OutStreamer, TmpInst);
1689 case ARM::BR_JTm_i12: {
1692 TmpInst.setOpcode(ARM::LDRi12);
1693 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1694 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1695 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1696 // Add predicate operands.
1697 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1698 TmpInst.addOperand(MCOperand::createReg(0));
1699 EmitToStreamer(*OutStreamer, TmpInst);
1702 case ARM::BR_JTm_rs: {
1705 TmpInst.setOpcode(ARM::LDRrs);
1706 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1707 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1708 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1709 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1710 // Add predicate operands.
1711 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1712 TmpInst.addOperand(MCOperand::createReg(0));
1713 EmitToStreamer(*OutStreamer, TmpInst);
1716 case ARM::BR_JTadd: {
1717 // add pc, target, idx
1718 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1720 .addReg(MI->getOperand(0).getReg())
1721 .addReg(MI->getOperand(1).getReg())
1722 // Add predicate operands.
1725 // Add 's' bit operand (always reg0 for this)
1730 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1733 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1734 // FIXME: Remove this special case when they do.
1735 if (!Subtarget->isTargetMachO()) {
1736 uint32_t Val = 0xe7ffdefeUL;
1737 OutStreamer->AddComment("trap");
1743 case ARM::TRAPNaCl: {
1744 uint32_t Val = 0xe7fedef0UL;
1745 OutStreamer->AddComment("trap");
1750 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1751 // FIXME: Remove this special case when they do.
1752 if (!Subtarget->isTargetMachO()) {
1753 uint16_t Val = 0xdefe;
1754 OutStreamer->AddComment("trap");
1755 ATS.emitInst(Val, 'n');
1760 case ARM::t2Int_eh_sjlj_setjmp:
1761 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1762 case ARM::tInt_eh_sjlj_setjmp: {
1763 // Two incoming args: GPR:$src, GPR:$val
1766 // str $val, [$src, #4]
1771 unsigned SrcReg = MI->getOperand(0).getReg();
1772 unsigned ValReg = MI->getOperand(1).getReg();
1773 MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1774 OutStreamer->AddComment("eh_setjmp begin");
1775 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1782 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1792 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1795 // The offset immediate is #4. The operand value is scaled by 4 for the
1796 // tSTR instruction.
1802 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1810 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1811 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1812 .addExpr(SymbolExpr)
1816 OutStreamer->AddComment("eh_setjmp end");
1817 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1825 OutStreamer->EmitLabel(Label);
1829 case ARM::Int_eh_sjlj_setjmp_nofp:
1830 case ARM::Int_eh_sjlj_setjmp: {
1831 // Two incoming args: GPR:$src, GPR:$val
1833 // str $val, [$src, #+4]
1837 unsigned SrcReg = MI->getOperand(0).getReg();
1838 unsigned ValReg = MI->getOperand(1).getReg();
1840 OutStreamer->AddComment("eh_setjmp begin");
1841 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1848 // 's' bit operand (always reg0 for this).
1851 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
1859 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1865 // 's' bit operand (always reg0 for this).
1868 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1875 // 's' bit operand (always reg0 for this).
1878 OutStreamer->AddComment("eh_setjmp end");
1879 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1885 // 's' bit operand (always reg0 for this).
1889 case ARM::Int_eh_sjlj_longjmp: {
1890 // ldr sp, [$src, #8]
1891 // ldr $scratch, [$src, #4]
1894 unsigned SrcReg = MI->getOperand(0).getReg();
1895 unsigned ScratchReg = MI->getOperand(1).getReg();
1896 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1904 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1912 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1913 // These platforms always use the same frame register
1914 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1922 // If the calling code might use either R7 or R11 as
1923 // frame pointer register, restore it into both.
1924 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1931 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1940 assert(Subtarget->hasV4TOps());
1941 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1948 case ARM::tInt_eh_sjlj_longjmp: {
1949 // ldr $scratch, [$src, #8]
1951 // ldr $scratch, [$src, #4]
1954 unsigned SrcReg = MI->getOperand(0).getReg();
1955 unsigned ScratchReg = MI->getOperand(1).getReg();
1957 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1960 // The offset immediate is #8. The operand value is scaled by 4 for the
1961 // tLDR instruction.
1967 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1974 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1982 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1983 // These platforms always use the same frame register
1984 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1992 // If the calling code might use either R7 or R11 as
1993 // frame pointer register, restore it into both.
1994 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
2001 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
2010 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
2017 case ARM::tInt_WIN_eh_sjlj_longjmp: {
2018 // ldr.w r11, [$src, #0]
2019 // ldr.w sp, [$src, #8]
2020 // ldr.w pc, [$src, #4]
2022 unsigned SrcReg = MI->getOperand(0).getReg();
2024 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2031 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2038 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2047 case ARM::PATCHABLE_FUNCTION_ENTER:
2048 LowerPATCHABLE_FUNCTION_ENTER(*MI);
2050 case ARM::PATCHABLE_FUNCTION_EXIT:
2051 LowerPATCHABLE_FUNCTION_EXIT(*MI);
2053 case ARM::PATCHABLE_TAIL_CALL:
2054 LowerPATCHABLE_TAIL_CALL(*MI);
2059 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2061 EmitToStreamer(*OutStreamer, TmpInst);
2064 //===----------------------------------------------------------------------===//
2065 // Target Registry Stuff
2066 //===----------------------------------------------------------------------===//
2068 // Force static initialization.
2069 extern "C" void LLVMInitializeARMAsmPrinter() {
2070 RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
2071 RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
2072 RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
2073 RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());