1 //=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetOptions.h"
28 /// hasFP - Return true if the specified function should have a dedicated frame
29 /// pointer register. This is true if the function has variable sized allocas
30 /// or if frame pointer elimination is disabled.
31 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
32 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
34 // Mac OS X requires FP not to be clobbered for backtracing purpose.
35 if (STI.isTargetDarwin())
38 const MachineFrameInfo *MFI = MF.getFrameInfo();
39 // Always eliminate non-leaf frame pointers.
40 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
41 RegInfo->needsStackRealignment(MF) ||
42 MFI->hasVarSizedObjects() ||
43 MFI->isFrameAddressTaken());
46 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
47 /// not required, we reserve argument space for call sites in the function
48 /// immediately on entry to the current function. This eliminates the need for
49 /// add/sub sp brackets around call sites. Returns true if the call frame is
50 /// included as part of the stack frame.
51 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
52 const MachineFrameInfo *FFI = MF.getFrameInfo();
53 unsigned CFSize = FFI->getMaxCallFrameSize();
54 // It's not always a good idea to include the call frame as part of the
55 // stack frame. ARM (especially Thumb) has small immediate offset to
56 // address the stack frame. So a large call frame can cause poor codegen
57 // and may even makes it impossible to scavenge a register.
58 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
61 return !MF.getFrameInfo()->hasVarSizedObjects();
64 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
65 /// call frame pseudos can be simplified. Unlike most targets, having a FP
66 /// is not sufficient here since we still may reference some objects via SP
67 /// even when FP is available in Thumb2 mode.
69 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
70 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
73 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
74 for (unsigned i = 0; CSRegs[i]; ++i)
80 static bool isCSRestore(MachineInstr *MI,
81 const ARMBaseInstrInfo &TII,
82 const unsigned *CSRegs) {
83 // Integer spill area is handled with "pop".
84 if (MI->getOpcode() == ARM::LDMIA_RET ||
85 MI->getOpcode() == ARM::t2LDMIA_RET ||
86 MI->getOpcode() == ARM::LDMIA_UPD ||
87 MI->getOpcode() == ARM::t2LDMIA_UPD ||
88 MI->getOpcode() == ARM::VLDMDIA_UPD) {
89 // The first two operands are predicates. The last two are
90 // imp-def and imp-use of SP. Check everything in between.
91 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
92 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
96 if ((MI->getOpcode() == ARM::LDR_POST ||
97 MI->getOpcode() == ARM::t2LDR_POST) &&
98 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
99 MI->getOperand(1).getReg() == ARM::SP)
106 emitSPUpdate(bool isARM,
107 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
108 DebugLoc dl, const ARMBaseInstrInfo &TII,
109 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
111 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
112 ARMCC::AL, 0, TII, MIFlags);
114 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
115 ARMCC::AL, 0, TII, MIFlags);
118 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
119 MachineBasicBlock &MBB = MF.front();
120 MachineBasicBlock::iterator MBBI = MBB.begin();
121 MachineFrameInfo *MFI = MF.getFrameInfo();
122 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
123 const ARMBaseRegisterInfo *RegInfo =
124 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
125 const ARMBaseInstrInfo &TII =
126 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
127 assert(!AFI->isThumb1OnlyFunction() &&
128 "This emitPrologue does not support Thumb1!");
129 bool isARM = !AFI->isThumbFunction();
130 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
131 unsigned NumBytes = MFI->getStackSize();
132 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
133 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
134 unsigned FramePtr = RegInfo->getFrameRegister(MF);
136 // Determine the sizes of each callee-save spill areas and record which frame
137 // belongs to which callee-save spill areas.
138 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
139 int FramePtrSpillFI = 0;
141 // Allocate the vararg register save area. This is not counted in NumBytes.
143 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
144 MachineInstr::FrameSetup);
146 if (!AFI->hasStackFrame()) {
148 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
149 MachineInstr::FrameSetup);
153 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
154 unsigned Reg = CSI[i].getReg();
155 int FI = CSI[i].getFrameIdx();
163 FramePtrSpillFI = FI;
164 AFI->addGPRCalleeSavedArea1Frame(FI);
172 FramePtrSpillFI = FI;
173 if (STI.isTargetDarwin()) {
174 AFI->addGPRCalleeSavedArea2Frame(FI);
177 AFI->addGPRCalleeSavedArea1Frame(FI);
182 AFI->addDPRCalleeSavedAreaFrame(FI);
188 if (GPRCS1Size > 0) MBBI++;
190 // Set FP to point to the stack slot that contains the previous FP.
191 // For Darwin, FP is R7, which has now been stored in spill area 1.
192 // Otherwise, if this is not Darwin, all the callee-saved registers go
193 // into spill area 1, including the FP in R11. In either case, it is
194 // now safe to emit this assignment.
195 bool HasFP = hasFP(MF);
197 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
198 MachineInstrBuilder MIB =
199 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
200 .addFrameIndex(FramePtrSpillFI).addImm(0)
201 .setMIFlag(MachineInstr::FrameSetup);
202 AddDefaultCC(AddDefaultPred(MIB));
206 if (GPRCS2Size > 0) MBBI++;
208 // Determine starting offsets of spill areas.
209 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
210 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
211 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
213 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
215 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
216 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
217 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
222 // Since vpush register list cannot have gaps, there may be multiple vpush
223 // instructions in the prologue.
224 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
228 NumBytes = DPRCSOffset;
230 // Adjust SP after all the callee-save spills.
231 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
232 MachineInstr::FrameSetup);
234 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
235 // Note it's not safe to do this in Thumb2 mode because it would have
236 // taken two instructions:
239 // If an interrupt is taken between the two instructions, then sp is in
240 // an inconsistent state (pointing to the middle of callee-saved area).
241 // The interrupt handler can end up clobbering the registers.
242 AFI->setShouldRestoreSPFromFP(true);
245 if (STI.isTargetELF() && hasFP(MF))
246 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
247 AFI->getFramePtrSpillOffset());
249 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
250 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
251 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
253 // If we need dynamic stack realignment, do it here. Be paranoid and make
254 // sure if we also have VLAs, we have a base pointer for frame access.
255 if (RegInfo->needsStackRealignment(MF)) {
256 unsigned MaxAlign = MFI->getMaxAlignment();
257 assert (!AFI->isThumb1OnlyFunction());
258 if (!AFI->isThumbFunction()) {
259 // Emit bic sp, sp, MaxAlign
260 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
261 TII.get(ARM::BICri), ARM::SP)
262 .addReg(ARM::SP, RegState::Kill)
263 .addImm(MaxAlign-1)));
265 // We cannot use sp as source/dest register here, thus we're emitting the
266 // following sequence:
268 // bic r4, r4, MaxAlign
270 // FIXME: It will be better just to find spare register here.
271 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
272 .addReg(ARM::SP, RegState::Kill);
273 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
274 TII.get(ARM::t2BICri), ARM::R4)
275 .addReg(ARM::R4, RegState::Kill)
276 .addImm(MaxAlign-1)));
277 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
278 .addReg(ARM::R4, RegState::Kill);
281 AFI->setShouldRestoreSPFromFP(true);
284 // If we need a base pointer, set it up here. It's whatever the value
285 // of the stack pointer is at this point. Any variable size objects
286 // will be allocated after this, so we can still use the base pointer
287 // to reference locals.
288 // FIXME: Clarify FrameSetup flags here.
289 if (RegInfo->hasBasePointer(MF)) {
291 BuildMI(MBB, MBBI, dl,
292 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
294 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
296 BuildMI(MBB, MBBI, dl,
297 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
301 // If the frame has variable sized objects then the epilogue must restore
302 // the sp from fp. We can assume there's an FP here since hasFP already
303 // checks for hasVarSizedObjects.
304 if (MFI->hasVarSizedObjects())
305 AFI->setShouldRestoreSPFromFP(true);
308 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
309 MachineBasicBlock &MBB) const {
310 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
311 assert(MBBI->getDesc().isReturn() &&
312 "Can only insert epilog into returning blocks");
313 unsigned RetOpcode = MBBI->getOpcode();
314 DebugLoc dl = MBBI->getDebugLoc();
315 MachineFrameInfo *MFI = MF.getFrameInfo();
316 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
317 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
318 const ARMBaseInstrInfo &TII =
319 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
320 assert(!AFI->isThumb1OnlyFunction() &&
321 "This emitEpilogue does not support Thumb1!");
322 bool isARM = !AFI->isThumbFunction();
324 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
325 int NumBytes = (int)MFI->getStackSize();
326 unsigned FramePtr = RegInfo->getFrameRegister(MF);
328 if (!AFI->hasStackFrame()) {
330 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
332 // Unwind MBBI to point to first LDR / VLDRD.
333 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
334 if (MBBI != MBB.begin()) {
337 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
338 if (!isCSRestore(MBBI, TII, CSRegs))
342 // Move SP to start of FP callee save spill area.
343 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
344 AFI->getGPRCalleeSavedArea2Size() +
345 AFI->getDPRCalleeSavedAreaSize());
347 // Reset SP based on frame pointer only if the stack frame extends beyond
348 // frame pointer stack slot or target is ELF and the function has FP.
349 if (AFI->shouldRestoreSPFromFP()) {
350 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
353 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
356 // It's not possible to restore SP from FP in a single instruction.
357 // For Darwin, this looks like:
360 // This is bad, if an interrupt is taken after the mov, sp is in an
361 // inconsistent state.
362 // Use the first callee-saved register as a scratch register.
363 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
364 "No scratch register to restore SP from FP!");
365 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
367 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
373 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
374 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
376 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
380 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
382 // Increment past our save areas.
383 if (AFI->getDPRCalleeSavedAreaSize()) {
385 // Since vpop register list cannot have gaps, there may be multiple vpop
386 // instructions in the epilogue.
387 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
390 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
391 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
394 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
395 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
396 // Tail call return: adjust the stack pointer and jump to callee.
397 MBBI = MBB.getLastNonDebugInstr();
398 MachineOperand &JumpTarget = MBBI->getOperand(0);
400 // Jump to label or value in register.
401 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) {
402 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi)
403 ? (STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)
404 : (STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND);
405 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
406 if (JumpTarget.isGlobal())
407 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
408 JumpTarget.getTargetFlags());
410 assert(JumpTarget.isSymbol());
411 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
412 JumpTarget.getTargetFlags());
414 } else if (RetOpcode == ARM::TCRETURNri) {
415 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
416 addReg(JumpTarget.getReg(), RegState::Kill);
417 } else if (RetOpcode == ARM::TCRETURNriND) {
418 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
419 addReg(JumpTarget.getReg(), RegState::Kill);
422 MachineInstr *NewMI = prior(MBBI);
423 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
424 NewMI->addOperand(MBBI->getOperand(i));
426 // Delete the pseudo instruction TCRETURN.
431 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
434 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
435 /// debug info. It's the same as what we use for resolving the code-gen
436 /// references for now. FIXME: This can go wrong when references are
437 /// SP-relative and simple call frames aren't used.
439 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
440 unsigned &FrameReg) const {
441 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
445 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
449 const MachineFrameInfo *MFI = MF.getFrameInfo();
450 const ARMBaseRegisterInfo *RegInfo =
451 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
452 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
453 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
454 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
455 bool isFixed = MFI->isFixedObjectIndex(FI);
459 if (AFI->isGPRCalleeSavedArea1Frame(FI))
460 return Offset - AFI->getGPRCalleeSavedArea1Offset();
461 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
462 return Offset - AFI->getGPRCalleeSavedArea2Offset();
463 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
464 return Offset - AFI->getDPRCalleeSavedAreaOffset();
466 // When dynamically realigning the stack, use the frame pointer for
467 // parameters, and the stack/base pointer for locals.
468 if (RegInfo->needsStackRealignment(MF)) {
469 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
471 FrameReg = RegInfo->getFrameRegister(MF);
473 } else if (MFI->hasVarSizedObjects()) {
474 assert(RegInfo->hasBasePointer(MF) &&
475 "VLAs and dynamic stack alignment, but missing base pointer!");
476 FrameReg = RegInfo->getBaseRegister();
481 // If there is a frame pointer, use it when we can.
482 if (hasFP(MF) && AFI->hasStackFrame()) {
483 // Use frame pointer to reference fixed objects. Use it for locals if
484 // there are VLAs (and thus the SP isn't reliable as a base).
485 if (isFixed || (MFI->hasVarSizedObjects() &&
486 !RegInfo->hasBasePointer(MF))) {
487 FrameReg = RegInfo->getFrameRegister(MF);
489 } else if (MFI->hasVarSizedObjects()) {
490 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
491 // Try to use the frame pointer if we can, else use the base pointer
492 // since it's available. This is handy for the emergency spill slot, in
494 if (AFI->isThumb2Function()) {
495 if (FPOffset >= -255 && FPOffset < 0) {
496 FrameReg = RegInfo->getFrameRegister(MF);
500 FrameReg = RegInfo->getBaseRegister();
501 } else if (AFI->isThumb2Function()) {
502 // In Thumb2 mode, the negative offset is very limited. Try to avoid
503 // out of range references.
504 if (FPOffset >= -255 && FPOffset < 0) {
505 FrameReg = RegInfo->getFrameRegister(MF);
508 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
509 // Otherwise, use SP or FP, whichever is closer to the stack slot.
510 FrameReg = RegInfo->getFrameRegister(MF);
514 // Use the base pointer if we have one.
515 if (RegInfo->hasBasePointer(MF))
516 FrameReg = RegInfo->getBaseRegister();
520 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
523 return getFrameIndexReference(MF, FI, FrameReg);
526 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
527 MachineBasicBlock::iterator MI,
528 const std::vector<CalleeSavedInfo> &CSI,
529 unsigned StmOpc, unsigned StrOpc,
531 bool(*Func)(unsigned, bool),
532 unsigned MIFlags) const {
533 MachineFunction &MF = *MBB.getParent();
534 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
537 if (MI != MBB.end()) DL = MI->getDebugLoc();
539 SmallVector<std::pair<unsigned,bool>, 4> Regs;
540 unsigned i = CSI.size();
542 unsigned LastReg = 0;
543 for (; i != 0; --i) {
544 unsigned Reg = CSI[i-1].getReg();
545 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
547 // Add the callee-saved register as live-in unless it's LR and
548 // @llvm.returnaddress is called. If LR is returned for
549 // @llvm.returnaddress then it's already added to the function and
550 // entry block live-in sets.
552 if (Reg == ARM::LR) {
553 if (MF.getFrameInfo()->isReturnAddressTaken() &&
554 MF.getRegInfo().isLiveIn(Reg))
561 // If NoGap is true, push consecutive registers and then leave the rest
562 // for other instructions. e.g.
563 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
564 if (NoGap && LastReg && LastReg != Reg-1)
567 Regs.push_back(std::make_pair(Reg, isKill));
572 if (Regs.size() > 1 || StrOpc== 0) {
573 MachineInstrBuilder MIB =
574 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
575 .addReg(ARM::SP).setMIFlags(MIFlags));
576 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
577 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
578 } else if (Regs.size() == 1) {
579 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
581 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
582 .addReg(ARM::SP).setMIFlags(MIFlags);
583 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
584 // that refactoring is complete (eventually).
585 if (StrOpc == ARM::STR_PRE) {
587 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift));
596 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
597 MachineBasicBlock::iterator MI,
598 const std::vector<CalleeSavedInfo> &CSI,
599 unsigned LdmOpc, unsigned LdrOpc,
600 bool isVarArg, bool NoGap,
601 bool(*Func)(unsigned, bool)) const {
602 MachineFunction &MF = *MBB.getParent();
603 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
604 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
605 DebugLoc DL = MI->getDebugLoc();
606 unsigned RetOpcode = MI->getOpcode();
607 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
608 RetOpcode == ARM::TCRETURNdiND ||
609 RetOpcode == ARM::TCRETURNri ||
610 RetOpcode == ARM::TCRETURNriND);
612 SmallVector<unsigned, 4> Regs;
613 unsigned i = CSI.size();
615 unsigned LastReg = 0;
616 bool DeleteRet = false;
617 for (; i != 0; --i) {
618 unsigned Reg = CSI[i-1].getReg();
619 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
621 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
623 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
624 // Fold the return instruction into the LDM.
628 // If NoGap is true, pop consecutive registers and then leave the rest
629 // for other instructions. e.g.
630 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
631 if (NoGap && LastReg && LastReg != Reg-1)
640 if (Regs.size() > 1 || LdrOpc == 0) {
641 MachineInstrBuilder MIB =
642 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
644 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
645 MIB.addReg(Regs[i], getDefRegState(true));
647 MI->eraseFromParent();
649 } else if (Regs.size() == 1) {
650 // If we adjusted the reg to PC from LR above, switch it back here. We
651 // only do that for LDM.
652 if (Regs[0] == ARM::PC)
654 MachineInstrBuilder MIB =
655 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
656 .addReg(ARM::SP, RegState::Define)
658 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
659 // that refactoring is complete (eventually).
660 if (LdrOpc == ARM::LDR_POST) {
662 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
671 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
672 MachineBasicBlock::iterator MI,
673 const std::vector<CalleeSavedInfo> &CSI,
674 const TargetRegisterInfo *TRI) const {
678 MachineFunction &MF = *MBB.getParent();
679 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
681 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
682 unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;
683 unsigned FltOpc = ARM::VSTMDDB_UPD;
684 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register,
685 MachineInstr::FrameSetup);
686 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register,
687 MachineInstr::FrameSetup);
688 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
689 MachineInstr::FrameSetup);
694 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
695 MachineBasicBlock::iterator MI,
696 const std::vector<CalleeSavedInfo> &CSI,
697 const TargetRegisterInfo *TRI) const {
701 MachineFunction &MF = *MBB.getParent();
702 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
703 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
705 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
706 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST;
707 unsigned FltOpc = ARM::VLDMDIA_UPD;
708 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);
709 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
710 &isARMArea2Register);
711 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
712 &isARMArea1Register);
717 // FIXME: Make generic?
718 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
719 const ARMBaseInstrInfo &TII) {
721 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
723 const MachineBasicBlock &MBB = *MBBI;
724 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
726 FnSize += TII.GetInstSizeInBytes(I);
731 /// estimateStackSize - Estimate and return the size of the frame.
732 /// FIXME: Make generic?
733 static unsigned estimateStackSize(MachineFunction &MF) {
734 const MachineFrameInfo *FFI = MF.getFrameInfo();
736 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
737 int FixedOff = -FFI->getObjectOffset(i);
738 if (FixedOff > Offset) Offset = FixedOff;
740 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
741 if (FFI->isDeadObjectIndex(i))
743 Offset += FFI->getObjectSize(i);
744 unsigned Align = FFI->getObjectAlignment(i);
745 // Adjust to alignment boundary
746 Offset = (Offset+Align-1)/Align*Align;
748 return (unsigned)Offset;
751 /// estimateRSStackSizeLimit - Look at each instruction that references stack
752 /// frames and return the stack size limit beyond which some of these
753 /// instructions will require a scratch register during their expansion later.
754 // FIXME: Move to TII?
755 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
756 const TargetFrameLowering *TFI) {
757 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
758 unsigned Limit = (1 << 12) - 1;
759 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
760 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
762 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
763 if (!I->getOperand(i).isFI()) continue;
765 // When using ADDri to get the address of a stack object, 255 is the
766 // largest offset guaranteed to fit in the immediate offset.
767 if (I->getOpcode() == ARM::ADDri) {
768 Limit = std::min(Limit, (1U << 8) - 1);
772 // Otherwise check the addressing mode.
773 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
774 case ARMII::AddrMode3:
775 case ARMII::AddrModeT2_i8:
776 Limit = std::min(Limit, (1U << 8) - 1);
778 case ARMII::AddrMode5:
779 case ARMII::AddrModeT2_i8s4:
780 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
782 case ARMII::AddrModeT2_i12:
783 // i12 supports only positive offset so these will be converted to
784 // i8 opcodes. See llvm::rewriteT2FrameIndex.
785 if (TFI->hasFP(MF) && AFI->hasStackFrame())
786 Limit = std::min(Limit, (1U << 8) - 1);
788 case ARMII::AddrMode4:
789 case ARMII::AddrMode6:
790 // Addressing modes 4 & 6 (load/store) instructions can't encode an
791 // immediate offset for stack references.
796 break; // At most one FI per instruction
805 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
806 RegScavenger *RS) const {
807 // This tells PEI to spill the FP as if it is any other callee-save register
808 // to take advantage the eliminateFrameIndex machinery. This also ensures it
809 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
810 // to combine multiple loads / stores.
811 bool CanEliminateFrame = true;
812 bool CS1Spilled = false;
813 bool LRSpilled = false;
814 unsigned NumGPRSpills = 0;
815 SmallVector<unsigned, 4> UnspilledCS1GPRs;
816 SmallVector<unsigned, 4> UnspilledCS2GPRs;
817 const ARMBaseRegisterInfo *RegInfo =
818 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
819 const ARMBaseInstrInfo &TII =
820 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
821 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
822 MachineFrameInfo *MFI = MF.getFrameInfo();
823 unsigned FramePtr = RegInfo->getFrameRegister(MF);
825 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
826 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
827 // since it's not always possible to restore sp from fp in a single
829 // FIXME: It will be better just to find spare register here.
830 if (AFI->isThumb2Function() &&
831 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
832 MF.getRegInfo().setPhysRegUsed(ARM::R4);
834 if (AFI->isThumb1OnlyFunction()) {
835 // Spill LR if Thumb1 function uses variable length argument lists.
836 if (AFI->getVarArgsRegSaveSize() > 0)
837 MF.getRegInfo().setPhysRegUsed(ARM::LR);
839 // Spill R4 if Thumb1 epilogue has to restore SP from FP since
840 // FIXME: It will be better just to find spare register here.
841 if (MFI->hasVarSizedObjects())
842 MF.getRegInfo().setPhysRegUsed(ARM::R4);
845 // Spill the BasePtr if it's used.
846 if (RegInfo->hasBasePointer(MF))
847 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
849 // Don't spill FP if the frame can be eliminated. This is determined
850 // by scanning the callee-save registers to see if any is used.
851 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
852 for (unsigned i = 0; CSRegs[i]; ++i) {
853 unsigned Reg = CSRegs[i];
854 bool Spilled = false;
855 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
857 CanEliminateFrame = false;
859 // Check alias registers too.
860 for (const unsigned *Aliases =
861 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) {
862 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
864 CanEliminateFrame = false;
869 if (!ARM::GPRRegisterClass->contains(Reg))
875 if (!STI.isTargetDarwin()) {
882 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
887 case ARM::R4: case ARM::R5:
888 case ARM::R6: case ARM::R7:
895 if (!STI.isTargetDarwin()) {
896 UnspilledCS1GPRs.push_back(Reg);
901 case ARM::R4: case ARM::R5:
902 case ARM::R6: case ARM::R7:
904 UnspilledCS1GPRs.push_back(Reg);
907 UnspilledCS2GPRs.push_back(Reg);
913 bool ForceLRSpill = false;
914 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
915 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
916 // Force LR to be spilled if the Thumb function size is > 2048. This enables
917 // use of BL to implement far jump. If it turns out that it's not needed
918 // then the branch fix up path will undo it.
919 if (FnSize >= (1 << 11)) {
920 CanEliminateFrame = false;
925 // If any of the stack slot references may be out of range of an immediate
926 // offset, make sure a register (or a spill slot) is available for the
927 // register scavenger. Note that if we're indexing off the frame pointer, the
928 // effective stack size is 4 bytes larger since the FP points to the stack
929 // slot of the previous FP. Also, if we have variable sized objects in the
930 // function, stack slot references will often be negative, and some of
931 // our instructions are positive-offset only, so conservatively consider
932 // that case to want a spill slot (or register) as well. Similarly, if
933 // the function adjusts the stack pointer during execution and the
934 // adjustments aren't already part of our stack size estimate, our offset
935 // calculations may be off, so be conservative.
936 // FIXME: We could add logic to be more precise about negative offsets
937 // and which instructions will need a scratch register for them. Is it
938 // worth the effort and added fragility?
941 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
942 estimateRSStackSizeLimit(MF, this)))
943 || MFI->hasVarSizedObjects()
944 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
946 bool ExtraCSSpill = false;
947 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
948 AFI->setHasStackFrame(true);
950 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
951 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
952 if (!LRSpilled && CS1Spilled) {
953 MF.getRegInfo().setPhysRegUsed(ARM::LR);
955 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
956 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
957 ForceLRSpill = false;
962 MF.getRegInfo().setPhysRegUsed(FramePtr);
966 // If stack and double are 8-byte aligned and we are spilling an odd number
967 // of GPRs, spill one extra callee save GPR so we won't have to pad between
968 // the integer and double callee save areas.
969 unsigned TargetAlign = getStackAlignment();
970 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
971 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
972 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
973 unsigned Reg = UnspilledCS1GPRs[i];
974 // Don't spill high register if the function is thumb1
975 if (!AFI->isThumb1OnlyFunction() ||
976 isARMLowRegister(Reg) || Reg == ARM::LR) {
977 MF.getRegInfo().setPhysRegUsed(Reg);
978 if (!RegInfo->isReservedReg(MF, Reg))
983 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
984 unsigned Reg = UnspilledCS2GPRs.front();
985 MF.getRegInfo().setPhysRegUsed(Reg);
986 if (!RegInfo->isReservedReg(MF, Reg))
991 // Estimate if we might need to scavenge a register at some point in order
992 // to materialize a stack offset. If so, either spill one additional
993 // callee-saved register or reserve a special spill slot to facilitate
994 // register scavenging. Thumb1 needs a spill slot for stack pointer
995 // adjustments also, even when the frame itself is small.
996 if (BigStack && !ExtraCSSpill) {
997 // If any non-reserved CS register isn't spilled, just spill one or two
998 // extra. That should take care of it!
999 unsigned NumExtras = TargetAlign / 4;
1000 SmallVector<unsigned, 2> Extras;
1001 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1002 unsigned Reg = UnspilledCS1GPRs.back();
1003 UnspilledCS1GPRs.pop_back();
1004 if (!RegInfo->isReservedReg(MF, Reg) &&
1005 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1007 Extras.push_back(Reg);
1011 // For non-Thumb1 functions, also check for hi-reg CS registers
1012 if (!AFI->isThumb1OnlyFunction()) {
1013 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1014 unsigned Reg = UnspilledCS2GPRs.back();
1015 UnspilledCS2GPRs.pop_back();
1016 if (!RegInfo->isReservedReg(MF, Reg)) {
1017 Extras.push_back(Reg);
1022 if (Extras.size() && NumExtras == 0) {
1023 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1024 MF.getRegInfo().setPhysRegUsed(Extras[i]);
1026 } else if (!AFI->isThumb1OnlyFunction()) {
1027 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1028 // closest to SP or frame pointer.
1029 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
1030 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1038 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1039 AFI->setLRIsSpilledForFarJump(true);