1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
152 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
154 // Use VSTM to store a Q register as a D register pair.
155 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
157 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
159 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
161 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
163 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
165 // Classes for VLD* pseudo-instructions with multi-register operands.
166 // These are expanded to real instructions after register allocation.
167 class VLDQPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
169 class VLDQWBPseudo<InstrItinClass itin>
170 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
171 (ins addrmode6:$addr, am6offset:$offset), itin,
173 class VLDQQPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
175 class VLDQQWBPseudo<InstrItinClass itin>
176 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
177 (ins addrmode6:$addr, am6offset:$offset), itin,
179 class VLDQQQQWBPseudo<InstrItinClass itin>
180 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
181 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
182 "$addr.addr = $wb, $src = $dst">;
184 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
186 // VLD1 : Vector Load (multiple single elements)
187 class VLD1D<bits<4> op7_4, string Dt>
188 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
189 (ins addrmode6:$Rn), IIC_VLD1,
190 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
194 class VLD1Q<bits<4> op7_4, string Dt>
195 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
196 (ins addrmode6:$Rn), IIC_VLD1x2,
197 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
199 let Inst{5-4} = Rn{5-4};
202 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
203 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
204 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
205 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
207 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
208 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
209 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
210 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
212 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
213 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
214 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
215 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
217 // ...with address register writeback:
218 class VLD1DWB<bits<4> op7_4, string Dt>
219 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
220 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
221 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
222 "$Rn.addr = $wb", []> {
225 class VLD1QWB<bits<4> op7_4, string Dt>
226 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
227 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
228 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
229 "$Rn.addr = $wb", []> {
230 let Inst{5-4} = Rn{5-4};
233 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
234 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
235 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
236 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
238 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
239 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
240 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
241 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
243 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
244 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
245 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
246 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
248 // ...with 3 registers (some of these are only for the disassembler):
249 class VLD1D3<bits<4> op7_4, string Dt>
250 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
251 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
252 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
256 class VLD1D3WB<bits<4> op7_4, string Dt>
257 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
258 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
259 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
263 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
264 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
265 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
266 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
268 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
269 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
270 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
271 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
273 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
274 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
276 // ...with 4 registers (some of these are only for the disassembler):
277 class VLD1D4<bits<4> op7_4, string Dt>
278 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
279 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
280 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
282 let Inst{5-4} = Rn{5-4};
284 class VLD1D4WB<bits<4> op7_4, string Dt>
285 : NLdSt<0,0b10,0b0010,op7_4,
286 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
287 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4, "vld1", Dt,
288 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
290 let Inst{5-4} = Rn{5-4};
293 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
294 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
295 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
296 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
298 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
299 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
300 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
301 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
303 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
304 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
306 // VLD2 : Vector Load (multiple 2-element structures)
307 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
308 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
309 (ins addrmode6:$Rn), IIC_VLD2,
310 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
312 let Inst{5-4} = Rn{5-4};
314 class VLD2Q<bits<4> op7_4, string Dt>
315 : NLdSt<0, 0b10, 0b0011, op7_4,
316 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
317 (ins addrmode6:$Rn), IIC_VLD2x2,
318 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
320 let Inst{5-4} = Rn{5-4};
323 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
324 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
325 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
327 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
328 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
329 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
331 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
332 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
333 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
335 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
336 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
337 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
339 // ...with address register writeback:
340 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
341 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
342 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
343 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
344 "$Rn.addr = $wb", []> {
345 let Inst{5-4} = Rn{5-4};
347 class VLD2QWB<bits<4> op7_4, string Dt>
348 : NLdSt<0, 0b10, 0b0011, op7_4,
349 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
350 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
351 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
352 "$Rn.addr = $wb", []> {
353 let Inst{5-4} = Rn{5-4};
356 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
357 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
358 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
360 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
361 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
362 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
364 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
365 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
366 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
368 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
369 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
370 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
372 // ...with double-spaced registers (for disassembly only):
373 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
374 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
375 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
376 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
377 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
378 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
380 // VLD3 : Vector Load (multiple 3-element structures)
381 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
382 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
383 (ins addrmode6:$Rn), IIC_VLD3,
384 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
389 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
390 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
391 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
393 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
394 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
395 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
397 // ...with address register writeback:
398 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
399 : NLdSt<0, 0b10, op11_8, op7_4,
400 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
401 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
402 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
403 "$Rn.addr = $wb", []> {
407 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
408 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
409 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
411 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
412 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
413 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
415 // ...with double-spaced registers (non-updating versions for disassembly only):
416 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
417 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
418 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
419 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
420 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
421 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
423 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
424 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
425 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 // ...alternate versions to be allocated odd register numbers:
428 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
429 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
430 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
432 // VLD4 : Vector Load (multiple 4-element structures)
433 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
434 : NLdSt<0, 0b10, op11_8, op7_4,
435 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
436 (ins addrmode6:$Rn), IIC_VLD4,
437 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
439 let Inst{5-4} = Rn{5-4};
442 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
443 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
444 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
446 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
447 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
448 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
450 // ...with address register writeback:
451 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
452 : NLdSt<0, 0b10, op11_8, op7_4,
453 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
454 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4,
455 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
456 "$Rn.addr = $wb", []> {
457 let Inst{5-4} = Rn{5-4};
460 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
461 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
462 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
464 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
465 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
466 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
468 // ...with double-spaced registers (non-updating versions for disassembly only):
469 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
470 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
471 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
472 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
473 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
474 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
476 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
477 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
478 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
480 // ...alternate versions to be allocated odd register numbers:
481 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
482 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
483 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4>;
485 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
487 // Classes for VLD*LN pseudo-instructions with multi-register operands.
488 // These are expanded to real instructions after register allocation.
489 class VLDQLNPseudo<InstrItinClass itin>
490 : PseudoNLdSt<(outs QPR:$dst),
491 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
492 itin, "$src = $dst">;
493 class VLDQLNWBPseudo<InstrItinClass itin>
494 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
495 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
496 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
497 class VLDQQLNPseudo<InstrItinClass itin>
498 : PseudoNLdSt<(outs QQPR:$dst),
499 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
500 itin, "$src = $dst">;
501 class VLDQQLNWBPseudo<InstrItinClass itin>
502 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
503 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
504 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
505 class VLDQQQQLNPseudo<InstrItinClass itin>
506 : PseudoNLdSt<(outs QQQQPR:$dst),
507 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
508 itin, "$src = $dst">;
509 class VLDQQQQLNWBPseudo<InstrItinClass itin>
510 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
511 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
512 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
514 // VLD1LN : Vector Load (single element to one lane)
515 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
517 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
518 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
519 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
521 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
522 (i32 (LoadOp addrmode6:$Rn)),
526 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
527 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
528 (i32 (LoadOp addrmode6:$addr)),
532 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
533 let Inst{7-5} = lane{2-0};
535 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
536 let Inst{7-6} = lane{1-0};
539 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
540 let Inst{7} = lane{0};
545 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
546 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
547 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
549 def : Pat<(vector_insert (v2f32 DPR:$src),
550 (f32 (load addrmode6:$addr)), imm:$lane),
551 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
552 def : Pat<(vector_insert (v4f32 QPR:$src),
553 (f32 (load addrmode6:$addr)), imm:$lane),
554 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
556 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
558 // ...with address register writeback:
559 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
560 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
561 (ins addrmode6:$Rn, am6offset:$Rm,
562 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
563 "\\{$Vd[$lane]\\}, $Rn$Rm",
564 "$src = $Vd, $Rn.addr = $wb", []>;
566 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
567 let Inst{7-5} = lane{2-0};
569 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
570 let Inst{7-6} = lane{1-0};
573 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
574 let Inst{7} = lane{0};
579 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
580 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
581 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
583 // VLD2LN : Vector Load (single 2-element structure to one lane)
584 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
585 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
586 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
587 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
588 "$src1 = $Vd, $src2 = $dst2", []> {
593 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
594 let Inst{7-5} = lane{2-0};
596 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
597 let Inst{7-6} = lane{1-0};
599 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
600 let Inst{7} = lane{0};
603 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
604 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
605 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
607 // ...with double-spaced registers:
608 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
609 let Inst{7-6} = lane{1-0};
611 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
612 let Inst{7} = lane{0};
615 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
616 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
618 // ...with address register writeback:
619 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
620 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
621 (ins addrmode6:$Rn, am6offset:$Rm,
622 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
623 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
624 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
628 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
629 let Inst{7-5} = lane{2-0};
631 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
632 let Inst{7-6} = lane{1-0};
634 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
635 let Inst{7} = lane{0};
638 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
639 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
640 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
642 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
643 let Inst{7-6} = lane{1-0};
645 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
646 let Inst{7} = lane{0};
649 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
650 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
652 // VLD3LN : Vector Load (single 3-element structure to one lane)
653 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
654 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
655 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
656 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
657 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
658 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
662 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
663 let Inst{7-5} = lane{2-0};
665 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
666 let Inst{7-6} = lane{1-0};
668 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
669 let Inst{7} = lane{0};
672 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
673 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
674 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
676 // ...with double-spaced registers:
677 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
678 let Inst{7-6} = lane{1-0};
680 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
681 let Inst{7} = lane{0};
684 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
685 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
687 // ...with address register writeback:
688 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
689 : NLdStLn<1, 0b10, op11_8, op7_4,
690 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
691 (ins addrmode6:$Rn, am6offset:$Rm,
692 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
693 IIC_VLD3lnu, "vld3", Dt,
694 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
695 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
698 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
699 let Inst{7-5} = lane{2-0};
701 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
702 let Inst{7-6} = lane{1-0};
704 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
705 let Inst{7} = lane{0};
708 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
709 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
710 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
712 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
713 let Inst{7-6} = lane{1-0};
715 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
716 let Inst{7} = lane{0};
719 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
720 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
722 // VLD4LN : Vector Load (single 4-element structure to one lane)
723 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
724 : NLdStLn<1, 0b10, op11_8, op7_4,
725 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
726 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
727 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
728 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
729 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
734 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
735 let Inst{7-5} = lane{2-0};
737 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
738 let Inst{7-6} = lane{1-0};
740 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
741 let Inst{7} = lane{0};
745 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
746 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
747 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
749 // ...with double-spaced registers:
750 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
751 let Inst{7-6} = lane{1-0};
753 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
754 let Inst{7} = lane{0};
758 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
759 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
761 // ...with address register writeback:
762 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
763 : NLdStLn<1, 0b10, op11_8, op7_4,
764 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
765 (ins addrmode6:$Rn, am6offset:$Rm,
766 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
767 IIC_VLD4ln, "vld4", Dt,
768 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
769 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
774 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
775 let Inst{7-5} = lane{2-0};
777 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
778 let Inst{7-6} = lane{1-0};
780 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
781 let Inst{7} = lane{0};
785 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
786 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
787 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
789 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
790 let Inst{7-6} = lane{1-0};
792 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
793 let Inst{7} = lane{0};
797 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
798 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
800 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
802 // VLD1DUP : Vector Load (single element to all lanes)
803 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
804 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
805 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
806 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
810 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
811 let Pattern = [(set QPR:$dst,
812 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
815 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
816 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
817 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
819 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
820 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
821 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
823 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
824 (VLD1DUPd32 addrmode6:$addr)>;
825 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
826 (VLD1DUPq32Pseudo addrmode6:$addr)>;
828 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
830 class VLD1QDUP<bits<4> op7_4, string Dt>
831 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
832 (ins addrmode6dup:$Rn), IIC_VLD1dup,
833 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
838 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
839 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
840 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
842 // ...with address register writeback:
843 class VLD1DUPWB<bits<4> op7_4, string Dt>
844 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
845 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
846 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
849 class VLD1QDUPWB<bits<4> op7_4, string Dt>
850 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
851 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
852 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
856 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
857 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
858 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
860 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
861 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
862 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
864 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
865 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
866 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
868 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
869 class VLD2DUP<bits<4> op7_4, string Dt>
870 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
871 (ins addrmode6dup:$Rn), IIC_VLD2dup,
872 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
877 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
878 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
879 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
881 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
882 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
883 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
885 // ...with double-spaced registers (not used for codegen):
886 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
887 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
888 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
890 // ...with address register writeback:
891 class VLD2DUPWB<bits<4> op7_4, string Dt>
892 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
893 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
894 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
898 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
899 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
900 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
902 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
903 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
904 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
906 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
907 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
908 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
910 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
911 class VLD3DUP<bits<4> op7_4, string Dt>
912 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
913 (ins addrmode6dup:$Rn), IIC_VLD3dup,
914 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
919 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
920 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
921 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
923 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
924 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
925 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
927 // ...with double-spaced registers (not used for codegen):
928 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
929 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
930 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
932 // ...with address register writeback:
933 class VLD3DUPWB<bits<4> op7_4, string Dt>
934 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
935 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
936 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
937 "$Rn.addr = $wb", []> {
941 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
942 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
943 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
945 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
946 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
947 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
949 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
950 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
951 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
953 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
954 class VLD4DUP<bits<4> op7_4, string Dt>
955 : NLdSt<1, 0b10, 0b1111, op7_4,
956 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
957 (ins addrmode6dup:$Rn), IIC_VLD4dup,
958 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
963 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
964 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
965 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
967 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
968 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
969 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
971 // ...with double-spaced registers (not used for codegen):
972 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
973 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
974 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
976 // ...with address register writeback:
977 class VLD4DUPWB<bits<4> op7_4, string Dt>
978 : NLdSt<1, 0b10, 0b1111, op7_4,
979 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
980 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
981 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
982 "$Rn.addr = $wb", []> {
986 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
987 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
988 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
990 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
991 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
992 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
994 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
995 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
996 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
998 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1000 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1002 // Classes for VST* pseudo-instructions with multi-register operands.
1003 // These are expanded to real instructions after register allocation.
1004 class VSTQPseudo<InstrItinClass itin>
1005 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1006 class VSTQWBPseudo<InstrItinClass itin>
1007 : PseudoNLdSt<(outs GPR:$wb),
1008 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1009 "$addr.addr = $wb">;
1010 class VSTQQPseudo<InstrItinClass itin>
1011 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1012 class VSTQQWBPseudo<InstrItinClass itin>
1013 : PseudoNLdSt<(outs GPR:$wb),
1014 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1015 "$addr.addr = $wb">;
1016 class VSTQQQQWBPseudo<InstrItinClass itin>
1017 : PseudoNLdSt<(outs GPR:$wb),
1018 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1019 "$addr.addr = $wb">;
1021 // VST1 : Vector Store (multiple single elements)
1022 class VST1D<bits<4> op7_4, string Dt>
1023 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1024 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1026 let Inst{4} = Rn{4};
1028 class VST1Q<bits<4> op7_4, string Dt>
1029 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1030 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1031 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1033 let Inst{5-4} = Rn{5-4};
1036 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1037 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1038 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1039 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1041 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1042 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1043 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1044 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1046 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1047 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1048 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1049 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1051 // ...with address register writeback:
1052 class VST1DWB<bits<4> op7_4, string Dt>
1053 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1054 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1055 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1056 let Inst{4} = Rn{4};
1058 class VST1QWB<bits<4> op7_4, string Dt>
1059 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1060 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1061 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1062 "$Rn.addr = $wb", []> {
1063 let Inst{5-4} = Rn{5-4};
1066 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1067 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1068 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1069 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1071 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1072 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1073 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1074 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1076 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1077 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1078 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1079 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1081 // ...with 3 registers (some of these are only for the disassembler):
1082 class VST1D3<bits<4> op7_4, string Dt>
1083 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1084 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1085 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1087 let Inst{4} = Rn{4};
1089 class VST1D3WB<bits<4> op7_4, string Dt>
1090 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1091 (ins addrmode6:$Rn, am6offset:$Rm,
1092 DPR:$Vd, DPR:$src2, DPR:$src3),
1093 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1094 "$Rn.addr = $wb", []> {
1095 let Inst{4} = Rn{4};
1098 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1099 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1100 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1101 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1103 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1104 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1105 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1106 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1108 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1109 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1111 // ...with 4 registers (some of these are only for the disassembler):
1112 class VST1D4<bits<4> op7_4, string Dt>
1113 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1114 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1115 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1118 let Inst{5-4} = Rn{5-4};
1120 class VST1D4WB<bits<4> op7_4, string Dt>
1121 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1122 (ins addrmode6:$Rn, am6offset:$Rm,
1123 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1124 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1125 "$Rn.addr = $wb", []> {
1126 let Inst{5-4} = Rn{5-4};
1129 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1130 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1131 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1132 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1134 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1135 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1136 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1137 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1139 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1140 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1142 // VST2 : Vector Store (multiple 2-element structures)
1143 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1144 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1145 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1146 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1148 let Inst{5-4} = Rn{5-4};
1150 class VST2Q<bits<4> op7_4, string Dt>
1151 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1152 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1153 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1156 let Inst{5-4} = Rn{5-4};
1159 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1160 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1161 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1163 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1164 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1165 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1167 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1168 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1169 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1171 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1172 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1173 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1175 // ...with address register writeback:
1176 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1177 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1178 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1179 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1180 "$Rn.addr = $wb", []> {
1181 let Inst{5-4} = Rn{5-4};
1183 class VST2QWB<bits<4> op7_4, string Dt>
1184 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1185 (ins addrmode6:$Rn, am6offset:$Rm,
1186 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1187 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1188 "$Rn.addr = $wb", []> {
1189 let Inst{5-4} = Rn{5-4};
1192 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1193 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1194 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1196 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1197 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1198 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1200 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1201 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1202 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1204 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1205 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1206 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1208 // ...with double-spaced registers (for disassembly only):
1209 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1210 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1211 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1212 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1213 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1214 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1216 // VST3 : Vector Store (multiple 3-element structures)
1217 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1218 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1219 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1220 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1222 let Inst{4} = Rn{4};
1225 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1226 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1227 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1229 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1230 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1231 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1233 // ...with address register writeback:
1234 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1235 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1236 (ins addrmode6:$Rn, am6offset:$Rm,
1237 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1238 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1239 "$Rn.addr = $wb", []> {
1240 let Inst{4} = Rn{4};
1243 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1244 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1245 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1247 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1248 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1249 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1251 // ...with double-spaced registers (non-updating versions for disassembly only):
1252 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1253 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1254 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1255 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1256 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1257 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1259 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1260 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1261 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1263 // ...alternate versions to be allocated odd register numbers:
1264 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1265 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1266 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1268 // VST4 : Vector Store (multiple 4-element structures)
1269 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1270 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1271 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1272 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1275 let Inst{5-4} = Rn{5-4};
1278 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1279 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1280 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1282 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1283 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1284 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1286 // ...with address register writeback:
1287 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1288 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1289 (ins addrmode6:$Rn, am6offset:$Rm,
1290 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1291 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1292 "$Rn.addr = $wb", []> {
1293 let Inst{5-4} = Rn{5-4};
1296 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1297 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1298 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1300 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1301 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1302 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1304 // ...with double-spaced registers (non-updating versions for disassembly only):
1305 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1306 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1307 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1308 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1309 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1310 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1312 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1313 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1314 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1316 // ...alternate versions to be allocated odd register numbers:
1317 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1318 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1319 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1321 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1323 // Classes for VST*LN pseudo-instructions with multi-register operands.
1324 // These are expanded to real instructions after register allocation.
1325 class VSTQLNPseudo<InstrItinClass itin>
1326 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1328 class VSTQLNWBPseudo<InstrItinClass itin>
1329 : PseudoNLdSt<(outs GPR:$wb),
1330 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1331 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1332 class VSTQQLNPseudo<InstrItinClass itin>
1333 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1335 class VSTQQLNWBPseudo<InstrItinClass itin>
1336 : PseudoNLdSt<(outs GPR:$wb),
1337 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1338 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1339 class VSTQQQQLNPseudo<InstrItinClass itin>
1340 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1342 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1343 : PseudoNLdSt<(outs GPR:$wb),
1344 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1345 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1347 // VST1LN : Vector Store (single element from one lane)
1348 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1349 PatFrag StoreOp, SDNode ExtractOp>
1350 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1351 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1352 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1353 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1356 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1357 : VSTQLNPseudo<IIC_VST1ln> {
1358 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1362 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1364 let Inst{7-5} = lane{2-0};
1366 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1368 let Inst{7-6} = lane{1-0};
1369 let Inst{4} = Rn{5};
1371 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1372 let Inst{7} = lane{0};
1373 let Inst{5-4} = Rn{5-4};
1376 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1377 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1378 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1380 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1381 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1382 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1383 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1385 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1387 // ...with address register writeback:
1388 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1389 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1390 (ins addrmode6:$Rn, am6offset:$Rm,
1391 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1392 "\\{$Vd[$lane]\\}, $Rn$Rm",
1393 "$Rn.addr = $wb", []>;
1395 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8"> {
1396 let Inst{7-5} = lane{2-0};
1398 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16"> {
1399 let Inst{7-6} = lane{1-0};
1400 let Inst{4} = Rn{5};
1402 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32"> {
1403 let Inst{7} = lane{0};
1404 let Inst{5-4} = Rn{5-4};
1407 def VST1LNq8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1408 def VST1LNq16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1409 def VST1LNq32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST1lnu>;
1411 // VST2LN : Vector Store (single 2-element structure from one lane)
1412 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1413 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1414 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1415 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1418 let Inst{4} = Rn{4};
1421 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1422 let Inst{7-5} = lane{2-0};
1424 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1425 let Inst{7-6} = lane{1-0};
1427 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1428 let Inst{7} = lane{0};
1431 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1432 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1433 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1435 // ...with double-spaced registers:
1436 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1437 let Inst{7-6} = lane{1-0};
1438 let Inst{4} = Rn{4};
1440 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1441 let Inst{7} = lane{0};
1442 let Inst{4} = Rn{4};
1445 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1446 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1448 // ...with address register writeback:
1449 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1450 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1451 (ins addrmode6:$addr, am6offset:$offset,
1452 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1453 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1454 "$addr.addr = $wb", []> {
1455 let Inst{4} = Rn{4};
1458 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1459 let Inst{7-5} = lane{2-0};
1461 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1462 let Inst{7-6} = lane{1-0};
1464 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1465 let Inst{7} = lane{0};
1468 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1469 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1470 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1472 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1473 let Inst{7-6} = lane{1-0};
1475 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1476 let Inst{7} = lane{0};
1479 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1480 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1482 // VST3LN : Vector Store (single 3-element structure from one lane)
1483 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1484 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1485 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1486 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1487 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1491 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1492 let Inst{7-5} = lane{2-0};
1494 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1495 let Inst{7-6} = lane{1-0};
1497 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1498 let Inst{7} = lane{0};
1501 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1502 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1503 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1505 // ...with double-spaced registers:
1506 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1507 let Inst{7-6} = lane{1-0};
1509 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1510 let Inst{7} = lane{0};
1513 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1514 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1516 // ...with address register writeback:
1517 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1518 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1519 (ins addrmode6:$Rn, am6offset:$Rm,
1520 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1521 IIC_VST3lnu, "vst3", Dt,
1522 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1523 "$Rn.addr = $wb", []>;
1525 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1526 let Inst{7-5} = lane{2-0};
1528 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1529 let Inst{7-6} = lane{1-0};
1531 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1532 let Inst{7} = lane{0};
1535 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1536 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1537 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1539 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1540 let Inst{7-6} = lane{1-0};
1542 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1543 let Inst{7} = lane{0};
1546 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1547 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1549 // VST4LN : Vector Store (single 4-element structure from one lane)
1550 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1551 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1552 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1553 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1554 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1557 let Inst{4} = Rn{4};
1560 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1561 let Inst{7-5} = lane{2-0};
1563 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1564 let Inst{7-6} = lane{1-0};
1566 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1567 let Inst{7} = lane{0};
1568 let Inst{5} = Rn{5};
1571 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1572 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1573 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1575 // ...with double-spaced registers:
1576 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1577 let Inst{7-6} = lane{1-0};
1579 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1580 let Inst{7} = lane{0};
1581 let Inst{5} = Rn{5};
1584 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1585 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1587 // ...with address register writeback:
1588 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1589 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1590 (ins addrmode6:$Rn, am6offset:$Rm,
1591 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1592 IIC_VST4lnu, "vst4", Dt,
1593 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1594 "$Rn.addr = $wb", []> {
1595 let Inst{4} = Rn{4};
1598 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1599 let Inst{7-5} = lane{2-0};
1601 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1602 let Inst{7-6} = lane{1-0};
1604 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1605 let Inst{7} = lane{0};
1606 let Inst{5} = Rn{5};
1609 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1610 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1611 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1613 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1614 let Inst{7-6} = lane{1-0};
1616 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1617 let Inst{7} = lane{0};
1618 let Inst{5} = Rn{5};
1621 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1622 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1624 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1627 //===----------------------------------------------------------------------===//
1628 // NEON pattern fragments
1629 //===----------------------------------------------------------------------===//
1631 // Extract D sub-registers of Q registers.
1632 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1633 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1634 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1636 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1637 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1638 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1640 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1641 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1642 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1644 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1645 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1646 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1649 // Extract S sub-registers of Q/D registers.
1650 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1651 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1652 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1655 // Translate lane numbers from Q registers to D subregs.
1656 def SubReg_i8_lane : SDNodeXForm<imm, [{
1657 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1659 def SubReg_i16_lane : SDNodeXForm<imm, [{
1660 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1662 def SubReg_i32_lane : SDNodeXForm<imm, [{
1663 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1666 //===----------------------------------------------------------------------===//
1667 // Instruction Classes
1668 //===----------------------------------------------------------------------===//
1670 // Basic 2-register operations: double- and quad-register.
1671 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1672 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1673 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1674 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1675 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1676 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1677 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1678 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1679 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1680 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1681 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1682 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1684 // Basic 2-register intrinsics, both double- and quad-register.
1685 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1686 bits<2> op17_16, bits<5> op11_7, bit op4,
1687 InstrItinClass itin, string OpcodeStr, string Dt,
1688 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1689 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1690 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1691 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1692 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1693 bits<2> op17_16, bits<5> op11_7, bit op4,
1694 InstrItinClass itin, string OpcodeStr, string Dt,
1695 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1696 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1697 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1698 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1700 // Narrow 2-register operations.
1701 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1702 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1703 InstrItinClass itin, string OpcodeStr, string Dt,
1704 ValueType TyD, ValueType TyQ, SDNode OpNode>
1705 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1706 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1707 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1709 // Narrow 2-register intrinsics.
1710 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1711 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1712 InstrItinClass itin, string OpcodeStr, string Dt,
1713 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1714 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1715 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1716 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1718 // Long 2-register operations (currently only used for VMOVL).
1719 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1720 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1721 InstrItinClass itin, string OpcodeStr, string Dt,
1722 ValueType TyQ, ValueType TyD, SDNode OpNode>
1723 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1724 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1725 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1727 // Long 2-register intrinsics.
1728 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1729 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1730 InstrItinClass itin, string OpcodeStr, string Dt,
1731 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1732 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1733 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1734 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1736 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1737 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1738 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1739 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1740 OpcodeStr, Dt, "$Vd, $Vm",
1741 "$src1 = $Vd, $src2 = $Vm", []>;
1742 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1743 InstrItinClass itin, string OpcodeStr, string Dt>
1744 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1745 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1746 "$src1 = $Vd, $src2 = $Vm", []>;
1748 // Basic 3-register operations: double- and quad-register.
1749 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1750 InstrItinClass itin, string OpcodeStr, string Dt,
1751 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1752 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1753 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1754 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1755 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1756 let isCommutable = Commutable;
1758 // Same as N3VD but no data type.
1759 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1760 InstrItinClass itin, string OpcodeStr,
1761 ValueType ResTy, ValueType OpTy,
1762 SDNode OpNode, bit Commutable>
1763 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1764 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1765 OpcodeStr, "$Vd, $Vn, $Vm", "",
1766 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1767 let isCommutable = Commutable;
1770 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1771 InstrItinClass itin, string OpcodeStr, string Dt,
1772 ValueType Ty, SDNode ShOp>
1773 : N3V<0, 1, op21_20, op11_8, 1, 0,
1774 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1775 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1777 (Ty (ShOp (Ty DPR:$Vn),
1778 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1779 let isCommutable = 0;
1781 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1782 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1783 : N3V<0, 1, op21_20, op11_8, 1, 0,
1784 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1785 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1787 (Ty (ShOp (Ty DPR:$Vn),
1788 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1789 let isCommutable = 0;
1792 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1793 InstrItinClass itin, string OpcodeStr, string Dt,
1794 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1795 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1796 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1797 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1798 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1799 let isCommutable = Commutable;
1801 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1802 InstrItinClass itin, string OpcodeStr,
1803 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1804 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1805 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1806 OpcodeStr, "$Vd, $Vn, $Vm", "",
1807 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1808 let isCommutable = Commutable;
1810 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1811 InstrItinClass itin, string OpcodeStr, string Dt,
1812 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1813 : N3V<1, 1, op21_20, op11_8, 1, 0,
1814 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1815 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1816 [(set (ResTy QPR:$Vd),
1817 (ResTy (ShOp (ResTy QPR:$Vn),
1818 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1820 let isCommutable = 0;
1822 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1823 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1824 : N3V<1, 1, op21_20, op11_8, 1, 0,
1825 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1826 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1827 [(set (ResTy QPR:$Vd),
1828 (ResTy (ShOp (ResTy QPR:$Vn),
1829 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1831 let isCommutable = 0;
1834 // Basic 3-register intrinsics, both double- and quad-register.
1835 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1836 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1837 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1838 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1839 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1840 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1841 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1842 let isCommutable = Commutable;
1844 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1845 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1846 : N3V<0, 1, op21_20, op11_8, 1, 0,
1847 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1848 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1850 (Ty (IntOp (Ty DPR:$Vn),
1851 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1853 let isCommutable = 0;
1855 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1856 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1857 : N3V<0, 1, op21_20, op11_8, 1, 0,
1858 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1859 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1861 (Ty (IntOp (Ty DPR:$Vn),
1862 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1863 let isCommutable = 0;
1865 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1866 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1867 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1868 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1869 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1870 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1871 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1872 let isCommutable = 0;
1875 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1876 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1877 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1878 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1879 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1880 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1881 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1882 let isCommutable = Commutable;
1884 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1885 string OpcodeStr, string Dt,
1886 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1887 : N3V<1, 1, op21_20, op11_8, 1, 0,
1888 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1889 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1890 [(set (ResTy QPR:$Vd),
1891 (ResTy (IntOp (ResTy QPR:$Vn),
1892 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1894 let isCommutable = 0;
1896 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1897 string OpcodeStr, string Dt,
1898 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1899 : N3V<1, 1, op21_20, op11_8, 1, 0,
1900 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1901 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1902 [(set (ResTy QPR:$Vd),
1903 (ResTy (IntOp (ResTy QPR:$Vn),
1904 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1906 let isCommutable = 0;
1908 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1909 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1910 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1911 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1912 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1913 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1914 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1915 let isCommutable = 0;
1918 // Multiply-Add/Sub operations: double- and quad-register.
1919 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1920 InstrItinClass itin, string OpcodeStr, string Dt,
1921 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
1922 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1923 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1924 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1925 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1926 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1928 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1929 string OpcodeStr, string Dt,
1930 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
1931 : N3V<0, 1, op21_20, op11_8, 1, 0,
1933 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1935 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1937 (Ty (ShOp (Ty DPR:$src1),
1939 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1941 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1942 string OpcodeStr, string Dt,
1943 ValueType Ty, SDNode MulOp, SDNode ShOp>
1944 : N3V<0, 1, op21_20, op11_8, 1, 0,
1946 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1948 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1950 (Ty (ShOp (Ty DPR:$src1),
1952 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1955 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1956 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1957 SDPatternOperator MulOp, SDPatternOperator OpNode>
1958 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1959 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1960 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1961 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1962 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1963 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1964 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1965 SDPatternOperator MulOp, SDPatternOperator ShOp>
1966 : N3V<1, 1, op21_20, op11_8, 1, 0,
1968 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1970 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1971 [(set (ResTy QPR:$Vd),
1972 (ResTy (ShOp (ResTy QPR:$src1),
1973 (ResTy (MulOp QPR:$Vn,
1974 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1976 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1977 string OpcodeStr, string Dt,
1978 ValueType ResTy, ValueType OpTy,
1979 SDNode MulOp, SDNode ShOp>
1980 : N3V<1, 1, op21_20, op11_8, 1, 0,
1982 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1984 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1985 [(set (ResTy QPR:$Vd),
1986 (ResTy (ShOp (ResTy QPR:$src1),
1987 (ResTy (MulOp QPR:$Vn,
1988 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1991 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
1992 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1993 InstrItinClass itin, string OpcodeStr, string Dt,
1994 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
1995 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1996 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1997 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1998 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1999 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2000 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2001 InstrItinClass itin, string OpcodeStr, string Dt,
2002 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2003 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2004 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2005 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2006 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2007 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2009 // Neon 3-argument intrinsics, both double- and quad-register.
2010 // The destination register is also used as the first source operand register.
2011 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2012 InstrItinClass itin, string OpcodeStr, string Dt,
2013 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2014 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2015 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2016 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2017 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2018 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2019 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2020 InstrItinClass itin, string OpcodeStr, string Dt,
2021 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2022 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2023 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2024 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2025 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2026 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2028 // Long Multiply-Add/Sub operations.
2029 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2030 InstrItinClass itin, string OpcodeStr, string Dt,
2031 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2032 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2033 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2034 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2035 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2036 (TyQ (MulOp (TyD DPR:$Vn),
2037 (TyD DPR:$Vm)))))]>;
2038 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2039 InstrItinClass itin, string OpcodeStr, string Dt,
2040 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2041 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2042 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2044 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2046 (OpNode (TyQ QPR:$src1),
2047 (TyQ (MulOp (TyD DPR:$Vn),
2048 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2050 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2051 InstrItinClass itin, string OpcodeStr, string Dt,
2052 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2053 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2054 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2056 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2058 (OpNode (TyQ QPR:$src1),
2059 (TyQ (MulOp (TyD DPR:$Vn),
2060 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2063 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2064 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2065 InstrItinClass itin, string OpcodeStr, string Dt,
2066 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2068 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2069 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2070 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2071 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2072 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2073 (TyD DPR:$Vm)))))))]>;
2075 // Neon Long 3-argument intrinsic. The destination register is
2076 // a quad-register and is also used as the first source operand register.
2077 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2078 InstrItinClass itin, string OpcodeStr, string Dt,
2079 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2080 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2081 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2082 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2084 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2085 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2086 string OpcodeStr, string Dt,
2087 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2088 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2090 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2092 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2093 [(set (ResTy QPR:$Vd),
2094 (ResTy (IntOp (ResTy QPR:$src1),
2096 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2098 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2099 InstrItinClass itin, string OpcodeStr, string Dt,
2100 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2101 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2103 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2105 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2106 [(set (ResTy QPR:$Vd),
2107 (ResTy (IntOp (ResTy QPR:$src1),
2109 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2112 // Narrowing 3-register intrinsics.
2113 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2114 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2115 Intrinsic IntOp, bit Commutable>
2116 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2117 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2118 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2119 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2120 let isCommutable = Commutable;
2123 // Long 3-register operations.
2124 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2125 InstrItinClass itin, string OpcodeStr, string Dt,
2126 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2127 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2128 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2129 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2130 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2131 let isCommutable = Commutable;
2133 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2134 InstrItinClass itin, string OpcodeStr, string Dt,
2135 ValueType TyQ, ValueType TyD, SDNode OpNode>
2136 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2137 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2138 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2140 (TyQ (OpNode (TyD DPR:$Vn),
2141 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2142 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2143 InstrItinClass itin, string OpcodeStr, string Dt,
2144 ValueType TyQ, ValueType TyD, SDNode OpNode>
2145 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2146 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2147 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2149 (TyQ (OpNode (TyD DPR:$Vn),
2150 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2152 // Long 3-register operations with explicitly extended operands.
2153 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2154 InstrItinClass itin, string OpcodeStr, string Dt,
2155 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2157 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2158 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2159 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2160 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2161 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2162 let isCommutable = Commutable;
2165 // Long 3-register intrinsics with explicit extend (VABDL).
2166 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2167 InstrItinClass itin, string OpcodeStr, string Dt,
2168 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2170 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2171 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2172 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2173 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2174 (TyD DPR:$Vm))))))]> {
2175 let isCommutable = Commutable;
2178 // Long 3-register intrinsics.
2179 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2180 InstrItinClass itin, string OpcodeStr, string Dt,
2181 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2182 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2183 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2184 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2185 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2186 let isCommutable = Commutable;
2188 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2189 string OpcodeStr, string Dt,
2190 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2191 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2192 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2193 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2194 [(set (ResTy QPR:$Vd),
2195 (ResTy (IntOp (OpTy DPR:$Vn),
2196 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2198 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2199 InstrItinClass itin, string OpcodeStr, string Dt,
2200 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2201 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2202 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2203 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2204 [(set (ResTy QPR:$Vd),
2205 (ResTy (IntOp (OpTy DPR:$Vn),
2206 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2209 // Wide 3-register operations.
2210 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2211 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2212 SDNode OpNode, SDNode ExtOp, bit Commutable>
2213 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2214 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2215 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2216 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2217 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2218 let isCommutable = Commutable;
2221 // Pairwise long 2-register intrinsics, both double- and quad-register.
2222 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2223 bits<2> op17_16, bits<5> op11_7, bit op4,
2224 string OpcodeStr, string Dt,
2225 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2226 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2227 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2228 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2229 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2230 bits<2> op17_16, bits<5> op11_7, bit op4,
2231 string OpcodeStr, string Dt,
2232 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2233 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2234 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2235 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2237 // Pairwise long 2-register accumulate intrinsics,
2238 // both double- and quad-register.
2239 // The destination register is also used as the first source operand register.
2240 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2241 bits<2> op17_16, bits<5> op11_7, bit op4,
2242 string OpcodeStr, string Dt,
2243 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2244 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2245 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2246 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2247 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2248 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2249 bits<2> op17_16, bits<5> op11_7, bit op4,
2250 string OpcodeStr, string Dt,
2251 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2252 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2253 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2254 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2255 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2257 // Shift by immediate,
2258 // both double- and quad-register.
2259 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2260 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2261 ValueType Ty, SDNode OpNode>
2262 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2263 (outs DPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), f, itin,
2264 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2265 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2266 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2267 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2268 ValueType Ty, SDNode OpNode>
2269 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2270 (outs QPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), f, itin,
2271 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2272 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2274 // Long shift by immediate.
2275 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2276 string OpcodeStr, string Dt,
2277 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2278 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2279 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2280 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2281 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2282 (i32 imm:$SIMM))))]>;
2284 // Narrow shift by immediate.
2285 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2286 InstrItinClass itin, string OpcodeStr, string Dt,
2287 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2288 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2289 (outs DPR:$Vd), (ins QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, itin,
2290 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2291 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2292 (i32 imm:$SIMM))))]>;
2294 // Shift right by immediate and accumulate,
2295 // both double- and quad-register.
2296 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2297 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2298 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2299 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2300 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2301 [(set DPR:$Vd, (Ty (add DPR:$src1,
2302 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2303 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2304 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2305 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2306 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2307 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2308 [(set QPR:$Vd, (Ty (add QPR:$src1,
2309 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2311 // Shift by immediate and insert,
2312 // both double- and quad-register.
2313 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2314 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2315 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2316 (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
2317 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2318 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2319 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2320 Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
2321 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2322 (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
2323 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2324 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2326 // Convert, with fractional bits immediate,
2327 // both double- and quad-register.
2328 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2329 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2331 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2332 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2333 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2334 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2335 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2336 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2338 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2339 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2340 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2341 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2343 //===----------------------------------------------------------------------===//
2345 //===----------------------------------------------------------------------===//
2347 // Abbreviations used in multiclass suffixes:
2348 // Q = quarter int (8 bit) elements
2349 // H = half int (16 bit) elements
2350 // S = single int (32 bit) elements
2351 // D = double int (64 bit) elements
2353 // Neon 2-register vector operations and intrinsics.
2355 // Neon 2-register comparisons.
2356 // source operand element sizes of 8, 16 and 32 bits:
2357 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2358 bits<5> op11_7, bit op4, string opc, string Dt,
2359 string asm, SDNode OpNode> {
2360 // 64-bit vector types.
2361 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2362 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2363 opc, !strconcat(Dt, "8"), asm, "",
2364 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2365 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2366 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2367 opc, !strconcat(Dt, "16"), asm, "",
2368 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2369 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2370 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2371 opc, !strconcat(Dt, "32"), asm, "",
2372 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2373 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2374 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2375 opc, "f32", asm, "",
2376 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2377 let Inst{10} = 1; // overwrite F = 1
2380 // 128-bit vector types.
2381 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2382 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2383 opc, !strconcat(Dt, "8"), asm, "",
2384 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2385 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2386 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2387 opc, !strconcat(Dt, "16"), asm, "",
2388 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2389 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2390 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2391 opc, !strconcat(Dt, "32"), asm, "",
2392 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2393 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2394 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2395 opc, "f32", asm, "",
2396 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2397 let Inst{10} = 1; // overwrite F = 1
2402 // Neon 2-register vector intrinsics,
2403 // element sizes of 8, 16 and 32 bits:
2404 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2405 bits<5> op11_7, bit op4,
2406 InstrItinClass itinD, InstrItinClass itinQ,
2407 string OpcodeStr, string Dt, Intrinsic IntOp> {
2408 // 64-bit vector types.
2409 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2410 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2411 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2412 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2413 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2414 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2416 // 128-bit vector types.
2417 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2418 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2419 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2420 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2421 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2422 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2426 // Neon Narrowing 2-register vector operations,
2427 // source operand element sizes of 16, 32 and 64 bits:
2428 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2429 bits<5> op11_7, bit op6, bit op4,
2430 InstrItinClass itin, string OpcodeStr, string Dt,
2432 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2433 itin, OpcodeStr, !strconcat(Dt, "16"),
2434 v8i8, v8i16, OpNode>;
2435 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2436 itin, OpcodeStr, !strconcat(Dt, "32"),
2437 v4i16, v4i32, OpNode>;
2438 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2439 itin, OpcodeStr, !strconcat(Dt, "64"),
2440 v2i32, v2i64, OpNode>;
2443 // Neon Narrowing 2-register vector intrinsics,
2444 // source operand element sizes of 16, 32 and 64 bits:
2445 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2446 bits<5> op11_7, bit op6, bit op4,
2447 InstrItinClass itin, string OpcodeStr, string Dt,
2449 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2450 itin, OpcodeStr, !strconcat(Dt, "16"),
2451 v8i8, v8i16, IntOp>;
2452 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2453 itin, OpcodeStr, !strconcat(Dt, "32"),
2454 v4i16, v4i32, IntOp>;
2455 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2456 itin, OpcodeStr, !strconcat(Dt, "64"),
2457 v2i32, v2i64, IntOp>;
2461 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2462 // source operand element sizes of 16, 32 and 64 bits:
2463 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2464 string OpcodeStr, string Dt, SDNode OpNode> {
2465 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2466 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2467 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2468 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2469 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2470 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2474 // Neon 3-register vector operations.
2476 // First with only element sizes of 8, 16 and 32 bits:
2477 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2478 InstrItinClass itinD16, InstrItinClass itinD32,
2479 InstrItinClass itinQ16, InstrItinClass itinQ32,
2480 string OpcodeStr, string Dt,
2481 SDNode OpNode, bit Commutable = 0> {
2482 // 64-bit vector types.
2483 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2484 OpcodeStr, !strconcat(Dt, "8"),
2485 v8i8, v8i8, OpNode, Commutable>;
2486 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2487 OpcodeStr, !strconcat(Dt, "16"),
2488 v4i16, v4i16, OpNode, Commutable>;
2489 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2490 OpcodeStr, !strconcat(Dt, "32"),
2491 v2i32, v2i32, OpNode, Commutable>;
2493 // 128-bit vector types.
2494 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2495 OpcodeStr, !strconcat(Dt, "8"),
2496 v16i8, v16i8, OpNode, Commutable>;
2497 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2498 OpcodeStr, !strconcat(Dt, "16"),
2499 v8i16, v8i16, OpNode, Commutable>;
2500 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2501 OpcodeStr, !strconcat(Dt, "32"),
2502 v4i32, v4i32, OpNode, Commutable>;
2505 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2506 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2508 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2510 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2511 v8i16, v4i16, ShOp>;
2512 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2513 v4i32, v2i32, ShOp>;
2516 // ....then also with element size 64 bits:
2517 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2518 InstrItinClass itinD, InstrItinClass itinQ,
2519 string OpcodeStr, string Dt,
2520 SDNode OpNode, bit Commutable = 0>
2521 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2522 OpcodeStr, Dt, OpNode, Commutable> {
2523 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2524 OpcodeStr, !strconcat(Dt, "64"),
2525 v1i64, v1i64, OpNode, Commutable>;
2526 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2527 OpcodeStr, !strconcat(Dt, "64"),
2528 v2i64, v2i64, OpNode, Commutable>;
2532 // Neon 3-register vector intrinsics.
2534 // First with only element sizes of 16 and 32 bits:
2535 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2536 InstrItinClass itinD16, InstrItinClass itinD32,
2537 InstrItinClass itinQ16, InstrItinClass itinQ32,
2538 string OpcodeStr, string Dt,
2539 Intrinsic IntOp, bit Commutable = 0> {
2540 // 64-bit vector types.
2541 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2542 OpcodeStr, !strconcat(Dt, "16"),
2543 v4i16, v4i16, IntOp, Commutable>;
2544 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2545 OpcodeStr, !strconcat(Dt, "32"),
2546 v2i32, v2i32, IntOp, Commutable>;
2548 // 128-bit vector types.
2549 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2550 OpcodeStr, !strconcat(Dt, "16"),
2551 v8i16, v8i16, IntOp, Commutable>;
2552 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2553 OpcodeStr, !strconcat(Dt, "32"),
2554 v4i32, v4i32, IntOp, Commutable>;
2556 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2557 InstrItinClass itinD16, InstrItinClass itinD32,
2558 InstrItinClass itinQ16, InstrItinClass itinQ32,
2559 string OpcodeStr, string Dt,
2561 // 64-bit vector types.
2562 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2563 OpcodeStr, !strconcat(Dt, "16"),
2564 v4i16, v4i16, IntOp>;
2565 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2566 OpcodeStr, !strconcat(Dt, "32"),
2567 v2i32, v2i32, IntOp>;
2569 // 128-bit vector types.
2570 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2571 OpcodeStr, !strconcat(Dt, "16"),
2572 v8i16, v8i16, IntOp>;
2573 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2574 OpcodeStr, !strconcat(Dt, "32"),
2575 v4i32, v4i32, IntOp>;
2578 multiclass N3VIntSL_HS<bits<4> op11_8,
2579 InstrItinClass itinD16, InstrItinClass itinD32,
2580 InstrItinClass itinQ16, InstrItinClass itinQ32,
2581 string OpcodeStr, string Dt, Intrinsic IntOp> {
2582 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2583 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2584 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2585 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2586 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2587 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2588 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2589 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2592 // ....then also with element size of 8 bits:
2593 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2594 InstrItinClass itinD16, InstrItinClass itinD32,
2595 InstrItinClass itinQ16, InstrItinClass itinQ32,
2596 string OpcodeStr, string Dt,
2597 Intrinsic IntOp, bit Commutable = 0>
2598 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2599 OpcodeStr, Dt, IntOp, Commutable> {
2600 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2601 OpcodeStr, !strconcat(Dt, "8"),
2602 v8i8, v8i8, IntOp, Commutable>;
2603 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2604 OpcodeStr, !strconcat(Dt, "8"),
2605 v16i8, v16i8, IntOp, Commutable>;
2607 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2608 InstrItinClass itinD16, InstrItinClass itinD32,
2609 InstrItinClass itinQ16, InstrItinClass itinQ32,
2610 string OpcodeStr, string Dt,
2612 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2613 OpcodeStr, Dt, IntOp> {
2614 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2615 OpcodeStr, !strconcat(Dt, "8"),
2617 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2618 OpcodeStr, !strconcat(Dt, "8"),
2619 v16i8, v16i8, IntOp>;
2623 // ....then also with element size of 64 bits:
2624 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2625 InstrItinClass itinD16, InstrItinClass itinD32,
2626 InstrItinClass itinQ16, InstrItinClass itinQ32,
2627 string OpcodeStr, string Dt,
2628 Intrinsic IntOp, bit Commutable = 0>
2629 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2630 OpcodeStr, Dt, IntOp, Commutable> {
2631 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2632 OpcodeStr, !strconcat(Dt, "64"),
2633 v1i64, v1i64, IntOp, Commutable>;
2634 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2635 OpcodeStr, !strconcat(Dt, "64"),
2636 v2i64, v2i64, IntOp, Commutable>;
2638 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2639 InstrItinClass itinD16, InstrItinClass itinD32,
2640 InstrItinClass itinQ16, InstrItinClass itinQ32,
2641 string OpcodeStr, string Dt,
2643 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2644 OpcodeStr, Dt, IntOp> {
2645 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2646 OpcodeStr, !strconcat(Dt, "64"),
2647 v1i64, v1i64, IntOp>;
2648 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2649 OpcodeStr, !strconcat(Dt, "64"),
2650 v2i64, v2i64, IntOp>;
2653 // Neon Narrowing 3-register vector intrinsics,
2654 // source operand element sizes of 16, 32 and 64 bits:
2655 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2656 string OpcodeStr, string Dt,
2657 Intrinsic IntOp, bit Commutable = 0> {
2658 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2659 OpcodeStr, !strconcat(Dt, "16"),
2660 v8i8, v8i16, IntOp, Commutable>;
2661 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2662 OpcodeStr, !strconcat(Dt, "32"),
2663 v4i16, v4i32, IntOp, Commutable>;
2664 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2665 OpcodeStr, !strconcat(Dt, "64"),
2666 v2i32, v2i64, IntOp, Commutable>;
2670 // Neon Long 3-register vector operations.
2672 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2673 InstrItinClass itin16, InstrItinClass itin32,
2674 string OpcodeStr, string Dt,
2675 SDNode OpNode, bit Commutable = 0> {
2676 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2677 OpcodeStr, !strconcat(Dt, "8"),
2678 v8i16, v8i8, OpNode, Commutable>;
2679 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2680 OpcodeStr, !strconcat(Dt, "16"),
2681 v4i32, v4i16, OpNode, Commutable>;
2682 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2683 OpcodeStr, !strconcat(Dt, "32"),
2684 v2i64, v2i32, OpNode, Commutable>;
2687 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2688 InstrItinClass itin, string OpcodeStr, string Dt,
2690 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2691 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2692 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2693 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2696 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2697 InstrItinClass itin16, InstrItinClass itin32,
2698 string OpcodeStr, string Dt,
2699 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2700 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2701 OpcodeStr, !strconcat(Dt, "8"),
2702 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2703 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2704 OpcodeStr, !strconcat(Dt, "16"),
2705 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2706 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2707 OpcodeStr, !strconcat(Dt, "32"),
2708 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2711 // Neon Long 3-register vector intrinsics.
2713 // First with only element sizes of 16 and 32 bits:
2714 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2715 InstrItinClass itin16, InstrItinClass itin32,
2716 string OpcodeStr, string Dt,
2717 Intrinsic IntOp, bit Commutable = 0> {
2718 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2719 OpcodeStr, !strconcat(Dt, "16"),
2720 v4i32, v4i16, IntOp, Commutable>;
2721 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2722 OpcodeStr, !strconcat(Dt, "32"),
2723 v2i64, v2i32, IntOp, Commutable>;
2726 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2727 InstrItinClass itin, string OpcodeStr, string Dt,
2729 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2730 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2731 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2732 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2735 // ....then also with element size of 8 bits:
2736 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2737 InstrItinClass itin16, InstrItinClass itin32,
2738 string OpcodeStr, string Dt,
2739 Intrinsic IntOp, bit Commutable = 0>
2740 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2741 IntOp, Commutable> {
2742 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2743 OpcodeStr, !strconcat(Dt, "8"),
2744 v8i16, v8i8, IntOp, Commutable>;
2747 // ....with explicit extend (VABDL).
2748 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2749 InstrItinClass itin, string OpcodeStr, string Dt,
2750 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2751 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2752 OpcodeStr, !strconcat(Dt, "8"),
2753 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2754 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2755 OpcodeStr, !strconcat(Dt, "16"),
2756 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2757 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2758 OpcodeStr, !strconcat(Dt, "32"),
2759 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2763 // Neon Wide 3-register vector intrinsics,
2764 // source operand element sizes of 8, 16 and 32 bits:
2765 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2766 string OpcodeStr, string Dt,
2767 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2768 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2769 OpcodeStr, !strconcat(Dt, "8"),
2770 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2771 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2772 OpcodeStr, !strconcat(Dt, "16"),
2773 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2774 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2775 OpcodeStr, !strconcat(Dt, "32"),
2776 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2780 // Neon Multiply-Op vector operations,
2781 // element sizes of 8, 16 and 32 bits:
2782 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2783 InstrItinClass itinD16, InstrItinClass itinD32,
2784 InstrItinClass itinQ16, InstrItinClass itinQ32,
2785 string OpcodeStr, string Dt, SDNode OpNode> {
2786 // 64-bit vector types.
2787 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2788 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2789 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2790 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2791 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2792 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2794 // 128-bit vector types.
2795 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2796 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2797 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2798 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2799 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2800 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2803 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2804 InstrItinClass itinD16, InstrItinClass itinD32,
2805 InstrItinClass itinQ16, InstrItinClass itinQ32,
2806 string OpcodeStr, string Dt, SDNode ShOp> {
2807 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2808 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2809 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2810 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2811 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2812 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2814 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2815 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2819 // Neon Intrinsic-Op vector operations,
2820 // element sizes of 8, 16 and 32 bits:
2821 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2822 InstrItinClass itinD, InstrItinClass itinQ,
2823 string OpcodeStr, string Dt, Intrinsic IntOp,
2825 // 64-bit vector types.
2826 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2827 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2828 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2829 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2830 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2831 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2833 // 128-bit vector types.
2834 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2835 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2836 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2837 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2838 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2839 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2842 // Neon 3-argument intrinsics,
2843 // element sizes of 8, 16 and 32 bits:
2844 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2845 InstrItinClass itinD, InstrItinClass itinQ,
2846 string OpcodeStr, string Dt, Intrinsic IntOp> {
2847 // 64-bit vector types.
2848 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2849 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2850 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2851 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2852 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2853 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2855 // 128-bit vector types.
2856 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2857 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2858 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2859 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2860 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2861 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2865 // Neon Long Multiply-Op vector operations,
2866 // element sizes of 8, 16 and 32 bits:
2867 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2868 InstrItinClass itin16, InstrItinClass itin32,
2869 string OpcodeStr, string Dt, SDNode MulOp,
2871 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2872 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2873 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2874 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2875 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2876 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2879 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2880 string Dt, SDNode MulOp, SDNode OpNode> {
2881 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2882 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2883 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2884 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2888 // Neon Long 3-argument intrinsics.
2890 // First with only element sizes of 16 and 32 bits:
2891 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2892 InstrItinClass itin16, InstrItinClass itin32,
2893 string OpcodeStr, string Dt, Intrinsic IntOp> {
2894 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2895 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2896 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2897 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2900 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2901 string OpcodeStr, string Dt, Intrinsic IntOp> {
2902 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2903 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2904 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2905 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2908 // ....then also with element size of 8 bits:
2909 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2910 InstrItinClass itin16, InstrItinClass itin32,
2911 string OpcodeStr, string Dt, Intrinsic IntOp>
2912 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2913 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2914 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2917 // ....with explicit extend (VABAL).
2918 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2919 InstrItinClass itin, string OpcodeStr, string Dt,
2920 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2921 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2922 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2923 IntOp, ExtOp, OpNode>;
2924 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2925 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2926 IntOp, ExtOp, OpNode>;
2927 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2928 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2929 IntOp, ExtOp, OpNode>;
2933 // Neon Pairwise long 2-register intrinsics,
2934 // element sizes of 8, 16 and 32 bits:
2935 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2936 bits<5> op11_7, bit op4,
2937 string OpcodeStr, string Dt, Intrinsic IntOp> {
2938 // 64-bit vector types.
2939 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2940 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2941 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2942 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2943 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2944 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2946 // 128-bit vector types.
2947 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2948 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2949 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2950 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2951 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2952 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2956 // Neon Pairwise long 2-register accumulate intrinsics,
2957 // element sizes of 8, 16 and 32 bits:
2958 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2959 bits<5> op11_7, bit op4,
2960 string OpcodeStr, string Dt, Intrinsic IntOp> {
2961 // 64-bit vector types.
2962 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2963 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2964 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2965 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2966 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2967 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2969 // 128-bit vector types.
2970 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2971 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2972 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2973 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2974 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2975 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2979 // Neon 2-register vector shift by immediate,
2980 // with f of either N2RegVShLFrm or N2RegVShRFrm
2981 // element sizes of 8, 16, 32 and 64 bits:
2982 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2983 InstrItinClass itin, string OpcodeStr, string Dt,
2984 SDNode OpNode, Format f> {
2985 // 64-bit vector types.
2986 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2987 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
2988 let Inst{21-19} = 0b001; // imm6 = 001xxx
2990 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2991 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
2992 let Inst{21-20} = 0b01; // imm6 = 01xxxx
2994 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, f, itin,
2995 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
2996 let Inst{21} = 0b1; // imm6 = 1xxxxx
2998 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, f, itin,
2999 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3002 // 128-bit vector types.
3003 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3004 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3005 let Inst{21-19} = 0b001; // imm6 = 001xxx
3007 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3008 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3009 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3011 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, f, itin,
3012 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3013 let Inst{21} = 0b1; // imm6 = 1xxxxx
3015 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, f, itin,
3016 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3020 // Neon Shift-Accumulate vector operations,
3021 // element sizes of 8, 16, 32 and 64 bits:
3022 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3023 string OpcodeStr, string Dt, SDNode ShOp> {
3024 // 64-bit vector types.
3025 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3026 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3027 let Inst{21-19} = 0b001; // imm6 = 001xxx
3029 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3030 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3031 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3033 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4,
3034 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3035 let Inst{21} = 0b1; // imm6 = 1xxxxx
3037 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4,
3038 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3041 // 128-bit vector types.
3042 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3043 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3044 let Inst{21-19} = 0b001; // imm6 = 001xxx
3046 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3047 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3048 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3050 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4,
3051 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3052 let Inst{21} = 0b1; // imm6 = 1xxxxx
3054 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4,
3055 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3060 // Neon Shift-Insert vector operations,
3061 // with f of either N2RegVShLFrm or N2RegVShRFrm
3062 // element sizes of 8, 16, 32 and 64 bits:
3063 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3064 string OpcodeStr, SDNode ShOp,
3066 // 64-bit vector types.
3067 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4,
3068 f, OpcodeStr, "8", v8i8, ShOp> {
3069 let Inst{21-19} = 0b001; // imm6 = 001xxx
3071 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4,
3072 f, OpcodeStr, "16", v4i16, ShOp> {
3073 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3075 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4,
3076 f, OpcodeStr, "32", v2i32, ShOp> {
3077 let Inst{21} = 0b1; // imm6 = 1xxxxx
3079 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4,
3080 f, OpcodeStr, "64", v1i64, ShOp>;
3083 // 128-bit vector types.
3084 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4,
3085 f, OpcodeStr, "8", v16i8, ShOp> {
3086 let Inst{21-19} = 0b001; // imm6 = 001xxx
3088 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4,
3089 f, OpcodeStr, "16", v8i16, ShOp> {
3090 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3092 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4,
3093 f, OpcodeStr, "32", v4i32, ShOp> {
3094 let Inst{21} = 0b1; // imm6 = 1xxxxx
3096 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4,
3097 f, OpcodeStr, "64", v2i64, ShOp>;
3101 // Neon Shift Long operations,
3102 // element sizes of 8, 16, 32 bits:
3103 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3104 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3105 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3106 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3107 let Inst{21-19} = 0b001; // imm6 = 001xxx
3109 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3110 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3111 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3113 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3114 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3115 let Inst{21} = 0b1; // imm6 = 1xxxxx
3119 // Neon Shift Narrow operations,
3120 // element sizes of 16, 32, 64 bits:
3121 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3122 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3124 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3125 OpcodeStr, !strconcat(Dt, "16"), v8i8, v8i16, OpNode> {
3126 let Inst{21-19} = 0b001; // imm6 = 001xxx
3128 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3129 OpcodeStr, !strconcat(Dt, "32"), v4i16, v4i32, OpNode> {
3130 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3132 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3133 OpcodeStr, !strconcat(Dt, "64"), v2i32, v2i64, OpNode> {
3134 let Inst{21} = 0b1; // imm6 = 1xxxxx
3138 //===----------------------------------------------------------------------===//
3139 // Instruction Definitions.
3140 //===----------------------------------------------------------------------===//
3142 // Vector Add Operations.
3144 // VADD : Vector Add (integer and floating-point)
3145 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3147 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3148 v2f32, v2f32, fadd, 1>;
3149 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3150 v4f32, v4f32, fadd, 1>;
3151 // VADDL : Vector Add Long (Q = D + D)
3152 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3153 "vaddl", "s", add, sext, 1>;
3154 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3155 "vaddl", "u", add, zext, 1>;
3156 // VADDW : Vector Add Wide (Q = Q + D)
3157 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3158 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3159 // VHADD : Vector Halving Add
3160 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3161 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3162 "vhadd", "s", int_arm_neon_vhadds, 1>;
3163 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3164 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3165 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3166 // VRHADD : Vector Rounding Halving Add
3167 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3168 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3169 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3170 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3171 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3172 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3173 // VQADD : Vector Saturating Add
3174 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3175 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3176 "vqadd", "s", int_arm_neon_vqadds, 1>;
3177 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3178 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3179 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3180 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3181 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3182 int_arm_neon_vaddhn, 1>;
3183 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3184 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3185 int_arm_neon_vraddhn, 1>;
3187 // Vector Multiply Operations.
3189 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3190 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3191 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3192 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3193 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3194 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3195 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3196 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3197 v2f32, v2f32, fmul, 1>;
3198 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3199 v4f32, v4f32, fmul, 1>;
3200 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3201 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3202 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3205 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3206 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3207 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3208 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3209 (DSubReg_i16_reg imm:$lane))),
3210 (SubReg_i16_lane imm:$lane)))>;
3211 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3212 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3213 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3214 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3215 (DSubReg_i32_reg imm:$lane))),
3216 (SubReg_i32_lane imm:$lane)))>;
3217 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3218 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3219 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3220 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3221 (DSubReg_i32_reg imm:$lane))),
3222 (SubReg_i32_lane imm:$lane)))>;
3224 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3225 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3226 IIC_VMULi16Q, IIC_VMULi32Q,
3227 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3228 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3229 IIC_VMULi16Q, IIC_VMULi32Q,
3230 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3231 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3232 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3234 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3235 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3236 (DSubReg_i16_reg imm:$lane))),
3237 (SubReg_i16_lane imm:$lane)))>;
3238 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3239 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3241 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3242 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3243 (DSubReg_i32_reg imm:$lane))),
3244 (SubReg_i32_lane imm:$lane)))>;
3246 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3247 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3248 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3249 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3250 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3251 IIC_VMULi16Q, IIC_VMULi32Q,
3252 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3253 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3254 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3256 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3257 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3258 (DSubReg_i16_reg imm:$lane))),
3259 (SubReg_i16_lane imm:$lane)))>;
3260 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3261 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3263 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3264 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3265 (DSubReg_i32_reg imm:$lane))),
3266 (SubReg_i32_lane imm:$lane)))>;
3268 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3269 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3270 "vmull", "s", NEONvmulls, 1>;
3271 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3272 "vmull", "u", NEONvmullu, 1>;
3273 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3274 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3275 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3276 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3278 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3279 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3280 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3281 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3282 "vqdmull", "s", int_arm_neon_vqdmull>;
3284 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3286 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3287 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3288 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3289 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3290 v2f32, fmul_su, fadd_mlx>,
3291 Requires<[HasNEON, UseFPVMLx]>;
3292 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3293 v4f32, fmul_su, fadd_mlx>,
3294 Requires<[HasNEON, UseFPVMLx]>;
3295 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3296 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3297 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3298 v2f32, fmul_su, fadd_mlx>,
3299 Requires<[HasNEON, UseFPVMLx]>;
3300 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3301 v4f32, v2f32, fmul_su, fadd_mlx>,
3302 Requires<[HasNEON, UseFPVMLx]>;
3304 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3305 (mul (v8i16 QPR:$src2),
3306 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3307 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3308 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3309 (DSubReg_i16_reg imm:$lane))),
3310 (SubReg_i16_lane imm:$lane)))>;
3312 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3313 (mul (v4i32 QPR:$src2),
3314 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3315 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3316 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3317 (DSubReg_i32_reg imm:$lane))),
3318 (SubReg_i32_lane imm:$lane)))>;
3320 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3321 (fmul_su (v4f32 QPR:$src2),
3322 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3323 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3325 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3326 (DSubReg_i32_reg imm:$lane))),
3327 (SubReg_i32_lane imm:$lane)))>,
3328 Requires<[HasNEON, UseFPVMLx]>;
3330 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3331 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3332 "vmlal", "s", NEONvmulls, add>;
3333 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3334 "vmlal", "u", NEONvmullu, add>;
3336 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3337 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3339 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3340 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3341 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3342 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3344 // VMLS : Vector Multiply Subtract (integer and floating-point)
3345 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3346 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3347 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3348 v2f32, fmul_su, fsub_mlx>,
3349 Requires<[HasNEON, UseFPVMLx]>;
3350 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3351 v4f32, fmul_su, fsub_mlx>,
3352 Requires<[HasNEON, UseFPVMLx]>;
3353 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3354 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3355 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3356 v2f32, fmul_su, fsub_mlx>,
3357 Requires<[HasNEON, UseFPVMLx]>;
3358 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3359 v4f32, v2f32, fmul_su, fsub_mlx>,
3360 Requires<[HasNEON, UseFPVMLx]>;
3362 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3363 (mul (v8i16 QPR:$src2),
3364 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3365 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3366 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3367 (DSubReg_i16_reg imm:$lane))),
3368 (SubReg_i16_lane imm:$lane)))>;
3370 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3371 (mul (v4i32 QPR:$src2),
3372 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3373 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3374 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3375 (DSubReg_i32_reg imm:$lane))),
3376 (SubReg_i32_lane imm:$lane)))>;
3378 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3379 (fmul_su (v4f32 QPR:$src2),
3380 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3381 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3382 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3383 (DSubReg_i32_reg imm:$lane))),
3384 (SubReg_i32_lane imm:$lane)))>,
3385 Requires<[HasNEON, UseFPVMLx]>;
3387 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3388 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3389 "vmlsl", "s", NEONvmulls, sub>;
3390 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3391 "vmlsl", "u", NEONvmullu, sub>;
3393 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3394 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3396 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3397 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3398 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3399 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3401 // Vector Subtract Operations.
3403 // VSUB : Vector Subtract (integer and floating-point)
3404 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3405 "vsub", "i", sub, 0>;
3406 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3407 v2f32, v2f32, fsub, 0>;
3408 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3409 v4f32, v4f32, fsub, 0>;
3410 // VSUBL : Vector Subtract Long (Q = D - D)
3411 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3412 "vsubl", "s", sub, sext, 0>;
3413 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3414 "vsubl", "u", sub, zext, 0>;
3415 // VSUBW : Vector Subtract Wide (Q = Q - D)
3416 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3417 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3418 // VHSUB : Vector Halving Subtract
3419 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3420 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3421 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3422 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3423 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3424 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3425 // VQSUB : Vector Saturing Subtract
3426 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3427 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3428 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3429 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3430 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3431 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3432 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3433 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3434 int_arm_neon_vsubhn, 0>;
3435 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3436 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3437 int_arm_neon_vrsubhn, 0>;
3439 // Vector Comparisons.
3441 // VCEQ : Vector Compare Equal
3442 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3443 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3444 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3446 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3449 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3450 "$Vd, $Vm, #0", NEONvceqz>;
3452 // VCGE : Vector Compare Greater Than or Equal
3453 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3454 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3455 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3456 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3457 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3459 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3462 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3463 "$Vd, $Vm, #0", NEONvcgez>;
3464 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3465 "$Vd, $Vm, #0", NEONvclez>;
3467 // VCGT : Vector Compare Greater Than
3468 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3469 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3470 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3471 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3472 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3474 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3477 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3478 "$Vd, $Vm, #0", NEONvcgtz>;
3479 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3480 "$Vd, $Vm, #0", NEONvcltz>;
3482 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3483 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3484 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3485 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3486 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3487 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3488 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3489 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3490 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3491 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3492 // VTST : Vector Test Bits
3493 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3494 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3496 // Vector Bitwise Operations.
3498 def vnotd : PatFrag<(ops node:$in),
3499 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3500 def vnotq : PatFrag<(ops node:$in),
3501 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3504 // VAND : Vector Bitwise AND
3505 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3506 v2i32, v2i32, and, 1>;
3507 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3508 v4i32, v4i32, and, 1>;
3510 // VEOR : Vector Bitwise Exclusive OR
3511 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3512 v2i32, v2i32, xor, 1>;
3513 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3514 v4i32, v4i32, xor, 1>;
3516 // VORR : Vector Bitwise OR
3517 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3518 v2i32, v2i32, or, 1>;
3519 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3520 v4i32, v4i32, or, 1>;
3522 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3523 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3525 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3527 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3528 let Inst{9} = SIMM{9};
3531 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3532 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3534 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3536 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3537 let Inst{10-9} = SIMM{10-9};
3540 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3541 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3543 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3545 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3546 let Inst{9} = SIMM{9};
3549 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3550 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3552 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3554 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3555 let Inst{10-9} = SIMM{10-9};
3559 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3560 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3561 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3562 "vbic", "$Vd, $Vn, $Vm", "",
3563 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3564 (vnotd DPR:$Vm))))]>;
3565 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3566 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3567 "vbic", "$Vd, $Vn, $Vm", "",
3568 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3569 (vnotq QPR:$Vm))))]>;
3571 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3572 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3574 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3576 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3577 let Inst{9} = SIMM{9};
3580 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3581 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3583 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3585 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3586 let Inst{10-9} = SIMM{10-9};
3589 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3590 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3592 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3594 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3595 let Inst{9} = SIMM{9};
3598 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3599 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3601 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3603 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3604 let Inst{10-9} = SIMM{10-9};
3607 // VORN : Vector Bitwise OR NOT
3608 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3609 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3610 "vorn", "$Vd, $Vn, $Vm", "",
3611 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3612 (vnotd DPR:$Vm))))]>;
3613 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3614 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3615 "vorn", "$Vd, $Vn, $Vm", "",
3616 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3617 (vnotq QPR:$Vm))))]>;
3619 // VMVN : Vector Bitwise NOT (Immediate)
3621 let isReMaterializable = 1 in {
3623 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3624 (ins nModImm:$SIMM), IIC_VMOVImm,
3625 "vmvn", "i16", "$Vd, $SIMM", "",
3626 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3627 let Inst{9} = SIMM{9};
3630 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3631 (ins nModImm:$SIMM), IIC_VMOVImm,
3632 "vmvn", "i16", "$Vd, $SIMM", "",
3633 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3634 let Inst{9} = SIMM{9};
3637 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3638 (ins nModImm:$SIMM), IIC_VMOVImm,
3639 "vmvn", "i32", "$Vd, $SIMM", "",
3640 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3641 let Inst{11-8} = SIMM{11-8};
3644 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3645 (ins nModImm:$SIMM), IIC_VMOVImm,
3646 "vmvn", "i32", "$Vd, $SIMM", "",
3647 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3648 let Inst{11-8} = SIMM{11-8};
3652 // VMVN : Vector Bitwise NOT
3653 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3654 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3655 "vmvn", "$Vd, $Vm", "",
3656 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3657 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3658 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3659 "vmvn", "$Vd, $Vm", "",
3660 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3661 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3662 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3664 // VBSL : Vector Bitwise Select
3665 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3666 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3667 N3RegFrm, IIC_VCNTiD,
3668 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3670 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3671 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3672 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3673 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3674 N3RegFrm, IIC_VCNTiQ,
3675 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3677 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3678 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3680 // VBIF : Vector Bitwise Insert if False
3681 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3682 // FIXME: This instruction's encoding MAY NOT BE correct.
3683 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3684 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3685 N3RegFrm, IIC_VBINiD,
3686 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3687 [/* For disassembly only; pattern left blank */]>;
3688 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3689 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3690 N3RegFrm, IIC_VBINiQ,
3691 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3692 [/* For disassembly only; pattern left blank */]>;
3694 // VBIT : Vector Bitwise Insert if True
3695 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3696 // FIXME: This instruction's encoding MAY NOT BE correct.
3697 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3698 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3699 N3RegFrm, IIC_VBINiD,
3700 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3701 [/* For disassembly only; pattern left blank */]>;
3702 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3703 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3704 N3RegFrm, IIC_VBINiQ,
3705 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3706 [/* For disassembly only; pattern left blank */]>;
3708 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3709 // for equivalent operations with different register constraints; it just
3712 // Vector Absolute Differences.
3714 // VABD : Vector Absolute Difference
3715 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3716 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3717 "vabd", "s", int_arm_neon_vabds, 1>;
3718 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3719 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3720 "vabd", "u", int_arm_neon_vabdu, 1>;
3721 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3722 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3723 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3724 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3726 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3727 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3728 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3729 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3730 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3732 // VABA : Vector Absolute Difference and Accumulate
3733 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3734 "vaba", "s", int_arm_neon_vabds, add>;
3735 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3736 "vaba", "u", int_arm_neon_vabdu, add>;
3738 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3739 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3740 "vabal", "s", int_arm_neon_vabds, zext, add>;
3741 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3742 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3744 // Vector Maximum and Minimum.
3746 // VMAX : Vector Maximum
3747 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3748 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3749 "vmax", "s", int_arm_neon_vmaxs, 1>;
3750 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3751 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3752 "vmax", "u", int_arm_neon_vmaxu, 1>;
3753 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3755 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3756 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3758 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3760 // VMIN : Vector Minimum
3761 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3762 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3763 "vmin", "s", int_arm_neon_vmins, 1>;
3764 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3765 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3766 "vmin", "u", int_arm_neon_vminu, 1>;
3767 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3769 v2f32, v2f32, int_arm_neon_vmins, 1>;
3770 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3772 v4f32, v4f32, int_arm_neon_vmins, 1>;
3774 // Vector Pairwise Operations.
3776 // VPADD : Vector Pairwise Add
3777 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3779 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3780 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3782 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3783 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3785 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3786 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3787 IIC_VPBIND, "vpadd", "f32",
3788 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3790 // VPADDL : Vector Pairwise Add Long
3791 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3792 int_arm_neon_vpaddls>;
3793 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3794 int_arm_neon_vpaddlu>;
3796 // VPADAL : Vector Pairwise Add and Accumulate Long
3797 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3798 int_arm_neon_vpadals>;
3799 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3800 int_arm_neon_vpadalu>;
3802 // VPMAX : Vector Pairwise Maximum
3803 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3804 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3805 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3806 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3807 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3808 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3809 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3810 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3811 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3812 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3813 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3814 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3815 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3816 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3818 // VPMIN : Vector Pairwise Minimum
3819 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3820 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3821 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3822 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3823 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3824 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3825 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3826 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3827 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3828 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3829 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3830 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3831 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3832 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3834 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3836 // VRECPE : Vector Reciprocal Estimate
3837 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3838 IIC_VUNAD, "vrecpe", "u32",
3839 v2i32, v2i32, int_arm_neon_vrecpe>;
3840 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3841 IIC_VUNAQ, "vrecpe", "u32",
3842 v4i32, v4i32, int_arm_neon_vrecpe>;
3843 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3844 IIC_VUNAD, "vrecpe", "f32",
3845 v2f32, v2f32, int_arm_neon_vrecpe>;
3846 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3847 IIC_VUNAQ, "vrecpe", "f32",
3848 v4f32, v4f32, int_arm_neon_vrecpe>;
3850 // VRECPS : Vector Reciprocal Step
3851 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3852 IIC_VRECSD, "vrecps", "f32",
3853 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3854 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3855 IIC_VRECSQ, "vrecps", "f32",
3856 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3858 // VRSQRTE : Vector Reciprocal Square Root Estimate
3859 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3860 IIC_VUNAD, "vrsqrte", "u32",
3861 v2i32, v2i32, int_arm_neon_vrsqrte>;
3862 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3863 IIC_VUNAQ, "vrsqrte", "u32",
3864 v4i32, v4i32, int_arm_neon_vrsqrte>;
3865 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3866 IIC_VUNAD, "vrsqrte", "f32",
3867 v2f32, v2f32, int_arm_neon_vrsqrte>;
3868 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3869 IIC_VUNAQ, "vrsqrte", "f32",
3870 v4f32, v4f32, int_arm_neon_vrsqrte>;
3872 // VRSQRTS : Vector Reciprocal Square Root Step
3873 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3874 IIC_VRECSD, "vrsqrts", "f32",
3875 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3876 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3877 IIC_VRECSQ, "vrsqrts", "f32",
3878 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3882 // VSHL : Vector Shift
3883 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3884 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3885 "vshl", "s", int_arm_neon_vshifts>;
3886 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3887 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3888 "vshl", "u", int_arm_neon_vshiftu>;
3889 // VSHL : Vector Shift Left (Immediate)
3890 defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
3892 // VSHR : Vector Shift Right (Immediate)
3893 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", NEONvshrs,
3895 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", NEONvshru,
3898 // VSHLL : Vector Shift Left Long
3899 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
3900 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
3902 // VSHLL : Vector Shift Left Long (with maximum shift count)
3903 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
3904 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
3905 ValueType OpTy, SDNode OpNode>
3906 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
3907 ResTy, OpTy, OpNode> {
3908 let Inst{21-16} = op21_16;
3910 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
3911 v8i16, v8i8, NEONvshlli>;
3912 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
3913 v4i32, v4i16, NEONvshlli>;
3914 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
3915 v2i64, v2i32, NEONvshlli>;
3917 // VSHRN : Vector Shift Right and Narrow
3918 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
3921 // VRSHL : Vector Rounding Shift
3922 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
3923 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3924 "vrshl", "s", int_arm_neon_vrshifts>;
3925 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
3926 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3927 "vrshl", "u", int_arm_neon_vrshiftu>;
3928 // VRSHR : Vector Rounding Shift Right
3929 defm VRSHRs : N2VSh_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", NEONvrshrs,
3931 defm VRSHRu : N2VSh_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", NEONvrshru,
3934 // VRSHRN : Vector Rounding Shift Right and Narrow
3935 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
3938 // VQSHL : Vector Saturating Shift
3939 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
3940 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3941 "vqshl", "s", int_arm_neon_vqshifts>;
3942 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
3943 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3944 "vqshl", "u", int_arm_neon_vqshiftu>;
3945 // VQSHL : Vector Saturating Shift Left (Immediate)
3946 defm VQSHLsi : N2VSh_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls,
3948 defm VQSHLui : N2VSh_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu,
3950 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
3951 defm VQSHLsu : N2VSh_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu,
3954 // VQSHRN : Vector Saturating Shift Right and Narrow
3955 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
3957 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
3960 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
3961 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
3964 // VQRSHL : Vector Saturating Rounding Shift
3965 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
3966 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3967 "vqrshl", "s", int_arm_neon_vqrshifts>;
3968 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
3969 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
3970 "vqrshl", "u", int_arm_neon_vqrshiftu>;
3972 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
3973 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
3975 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
3978 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
3979 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
3982 // VSRA : Vector Shift Right and Accumulate
3983 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
3984 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
3985 // VRSRA : Vector Rounding Shift Right and Accumulate
3986 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
3987 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
3989 // VSLI : Vector Shift Left and Insert
3990 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli", NEONvsli, N2RegVShLFrm>;
3991 // VSRI : Vector Shift Right and Insert
3992 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri", NEONvsri, N2RegVShRFrm>;
3994 // Vector Absolute and Saturating Absolute.
3996 // VABS : Vector Absolute Value
3997 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
3998 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4000 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4001 IIC_VUNAD, "vabs", "f32",
4002 v2f32, v2f32, int_arm_neon_vabs>;
4003 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4004 IIC_VUNAQ, "vabs", "f32",
4005 v4f32, v4f32, int_arm_neon_vabs>;
4007 // VQABS : Vector Saturating Absolute Value
4008 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4009 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4010 int_arm_neon_vqabs>;
4014 def vnegd : PatFrag<(ops node:$in),
4015 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4016 def vnegq : PatFrag<(ops node:$in),
4017 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4019 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4020 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4021 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4022 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4023 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4024 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4025 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4026 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4028 // VNEG : Vector Negate (integer)
4029 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4030 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4031 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4032 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4033 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4034 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4036 // VNEG : Vector Negate (floating-point)
4037 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4038 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4039 "vneg", "f32", "$Vd, $Vm", "",
4040 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4041 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4042 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4043 "vneg", "f32", "$Vd, $Vm", "",
4044 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4046 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4047 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4048 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4049 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4050 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4051 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4053 // VQNEG : Vector Saturating Negate
4054 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4055 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4056 int_arm_neon_vqneg>;
4058 // Vector Bit Counting Operations.
4060 // VCLS : Vector Count Leading Sign Bits
4061 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4062 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4064 // VCLZ : Vector Count Leading Zeros
4065 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4066 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4068 // VCNT : Vector Count One Bits
4069 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4070 IIC_VCNTiD, "vcnt", "8",
4071 v8i8, v8i8, int_arm_neon_vcnt>;
4072 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4073 IIC_VCNTiQ, "vcnt", "8",
4074 v16i8, v16i8, int_arm_neon_vcnt>;
4076 // Vector Swap -- for disassembly only.
4077 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4078 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4079 "vswp", "$Vd, $Vm", "", []>;
4080 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4081 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4082 "vswp", "$Vd, $Vm", "", []>;
4084 // Vector Move Operations.
4086 // VMOV : Vector Move (Register)
4088 let neverHasSideEffects = 1 in {
4089 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4090 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4091 let Vn{4-0} = Vm{4-0};
4093 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4094 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4095 let Vn{4-0} = Vm{4-0};
4098 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4099 // be expanded after register allocation is completed.
4100 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4103 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4105 } // neverHasSideEffects
4107 // VMOV : Vector Move (Immediate)
4109 let isReMaterializable = 1 in {
4110 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4111 (ins nModImm:$SIMM), IIC_VMOVImm,
4112 "vmov", "i8", "$Vd, $SIMM", "",
4113 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4114 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4115 (ins nModImm:$SIMM), IIC_VMOVImm,
4116 "vmov", "i8", "$Vd, $SIMM", "",
4117 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4119 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4120 (ins nModImm:$SIMM), IIC_VMOVImm,
4121 "vmov", "i16", "$Vd, $SIMM", "",
4122 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4123 let Inst{9} = SIMM{9};
4126 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4127 (ins nModImm:$SIMM), IIC_VMOVImm,
4128 "vmov", "i16", "$Vd, $SIMM", "",
4129 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4130 let Inst{9} = SIMM{9};
4133 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4134 (ins nModImm:$SIMM), IIC_VMOVImm,
4135 "vmov", "i32", "$Vd, $SIMM", "",
4136 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4137 let Inst{11-8} = SIMM{11-8};
4140 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4141 (ins nModImm:$SIMM), IIC_VMOVImm,
4142 "vmov", "i32", "$Vd, $SIMM", "",
4143 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4144 let Inst{11-8} = SIMM{11-8};
4147 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4148 (ins nModImm:$SIMM), IIC_VMOVImm,
4149 "vmov", "i64", "$Vd, $SIMM", "",
4150 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4151 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4152 (ins nModImm:$SIMM), IIC_VMOVImm,
4153 "vmov", "i64", "$Vd, $SIMM", "",
4154 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4155 } // isReMaterializable
4157 // VMOV : Vector Get Lane (move scalar to ARM core register)
4159 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4160 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4161 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4162 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4164 let Inst{21} = lane{2};
4165 let Inst{6-5} = lane{1-0};
4167 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4168 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4169 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4170 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4172 let Inst{21} = lane{1};
4173 let Inst{6} = lane{0};
4175 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4176 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4177 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4178 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4180 let Inst{21} = lane{2};
4181 let Inst{6-5} = lane{1-0};
4183 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4184 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4185 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4186 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4188 let Inst{21} = lane{1};
4189 let Inst{6} = lane{0};
4191 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4192 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4193 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4194 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4196 let Inst{21} = lane{0};
4198 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4199 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4200 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4201 (DSubReg_i8_reg imm:$lane))),
4202 (SubReg_i8_lane imm:$lane))>;
4203 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4204 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4205 (DSubReg_i16_reg imm:$lane))),
4206 (SubReg_i16_lane imm:$lane))>;
4207 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4208 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4209 (DSubReg_i8_reg imm:$lane))),
4210 (SubReg_i8_lane imm:$lane))>;
4211 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4212 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4213 (DSubReg_i16_reg imm:$lane))),
4214 (SubReg_i16_lane imm:$lane))>;
4215 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4216 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4217 (DSubReg_i32_reg imm:$lane))),
4218 (SubReg_i32_lane imm:$lane))>;
4219 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4220 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4221 (SSubReg_f32_reg imm:$src2))>;
4222 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4223 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4224 (SSubReg_f32_reg imm:$src2))>;
4225 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4226 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4227 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4228 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4231 // VMOV : Vector Set Lane (move ARM core register to scalar)
4233 let Constraints = "$src1 = $V" in {
4234 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4235 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4236 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4237 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4238 GPR:$R, imm:$lane))]> {
4239 let Inst{21} = lane{2};
4240 let Inst{6-5} = lane{1-0};
4242 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4243 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4244 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4245 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4246 GPR:$R, imm:$lane))]> {
4247 let Inst{21} = lane{1};
4248 let Inst{6} = lane{0};
4250 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4251 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4252 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4253 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4254 GPR:$R, imm:$lane))]> {
4255 let Inst{21} = lane{0};
4258 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4259 (v16i8 (INSERT_SUBREG QPR:$src1,
4260 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4261 (DSubReg_i8_reg imm:$lane))),
4262 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4263 (DSubReg_i8_reg imm:$lane)))>;
4264 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4265 (v8i16 (INSERT_SUBREG QPR:$src1,
4266 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4267 (DSubReg_i16_reg imm:$lane))),
4268 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4269 (DSubReg_i16_reg imm:$lane)))>;
4270 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4271 (v4i32 (INSERT_SUBREG QPR:$src1,
4272 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4273 (DSubReg_i32_reg imm:$lane))),
4274 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4275 (DSubReg_i32_reg imm:$lane)))>;
4277 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4278 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4279 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4280 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4281 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4282 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4284 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4285 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4286 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4287 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4289 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4290 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4291 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4292 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4293 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4294 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4296 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4297 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4298 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4299 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4300 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4301 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4303 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4304 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4305 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4307 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4308 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4309 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4311 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4312 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4313 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4316 // VDUP : Vector Duplicate (from ARM core register to all elements)
4318 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4319 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4320 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4321 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4322 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4323 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4324 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4325 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4327 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4328 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4329 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4330 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4331 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4332 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4334 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$V), (ins GPR:$R),
4335 IIC_VMOVIS, "vdup", "32", "$V, $R",
4336 [(set DPR:$V, (v2f32 (NEONvdup
4337 (f32 (bitconvert GPR:$R)))))]>;
4338 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$V), (ins GPR:$R),
4339 IIC_VMOVIS, "vdup", "32", "$V, $R",
4340 [(set QPR:$V, (v4f32 (NEONvdup
4341 (f32 (bitconvert GPR:$R)))))]>;
4343 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4345 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4347 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4348 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4349 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4351 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4352 ValueType ResTy, ValueType OpTy>
4353 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4354 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4355 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4358 // Inst{19-16} is partially specified depending on the element size.
4360 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4361 let Inst{19-17} = lane{2-0};
4363 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4364 let Inst{19-18} = lane{1-0};
4366 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4367 let Inst{19} = lane{0};
4369 def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
4370 let Inst{19} = lane{0};
4372 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4373 let Inst{19-17} = lane{2-0};
4375 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4376 let Inst{19-18} = lane{1-0};
4378 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4379 let Inst{19} = lane{0};
4381 def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
4382 let Inst{19} = lane{0};
4385 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4386 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4387 (DSubReg_i8_reg imm:$lane))),
4388 (SubReg_i8_lane imm:$lane)))>;
4389 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4390 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4391 (DSubReg_i16_reg imm:$lane))),
4392 (SubReg_i16_lane imm:$lane)))>;
4393 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4394 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4395 (DSubReg_i32_reg imm:$lane))),
4396 (SubReg_i32_lane imm:$lane)))>;
4397 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4398 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
4399 (DSubReg_i32_reg imm:$lane))),
4400 (SubReg_i32_lane imm:$lane)))>;
4402 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4403 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4404 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4405 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4407 // VMOVN : Vector Narrowing Move
4408 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4409 "vmovn", "i", trunc>;
4410 // VQMOVN : Vector Saturating Narrowing Move
4411 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4412 "vqmovn", "s", int_arm_neon_vqmovns>;
4413 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4414 "vqmovn", "u", int_arm_neon_vqmovnu>;
4415 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4416 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4417 // VMOVL : Vector Lengthening Move
4418 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4419 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4421 // Vector Conversions.
4423 // VCVT : Vector Convert Between Floating-Point and Integers
4424 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4425 v2i32, v2f32, fp_to_sint>;
4426 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4427 v2i32, v2f32, fp_to_uint>;
4428 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4429 v2f32, v2i32, sint_to_fp>;
4430 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4431 v2f32, v2i32, uint_to_fp>;
4433 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4434 v4i32, v4f32, fp_to_sint>;
4435 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4436 v4i32, v4f32, fp_to_uint>;
4437 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4438 v4f32, v4i32, sint_to_fp>;
4439 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4440 v4f32, v4i32, uint_to_fp>;
4442 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4443 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4444 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4445 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4446 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4447 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4448 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4449 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4450 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4452 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4453 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4454 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4455 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4456 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4457 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4458 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4459 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4461 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4462 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4463 IIC_VUNAQ, "vcvt", "f16.f32",
4464 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4465 Requires<[HasNEON, HasFP16]>;
4466 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4467 IIC_VUNAQ, "vcvt", "f32.f16",
4468 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4469 Requires<[HasNEON, HasFP16]>;
4473 // VREV64 : Vector Reverse elements within 64-bit doublewords
4475 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4476 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4477 (ins DPR:$Vm), IIC_VMOVD,
4478 OpcodeStr, Dt, "$Vd, $Vm", "",
4479 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4480 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4481 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4482 (ins QPR:$Vm), IIC_VMOVQ,
4483 OpcodeStr, Dt, "$Vd, $Vm", "",
4484 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4486 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4487 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4488 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4489 def VREV64df : VREV64D<0b10, "vrev64", "32", v2f32>;
4491 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4492 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4493 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4494 def VREV64qf : VREV64Q<0b10, "vrev64", "32", v4f32>;
4496 // VREV32 : Vector Reverse elements within 32-bit words
4498 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4499 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4500 (ins DPR:$Vm), IIC_VMOVD,
4501 OpcodeStr, Dt, "$Vd, $Vm", "",
4502 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4503 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4504 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4505 (ins QPR:$Vm), IIC_VMOVQ,
4506 OpcodeStr, Dt, "$Vd, $Vm", "",
4507 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4509 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4510 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4512 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4513 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4515 // VREV16 : Vector Reverse elements within 16-bit halfwords
4517 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4518 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4519 (ins DPR:$Vm), IIC_VMOVD,
4520 OpcodeStr, Dt, "$Vd, $Vm", "",
4521 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4522 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4523 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4524 (ins QPR:$Vm), IIC_VMOVQ,
4525 OpcodeStr, Dt, "$Vd, $Vm", "",
4526 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4528 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4529 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4531 // Other Vector Shuffles.
4533 // VEXT : Vector Extract
4535 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4536 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4537 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4538 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4539 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4540 (Ty DPR:$Vm), imm:$index)))]> {
4542 let Inst{11-8} = index{3-0};
4545 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4546 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4547 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4548 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4549 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4550 (Ty QPR:$Vm), imm:$index)))]> {
4552 let Inst{11-8} = index{3-0};
4555 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4556 let Inst{11-8} = index{3-0};
4558 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4559 let Inst{11-9} = index{2-0};
4562 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4563 let Inst{11-10} = index{1-0};
4564 let Inst{9-8} = 0b00;
4566 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4567 let Inst{11} = index{0};
4568 let Inst{10-8} = 0b000;
4571 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4572 let Inst{11-8} = index{3-0};
4574 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4575 let Inst{11-9} = index{2-0};
4578 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4579 let Inst{11-10} = index{1-0};
4580 let Inst{9-8} = 0b00;
4582 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4583 let Inst{11} = index{0};
4584 let Inst{10-8} = 0b000;
4587 // VTRN : Vector Transpose
4589 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4590 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4591 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4593 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4594 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4595 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4597 // VUZP : Vector Unzip (Deinterleave)
4599 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4600 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4601 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4603 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4604 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4605 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4607 // VZIP : Vector Zip (Interleave)
4609 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4610 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4611 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4613 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4614 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4615 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4617 // Vector Table Lookup and Table Extension.
4619 // VTBL : Vector Table Lookup
4621 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4622 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4623 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4624 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4625 let hasExtraSrcRegAllocReq = 1 in {
4627 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4628 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4629 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4631 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4632 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4633 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4635 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4636 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4638 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4639 } // hasExtraSrcRegAllocReq = 1
4642 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4644 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4646 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4648 // VTBX : Vector Table Extension
4650 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4651 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4652 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4653 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4654 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4655 let hasExtraSrcRegAllocReq = 1 in {
4657 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4658 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4659 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4661 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4662 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4663 NVTBLFrm, IIC_VTBX3,
4664 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4667 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4668 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4669 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4671 } // hasExtraSrcRegAllocReq = 1
4674 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4675 IIC_VTBX2, "$orig = $dst", []>;
4677 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4678 IIC_VTBX3, "$orig = $dst", []>;
4680 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4681 IIC_VTBX4, "$orig = $dst", []>;
4683 //===----------------------------------------------------------------------===//
4684 // NEON instructions for single-precision FP math
4685 //===----------------------------------------------------------------------===//
4687 class N2VSPat<SDNode OpNode, NeonI Inst>
4688 : NEONFPPat<(f32 (OpNode SPR:$a)),
4690 (v2f32 (COPY_TO_REGCLASS (Inst
4692 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4693 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4695 class N3VSPat<SDNode OpNode, NeonI Inst>
4696 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4698 (v2f32 (COPY_TO_REGCLASS (Inst
4700 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4703 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4704 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4706 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4707 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4709 (v2f32 (COPY_TO_REGCLASS (Inst
4711 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4714 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4717 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4718 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4720 def : N3VSPat<fadd, VADDfd>;
4721 def : N3VSPat<fsub, VSUBfd>;
4722 def : N3VSPat<fmul, VMULfd>;
4723 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4724 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4725 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4726 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4727 def : N2VSPat<fabs, VABSfd>;
4728 def : N2VSPat<fneg, VNEGfd>;
4729 def : N3VSPat<NEONfmax, VMAXfd>;
4730 def : N3VSPat<NEONfmin, VMINfd>;
4731 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4732 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4733 def : N2VSPat<arm_sitof, VCVTs2fd>;
4734 def : N2VSPat<arm_uitof, VCVTu2fd>;
4736 //===----------------------------------------------------------------------===//
4737 // Non-Instruction Patterns
4738 //===----------------------------------------------------------------------===//
4741 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4742 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4743 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4744 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4745 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4746 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4747 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4748 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4749 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4750 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4751 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4752 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4753 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4754 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4755 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4756 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4757 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4758 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4759 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4760 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4761 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4762 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4763 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4764 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4765 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4766 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4767 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4768 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4769 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4770 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4772 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4773 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4774 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4775 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4776 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4777 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4778 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4779 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4780 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4781 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4782 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4783 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4784 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4785 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4786 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4787 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4788 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4789 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4790 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4791 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4792 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4793 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4794 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4795 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4796 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4797 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4798 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4799 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4800 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4801 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;