1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the Thumb2 instruction set.
11 //===----------------------------------------------------------------------===//
13 // IT block predicate field
14 def it_pred_asmoperand : AsmOperandClass {
15 let Name = "ITCondCode";
16 let ParserMethod = "parseITCondCode";
18 def it_pred : Operand<i32> {
19 let PrintMethod = "printMandatoryPredicateOperand";
20 let ParserMatchClass = it_pred_asmoperand;
23 // IT block condition mask
24 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
25 def it_mask : Operand<i32> {
26 let PrintMethod = "printThumbITMask";
27 let ParserMatchClass = it_mask_asmoperand;
30 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
31 // (asr or lsl). The 6-bit immediate encodes as:
34 // {4-0} imm5 shift amount.
35 // asr #32 not allowed
36 def t2_shift_imm : Operand<i32> {
37 let PrintMethod = "printShiftImmOperand";
38 let ParserMatchClass = ShifterImmAsmOperand;
39 let DecoderMethod = "DecodeT2ShifterImmOperand";
42 // Shifted operands. No register controlled shifts for Thumb2.
43 // Note: We do not support rrx shifted operands yet.
44 def t2_so_reg : Operand<i32>, // reg imm
45 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
47 let EncoderMethod = "getT2SORegOpValue";
48 let PrintMethod = "printT2SOOperand";
49 let DecoderMethod = "DecodeSORegImmOperand";
50 let ParserMatchClass = ShiftedImmAsmOperand;
51 let MIOperandInfo = (ops rGPR, i32imm);
54 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
55 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
56 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
66 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
67 // described for so_imm_notSext def below, with sign extension from 16
69 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
70 APInt apIntN = N->getAPIntValue();
71 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
72 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
75 // t2_so_imm - Match a 32-bit immediate operand, which is an
76 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
77 // immediate splatted into multiple bytes of the word.
78 def t2_so_imm_asmoperand : AsmOperandClass {
80 let RenderMethod = "addImmOperands";
83 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
84 return ARM_AM::getT2SOImmVal(Imm) != -1;
86 let ParserMatchClass = t2_so_imm_asmoperand;
87 let EncoderMethod = "getT2SOImmOpValue";
88 let DecoderMethod = "DecodeT2SOImm";
91 // t2_so_imm_not - Match an immediate that is a complement
93 // Note: this pattern doesn't require an encoder method and such, as it's
94 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
95 // is handled by the destination instructions, which use t2_so_imm.
96 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
97 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
98 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
99 }], t2_so_imm_not_XFORM> {
100 let ParserMatchClass = t2_so_imm_not_asmoperand;
103 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
104 // if the upper 16 bits are zero.
105 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
106 APInt apIntN = N->getAPIntValue();
107 if (!apIntN.isIntN(16)) return false;
108 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
109 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
110 }], t2_so_imm_notSext16_XFORM> {
111 let ParserMatchClass = t2_so_imm_not_asmoperand;
114 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
115 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
116 def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{
117 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
118 }], t2_so_imm_neg_XFORM> {
119 let ParserMatchClass = t2_so_imm_neg_asmoperand;
122 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].
123 def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; }
124 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
125 return Imm >= 0 && Imm < 4096;
127 let ParserMatchClass = imm0_4095_asmoperand;
130 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
131 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
132 return (uint32_t)(-N->getZExtValue()) < 4096;
134 let ParserMatchClass = imm0_4095_neg_asmoperand;
137 def imm1_255_neg : PatLeaf<(i32 imm), [{
138 uint32_t Val = -N->getZExtValue();
139 return (Val > 0 && Val < 255);
142 def imm0_255_not : PatLeaf<(i32 imm), [{
143 return (uint32_t)(~N->getZExtValue()) < 255;
146 def lo5AllOne : PatLeaf<(i32 imm), [{
147 // Returns true if all low 5-bits are 1.
148 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
151 // Define Thumb2 specific addressing modes.
153 // t2addrmode_imm12 := reg + imm12
154 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
155 def t2addrmode_imm12 : MemOperand,
156 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
157 let PrintMethod = "printAddrModeImm12Operand<false>";
158 let EncoderMethod = "getAddrModeImm12OpValue";
159 let DecoderMethod = "DecodeT2AddrModeImm12";
160 let ParserMatchClass = t2addrmode_imm12_asmoperand;
161 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
164 // t2ldrlabel := imm12
165 def t2ldrlabel : Operand<i32> {
166 let EncoderMethod = "getAddrModeImm12OpValue";
167 let PrintMethod = "printThumbLdrLabelOperand";
170 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
171 def t2ldr_pcrel_imm12 : Operand<i32> {
172 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
173 // used for assembler pseudo instruction and maps to t2ldrlabel, so
174 // doesn't need encoder or print methods of its own.
177 // ADR instruction labels.
178 def t2adrlabel : Operand<i32> {
179 let EncoderMethod = "getT2AdrLabelOpValue";
180 let PrintMethod = "printAdrLabelOperand<0>";
183 // t2addrmode_posimm8 := reg + imm8
184 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
185 def t2addrmode_posimm8 : MemOperand {
186 let PrintMethod = "printT2AddrModeImm8Operand<false>";
187 let EncoderMethod = "getT2AddrModeImm8OpValue";
188 let DecoderMethod = "DecodeT2AddrModeImm8";
189 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
190 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
193 // t2addrmode_negimm8 := reg - imm8
194 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
195 def t2addrmode_negimm8 : MemOperand,
196 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
197 let PrintMethod = "printT2AddrModeImm8Operand<false>";
198 let EncoderMethod = "getT2AddrModeImm8OpValue";
199 let DecoderMethod = "DecodeT2AddrModeImm8";
200 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
201 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
204 // t2addrmode_imm8 := reg +/- imm8
205 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
206 class T2AddrMode_Imm8 : MemOperand,
207 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
208 let EncoderMethod = "getT2AddrModeImm8OpValue";
209 let DecoderMethod = "DecodeT2AddrModeImm8";
210 let ParserMatchClass = MemImm8OffsetAsmOperand;
211 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
214 def t2addrmode_imm8 : T2AddrMode_Imm8 {
215 let PrintMethod = "printT2AddrModeImm8Operand<false>";
218 def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
219 let PrintMethod = "printT2AddrModeImm8Operand<true>";
222 def t2am_imm8_offset : MemOperand,
223 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
224 [], [SDNPWantRoot]> {
225 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
226 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
227 let DecoderMethod = "DecodeT2Imm8";
230 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
231 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
232 class T2AddrMode_Imm8s4 : MemOperand {
233 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
234 let DecoderMethod = "DecodeT2AddrModeImm8s4";
235 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
236 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
239 def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 {
240 let PrintMethod = "printT2AddrModeImm8s4Operand<false>";
243 def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 {
244 let PrintMethod = "printT2AddrModeImm8s4Operand<true>";
247 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
248 def t2am_imm8s4_offset : MemOperand {
249 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
250 let EncoderMethod = "getT2Imm8s4OpValue";
251 let DecoderMethod = "DecodeT2Imm8S4";
254 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
255 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
256 let Name = "MemImm0_1020s4Offset";
258 def t2addrmode_imm0_1020s4 : MemOperand,
259 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> {
260 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
261 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
262 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
263 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
264 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
267 // t2addrmode_so_reg := reg + (reg << imm2)
268 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
269 def t2addrmode_so_reg : MemOperand,
270 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
271 let PrintMethod = "printT2AddrModeSoRegOperand";
272 let EncoderMethod = "getT2AddrModeSORegOpValue";
273 let DecoderMethod = "DecodeT2AddrModeSOReg";
274 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
275 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm);
278 // Addresses for the TBB/TBH instructions.
279 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
280 def addrmode_tbb : MemOperand {
281 let PrintMethod = "printAddrModeTBB";
282 let ParserMatchClass = addrmode_tbb_asmoperand;
283 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
285 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
286 def addrmode_tbh : MemOperand {
287 let PrintMethod = "printAddrModeTBH";
288 let ParserMatchClass = addrmode_tbh_asmoperand;
289 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
292 //===----------------------------------------------------------------------===//
293 // Multiclass helpers...
297 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
298 string opc, string asm, list<dag> pattern>
299 : T2I<oops, iops, itin, opc, asm, pattern> {
304 let Inst{26} = imm{11};
305 let Inst{14-12} = imm{10-8};
306 let Inst{7-0} = imm{7-0};
310 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
311 string opc, string asm, list<dag> pattern>
312 : T2sI<oops, iops, itin, opc, asm, pattern> {
318 let Inst{26} = imm{11};
319 let Inst{14-12} = imm{10-8};
320 let Inst{7-0} = imm{7-0};
323 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
324 string opc, string asm, list<dag> pattern>
325 : T2I<oops, iops, itin, opc, asm, pattern> {
329 let Inst{19-16} = Rn;
330 let Inst{26} = imm{11};
331 let Inst{14-12} = imm{10-8};
332 let Inst{7-0} = imm{7-0};
336 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
337 string opc, string asm, list<dag> pattern>
338 : T2I<oops, iops, itin, opc, asm, pattern> {
343 let Inst{3-0} = ShiftedRm{3-0};
344 let Inst{5-4} = ShiftedRm{6-5};
345 let Inst{14-12} = ShiftedRm{11-9};
346 let Inst{7-6} = ShiftedRm{8-7};
349 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
350 string opc, string asm, list<dag> pattern>
351 : T2sI<oops, iops, itin, opc, asm, pattern> {
356 let Inst{3-0} = ShiftedRm{3-0};
357 let Inst{5-4} = ShiftedRm{6-5};
358 let Inst{14-12} = ShiftedRm{11-9};
359 let Inst{7-6} = ShiftedRm{8-7};
362 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
363 string opc, string asm, list<dag> pattern>
364 : T2I<oops, iops, itin, opc, asm, pattern> {
368 let Inst{19-16} = Rn;
369 let Inst{3-0} = ShiftedRm{3-0};
370 let Inst{5-4} = ShiftedRm{6-5};
371 let Inst{14-12} = ShiftedRm{11-9};
372 let Inst{7-6} = ShiftedRm{8-7};
375 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
376 string opc, string asm, list<dag> pattern>
377 : T2I<oops, iops, itin, opc, asm, pattern> {
385 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
386 string opc, string asm, list<dag> pattern>
387 : T2sI<oops, iops, itin, opc, asm, pattern> {
395 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
396 string opc, string asm, list<dag> pattern>
397 : T2I<oops, iops, itin, opc, asm, pattern> {
401 let Inst{19-16} = Rn;
406 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
407 string opc, string asm, list<dag> pattern>
408 : T2I<oops, iops, itin, opc, asm, pattern> {
414 let Inst{19-16} = Rn;
415 let Inst{26} = imm{11};
416 let Inst{14-12} = imm{10-8};
417 let Inst{7-0} = imm{7-0};
420 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
421 string opc, string asm, list<dag> pattern>
422 : T2sI<oops, iops, itin, opc, asm, pattern> {
428 let Inst{19-16} = Rn;
429 let Inst{26} = imm{11};
430 let Inst{14-12} = imm{10-8};
431 let Inst{7-0} = imm{7-0};
434 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
435 string opc, string asm, list<dag> pattern>
436 : T2I<oops, iops, itin, opc, asm, pattern> {
443 let Inst{14-12} = imm{4-2};
444 let Inst{7-6} = imm{1-0};
447 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
448 string opc, string asm, list<dag> pattern>
449 : T2sI<oops, iops, itin, opc, asm, pattern> {
456 let Inst{14-12} = imm{4-2};
457 let Inst{7-6} = imm{1-0};
460 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
461 string opc, string asm, list<dag> pattern>
462 : T2I<oops, iops, itin, opc, asm, pattern> {
468 let Inst{19-16} = Rn;
472 class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin,
473 string asm, list<dag> pattern>
474 : T2XI<oops, iops, itin, asm, pattern> {
480 let Inst{19-16} = Rn;
484 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
485 string opc, string asm, list<dag> pattern>
486 : T2sI<oops, iops, itin, opc, asm, pattern> {
492 let Inst{19-16} = Rn;
496 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
497 string opc, string asm, list<dag> pattern>
498 : T2I<oops, iops, itin, opc, asm, pattern> {
504 let Inst{19-16} = Rn;
505 let Inst{3-0} = ShiftedRm{3-0};
506 let Inst{5-4} = ShiftedRm{6-5};
507 let Inst{14-12} = ShiftedRm{11-9};
508 let Inst{7-6} = ShiftedRm{8-7};
511 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
512 string opc, string asm, list<dag> pattern>
513 : T2sI<oops, iops, itin, opc, asm, pattern> {
519 let Inst{19-16} = Rn;
520 let Inst{3-0} = ShiftedRm{3-0};
521 let Inst{5-4} = ShiftedRm{6-5};
522 let Inst{14-12} = ShiftedRm{11-9};
523 let Inst{7-6} = ShiftedRm{8-7};
526 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
527 string opc, string asm, list<dag> pattern>
528 : T2I<oops, iops, itin, opc, asm, pattern> {
534 let Inst{19-16} = Rn;
535 let Inst{15-12} = Ra;
540 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
541 string opc, list<dag> pattern>
542 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
543 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>,
544 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> {
550 let Inst{31-23} = 0b111110111;
551 let Inst{22-20} = opc22_20;
552 let Inst{19-16} = Rn;
553 let Inst{15-12} = RdLo;
554 let Inst{11-8} = RdHi;
555 let Inst{7-4} = opc7_4;
558 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc>
559 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi),
560 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
561 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
562 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
563 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
569 let Inst{31-23} = 0b111110111;
570 let Inst{22-20} = opc22_20;
571 let Inst{19-16} = Rn;
572 let Inst{15-12} = RdLo;
573 let Inst{11-8} = RdHi;
574 let Inst{7-4} = opc7_4;
579 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
580 /// binary operation that produces a value. These are predicable and can be
581 /// changed to modify CPSR.
582 multiclass T2I_bin_irs<bits<4> opcod, string opc,
583 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
584 SDPatternOperator opnode, bit Commutable = 0,
587 def ri : T2sTwoRegImm<
588 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
589 opc, "\t$Rd, $Rn, $imm",
590 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
591 Sched<[WriteALU, ReadALU]> {
592 let Inst{31-27} = 0b11110;
594 let Inst{24-21} = opcod;
598 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
599 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
600 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
601 Sched<[WriteALU, ReadALU, ReadALU]> {
602 let isCommutable = Commutable;
603 let Inst{31-27} = 0b11101;
604 let Inst{26-25} = 0b01;
605 let Inst{24-21} = opcod;
606 let Inst{14-12} = 0b000; // imm3
607 let Inst{7-6} = 0b00; // imm2
608 let Inst{5-4} = 0b00; // type
611 def rs : T2sTwoRegShiftedReg<
612 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
613 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
614 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
615 Sched<[WriteALUsi, ReadALU]> {
616 let Inst{31-27} = 0b11101;
617 let Inst{26-25} = 0b01;
618 let Inst{24-21} = opcod;
620 // Assembly aliases for optional destination operand when it's the same
621 // as the source operand.
622 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
623 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
624 t2_so_imm:$imm, pred:$p,
626 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
627 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
630 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
631 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
632 t2_so_reg:$shift, pred:$p,
636 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
637 // the ".w" suffix to indicate that they are wide.
638 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
639 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
640 SDPatternOperator opnode, bit Commutable = 0> :
641 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
642 // Assembler aliases w/ the ".w" suffix.
643 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
644 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
646 // Assembler aliases w/o the ".w" suffix.
647 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
648 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
650 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
651 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
652 pred:$p, cc_out:$s)>;
654 // and with the optional destination operand, too.
655 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
656 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
657 pred:$p, cc_out:$s)>;
658 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
659 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
661 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
662 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
663 pred:$p, cc_out:$s)>;
666 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
667 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
668 /// it is equivalent to the T2I_bin_irs counterpart.
669 multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> {
671 def ri : T2sTwoRegImm<
672 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
673 opc, ".w\t$Rd, $Rn, $imm",
674 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
675 Sched<[WriteALU, ReadALU]> {
676 let Inst{31-27} = 0b11110;
678 let Inst{24-21} = opcod;
682 def rr : T2sThreeReg<
683 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
684 opc, "\t$Rd, $Rn, $Rm",
685 [/* For disassembly only; pattern left blank */]>,
686 Sched<[WriteALU, ReadALU, ReadALU]> {
687 let Inst{31-27} = 0b11101;
688 let Inst{26-25} = 0b01;
689 let Inst{24-21} = opcod;
690 let Inst{14-12} = 0b000; // imm3
691 let Inst{7-6} = 0b00; // imm2
692 let Inst{5-4} = 0b00; // type
695 def rs : T2sTwoRegShiftedReg<
696 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
697 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
698 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
699 Sched<[WriteALUsi, ReadALU]> {
700 let Inst{31-27} = 0b11101;
701 let Inst{26-25} = 0b01;
702 let Inst{24-21} = opcod;
706 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
707 /// instruction modifies the CPSR register.
709 /// These opcodes will be converted to the real non-S opcodes by
710 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
711 let hasPostISelHook = 1, Defs = [CPSR] in {
712 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
713 InstrItinClass iis, SDNode opnode,
714 bit Commutable = 0> {
716 def ri : t2PseudoInst<(outs rGPR:$Rd),
717 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
719 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
721 Sched<[WriteALU, ReadALU]>;
723 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
725 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
727 Sched<[WriteALU, ReadALU, ReadALU]> {
728 let isCommutable = Commutable;
731 def rs : t2PseudoInst<(outs rGPR:$Rd),
732 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
734 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
735 t2_so_reg:$ShiftedRm))]>,
736 Sched<[WriteALUsi, ReadALUsr]>;
740 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
741 /// operands are reversed.
742 let hasPostISelHook = 1, Defs = [CPSR] in {
743 multiclass T2I_rbin_s_is<SDNode opnode> {
745 def ri : t2PseudoInst<(outs rGPR:$Rd),
746 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
748 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
750 Sched<[WriteALU, ReadALU]>;
752 def rs : t2PseudoInst<(outs rGPR:$Rd),
753 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
755 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
757 Sched<[WriteALUsi, ReadALU]>;
761 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
762 /// patterns for a binary operation that produces a value.
763 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
764 bit Commutable = 0> {
766 // The register-immediate version is re-materializable. This is useful
767 // in particular for taking the address of a local.
768 let isReMaterializable = 1 in {
769 def ri : T2sTwoRegImm<
770 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
771 opc, ".w\t$Rd, $Rn, $imm",
772 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
773 Sched<[WriteALU, ReadALU]> {
774 let Inst{31-27} = 0b11110;
777 let Inst{23-21} = op23_21;
783 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
784 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
785 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
786 Sched<[WriteALU, ReadALU]> {
790 let Inst{31-27} = 0b11110;
791 let Inst{26} = imm{11};
792 let Inst{25-24} = 0b10;
793 let Inst{23-21} = op23_21;
794 let Inst{20} = 0; // The S bit.
795 let Inst{19-16} = Rn;
797 let Inst{14-12} = imm{10-8};
799 let Inst{7-0} = imm{7-0};
802 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
803 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
804 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
805 Sched<[WriteALU, ReadALU, ReadALU]> {
806 let isCommutable = Commutable;
807 let Inst{31-27} = 0b11101;
808 let Inst{26-25} = 0b01;
810 let Inst{23-21} = op23_21;
811 let Inst{14-12} = 0b000; // imm3
812 let Inst{7-6} = 0b00; // imm2
813 let Inst{5-4} = 0b00; // type
816 def rs : T2sTwoRegShiftedReg<
817 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
818 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
819 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
820 Sched<[WriteALUsi, ReadALU]> {
821 let Inst{31-27} = 0b11101;
822 let Inst{26-25} = 0b01;
824 let Inst{23-21} = op23_21;
828 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
829 /// for a binary operation that produces a value and use the carry
830 /// bit. It's not predicable.
831 let Defs = [CPSR], Uses = [CPSR] in {
832 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode,
833 bit Commutable = 0> {
835 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
836 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
837 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
838 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
839 let Inst{31-27} = 0b11110;
841 let Inst{24-21} = opcod;
845 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
846 opc, ".w\t$Rd, $Rn, $Rm",
847 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
848 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
849 let isCommutable = Commutable;
850 let Inst{31-27} = 0b11101;
851 let Inst{26-25} = 0b01;
852 let Inst{24-21} = opcod;
853 let Inst{14-12} = 0b000; // imm3
854 let Inst{7-6} = 0b00; // imm2
855 let Inst{5-4} = 0b00; // type
858 def rs : T2sTwoRegShiftedReg<
859 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
860 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
861 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
862 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
863 let Inst{31-27} = 0b11101;
864 let Inst{26-25} = 0b01;
865 let Inst{24-21} = opcod;
870 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
871 // rotate operation that produces a value.
872 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> {
874 def ri : T2sTwoRegShiftImm<
875 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
876 opc, ".w\t$Rd, $Rm, $imm",
877 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
879 let Inst{31-27} = 0b11101;
880 let Inst{26-21} = 0b010010;
881 let Inst{19-16} = 0b1111; // Rn
882 let Inst{5-4} = opcod;
885 def rr : T2sThreeReg<
886 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
887 opc, ".w\t$Rd, $Rn, $Rm",
888 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
890 let Inst{31-27} = 0b11111;
891 let Inst{26-23} = 0b0100;
892 let Inst{22-21} = opcod;
893 let Inst{15-12} = 0b1111;
894 let Inst{7-4} = 0b0000;
897 // Optional destination register
898 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
899 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
901 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
902 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
905 // Assembler aliases w/o the ".w" suffix.
906 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
907 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
909 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
910 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
913 // and with the optional destination operand, too.
914 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
915 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
917 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
918 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
922 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
923 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
924 /// a explicit result, only implicitly set CPSR.
925 multiclass T2I_cmp_irs<bits<4> opcod, string opc, RegisterClass LHSGPR,
926 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
927 SDPatternOperator opnode> {
928 let isCompare = 1, Defs = [CPSR] in {
930 def ri : T2OneRegCmpImm<
931 (outs), (ins LHSGPR:$Rn, t2_so_imm:$imm), iii,
932 opc, ".w\t$Rn, $imm",
933 [(opnode LHSGPR:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
934 let Inst{31-27} = 0b11110;
936 let Inst{24-21} = opcod;
937 let Inst{20} = 1; // The S bit.
939 let Inst{11-8} = 0b1111; // Rd
942 def rr : T2TwoRegCmp<
943 (outs), (ins LHSGPR:$Rn, rGPR:$Rm), iir,
945 [(opnode LHSGPR:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
946 let Inst{31-27} = 0b11101;
947 let Inst{26-25} = 0b01;
948 let Inst{24-21} = opcod;
949 let Inst{20} = 1; // The S bit.
950 let Inst{14-12} = 0b000; // imm3
951 let Inst{11-8} = 0b1111; // Rd
952 let Inst{7-6} = 0b00; // imm2
953 let Inst{5-4} = 0b00; // type
956 def rs : T2OneRegCmpShiftedReg<
957 (outs), (ins LHSGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
958 opc, ".w\t$Rn, $ShiftedRm",
959 [(opnode LHSGPR:$Rn, t2_so_reg:$ShiftedRm)]>,
960 Sched<[WriteCMPsi]> {
961 let Inst{31-27} = 0b11101;
962 let Inst{26-25} = 0b01;
963 let Inst{24-21} = opcod;
964 let Inst{20} = 1; // The S bit.
965 let Inst{11-8} = 0b1111; // Rd
969 // Assembler aliases w/o the ".w" suffix.
970 // No alias here for 'rr' version as not all instantiations of this
971 // multiclass want one (CMP in particular, does not).
972 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
973 (!cast<Instruction>(NAME#"ri") LHSGPR:$Rn, t2_so_imm:$imm, pred:$p)>;
974 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
975 (!cast<Instruction>(NAME#"rs") LHSGPR:$Rn, t2_so_reg:$shift, pred:$p)>;
978 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
979 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
980 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
982 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
983 opc, ".w\t$Rt, $addr",
984 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
988 let Inst{31-25} = 0b1111100;
989 let Inst{24} = signed;
991 let Inst{22-21} = opcod;
992 let Inst{20} = 1; // load
993 let Inst{19-16} = addr{16-13}; // Rn
994 let Inst{15-12} = Rt;
995 let Inst{11-0} = addr{11-0}; // imm
997 let DecoderMethod = "DecodeT2LoadImm12";
999 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1000 opc, "\t$Rt, $addr",
1001 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1005 let Inst{31-27} = 0b11111;
1006 let Inst{26-25} = 0b00;
1007 let Inst{24} = signed;
1009 let Inst{22-21} = opcod;
1010 let Inst{20} = 1; // load
1011 let Inst{19-16} = addr{12-9}; // Rn
1012 let Inst{15-12} = Rt;
1014 // Offset: index==TRUE, wback==FALSE
1015 let Inst{10} = 1; // The P bit.
1016 let Inst{9} = addr{8}; // U
1017 let Inst{8} = 0; // The W bit.
1018 let Inst{7-0} = addr{7-0}; // imm
1020 let DecoderMethod = "DecodeT2LoadImm8";
1022 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
1023 opc, ".w\t$Rt, $addr",
1024 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]>,
1026 let Inst{31-27} = 0b11111;
1027 let Inst{26-25} = 0b00;
1028 let Inst{24} = signed;
1030 let Inst{22-21} = opcod;
1031 let Inst{20} = 1; // load
1032 let Inst{11-6} = 0b000000;
1035 let Inst{15-12} = Rt;
1038 let Inst{19-16} = addr{9-6}; // Rn
1039 let Inst{3-0} = addr{5-2}; // Rm
1040 let Inst{5-4} = addr{1-0}; // imm
1042 let DecoderMethod = "DecodeT2LoadShift";
1045 // pci variant is very similar to i12, but supports negative offsets
1047 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1048 opc, ".w\t$Rt, $addr",
1049 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>,
1051 let isReMaterializable = 1;
1052 let Inst{31-27} = 0b11111;
1053 let Inst{26-25} = 0b00;
1054 let Inst{24} = signed;
1055 let Inst{22-21} = opcod;
1056 let Inst{20} = 1; // load
1057 let Inst{19-16} = 0b1111; // Rn
1060 let Inst{15-12} = Rt{3-0};
1063 let Inst{23} = addr{12}; // add = (U == '1')
1064 let Inst{11-0} = addr{11-0};
1066 let DecoderMethod = "DecodeT2LoadLabel";
1070 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1071 multiclass T2I_st<bits<2> opcod, string opc,
1072 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1074 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1075 opc, ".w\t$Rt, $addr",
1076 [(opnode target:$Rt, t2addrmode_imm12:$addr)]>,
1078 let Inst{31-27} = 0b11111;
1079 let Inst{26-23} = 0b0001;
1080 let Inst{22-21} = opcod;
1081 let Inst{20} = 0; // !load
1084 let Inst{15-12} = Rt;
1087 let addr{12} = 1; // add = TRUE
1088 let Inst{19-16} = addr{16-13}; // Rn
1089 let Inst{23} = addr{12}; // U
1090 let Inst{11-0} = addr{11-0}; // imm
1092 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1093 opc, "\t$Rt, $addr",
1094 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]>,
1096 let Inst{31-27} = 0b11111;
1097 let Inst{26-23} = 0b0000;
1098 let Inst{22-21} = opcod;
1099 let Inst{20} = 0; // !load
1101 // Offset: index==TRUE, wback==FALSE
1102 let Inst{10} = 1; // The P bit.
1103 let Inst{8} = 0; // The W bit.
1106 let Inst{15-12} = Rt;
1109 let Inst{19-16} = addr{12-9}; // Rn
1110 let Inst{9} = addr{8}; // U
1111 let Inst{7-0} = addr{7-0}; // imm
1113 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1114 opc, ".w\t$Rt, $addr",
1115 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]>,
1117 let Inst{31-27} = 0b11111;
1118 let Inst{26-23} = 0b0000;
1119 let Inst{22-21} = opcod;
1120 let Inst{20} = 0; // !load
1121 let Inst{11-6} = 0b000000;
1124 let Inst{15-12} = Rt;
1127 let Inst{19-16} = addr{9-6}; // Rn
1128 let Inst{3-0} = addr{5-2}; // Rm
1129 let Inst{5-4} = addr{1-0}; // imm
1133 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1134 /// register and one whose operand is a register rotated by 8/16/24.
1135 class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops,
1136 string opc, string oprs,
1138 : T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> {
1140 let Inst{31-27} = 0b11111;
1141 let Inst{26-23} = 0b0100;
1142 let Inst{22-20} = opcod;
1143 let Inst{19-16} = 0b1111; // Rn
1144 let Inst{15-12} = 0b1111;
1146 let Inst{5-4} = rot; // rotate
1149 class T2I_ext_rrot<bits<3> opcod, string opc>
1150 : T2I_ext_rrot_base<opcod,
1152 (ins rGPR:$Rm, rot_imm:$rot),
1153 opc, ".w\t$Rd, $Rm$rot", []>,
1154 Requires<[IsThumb2]>,
1155 Sched<[WriteALU, ReadALU]>;
1157 // UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier.
1158 class T2I_ext_rrot_xtb16<bits<3> opcod, string opc>
1159 : T2I_ext_rrot_base<opcod,
1161 (ins rGPR:$Rm, rot_imm:$rot),
1162 opc, "\t$Rd, $Rm$rot", []>,
1163 Requires<[HasDSP, IsThumb2]>,
1164 Sched<[WriteALU, ReadALU]>;
1166 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1167 /// register and one whose operand is a register rotated by 8/16/24.
1168 class T2I_exta_rrot<bits<3> opcod, string opc>
1169 : T2ThreeReg<(outs rGPR:$Rd),
1170 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1171 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1172 Requires<[HasDSP, IsThumb2]>,
1173 Sched<[WriteALU, ReadALU]> {
1175 let Inst{31-27} = 0b11111;
1176 let Inst{26-23} = 0b0100;
1177 let Inst{22-20} = opcod;
1178 let Inst{15-12} = 0b1111;
1180 let Inst{5-4} = rot;
1183 //===----------------------------------------------------------------------===//
1185 //===----------------------------------------------------------------------===//
1187 //===----------------------------------------------------------------------===//
1188 // Miscellaneous Instructions.
1191 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1192 string asm, list<dag> pattern>
1193 : T2XI<oops, iops, itin, asm, pattern> {
1197 let Inst{11-8} = Rd;
1198 let Inst{26} = label{11};
1199 let Inst{14-12} = label{10-8};
1200 let Inst{7-0} = label{7-0};
1203 // LEApcrel - Load a pc-relative address into a register without offending the
1205 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1206 (ins t2adrlabel:$addr, pred:$p),
1207 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1208 Sched<[WriteALU, ReadALU]> {
1209 let Inst{31-27} = 0b11110;
1210 let Inst{25-24} = 0b10;
1211 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1214 let Inst{19-16} = 0b1111; // Rn
1219 let Inst{11-8} = Rd;
1220 let Inst{23} = addr{12};
1221 let Inst{21} = addr{12};
1222 let Inst{26} = addr{11};
1223 let Inst{14-12} = addr{10-8};
1224 let Inst{7-0} = addr{7-0};
1226 let DecoderMethod = "DecodeT2Adr";
1229 let hasSideEffects = 0, isReMaterializable = 1 in
1230 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1231 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1232 let hasSideEffects = 1 in
1233 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1234 (ins i32imm:$label, pred:$p),
1236 []>, Sched<[WriteALU, ReadALU]>;
1239 //===----------------------------------------------------------------------===//
1240 // Load / store Instructions.
1244 let canFoldAsLoad = 1, isReMaterializable = 1 in
1245 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
1247 // Loads with zero extension
1248 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1249 GPRnopc, zextloadi16>;
1250 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1251 GPRnopc, zextloadi8>;
1253 // Loads with sign extension
1254 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1255 GPRnopc, sextloadi16>;
1256 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1257 GPRnopc, sextloadi8>;
1259 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1261 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1262 (ins t2addrmode_imm8s4:$addr),
1263 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>,
1265 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1267 // zextload i1 -> zextload i8
1268 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1269 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1270 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1271 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1272 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1273 (t2LDRBs t2addrmode_so_reg:$addr)>;
1274 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1275 (t2LDRBpci tconstpool:$addr)>;
1277 // extload -> zextload
1278 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1280 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1281 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1282 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1283 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1284 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1285 (t2LDRBs t2addrmode_so_reg:$addr)>;
1286 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1287 (t2LDRBpci tconstpool:$addr)>;
1289 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1290 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1291 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1292 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1293 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1294 (t2LDRBs t2addrmode_so_reg:$addr)>;
1295 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1296 (t2LDRBpci tconstpool:$addr)>;
1298 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1299 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1300 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1301 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1302 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1303 (t2LDRHs t2addrmode_so_reg:$addr)>;
1304 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1305 (t2LDRHpci tconstpool:$addr)>;
1307 // FIXME: The destination register of the loads and stores can't be PC, but
1308 // can be SP. We need another regclass (similar to rGPR) to represent
1309 // that. Not a pressing issue since these are selected manually,
1314 let mayLoad = 1, hasSideEffects = 0 in {
1315 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1316 (ins t2addrmode_imm8_pre:$addr),
1317 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1318 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1321 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1322 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1323 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1324 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1327 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1328 (ins t2addrmode_imm8_pre:$addr),
1329 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1330 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1333 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1334 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1335 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1336 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1339 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1340 (ins t2addrmode_imm8_pre:$addr),
1341 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1342 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>,
1345 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1346 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1347 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1348 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1351 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1352 (ins t2addrmode_imm8_pre:$addr),
1353 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1354 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1355 []>, Sched<[WriteLd]>;
1357 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1358 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1359 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1360 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1363 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1364 (ins t2addrmode_imm8_pre:$addr),
1365 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1366 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1367 []>, Sched<[WriteLd]>;
1369 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1370 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1371 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1372 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
1374 } // mayLoad = 1, hasSideEffects = 0
1376 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1377 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1378 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1379 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1380 "\t$Rt, $addr", []>, Sched<[WriteLd]> {
1383 let Inst{31-27} = 0b11111;
1384 let Inst{26-25} = 0b00;
1385 let Inst{24} = signed;
1387 let Inst{22-21} = type;
1388 let Inst{20} = 1; // load
1389 let Inst{19-16} = addr{12-9};
1390 let Inst{15-12} = Rt;
1392 let Inst{10-8} = 0b110; // PUW.
1393 let Inst{7-0} = addr{7-0};
1395 let DecoderMethod = "DecodeT2LoadT";
1398 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1399 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1400 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1401 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1402 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1404 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
1405 string opc, string asm, list<dag> pattern>
1406 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
1407 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
1411 let Inst{31-27} = 0b11101;
1412 let Inst{26-24} = 0b000;
1413 let Inst{23-20} = bits23_20;
1414 let Inst{11-6} = 0b111110;
1415 let Inst{5-4} = bit54;
1416 let Inst{3-0} = 0b1111;
1418 // Encode instruction operands
1419 let Inst{19-16} = addr;
1420 let Inst{15-12} = Rt;
1423 def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
1424 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>,
1426 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1427 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>,
1429 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1430 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>,
1434 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>;
1435 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1436 rGPR, truncstorei8>;
1437 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1438 rGPR, truncstorei16>;
1441 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1442 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1443 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1444 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>,
1449 let mayStore = 1, hasSideEffects = 0 in {
1450 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1451 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
1452 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1453 "str", "\t$Rt, $addr!",
1454 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1457 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1458 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1459 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1460 "strh", "\t$Rt, $addr!",
1461 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1464 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1465 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
1466 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1467 "strb", "\t$Rt, $addr!",
1468 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>,
1470 } // mayStore = 1, hasSideEffects = 0
1472 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1473 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1474 t2am_imm8_offset:$offset),
1475 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1476 "str", "\t$Rt, $Rn$offset",
1477 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1478 [(set GPRnopc:$Rn_wb,
1479 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1480 t2am_imm8_offset:$offset))]>,
1483 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1484 (ins rGPR:$Rt, addr_offset_none:$Rn,
1485 t2am_imm8_offset:$offset),
1486 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1487 "strh", "\t$Rt, $Rn$offset",
1488 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1489 [(set GPRnopc:$Rn_wb,
1490 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1491 t2am_imm8_offset:$offset))]>,
1494 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1495 (ins rGPR:$Rt, addr_offset_none:$Rn,
1496 t2am_imm8_offset:$offset),
1497 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1498 "strb", "\t$Rt, $Rn$offset",
1499 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1500 [(set GPRnopc:$Rn_wb,
1501 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1502 t2am_imm8_offset:$offset))]>,
1505 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1506 // put the patterns on the instruction definitions directly as ISel wants
1507 // the address base and offset to be separate operands, not a single
1508 // complex operand like we represent the instructions themselves. The
1509 // pseudos map between the two.
1510 let usesCustomInserter = 1,
1511 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1512 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1513 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1515 [(set GPRnopc:$Rn_wb,
1516 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1518 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1519 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1521 [(set GPRnopc:$Rn_wb,
1522 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1524 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1525 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1527 [(set GPRnopc:$Rn_wb,
1528 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
1532 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1534 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1535 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1536 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1537 "\t$Rt, $addr", []>, Sched<[WriteST]> {
1538 let Inst{31-27} = 0b11111;
1539 let Inst{26-25} = 0b00;
1540 let Inst{24} = 0; // not signed
1542 let Inst{22-21} = type;
1543 let Inst{20} = 0; // store
1545 let Inst{10-8} = 0b110; // PUW
1549 let Inst{15-12} = Rt;
1550 let Inst{19-16} = addr{12-9};
1551 let Inst{7-0} = addr{7-0};
1554 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1555 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1556 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1558 // ldrd / strd pre / post variants
1561 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1562 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
1563 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1565 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1569 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1570 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1571 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1572 "$addr.base = $wb", []>, Sched<[WriteLd]>;
1575 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1576 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1577 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1578 "$addr.base = $wb", []>, Sched<[WriteST]> {
1579 let DecoderMethod = "DecodeT2STRDPreInstruction";
1583 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1584 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1585 t2am_imm8s4_offset:$imm),
1586 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1587 "$addr.base = $wb", []>, Sched<[WriteST]>;
1589 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
1590 string opc, string asm, list<dag> pattern>
1591 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
1592 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]>,
1597 let Inst{31-27} = 0b11101;
1598 let Inst{26-20} = 0b0001100;
1599 let Inst{11-6} = 0b111110;
1600 let Inst{5-4} = bit54;
1601 let Inst{3-0} = 0b1111;
1603 // Encode instruction operands
1604 let Inst{19-16} = addr;
1605 let Inst{15-12} = Rt;
1608 def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1609 "stl", "\t$Rt, $addr", []>;
1610 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1611 "stlb", "\t$Rt, $addr", []>;
1612 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1613 "stlh", "\t$Rt, $addr", []>;
1615 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1616 // data/instruction access.
1617 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1618 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1619 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1621 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1623 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1624 Sched<[WritePreLd]> {
1625 let Inst{31-25} = 0b1111100;
1626 let Inst{24} = instr;
1629 let Inst{21} = write;
1631 let Inst{15-12} = 0b1111;
1634 let Inst{19-16} = addr{16-13}; // Rn
1635 let Inst{11-0} = addr{11-0}; // imm12
1637 let DecoderMethod = "DecodeT2LoadImm12";
1640 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1642 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1643 Sched<[WritePreLd]> {
1644 let Inst{31-25} = 0b1111100;
1645 let Inst{24} = instr;
1646 let Inst{23} = 0; // U = 0
1648 let Inst{21} = write;
1650 let Inst{15-12} = 0b1111;
1651 let Inst{11-8} = 0b1100;
1654 let Inst{19-16} = addr{12-9}; // Rn
1655 let Inst{7-0} = addr{7-0}; // imm8
1657 let DecoderMethod = "DecodeT2LoadImm8";
1660 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1662 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1663 Sched<[WritePreLd]> {
1664 let Inst{31-25} = 0b1111100;
1665 let Inst{24} = instr;
1666 let Inst{23} = 0; // add = TRUE for T1
1668 let Inst{21} = write;
1670 let Inst{15-12} = 0b1111;
1671 let Inst{11-6} = 0b000000;
1674 let Inst{19-16} = addr{9-6}; // Rn
1675 let Inst{3-0} = addr{5-2}; // Rm
1676 let Inst{5-4} = addr{1-0}; // imm2
1678 let DecoderMethod = "DecodeT2LoadShift";
1682 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1683 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1684 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1686 // pci variant is very similar to i12, but supports negative offsets
1687 // from the PC. Only PLD and PLI have pci variants (not PLDW)
1688 class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
1689 IIC_Preload, opc, "\t$addr",
1690 [(ARMPreload (ARMWrapper tconstpool:$addr),
1691 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
1692 let Inst{31-25} = 0b1111100;
1693 let Inst{24} = inst;
1694 let Inst{22-20} = 0b001;
1695 let Inst{19-16} = 0b1111;
1696 let Inst{15-12} = 0b1111;
1699 let Inst{23} = addr{12}; // add = (U == '1')
1700 let Inst{11-0} = addr{11-0}; // imm12
1702 let DecoderMethod = "DecodeT2LoadLabel";
1705 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1706 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1708 //===----------------------------------------------------------------------===//
1709 // Load / store multiple Instructions.
1712 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1713 InstrItinClass itin_upd, bit L_bit> {
1715 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1716 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1720 let Inst{31-27} = 0b11101;
1721 let Inst{26-25} = 0b00;
1722 let Inst{24-23} = 0b01; // Increment After
1724 let Inst{21} = 0; // No writeback
1725 let Inst{20} = L_bit;
1726 let Inst{19-16} = Rn;
1727 let Inst{15-0} = regs;
1730 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1731 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1735 let Inst{31-27} = 0b11101;
1736 let Inst{26-25} = 0b00;
1737 let Inst{24-23} = 0b01; // Increment After
1739 let Inst{21} = 1; // Writeback
1740 let Inst{20} = L_bit;
1741 let Inst{19-16} = Rn;
1742 let Inst{15-0} = regs;
1745 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1746 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1750 let Inst{31-27} = 0b11101;
1751 let Inst{26-25} = 0b00;
1752 let Inst{24-23} = 0b10; // Decrement Before
1754 let Inst{21} = 0; // No writeback
1755 let Inst{20} = L_bit;
1756 let Inst{19-16} = Rn;
1757 let Inst{15-0} = regs;
1760 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1761 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1765 let Inst{31-27} = 0b11101;
1766 let Inst{26-25} = 0b00;
1767 let Inst{24-23} = 0b10; // Decrement Before
1769 let Inst{21} = 1; // Writeback
1770 let Inst{20} = L_bit;
1771 let Inst{19-16} = Rn;
1772 let Inst{15-0} = regs;
1776 let hasSideEffects = 0 in {
1778 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
1779 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1781 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1782 InstrItinClass itin_upd, bit L_bit> {
1784 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1785 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1789 let Inst{31-27} = 0b11101;
1790 let Inst{26-25} = 0b00;
1791 let Inst{24-23} = 0b01; // Increment After
1793 let Inst{21} = 0; // No writeback
1794 let Inst{20} = L_bit;
1795 let Inst{19-16} = Rn;
1797 let Inst{14} = regs{14};
1799 let Inst{12-0} = regs{12-0};
1802 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1803 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1807 let Inst{31-27} = 0b11101;
1808 let Inst{26-25} = 0b00;
1809 let Inst{24-23} = 0b01; // Increment After
1811 let Inst{21} = 1; // Writeback
1812 let Inst{20} = L_bit;
1813 let Inst{19-16} = Rn;
1815 let Inst{14} = regs{14};
1817 let Inst{12-0} = regs{12-0};
1820 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1821 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1825 let Inst{31-27} = 0b11101;
1826 let Inst{26-25} = 0b00;
1827 let Inst{24-23} = 0b10; // Decrement Before
1829 let Inst{21} = 0; // No writeback
1830 let Inst{20} = L_bit;
1831 let Inst{19-16} = Rn;
1833 let Inst{14} = regs{14};
1835 let Inst{12-0} = regs{12-0};
1838 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1839 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1843 let Inst{31-27} = 0b11101;
1844 let Inst{26-25} = 0b00;
1845 let Inst{24-23} = 0b10; // Decrement Before
1847 let Inst{21} = 1; // Writeback
1848 let Inst{20} = L_bit;
1849 let Inst{19-16} = Rn;
1851 let Inst{14} = regs{14};
1853 let Inst{12-0} = regs{12-0};
1858 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1859 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1864 //===----------------------------------------------------------------------===//
1865 // Move Instructions.
1868 let hasSideEffects = 0 in
1869 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,
1870 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1871 let Inst{31-27} = 0b11101;
1872 let Inst{26-25} = 0b01;
1873 let Inst{24-21} = 0b0010;
1874 let Inst{19-16} = 0b1111; // Rn
1875 let Inst{14-12} = 0b000;
1876 let Inst{7-4} = 0b0000;
1878 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
1879 pred:$p, zero_reg)>;
1880 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
1882 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
1885 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1886 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1887 AddedComplexity = 1 in
1888 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1889 "mov", ".w\t$Rd, $imm",
1890 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1891 let Inst{31-27} = 0b11110;
1893 let Inst{24-21} = 0b0010;
1894 let Inst{19-16} = 0b1111; // Rn
1898 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1899 // Use aliases to get that to play nice here.
1900 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1902 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1905 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1906 pred:$p, zero_reg)>;
1907 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1908 pred:$p, zero_reg)>;
1910 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1911 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1912 "movw", "\t$Rd, $imm",
1913 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
1914 Requires<[IsThumb, HasV8MBaseline]> {
1915 let Inst{31-27} = 0b11110;
1917 let Inst{24-21} = 0b0010;
1918 let Inst{20} = 0; // The S bit.
1924 let Inst{11-8} = Rd;
1925 let Inst{19-16} = imm{15-12};
1926 let Inst{26} = imm{11};
1927 let Inst{14-12} = imm{10-8};
1928 let Inst{7-0} = imm{7-0};
1929 let DecoderMethod = "DecodeT2MOVTWInstruction";
1932 def : InstAlias<"mov${p} $Rd, $imm",
1933 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
1934 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;
1936 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1937 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1940 let Constraints = "$src = $Rd" in {
1941 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1942 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1943 "movt", "\t$Rd, $imm",
1945 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1947 Requires<[IsThumb, HasV8MBaseline]> {
1948 let Inst{31-27} = 0b11110;
1950 let Inst{24-21} = 0b0110;
1951 let Inst{20} = 0; // The S bit.
1957 let Inst{11-8} = Rd;
1958 let Inst{19-16} = imm{15-12};
1959 let Inst{26} = imm{11};
1960 let Inst{14-12} = imm{10-8};
1961 let Inst{7-0} = imm{7-0};
1962 let DecoderMethod = "DecodeT2MOVTWInstruction";
1965 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1966 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1967 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
1970 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1972 //===----------------------------------------------------------------------===//
1973 // Extend Instructions.
1978 def t2SXTB : T2I_ext_rrot<0b100, "sxtb">;
1979 def t2SXTH : T2I_ext_rrot<0b000, "sxth">;
1980 def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">;
1982 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">;
1983 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">;
1984 def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">;
1986 def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8),
1987 (t2SXTB rGPR:$Rn, rot_imm:$rot)>;
1988 def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16),
1989 (t2SXTH rGPR:$Rn, rot_imm:$rot)>;
1990 def : Thumb2DSPPat<(add rGPR:$Rn,
1991 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)),
1992 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
1993 def : Thumb2DSPPat<(add rGPR:$Rn,
1994 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)),
1995 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
1996 def : Thumb2DSPPat<(int_arm_sxtb16 rGPR:$Rn),
1997 (t2SXTB16 rGPR:$Rn, 0)>;
1998 def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm),
1999 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
2000 def : Thumb2DSPPat<(int_arm_sxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),
2001 (t2SXTB16 rGPR:$Rn, rot_imm:$rot)>;
2002 def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),
2003 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2006 // A simple right-shift can also be used in most cases (the exception is the
2007 // SXTH operations with a rotate of 24: there the non-contiguous bits are
2009 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2010 (srl rGPR:$Rm, rot_imm:$rot), i8)),
2011 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2012 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2013 (srl rGPR:$Rm, imm8_or_16:$rot), i16)),
2014 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2015 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2016 (rotr rGPR:$Rm, (i32 24)), i16)),
2017 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
2018 def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg
2019 (or (srl rGPR:$Rm, (i32 24)),
2020 (shl rGPR:$Rm, (i32 8))), i16)),
2021 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>;
2025 let AddedComplexity = 16 in {
2026 def t2UXTB : T2I_ext_rrot<0b101, "uxtb">;
2027 def t2UXTH : T2I_ext_rrot<0b001, "uxth">;
2028 def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">;
2030 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF),
2031 (t2UXTB rGPR:$Rm, rot_imm:$rot)>;
2032 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF),
2033 (t2UXTH rGPR:$Rm, rot_imm:$rot)>;
2034 def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF),
2035 (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>;
2037 def : Thumb2DSPPat<(int_arm_uxtb16 rGPR:$Rm),
2038 (t2UXTB16 rGPR:$Rm, 0)>;
2039 def : Thumb2DSPPat<(int_arm_uxtb16 (rotr rGPR:$Rn, rot_imm:$rot)),
2040 (t2UXTB16 rGPR:$Rn, rot_imm:$rot)>;
2042 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2043 // The transformation should probably be done as a combiner action
2044 // instead so we can include a check for masking back in the upper
2045 // eight bits of the source into the lower eight bits of the result.
2046 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
2047 // (t2UXTB16 rGPR:$Src, 3)>,
2048 // Requires<[HasDSP, IsThumb2]>;
2049 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
2050 (t2UXTB16 rGPR:$Src, 1)>,
2051 Requires<[HasDSP, IsThumb2]>;
2053 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">;
2054 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">;
2055 def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">;
2057 def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
2059 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2060 def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot),
2062 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2063 def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot),
2065 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2066 def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot),
2068 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2069 def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm),
2070 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>;
2071 def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),
2072 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
2076 //===----------------------------------------------------------------------===//
2077 // Arithmetic Instructions.
2081 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
2082 defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
2084 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
2086 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
2087 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
2088 // AdjustInstrPostInstrSelection where we determine whether or not to
2089 // set the "s" bit based on CPSR liveness.
2091 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
2092 // support for an optional CPSR definition that corresponds to the DAG
2093 // node's second value. We can then eliminate the implicit def of CPSR.
2094 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;
2095 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;
2097 def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm),
2098 (t2SUBSri $Rn, t2_so_imm:$imm)>;
2099 def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>;
2100 def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
2101 (t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>;
2103 let hasPostISelHook = 1 in {
2104 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>;
2105 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>;
2108 def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm",
2109 (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
2110 def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm",
2111 (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
2113 def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm",
2114 (t2SUBri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2115 def : t2InstSubst<"addw${p} $rd, $rn, $imm",
2116 (t2SUBri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2117 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
2118 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2119 def : t2InstSubst<"subw${p} $rd, $rn, $imm",
2120 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2121 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
2122 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
2123 def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",
2124 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2125 def : t2InstSubst<"sub${p} $rd, $rn, $imm",
2126 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2128 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;
2130 // FIXME: Eliminate them if we can write def : Pat patterns which defines
2131 // CPSR and the implicit def of CPSR is not needed.
2132 defm t2RSBS : T2I_rbin_s_is <ARMsubc>;
2134 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2135 // The assume-no-carry-in form uses the negation of the input since add/sub
2136 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2137 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2139 // The AddedComplexity preferences the first variant over the others since
2140 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
2141 let AddedComplexity = 1 in
2142 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
2143 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
2144 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
2145 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
2146 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
2147 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
2148 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
2149 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2151 // Do the same for v8m targets since they support movw with a 16-bit value.
2152 def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm),
2153 (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>,
2154 Requires<[HasV8MBaseline]>;
2156 let AddedComplexity = 1 in
2157 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
2158 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
2159 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
2160 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
2161 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
2162 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
2163 // The with-carry-in form matches bitwise not instead of the negation.
2164 // Effectively, the inverse interpretation of the carry flag already accounts
2165 // for part of the negation.
2166 let AddedComplexity = 1 in
2167 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
2168 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
2169 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
2170 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
2171 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
2172 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
2174 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2175 NoItinerary, "sel", "\t$Rd, $Rn, $Rm",
2176 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2177 Requires<[IsThumb2, HasDSP]> {
2178 let Inst{31-27} = 0b11111;
2179 let Inst{26-24} = 0b010;
2181 let Inst{22-20} = 0b010;
2182 let Inst{15-12} = 0b1111;
2184 let Inst{6-4} = 0b000;
2187 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
2188 // And Miscellaneous operations -- for disassembly only
2189 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2190 list<dag> pat, dag iops, string asm>
2191 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2192 Requires<[IsThumb2, HasDSP]> {
2193 let Inst{31-27} = 0b11111;
2194 let Inst{26-23} = 0b0101;
2195 let Inst{22-20} = op22_20;
2196 let Inst{15-12} = 0b1111;
2197 let Inst{7-4} = op7_4;
2203 let Inst{11-8} = Rd;
2204 let Inst{19-16} = Rn;
2208 class T2I_pam_intrinsics<bits<3> op22_20, bits<4> op7_4, string opc,
2209 Intrinsic intrinsic>
2210 : T2I_pam<op22_20, op7_4, opc,
2211 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))],
2212 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
2214 class T2I_pam_intrinsics_rev<bits<3> op22_20, bits<4> op7_4, string opc>
2215 : T2I_pam<op22_20, op7_4, opc, [],
2216 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2218 // Saturating add/subtract
2219 def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>;
2220 def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>;
2221 def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>;
2222 def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>;
2223 def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>;
2224 def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>;
2225 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
2226 def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>;
2227 def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>;
2228 def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>;
2229 def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>;
2230 def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>;
2231 def t2QADD : T2I_pam_intrinsics_rev<0b000, 0b1000, "qadd">;
2232 def t2QSUB : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">;
2233 def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">;
2234 def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;
2236 def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, rGPR:$Rn),
2237 (t2QADD rGPR:$Rm, rGPR:$Rn)>;
2238 def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, rGPR:$Rn),
2239 (t2QSUB rGPR:$Rm, rGPR:$Rn)>;
2240 def : Thumb2DSPPat<(int_arm_qadd(int_arm_qadd rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
2241 (t2QDADD rGPR:$Rm, rGPR:$Rn)>;
2242 def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)),
2243 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>;
2245 // Signed/Unsigned add/subtract
2247 def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;
2248 def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>;
2249 def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>;
2250 def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>;
2251 def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>;
2252 def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>;
2253 def t2UASX : T2I_pam_intrinsics<0b010, 0b0100, "uasx", int_arm_uasx>;
2254 def t2UADD16 : T2I_pam_intrinsics<0b001, 0b0100, "uadd16", int_arm_uadd16>;
2255 def t2UADD8 : T2I_pam_intrinsics<0b000, 0b0100, "uadd8", int_arm_uadd8>;
2256 def t2USAX : T2I_pam_intrinsics<0b110, 0b0100, "usax", int_arm_usax>;
2257 def t2USUB16 : T2I_pam_intrinsics<0b101, 0b0100, "usub16", int_arm_usub16>;
2258 def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>;
2260 // Signed/Unsigned halving add/subtract
2262 def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>;
2263 def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>;
2264 def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>;
2265 def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>;
2266 def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>;
2267 def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>;
2268 def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;
2269 def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>;
2270 def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>;
2271 def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;
2272 def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>;
2273 def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>;
2275 // Helper class for disassembly only
2276 // A6.3.16 & A6.3.17
2277 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2278 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2279 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2280 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2281 let Inst{31-27} = 0b11111;
2282 let Inst{26-24} = 0b011;
2283 let Inst{23} = long;
2284 let Inst{22-20} = op22_20;
2285 let Inst{7-4} = op7_4;
2288 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2289 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2290 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2291 let Inst{31-27} = 0b11111;
2292 let Inst{26-24} = 0b011;
2293 let Inst{23} = long;
2294 let Inst{22-20} = op22_20;
2295 let Inst{7-4} = op7_4;
2298 // Unsigned Sum of Absolute Differences [and Accumulate].
2299 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2300 (ins rGPR:$Rn, rGPR:$Rm),
2301 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm",
2302 [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))]>,
2303 Requires<[IsThumb2, HasDSP]> {
2304 let Inst{15-12} = 0b1111;
2306 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2307 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2308 "usada8", "\t$Rd, $Rn, $Rm, $Ra",
2309 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
2310 Requires<[IsThumb2, HasDSP]>;
2312 // Signed/Unsigned saturate.
2313 let hasSideEffects = 1 in
2314 class T2SatI<dag iops, string opc, string asm>
2315 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {
2321 let Inst{31-24} = 0b11110011;
2322 let Inst{21} = sh{5};
2324 let Inst{19-16} = Rn;
2326 let Inst{14-12} = sh{4-2};
2327 let Inst{11-8} = Rd;
2328 let Inst{7-6} = sh{1-0};
2330 let Inst{4-0} = sat_imm;
2333 def t2SSAT: T2SatI<(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2334 "ssat", "\t$Rd, $sat_imm, $Rn$sh">,
2335 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2336 let Inst{23-22} = 0b00;
2340 def t2SSAT16: T2SatI<(ins imm1_16:$sat_imm, rGPR:$Rn),
2341 "ssat16", "\t$Rd, $sat_imm, $Rn">,
2342 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2343 let Inst{23-22} = 0b00;
2348 def t2USAT: T2SatI<(ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2349 "usat", "\t$Rd, $sat_imm, $Rn$sh">,
2350 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2351 let Inst{23-22} = 0b10;
2354 def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn),
2355 "usat16", "\t$Rd, $sat_imm, $Rn">,
2356 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2357 let Inst{23-22} = 0b10;
2362 def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
2363 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2364 def : T2Pat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
2365 (t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
2366 def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos),
2367 (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
2368 def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos),
2369 (t2USAT imm0_31:$pos, GPR:$a, 0)>;
2370 def : T2Pat<(int_arm_ssat16 GPR:$a, imm1_16:$pos),
2371 (t2SSAT16 imm1_16:$pos, GPR:$a)>;
2372 def : T2Pat<(int_arm_usat16 GPR:$a, imm0_15:$pos),
2373 (t2USAT16 imm0_15:$pos, GPR:$a)>;
2375 //===----------------------------------------------------------------------===//
2376 // Shift and rotate Instructions.
2379 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
2380 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2381 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>;
2382 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, rotr>;
2384 // LSL #0 is actually MOV, and has slightly different permitted registers to
2385 // LSL with non-zero shift
2386 def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0",
2387 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2388 def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",
2389 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2391 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2392 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2393 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2395 let Uses = [CPSR] in {
2396 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2397 "rrx", "\t$Rd, $Rm",
2398 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2399 let Inst{31-27} = 0b11101;
2400 let Inst{26-25} = 0b01;
2401 let Inst{24-21} = 0b0010;
2402 let Inst{19-16} = 0b1111; // Rn
2403 let Inst{14-12} = 0b000;
2404 let Inst{7-4} = 0b0011;
2408 let isCodeGenOnly = 1, Defs = [CPSR] in {
2409 def t2MOVsrl_flag : T2TwoRegShiftImm<
2410 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2411 "lsrs", ".w\t$Rd, $Rm, #1",
2412 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2414 let Inst{31-27} = 0b11101;
2415 let Inst{26-25} = 0b01;
2416 let Inst{24-21} = 0b0010;
2417 let Inst{20} = 1; // The S bit.
2418 let Inst{19-16} = 0b1111; // Rn
2419 let Inst{5-4} = 0b01; // Shift type.
2420 // Shift amount = Inst{14-12:7-6} = 1.
2421 let Inst{14-12} = 0b000;
2422 let Inst{7-6} = 0b01;
2424 def t2MOVsra_flag : T2TwoRegShiftImm<
2425 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2426 "asrs", ".w\t$Rd, $Rm, #1",
2427 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2429 let Inst{31-27} = 0b11101;
2430 let Inst{26-25} = 0b01;
2431 let Inst{24-21} = 0b0010;
2432 let Inst{20} = 1; // The S bit.
2433 let Inst{19-16} = 0b1111; // Rn
2434 let Inst{5-4} = 0b10; // Shift type.
2435 // Shift amount = Inst{14-12:7-6} = 1.
2436 let Inst{14-12} = 0b000;
2437 let Inst{7-6} = 0b01;
2441 //===----------------------------------------------------------------------===//
2442 // Bitwise Instructions.
2445 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2446 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>;
2447 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2448 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>;
2449 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2450 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>;
2452 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2453 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2454 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2456 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2457 string opc, string asm, list<dag> pattern>
2458 : T2I<oops, iops, itin, opc, asm, pattern> {
2463 let Inst{11-8} = Rd;
2464 let Inst{4-0} = msb{4-0};
2465 let Inst{14-12} = lsb{4-2};
2466 let Inst{7-6} = lsb{1-0};
2469 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2470 string opc, string asm, list<dag> pattern>
2471 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2474 let Inst{19-16} = Rn;
2477 let Constraints = "$src = $Rd" in
2478 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2479 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2480 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2481 let Inst{31-27} = 0b11110;
2482 let Inst{26} = 0; // should be 0.
2484 let Inst{24-20} = 0b10110;
2485 let Inst{19-16} = 0b1111; // Rn
2487 let Inst{5} = 0; // should be 0.
2490 let msb{4-0} = imm{9-5};
2491 let lsb{4-0} = imm{4-0};
2494 def t2SBFX: T2TwoRegBitFI<
2495 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2496 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2497 let Inst{31-27} = 0b11110;
2499 let Inst{24-20} = 0b10100;
2503 def t2UBFX: T2TwoRegBitFI<
2504 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2505 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2506 let Inst{31-27} = 0b11110;
2508 let Inst{24-20} = 0b11100;
2512 // A8.8.247 UDF - Undefined (Encoding T2)
2513 def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
2514 [(int_arm_undefined imm0_65535:$imm16)]> {
2516 let Inst{31-29} = 0b111;
2517 let Inst{28-27} = 0b10;
2518 let Inst{26-20} = 0b1111111;
2519 let Inst{19-16} = imm16{15-12};
2521 let Inst{14-12} = 0b010;
2522 let Inst{11-0} = imm16{11-0};
2525 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2526 let Constraints = "$src = $Rd" in {
2527 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2528 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2529 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2530 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2531 bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2532 let Inst{31-27} = 0b11110;
2533 let Inst{26} = 0; // should be 0.
2535 let Inst{24-20} = 0b10110;
2537 let Inst{5} = 0; // should be 0.
2540 let msb{4-0} = imm{9-5};
2541 let lsb{4-0} = imm{4-0};
2545 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2546 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2547 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2549 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2550 /// unary operation that produces a value. These are predicable and can be
2551 /// changed to modify CPSR.
2552 multiclass T2I_un_irs<bits<4> opcod, string opc,
2553 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2555 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2557 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2559 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2560 let isAsCheapAsAMove = Cheap;
2561 let isReMaterializable = ReMat;
2562 let isMoveImm = MoveImm;
2563 let Inst{31-27} = 0b11110;
2565 let Inst{24-21} = opcod;
2566 let Inst{19-16} = 0b1111; // Rn
2570 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2571 opc, ".w\t$Rd, $Rm",
2572 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2573 let Inst{31-27} = 0b11101;
2574 let Inst{26-25} = 0b01;
2575 let Inst{24-21} = opcod;
2576 let Inst{19-16} = 0b1111; // Rn
2577 let Inst{14-12} = 0b000; // imm3
2578 let Inst{7-6} = 0b00; // imm2
2579 let Inst{5-4} = 0b00; // type
2582 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2583 opc, ".w\t$Rd, $ShiftedRm",
2584 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2586 let Inst{31-27} = 0b11101;
2587 let Inst{26-25} = 0b01;
2588 let Inst{24-21} = opcod;
2589 let Inst{19-16} = 0b1111; // Rn
2593 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2594 let AddedComplexity = 1 in
2595 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2596 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2599 let AddedComplexity = 1 in
2600 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2601 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2603 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2604 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2605 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2608 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2609 // will match the extended, not the original bitWidth for $src.
2610 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2611 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2614 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2615 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2616 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2617 Requires<[IsThumb2]>;
2619 def : T2Pat<(t2_so_imm_not:$src),
2620 (t2MVNi t2_so_imm_not:$src)>;
2622 // There are shorter Thumb encodings for ADD than ORR, so to increase
2623 // Thumb2SizeReduction's chances later on we select a t2ADD for an or where
2625 def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm),
2626 (t2ADDri $Rn, t2_so_imm:$imm)>;
2628 def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm),
2629 (t2ADDri12 $Rn, imm0_4095:$Rm)>;
2631 def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm),
2632 (t2ADDrr $Rn, $Rm)>;
2634 //===----------------------------------------------------------------------===//
2635 // Multiply Instructions.
2637 let isCommutable = 1 in
2638 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2639 "mul", "\t$Rd, $Rn, $Rm",
2640 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>,
2641 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
2642 let Inst{31-27} = 0b11111;
2643 let Inst{26-23} = 0b0110;
2644 let Inst{22-20} = 0b000;
2645 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2646 let Inst{7-4} = 0b0000; // Multiply
2649 class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern>
2650 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2651 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2652 Requires<[IsThumb2, UseMulOps]>,
2653 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2654 let Inst{31-27} = 0b11111;
2655 let Inst{26-23} = 0b0110;
2656 let Inst{22-20} = 0b000;
2657 let Inst{7-4} = op7_4;
2660 def t2MLA : T2FourRegMLA<0b0000, "mla",
2661 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
2663 def t2MLS: T2FourRegMLA<0b0001, "mls",
2664 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
2667 // Extra precision multiplies with low / high results
2668 let hasSideEffects = 0 in {
2669 let isCommutable = 1 in {
2670 def t2SMULL : T2MulLong<0b000, 0b0000, "smull",
2671 [(set rGPR:$RdLo, rGPR:$RdHi,
2672 (smullohi rGPR:$Rn, rGPR:$Rm))]>;
2673 def t2UMULL : T2MulLong<0b010, 0b0000, "umull",
2674 [(set rGPR:$RdLo, rGPR:$RdHi,
2675 (umullohi rGPR:$Rn, rGPR:$Rm))]>;
2678 // Multiply + accumulate
2679 def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">;
2680 def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">;
2681 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
2684 // Rounding variants of the below included for disassembly only
2686 // Most significant word multiply
2687 class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern>
2688 : T2ThreeReg<(outs rGPR:$Rd),
2689 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2690 opc, "\t$Rd, $Rn, $Rm", pattern>,
2691 Requires<[IsThumb2, HasDSP]>,
2692 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
2693 let Inst{31-27} = 0b11111;
2694 let Inst{26-23} = 0b0110;
2695 let Inst{22-20} = 0b101;
2696 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2697 let Inst{7-4} = op7_4;
2699 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
2702 T2SMMUL<0b0001, "smmulr",
2703 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>;
2705 class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
2707 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2708 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2709 Requires<[IsThumb2, HasDSP, UseMulOps]>,
2710 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2711 let Inst{31-27} = 0b11111;
2712 let Inst{26-23} = 0b0110;
2713 let Inst{22-20} = op22_20;
2714 let Inst{7-4} = op7_4;
2717 def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
2718 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
2719 def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar",
2720 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
2721 def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
2722 def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr",
2723 [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
2725 class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
2727 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
2728 "\t$Rd, $Rn, $Rm", pattern>,
2729 Requires<[IsThumb2, HasDSP]>,
2730 Sched<[WriteMUL16, ReadMUL, ReadMUL]> {
2731 let Inst{31-27} = 0b11111;
2732 let Inst{26-23} = 0b0110;
2733 let Inst{22-20} = op22_20;
2734 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2735 let Inst{7-6} = 0b00;
2736 let Inst{5-4} = op5_4;
2739 def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
2740 [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>;
2741 def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
2742 [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>;
2743 def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb",
2744 [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>;
2745 def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
2746 [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>;
2747 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
2748 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;
2749 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",
2750 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;
2752 def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_bottom_16 rGPR:$Rm)),
2753 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>;
2754 def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_top_16 rGPR:$Rm)),
2755 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;
2756 def : Thumb2DSPPat<(mul (sext_top_16 rGPR:$Rn), sext_16_node:$Rm),
2757 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;
2759 def : Thumb2DSPPat<(int_arm_smulbb rGPR:$Rn, rGPR:$Rm),
2760 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>;
2761 def : Thumb2DSPPat<(int_arm_smulbt rGPR:$Rn, rGPR:$Rm),
2762 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>;
2763 def : Thumb2DSPPat<(int_arm_smultb rGPR:$Rn, rGPR:$Rm),
2764 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>;
2765 def : Thumb2DSPPat<(int_arm_smultt rGPR:$Rn, rGPR:$Rm),
2766 (t2SMULTT rGPR:$Rn, rGPR:$Rm)>;
2767 def : Thumb2DSPPat<(int_arm_smulwb rGPR:$Rn, rGPR:$Rm),
2768 (t2SMULWB rGPR:$Rn, rGPR:$Rm)>;
2769 def : Thumb2DSPPat<(int_arm_smulwt rGPR:$Rn, rGPR:$Rm),
2770 (t2SMULWT rGPR:$Rn, rGPR:$Rm)>;
2772 class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc,
2774 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
2775 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2776 Requires<[IsThumb2, HasDSP, UseMulOps]>,
2777 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]> {
2778 let Inst{31-27} = 0b11111;
2779 let Inst{26-23} = 0b0110;
2780 let Inst{22-20} = op22_20;
2781 let Inst{7-6} = 0b00;
2782 let Inst{5-4} = op5_4;
2785 def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",
2786 [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>;
2787 def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",
2788 [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>;
2789 def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
2790 [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>;
2791 def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
2792 [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>;
2793 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
2794 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
2795 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
2796 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
2798 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),
2799 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2800 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,
2801 (sext_bottom_16 rGPR:$Rm))),
2802 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2803 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,
2804 (sext_top_16 rGPR:$Rm))),
2805 (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2806 def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn),
2808 (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
2810 def : Thumb2DSPPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),
2811 (t2SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
2812 def : Thumb2DSPPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),
2813 (t2SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
2814 def : Thumb2DSPPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),
2815 (t2SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
2816 def : Thumb2DSPPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),
2817 (t2SMLATT GPR:$a, GPR:$b, GPR:$acc)>;
2818 def : Thumb2DSPPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),
2819 (t2SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
2820 def : Thumb2DSPPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),
2821 (t2SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;
2823 // Halfword multiple accumulate long: SMLAL<x><y>
2824 def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">,
2825 Requires<[IsThumb2, HasDSP]>;
2826 def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">,
2827 Requires<[IsThumb2, HasDSP]>;
2828 def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">,
2829 Requires<[IsThumb2, HasDSP]>;
2830 def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">,
2831 Requires<[IsThumb2, HasDSP]>;
2833 def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2834 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>;
2835 def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2836 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>;
2837 def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2838 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>;
2839 def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
2840 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>;
2842 class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc,
2843 Intrinsic intrinsic>
2844 : T2ThreeReg_mac<0, op22_20, op7_4,
2846 (ins rGPR:$Rn, rGPR:$Rm),
2847 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm",
2848 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))]>,
2849 Requires<[IsThumb2, HasDSP]>,
2850 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
2851 let Inst{15-12} = 0b1111;
2854 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2855 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>;
2856 def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx", int_arm_smuadx>;
2857 def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>;
2858 def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>;
2860 class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc,
2861 Intrinsic intrinsic>
2862 : T2FourReg_mac<0, op22_20, op7_4,
2864 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra),
2865 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra",
2866 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
2867 Requires<[IsThumb2, HasDSP]>;
2869 def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad", int_arm_smlad>;
2870 def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx", int_arm_smladx>;
2871 def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd", int_arm_smlsd>;
2872 def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>;
2874 class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc>
2875 : T2FourReg_mac<1, op22_20, op7_4,
2876 (outs rGPR:$Ra, rGPR:$Rd),
2877 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
2878 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
2879 RegConstraint<"$Ra = $RLo, $Rd = $RHi">,
2880 Requires<[IsThumb2, HasDSP]>,
2881 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
2883 def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
2884 def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
2885 def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
2886 def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
2888 def : Thumb2DSPPat<(ARMSmlald rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
2889 (t2SMLALD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
2890 def : Thumb2DSPPat<(ARMSmlaldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
2891 (t2SMLALDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
2892 def : Thumb2DSPPat<(ARMSmlsld rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
2893 (t2SMLSLD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
2894 def : Thumb2DSPPat<(ARMSmlsldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
2895 (t2SMLSLDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>;
2897 //===----------------------------------------------------------------------===//
2898 // Division Instructions.
2899 // Signed and unsigned division on v7-M
2901 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2902 "sdiv", "\t$Rd, $Rn, $Rm",
2903 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2904 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
2906 let Inst{31-27} = 0b11111;
2907 let Inst{26-21} = 0b011100;
2909 let Inst{15-12} = 0b1111;
2910 let Inst{7-4} = 0b1111;
2913 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2914 "udiv", "\t$Rd, $Rn, $Rm",
2915 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2916 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>,
2918 let Inst{31-27} = 0b11111;
2919 let Inst{26-21} = 0b011101;
2921 let Inst{15-12} = 0b1111;
2922 let Inst{7-4} = 0b1111;
2925 //===----------------------------------------------------------------------===//
2926 // Misc. Arithmetic Instructions.
2929 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2930 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2931 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2932 let Inst{31-27} = 0b11111;
2933 let Inst{26-22} = 0b01010;
2934 let Inst{21-20} = op1;
2935 let Inst{15-12} = 0b1111;
2936 let Inst{7-6} = 0b10;
2937 let Inst{5-4} = op2;
2941 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2942 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2945 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2946 "rbit", "\t$Rd, $Rm",
2947 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
2950 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2951 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2954 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2955 "rev16", ".w\t$Rd, $Rm",
2956 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2959 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2960 "revsh", ".w\t$Rd, $Rm",
2961 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2964 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2965 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2966 (t2REVSH rGPR:$Rm)>;
2968 def t2PKHBT : T2ThreeReg<
2969 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2970 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2971 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2972 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2974 Requires<[HasDSP, IsThumb2]>,
2975 Sched<[WriteALUsi, ReadALU]> {
2976 let Inst{31-27} = 0b11101;
2977 let Inst{26-25} = 0b01;
2978 let Inst{24-20} = 0b01100;
2979 let Inst{5} = 0; // BT form
2983 let Inst{14-12} = sh{4-2};
2984 let Inst{7-6} = sh{1-0};
2987 // Alternate cases for PKHBT where identities eliminate some nodes.
2988 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2989 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2990 Requires<[HasDSP, IsThumb2]>;
2991 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2992 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2993 Requires<[HasDSP, IsThumb2]>;
2995 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2996 // will match the pattern below.
2997 def t2PKHTB : T2ThreeReg<
2998 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2999 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3000 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3001 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
3003 Requires<[HasDSP, IsThumb2]>,
3004 Sched<[WriteALUsi, ReadALU]> {
3005 let Inst{31-27} = 0b11101;
3006 let Inst{26-25} = 0b01;
3007 let Inst{24-20} = 0b01100;
3008 let Inst{5} = 1; // TB form
3012 let Inst{14-12} = sh{4-2};
3013 let Inst{7-6} = sh{1-0};
3016 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3017 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3018 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
3019 // pkhtb src1, src2, asr (17..31).
3020 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)),
3021 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>,
3022 Requires<[HasDSP, IsThumb2]>;
3023 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)),
3024 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
3025 Requires<[HasDSP, IsThumb2]>;
3026 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
3027 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
3028 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
3029 Requires<[HasDSP, IsThumb2]>;
3031 //===----------------------------------------------------------------------===//
3032 // CRC32 Instructions
3035 // + CRC32{B,H,W} 0x04C11DB7
3036 // + CRC32C{B,H,W} 0x1EDC6F41
3039 class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
3040 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
3041 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
3042 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
3043 Requires<[IsThumb2, HasV8, HasCRC]> {
3044 let Inst{31-27} = 0b11111;
3045 let Inst{26-21} = 0b010110;
3047 let Inst{15-12} = 0b1111;
3048 let Inst{7-6} = 0b10;
3052 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3053 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3054 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3055 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3056 def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>;
3057 def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>;
3059 //===----------------------------------------------------------------------===//
3060 // Comparison Instructions...
3062 defm t2CMP : T2I_cmp_irs<0b1101, "cmp", GPRnopc,
3063 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>;
3065 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
3066 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
3067 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
3068 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
3069 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
3070 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
3072 let isCompare = 1, Defs = [CPSR] in {
3074 def t2CMNri : T2OneRegCmpImm<
3075 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
3076 "cmn", ".w\t$Rn, $imm",
3077 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
3078 Sched<[WriteCMP, ReadALU]> {
3079 let Inst{31-27} = 0b11110;
3081 let Inst{24-21} = 0b1000;
3082 let Inst{20} = 1; // The S bit.
3084 let Inst{11-8} = 0b1111; // Rd
3087 def t2CMNzrr : T2TwoRegCmp<
3088 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
3089 "cmn", ".w\t$Rn, $Rm",
3090 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3091 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3092 let Inst{31-27} = 0b11101;
3093 let Inst{26-25} = 0b01;
3094 let Inst{24-21} = 0b1000;
3095 let Inst{20} = 1; // The S bit.
3096 let Inst{14-12} = 0b000; // imm3
3097 let Inst{11-8} = 0b1111; // Rd
3098 let Inst{7-6} = 0b00; // imm2
3099 let Inst{5-4} = 0b00; // type
3102 def t2CMNzrs : T2OneRegCmpShiftedReg<
3103 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
3104 "cmn", ".w\t$Rn, $ShiftedRm",
3105 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3106 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
3107 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3108 let Inst{31-27} = 0b11101;
3109 let Inst{26-25} = 0b01;
3110 let Inst{24-21} = 0b1000;
3111 let Inst{20} = 1; // The S bit.
3112 let Inst{11-8} = 0b1111; // Rd
3116 // Assembler aliases w/o the ".w" suffix.
3117 // No alias here for 'rr' version as not all instantiations of this multiclass
3118 // want one (CMP in particular, does not).
3119 def : t2InstAlias<"cmn${p} $Rn, $imm",
3120 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
3121 def : t2InstAlias<"cmn${p} $Rn, $shift",
3122 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
3124 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
3125 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
3127 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
3128 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
3130 defm t2TST : T2I_cmp_irs<0b0000, "tst", rGPR,
3131 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3132 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
3133 defm t2TEQ : T2I_cmp_irs<0b0100, "teq", rGPR,
3134 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
3135 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
3137 // Conditional moves
3138 let hasSideEffects = 0 in {
3140 let isCommutable = 1, isSelect = 1 in
3141 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3142 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p),
3144 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3146 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3148 let isMoveImm = 1 in
3150 : t2PseudoInst<(outs rGPR:$Rd),
3151 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3153 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3155 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3157 let isCodeGenOnly = 1 in {
3158 let isMoveImm = 1 in
3160 : t2PseudoInst<(outs rGPR:$Rd),
3161 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
3163 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3165 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3167 let isMoveImm = 1 in
3169 : t2PseudoInst<(outs rGPR:$Rd),
3170 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p),
3173 (ARMcmov rGPR:$false, t2_so_imm_not:$imm,
3175 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3177 class MOVCCShPseudo<SDPatternOperator opnode, Operand ty>
3178 : t2PseudoInst<(outs rGPR:$Rd),
3179 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p),
3181 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3182 (opnode rGPR:$Rm, (i32 ty:$imm)),
3184 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3186 def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>;
3187 def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>;
3188 def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>;
3189 def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>;
3191 let isMoveImm = 1 in
3193 : t2PseudoInst<(outs rGPR:$dst),
3194 (ins rGPR:$false, i32imm:$src, cmovpred:$p),
3196 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src,
3198 RegConstraint<"$false = $dst">;
3199 } // isCodeGenOnly = 1
3203 //===----------------------------------------------------------------------===//
3204 // Atomic operations intrinsics
3207 // memory barriers protect the atomic sequences
3208 let hasSideEffects = 1 in {
3209 def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3210 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
3211 Requires<[IsThumb, HasDB]> {
3213 let Inst{31-4} = 0xf3bf8f5;
3214 let Inst{3-0} = opt;
3217 def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary,
3218 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
3219 Requires<[IsThumb, HasDB]> {
3221 let Inst{31-4} = 0xf3bf8f4;
3222 let Inst{3-0} = opt;
3225 def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary,
3226 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>,
3227 Requires<[IsThumb, HasDB]> {
3229 let Inst{31-4} = 0xf3bf8f6;
3230 let Inst{3-0} = opt;
3233 let hasNoSchedulingInfo = 1 in
3234 def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary,
3235 "tsb", "\t$opt", []>, Requires<[IsThumb, HasV8_4a]> {
3236 let Inst{31-0} = 0xf3af8012;
3240 // Armv8.5-A speculation barrier
3241 def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
3242 Requires<[IsThumb2, HasSB]>, Sched<[]> {
3243 let Inst{31-0} = 0xf3bf8f70;
3244 let Unpredictable = 0x000f2f0f;
3245 let hasSideEffects = 1;
3248 class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3249 InstrItinClass itin, string opc, string asm, string cstr,
3250 list<dag> pattern, bits<4> rt2 = 0b1111>
3251 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3252 let Inst{31-27} = 0b11101;
3253 let Inst{26-20} = 0b0001101;
3254 let Inst{11-8} = rt2;
3255 let Inst{7-4} = opcod;
3256 let Inst{3-0} = 0b1111;
3260 let Inst{19-16} = addr;
3261 let Inst{15-12} = Rt;
3263 class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz,
3264 InstrItinClass itin, string opc, string asm, string cstr,
3265 list<dag> pattern, bits<4> rt2 = 0b1111>
3266 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3267 let Inst{31-27} = 0b11101;
3268 let Inst{26-20} = 0b0001100;
3269 let Inst{11-8} = rt2;
3270 let Inst{7-4} = opcod;
3276 let Inst{19-16} = addr;
3277 let Inst{15-12} = Rt;
3280 let mayLoad = 1 in {
3281 def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3282 AddrModeNone, 4, NoItinerary,
3283 "ldrexb", "\t$Rt, $addr", "",
3284 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>,
3285 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;
3286 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3287 AddrModeNone, 4, NoItinerary,
3288 "ldrexh", "\t$Rt, $addr", "",
3289 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,
3290 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;
3291 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3292 AddrModeT2_ldrex, 4, NoItinerary,
3293 "ldrex", "\t$Rt, $addr", "",
3294 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,
3295 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]> {
3298 let Inst{31-27} = 0b11101;
3299 let Inst{26-20} = 0b0000101;
3300 let Inst{19-16} = addr{11-8};
3301 let Inst{15-12} = Rt;
3302 let Inst{11-8} = 0b1111;
3303 let Inst{7-0} = addr{7-0};
3305 let hasExtraDefRegAllocReq = 1 in
3306 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3307 (ins addr_offset_none:$addr),
3308 AddrModeNone, 4, NoItinerary,
3309 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3311 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteLd]> {
3313 let Inst{11-8} = Rt2;
3315 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3316 AddrModeNone, 4, NoItinerary,
3317 "ldaexb", "\t$Rt, $addr", "",
3318 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
3319 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;
3320 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3321 AddrModeNone, 4, NoItinerary,
3322 "ldaexh", "\t$Rt, $addr", "",
3323 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
3324 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;
3325 def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
3326 AddrModeNone, 4, NoItinerary,
3327 "ldaex", "\t$Rt, $addr", "",
3328 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
3329 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]> {
3332 let Inst{31-27} = 0b11101;
3333 let Inst{26-20} = 0b0001101;
3334 let Inst{19-16} = addr;
3335 let Inst{15-12} = Rt;
3336 let Inst{11-8} = 0b1111;
3337 let Inst{7-0} = 0b11101111;
3339 let hasExtraDefRegAllocReq = 1 in
3340 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3341 (ins addr_offset_none:$addr),
3342 AddrModeNone, 4, NoItinerary,
3343 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3344 [], {?, ?, ?, ?}>, Requires<[IsThumb,
3345 HasAcquireRelease, HasV7Clrex, IsNotMClass]>, Sched<[WriteLd]> {
3347 let Inst{11-8} = Rt2;
3353 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3354 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3355 (ins rGPR:$Rt, addr_offset_none:$addr),
3356 AddrModeNone, 4, NoItinerary,
3357 "strexb", "\t$Rd, $Rt, $addr", "",
3359 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3360 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;
3361 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3362 (ins rGPR:$Rt, addr_offset_none:$addr),
3363 AddrModeNone, 4, NoItinerary,
3364 "strexh", "\t$Rd, $Rt, $addr", "",
3366 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3367 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;
3369 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3370 t2addrmode_imm0_1020s4:$addr),
3371 AddrModeT2_ldrex, 4, NoItinerary,
3372 "strex", "\t$Rd, $Rt, $addr", "",
3374 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,
3375 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]> {
3379 let Inst{31-27} = 0b11101;
3380 let Inst{26-20} = 0b0000100;
3381 let Inst{19-16} = addr{11-8};
3382 let Inst{15-12} = Rt;
3383 let Inst{11-8} = Rd;
3384 let Inst{7-0} = addr{7-0};
3386 let hasExtraSrcRegAllocReq = 1 in
3387 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3388 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3389 AddrModeNone, 4, NoItinerary,
3390 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3392 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteST]> {
3394 let Inst{11-8} = Rt2;
3396 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3397 (ins rGPR:$Rt, addr_offset_none:$addr),
3398 AddrModeNone, 4, NoItinerary,
3399 "stlexb", "\t$Rd, $Rt, $addr", "",
3401 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
3402 Requires<[IsThumb, HasAcquireRelease,
3403 HasV7Clrex]>, Sched<[WriteST]>;
3405 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3406 (ins rGPR:$Rt, addr_offset_none:$addr),
3407 AddrModeNone, 4, NoItinerary,
3408 "stlexh", "\t$Rd, $Rt, $addr", "",
3410 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
3411 Requires<[IsThumb, HasAcquireRelease,
3412 HasV7Clrex]>, Sched<[WriteST]>;
3414 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3415 addr_offset_none:$addr),
3416 AddrModeNone, 4, NoItinerary,
3417 "stlex", "\t$Rd, $Rt, $addr", "",
3419 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
3420 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>,
3425 let Inst{31-27} = 0b11101;
3426 let Inst{26-20} = 0b0001100;
3427 let Inst{19-16} = addr;
3428 let Inst{15-12} = Rt;
3429 let Inst{11-4} = 0b11111110;
3432 let hasExtraSrcRegAllocReq = 1 in
3433 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3434 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3435 AddrModeNone, 4, NoItinerary,
3436 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3437 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,
3438 HasV7Clrex, IsNotMClass]>, Sched<[WriteST]> {
3440 let Inst{11-8} = Rt2;
3444 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
3445 Requires<[IsThumb, HasV7Clrex]> {
3446 let Inst{31-16} = 0xf3bf;
3447 let Inst{15-14} = 0b10;
3450 let Inst{11-8} = 0b1111;
3451 let Inst{7-4} = 0b0010;
3452 let Inst{3-0} = 0b1111;
3455 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
3456 (t2LDREXB addr_offset_none:$addr)>,
3457 Requires<[IsThumb, HasV8MBaseline]>;
3458 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
3459 (t2LDREXH addr_offset_none:$addr)>,
3460 Requires<[IsThumb, HasV8MBaseline]>;
3461 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3462 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>,
3463 Requires<[IsThumb, HasV8MBaseline]>;
3464 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3465 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>,
3466 Requires<[IsThumb, HasV8MBaseline]>;
3468 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
3469 (t2LDAEXB addr_offset_none:$addr)>,
3470 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3471 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
3472 (t2LDAEXH addr_offset_none:$addr)>,
3473 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3474 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
3475 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>,
3476 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3477 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
3478 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>,
3479 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>;
3481 //===----------------------------------------------------------------------===//
3482 // SJLJ Exception handling intrinsics
3483 // eh_sjlj_setjmp() is an instruction sequence to store the return
3484 // address and save #0 in R0 for the non-longjmp case.
3485 // Since by its nature we may be coming from some other function to get
3486 // here, and we're using the stack frame for the containing function to
3487 // save/restore registers, we can't keep anything live in regs across
3488 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3489 // when we get here from a longjmp(). We force everything out of registers
3490 // except for our own input by listing the relevant registers in Defs. By
3491 // doing so, we also cause the prologue/epilogue code to actively preserve
3492 // all of the callee-saved resgisters, which is exactly what we want.
3493 // $val is a scratch register for our use.
3495 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3496 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3497 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3498 usesCustomInserter = 1 in {
3499 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3500 AddrModeNone, 0, NoItinerary, "", "",
3501 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3502 Requires<[IsThumb2, HasVFP2]>;
3506 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3507 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3508 usesCustomInserter = 1 in {
3509 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3510 AddrModeNone, 0, NoItinerary, "", "",
3511 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3512 Requires<[IsThumb2, NoVFP]>;
3516 //===----------------------------------------------------------------------===//
3517 // Control-Flow Instructions
3520 // FIXME: remove when we have a way to marking a MI with these properties.
3521 // FIXME: Should pc be an implicit operand like PICADD, etc?
3522 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3523 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3524 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3525 reglist:$regs, variable_ops),
3526 4, IIC_iLoad_mBr, [],
3527 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3528 RegConstraint<"$Rn = $wb">;
3530 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3531 let isPredicable = 1 in
3532 def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br,
3534 [(br bb:$target)]>, Sched<[WriteBr]>,
3535 Requires<[IsThumb, HasV8MBaseline]> {
3536 let Inst{31-27} = 0b11110;
3537 let Inst{15-14} = 0b10;
3541 let Inst{26} = target{23};
3542 let Inst{13} = target{22};
3543 let Inst{11} = target{21};
3544 let Inst{25-16} = target{20-11};
3545 let Inst{10-0} = target{10-0};
3546 let DecoderMethod = "DecodeT2BInstruction";
3547 let AsmMatchConverter = "cvtThumbBranches";
3550 let Size = 4, isNotDuplicable = 1, isBranch = 1, isTerminator = 1,
3551 isBarrier = 1, isIndirectBranch = 1 in {
3553 // available in both v8-M.Baseline and Thumb2 targets
3554 def t2BR_JT : t2basePseudoInst<(outs),
3555 (ins GPR:$target, GPR:$index, i32imm:$jt),
3557 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>,
3560 // FIXME: Add a case that can be predicated.
3561 def t2TBB_JT : t2PseudoInst<(outs),
3562 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3565 def t2TBH_JT : t2PseudoInst<(outs),
3566 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>,
3569 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3570 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3573 let Inst{31-20} = 0b111010001101;
3574 let Inst{19-16} = Rn;
3575 let Inst{15-5} = 0b11110000000;
3576 let Inst{4} = 0; // B form
3579 let DecoderMethod = "DecodeThumbTableBranch";
3582 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3583 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3586 let Inst{31-20} = 0b111010001101;
3587 let Inst{19-16} = Rn;
3588 let Inst{15-5} = 0b11110000000;
3589 let Inst{4} = 1; // H form
3592 let DecoderMethod = "DecodeThumbTableBranch";
3594 } // isNotDuplicable, isIndirectBranch
3596 } // isBranch, isTerminator, isBarrier
3598 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3599 // a two-value operand where a dag node expects ", "two operands. :(
3600 let isBranch = 1, isTerminator = 1 in
3601 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3603 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3604 let Inst{31-27} = 0b11110;
3605 let Inst{15-14} = 0b10;
3609 let Inst{25-22} = p;
3612 let Inst{26} = target{20};
3613 let Inst{11} = target{19};
3614 let Inst{13} = target{18};
3615 let Inst{21-16} = target{17-12};
3616 let Inst{10-0} = target{11-1};
3618 let DecoderMethod = "DecodeThumb2BCCInstruction";
3619 let AsmMatchConverter = "cvtThumbBranches";
3622 // Tail calls. The MachO version of thumb tail calls uses a t2 branch, so
3624 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3627 def tTAILJMPd: tPseudoExpand<(outs),
3628 (ins thumb_br_target:$dst, pred:$p),
3630 (t2B thumb_br_target:$dst, pred:$p)>,
3631 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>;
3635 let Defs = [ITSTATE] in
3636 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3637 AddrModeNone, 2, IIC_iALUx,
3638 "it$mask\t$cc", "", []>,
3639 ComplexDeprecationPredicate<"IT"> {
3640 // 16-bit instruction.
3641 let Inst{31-16} = 0x0000;
3642 let Inst{15-8} = 0b10111111;
3647 let Inst{3-0} = mask;
3649 let DecoderMethod = "DecodeIT";
3652 // Branch and Exchange Jazelle -- for disassembly only
3654 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
3655 def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
3656 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
3658 let Inst{31-27} = 0b11110;
3660 let Inst{25-20} = 0b111100;
3661 let Inst{19-16} = func;
3662 let Inst{15-0} = 0b1000111100000000;
3665 // Compare and branch on zero / non-zero
3666 let isBranch = 1, isTerminator = 1 in {
3667 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3668 "cbz\t$Rn, $target", []>,
3669 T1Misc<{0,0,?,1,?,?,?}>,
3670 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3674 let Inst{9} = target{5};
3675 let Inst{7-3} = target{4-0};
3679 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br,
3680 "cbnz\t$Rn, $target", []>,
3681 T1Misc<{1,0,?,1,?,?,?}>,
3682 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
3686 let Inst{9} = target{5};
3687 let Inst{7-3} = target{4-0};
3693 // Change Processor State is a system instruction.
3694 // FIXME: Since the asm parser has currently no clean way to handle optional
3695 // operands, create 3 versions of the same instruction. Once there's a clean
3696 // framework to represent optional operands, change this behavior.
3697 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3698 !strconcat("cps", asm_op), []>,
3699 Requires<[IsThumb2, IsNotMClass]> {
3705 let Inst{31-11} = 0b111100111010111110000;
3706 let Inst{10-9} = imod;
3708 let Inst{7-5} = iflags;
3709 let Inst{4-0} = mode;
3710 let DecoderMethod = "DecodeT2CPSInstruction";
3714 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3715 "$imod\t$iflags, $mode">;
3716 let mode = 0, M = 0 in
3717 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3718 "$imod.w\t$iflags">;
3719 let imod = 0, iflags = 0, M = 1 in
3720 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3722 def : t2InstAlias<"cps$imod.w $iflags, $mode",
3723 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>;
3724 def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
3726 // A6.3.4 Branches and miscellaneous control
3727 // Table A6-14 Change Processor State, and hint instructions
3728 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
3729 [(int_arm_hint imm0_239:$imm)]> {
3731 let Inst{31-3} = 0b11110011101011111000000000000;
3732 let Inst{7-0} = imm;
3735 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
3736 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
3737 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
3738 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
3739 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
3740 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
3741 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
3742 let Predicates = [IsThumb2, HasV8];
3744 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
3745 let Predicates = [IsThumb2, HasRAS];
3747 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
3748 let Predicates = [IsThumb2, HasRAS];
3750 def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
3751 def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;
3753 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
3754 [(int_arm_dbg imm0_15:$opt)]> {
3756 let Inst{31-20} = 0b111100111010;
3757 let Inst{19-16} = 0b1111;
3758 let Inst{15-8} = 0b10000000;
3759 let Inst{7-4} = 0b1111;
3760 let Inst{3-0} = opt;
3763 // Secure Monitor Call is a system instruction.
3764 // Option = Inst{19-16}
3765 let isCall = 1, Uses = [SP] in
3766 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3767 []>, Requires<[IsThumb2, HasTrustZone]> {
3768 let Inst{31-27} = 0b11110;
3769 let Inst{26-20} = 0b1111111;
3770 let Inst{15-12} = 0b1000;
3773 let Inst{19-16} = opt;
3776 class T2DCPS<bits<2> opt, string opc>
3777 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
3778 let Inst{31-27} = 0b11110;
3779 let Inst{26-20} = 0b1111000;
3780 let Inst{19-16} = 0b1111;
3781 let Inst{15-12} = 0b1000;
3782 let Inst{11-2} = 0b0000000000;
3783 let Inst{1-0} = opt;
3786 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
3787 def t2DCPS2 : T2DCPS<0b10, "dcps2">;
3788 def t2DCPS3 : T2DCPS<0b11, "dcps3">;
3790 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3791 string opc, string asm, list<dag> pattern>
3792 : T2I<oops, iops, itin, opc, asm, pattern>,
3793 Requires<[IsThumb2,IsNotMClass]> {
3795 let Inst{31-25} = 0b1110100;
3796 let Inst{24-23} = Op;
3799 let Inst{20-16} = 0b01101;
3800 let Inst{15-5} = 0b11000000000;
3801 let Inst{4-0} = mode{4-0};
3804 // Store Return State is a system instruction.
3805 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3806 "srsdb", "\tsp!, $mode", []>;
3807 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3808 "srsdb","\tsp, $mode", []>;
3809 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3810 "srsia","\tsp!, $mode", []>;
3811 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3812 "srsia","\tsp, $mode", []>;
3815 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3816 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3818 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3819 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3821 // Return From Exception is a system instruction.
3822 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3823 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3824 string opc, string asm, list<dag> pattern>
3825 : T2I<oops, iops, itin, opc, asm, pattern>,
3826 Requires<[IsThumb2,IsNotMClass]> {
3827 let Inst{31-20} = op31_20{11-0};
3830 let Inst{19-16} = Rn;
3831 let Inst{15-0} = 0xc000;
3834 def t2RFEDBW : T2RFE<0b111010000011,
3835 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3836 [/* For disassembly only; pattern left blank */]>;
3837 def t2RFEDB : T2RFE<0b111010000001,
3838 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3839 [/* For disassembly only; pattern left blank */]>;
3840 def t2RFEIAW : T2RFE<0b111010011011,
3841 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3842 [/* For disassembly only; pattern left blank */]>;
3843 def t2RFEIA : T2RFE<0b111010011001,
3844 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3845 [/* For disassembly only; pattern left blank */]>;
3847 // B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
3848 // Exception return instruction is "subs pc, lr, #imm".
3849 let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in
3850 def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary,
3851 "subs", "\tpc, lr, $imm",
3852 [(ARMintretflag imm0_255:$imm)]>,
3853 Requires<[IsThumb2,IsNotMClass]> {
3854 let Inst{31-8} = 0b111100111101111010001111;
3857 let Inst{7-0} = imm;
3860 // Hypervisor Call is a system instruction.
3862 def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>,
3863 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
3865 let Inst{31-20} = 0b111101111110;
3866 let Inst{19-16} = imm16{15-12};
3867 let Inst{15-12} = 0b1000;
3868 let Inst{11-0} = imm16{11-0};
3872 // Alias for HVC without the ".w" optional width specifier
3873 def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
3875 // ERET - Return from exception in Hypervisor mode.
3876 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
3877 // includes virtualization extensions.
3878 def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
3879 Requires<[IsThumb2, HasVirtualization]>;
3881 //===----------------------------------------------------------------------===//
3882 // Non-Instruction Patterns
3885 // 32-bit immediate using movw + movt.
3886 // This is a single pseudo instruction to make it re-materializable.
3887 // FIXME: Remove this when we can do generalized remat.
3888 let isReMaterializable = 1, isMoveImm = 1 in
3889 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3890 [(set rGPR:$dst, (i32 imm:$src))]>,
3891 Requires<[IsThumb, UseMovt]>;
3893 // Pseudo instruction that combines movw + movt + add pc (if pic).
3894 // It also makes it possible to rematerialize the instructions.
3895 // FIXME: Remove this when we can do generalized remat and when machine licm
3896 // can properly the instructions.
3897 let isReMaterializable = 1 in {
3898 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3900 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3901 Requires<[IsThumb, HasV8MBaseline, UseMovtInPic]>;
3905 def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst),
3906 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>,
3907 Requires<[IsThumb2, UseMovtInPic]>;
3908 def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst),
3909 (t2MOVi32imm tglobaltlsaddr:$dst)>,
3910 Requires<[IsThumb2, UseMovt]>;
3912 // ConstantPool, GlobalAddress, and JumpTable
3913 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3914 def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>,
3915 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3916 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3917 Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
3919 def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>;
3921 // Pseudo instruction that combines ldr from constpool and add pc. This should
3922 // be expanded into two instructions late to allow if-conversion and
3924 let canFoldAsLoad = 1, isReMaterializable = 1 in
3925 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3927 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3929 Requires<[IsThumb2]>;
3931 // Pseudo isntruction that combines movs + predicated rsbmi
3932 // to implement integer ABS
3933 let usesCustomInserter = 1, Defs = [CPSR] in {
3934 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3935 NoItinerary, []>, Requires<[IsThumb2]>;
3938 //===----------------------------------------------------------------------===//
3939 // Coprocessor load/store -- for disassembly only
3941 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern>
3942 : T2I<oops, iops, NoItinerary, opc, asm, pattern> {
3943 let Inst{31-28} = op31_28;
3944 let Inst{27-25} = 0b110;
3947 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> {
3948 def _OFFSET : T2CI<op31_28,
3949 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3950 asm, "\t$cop, $CRd, $addr", pattern> {
3954 let Inst{24} = 1; // P = 1
3955 let Inst{23} = addr{8};
3956 let Inst{22} = Dbit;
3957 let Inst{21} = 0; // W = 0
3958 let Inst{20} = load;
3959 let Inst{19-16} = addr{12-9};
3960 let Inst{15-12} = CRd;
3961 let Inst{11-8} = cop;
3962 let Inst{7-0} = addr{7-0};
3963 let DecoderMethod = "DecodeCopMemInstruction";
3965 def _PRE : T2CI<op31_28,
3966 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3967 asm, "\t$cop, $CRd, $addr!", []> {
3971 let Inst{24} = 1; // P = 1
3972 let Inst{23} = addr{8};
3973 let Inst{22} = Dbit;
3974 let Inst{21} = 1; // W = 1
3975 let Inst{20} = load;
3976 let Inst{19-16} = addr{12-9};
3977 let Inst{15-12} = CRd;
3978 let Inst{11-8} = cop;
3979 let Inst{7-0} = addr{7-0};
3980 let DecoderMethod = "DecodeCopMemInstruction";
3982 def _POST: T2CI<op31_28,
3983 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3984 postidx_imm8s4:$offset),
3985 asm, "\t$cop, $CRd, $addr, $offset", []> {
3990 let Inst{24} = 0; // P = 0
3991 let Inst{23} = offset{8};
3992 let Inst{22} = Dbit;
3993 let Inst{21} = 1; // W = 1
3994 let Inst{20} = load;
3995 let Inst{19-16} = addr;
3996 let Inst{15-12} = CRd;
3997 let Inst{11-8} = cop;
3998 let Inst{7-0} = offset{7-0};
3999 let DecoderMethod = "DecodeCopMemInstruction";
4001 def _OPTION : T2CI<op31_28, (outs),
4002 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4003 coproc_option_imm:$option),
4004 asm, "\t$cop, $CRd, $addr, $option", []> {
4009 let Inst{24} = 0; // P = 0
4010 let Inst{23} = 1; // U = 1
4011 let Inst{22} = Dbit;
4012 let Inst{21} = 0; // W = 0
4013 let Inst{20} = load;
4014 let Inst{19-16} = addr;
4015 let Inst{15-12} = CRd;
4016 let Inst{11-8} = cop;
4017 let Inst{7-0} = option;
4018 let DecoderMethod = "DecodeCopMemInstruction";
4022 let DecoderNamespace = "Thumb2CoProc" in {
4023 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4024 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4025 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4026 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4028 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4029 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
4030 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4031 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4035 //===----------------------------------------------------------------------===//
4036 // Move between special register and ARM core register -- for disassembly only
4038 // Move to ARM core register from Special Register
4042 // A/R class can only move from CPSR or SPSR.
4043 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
4044 []>, Requires<[IsThumb2,IsNotMClass]> {
4046 let Inst{31-12} = 0b11110011111011111000;
4047 let Inst{11-8} = Rd;
4048 let Inst{7-0} = 0b00000000;
4051 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
4053 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
4054 []>, Requires<[IsThumb2,IsNotMClass]> {
4056 let Inst{31-12} = 0b11110011111111111000;
4057 let Inst{11-8} = Rd;
4058 let Inst{7-0} = 0b00000000;
4061 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
4062 NoItinerary, "mrs", "\t$Rd, $banked", []>,
4063 Requires<[IsThumb, HasVirtualization]> {
4067 let Inst{31-21} = 0b11110011111;
4068 let Inst{20} = banked{5}; // R bit
4069 let Inst{19-16} = banked{3-0};
4070 let Inst{15-12} = 0b1000;
4071 let Inst{11-8} = Rd;
4072 let Inst{7-5} = 0b001;
4073 let Inst{4} = banked{4};
4074 let Inst{3-0} = 0b0000;
4080 // This MRS has a mask field in bits 7-0 and can take more values than
4081 // the A/R class (a full msr_mask).
4082 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
4083 "mrs", "\t$Rd, $SYSm", []>,
4084 Requires<[IsThumb,IsMClass]> {
4087 let Inst{31-12} = 0b11110011111011111000;
4088 let Inst{11-8} = Rd;
4089 let Inst{7-0} = SYSm;
4091 let Unpredictable{20-16} = 0b11111;
4092 let Unpredictable{13} = 0b1;
4096 // Move from ARM core register to Special Register
4100 // No need to have both system and application versions, the encodings are the
4101 // same and the assembly parser has no way to distinguish between them. The mask
4102 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4103 // the mask with the fields to be accessed in the special register.
4104 let Defs = [CPSR] in
4105 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
4106 NoItinerary, "msr", "\t$mask, $Rn", []>,
4107 Requires<[IsThumb2,IsNotMClass]> {
4110 let Inst{31-21} = 0b11110011100;
4111 let Inst{20} = mask{4}; // R Bit
4112 let Inst{19-16} = Rn;
4113 let Inst{15-12} = 0b1000;
4114 let Inst{11-8} = mask{3-0};
4118 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
4119 // separate encoding (distinguished by bit 5.
4120 def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn),
4121 NoItinerary, "msr", "\t$banked, $Rn", []>,
4122 Requires<[IsThumb, HasVirtualization]> {
4126 let Inst{31-21} = 0b11110011100;
4127 let Inst{20} = banked{5}; // R bit
4128 let Inst{19-16} = Rn;
4129 let Inst{15-12} = 0b1000;
4130 let Inst{11-8} = banked{3-0};
4131 let Inst{7-5} = 0b001;
4132 let Inst{4} = banked{4};
4133 let Inst{3-0} = 0b0000;
4139 // Move from ARM core register to Special Register
4140 let Defs = [CPSR] in
4141 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
4142 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
4143 Requires<[IsThumb,IsMClass]> {
4146 let Inst{31-21} = 0b11110011100;
4148 let Inst{19-16} = Rn;
4149 let Inst{15-12} = 0b1000;
4150 let Inst{11-10} = SYSm{11-10};
4151 let Inst{9-8} = 0b00;
4152 let Inst{7-0} = SYSm{7-0};
4154 let Unpredictable{20} = 0b1;
4155 let Unpredictable{13} = 0b1;
4156 let Unpredictable{9-8} = 0b11;
4160 //===----------------------------------------------------------------------===//
4161 // Move between coprocessor and ARM core register
4164 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4166 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4168 let Inst{27-24} = 0b1110;
4169 let Inst{20} = direction;
4179 let Inst{15-12} = Rt;
4180 let Inst{11-8} = cop;
4181 let Inst{23-21} = opc1;
4182 let Inst{7-5} = opc2;
4183 let Inst{3-0} = CRm;
4184 let Inst{19-16} = CRn;
4186 let DecoderNamespace = "Thumb2CoProc";
4189 class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
4190 list<dag> pattern = []>
4191 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4192 let Inst{27-24} = 0b1100;
4193 let Inst{23-21} = 0b010;
4194 let Inst{20} = direction;
4202 let Inst{15-12} = Rt;
4203 let Inst{19-16} = Rt2;
4204 let Inst{11-8} = cop;
4205 let Inst{7-4} = opc1;
4206 let Inst{3-0} = CRm;
4208 let DecoderNamespace = "Thumb2CoProc";
4211 /* from ARM core register to coprocessor */
4212 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
4214 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4215 c_imm:$CRm, imm0_7:$opc2),
4216 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4217 imm:$CRm, imm:$opc2)]>,
4218 ComplexDeprecationPredicate<"MCR">;
4219 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4220 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4221 c_imm:$CRm, 0, pred:$p)>;
4222 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
4223 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4224 c_imm:$CRm, imm0_7:$opc2),
4225 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4226 imm:$CRm, imm:$opc2)]> {
4227 let Predicates = [IsThumb2, PreV8];
4229 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4230 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4231 c_imm:$CRm, 0, pred:$p)>;
4233 /* from coprocessor to ARM core register */
4234 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
4235 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4236 c_imm:$CRm, imm0_7:$opc2), []>;
4237 def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4238 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4239 c_imm:$CRm, 0, pred:$p)>;
4241 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4242 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4243 c_imm:$CRm, imm0_7:$opc2), []> {
4244 let Predicates = [IsThumb2, PreV8];
4246 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
4247 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4248 c_imm:$CRm, 0, pred:$p)>;
4250 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4251 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4253 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4254 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4257 /* from ARM core register to coprocessor */
4258 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs),
4259 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4261 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4263 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs),
4264 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4266 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
4267 GPR:$Rt2, imm:$CRm)]> {
4268 let Predicates = [IsThumb2, PreV8];
4271 /* from coprocessor to ARM core register */
4272 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4273 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>;
4275 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),
4276 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> {
4277 let Predicates = [IsThumb2, PreV8];
4280 //===----------------------------------------------------------------------===//
4281 // Other Coprocessor Instructions.
4284 def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4285 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4286 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4287 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4288 imm:$CRm, imm:$opc2)]> {
4289 let Inst{27-24} = 0b1110;
4298 let Inst{3-0} = CRm;
4300 let Inst{7-5} = opc2;
4301 let Inst{11-8} = cop;
4302 let Inst{15-12} = CRd;
4303 let Inst{19-16} = CRn;
4304 let Inst{23-20} = opc1;
4306 let Predicates = [IsThumb2, PreV8];
4307 let DecoderNamespace = "Thumb2CoProc";
4310 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4311 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4312 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4313 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4314 imm:$CRm, imm:$opc2)]> {
4315 let Inst{27-24} = 0b1110;
4324 let Inst{3-0} = CRm;
4326 let Inst{7-5} = opc2;
4327 let Inst{11-8} = cop;
4328 let Inst{15-12} = CRd;
4329 let Inst{19-16} = CRn;
4330 let Inst{23-20} = opc1;
4332 let Predicates = [IsThumb2, PreV8];
4333 let DecoderNamespace = "Thumb2CoProc";
4338 //===----------------------------------------------------------------------===//
4339 // ARMv8.1 Privilege Access Never extension
4343 def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
4344 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4349 let Inst{2-0} = 0b000;
4351 let Unpredictable{4} = 0b1;
4352 let Unpredictable{2-0} = 0b111;
4355 //===----------------------------------------------------------------------===//
4356 // ARMv8-M Security Extensions instructions
4359 let hasSideEffects = 1 in
4360 def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
4361 Requires<[Has8MSecExt]> {
4362 let Inst = 0xe97fe97f;
4365 class T2TT<bits<2> at, string asm, list<dag> pattern>
4366 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
4371 let Inst{31-20} = 0b111010000100;
4372 let Inst{19-16} = Rn;
4373 let Inst{15-12} = 0b1111;
4374 let Inst{11-8} = Rt;
4376 let Inst{5-0} = 0b000000;
4378 let Unpredictable{5-0} = 0b111111;
4381 def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
4382 def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
4383 def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
4384 def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
4386 //===----------------------------------------------------------------------===//
4387 // Non-Instruction Patterns
4390 // SXT/UXT with no rotate
4391 let AddedComplexity = 16 in {
4392 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
4393 Requires<[IsThumb2]>;
4394 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
4395 Requires<[IsThumb2]>;
4396 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
4397 Requires<[HasDSP, IsThumb2]>;
4398 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
4399 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4400 Requires<[HasDSP, IsThumb2]>;
4401 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
4402 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4403 Requires<[HasDSP, IsThumb2]>;
4406 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
4407 Requires<[IsThumb2]>;
4408 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
4409 Requires<[IsThumb2]>;
4410 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
4411 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
4412 Requires<[HasDSP, IsThumb2]>;
4413 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
4414 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
4415 Requires<[HasDSP, IsThumb2]>;
4417 // Atomic load/store patterns
4418 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
4419 (t2LDRBi12 t2addrmode_imm12:$addr)>;
4420 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
4421 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
4422 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
4423 (t2LDRBs t2addrmode_so_reg:$addr)>;
4424 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
4425 (t2LDRHi12 t2addrmode_imm12:$addr)>;
4426 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
4427 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
4428 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
4429 (t2LDRHs t2addrmode_so_reg:$addr)>;
4430 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
4431 (t2LDRi12 t2addrmode_imm12:$addr)>;
4432 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
4433 (t2LDRi8 t2addrmode_negimm8:$addr)>;
4434 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
4435 (t2LDRs t2addrmode_so_reg:$addr)>;
4436 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
4437 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
4438 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
4439 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4440 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
4441 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
4442 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
4443 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
4444 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
4445 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4446 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
4447 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
4448 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
4449 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
4450 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4451 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4452 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4453 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4455 let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in {
4456 def : Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
4457 def : Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
4458 def : Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
4459 def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
4460 def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
4461 def : Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>;
4465 //===----------------------------------------------------------------------===//
4466 // Assembler aliases
4469 // Aliases for ADC without the ".w" optional width specifier.
4470 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4471 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4472 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4473 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4474 pred:$p, cc_out:$s)>;
4476 // Aliases for SBC without the ".w" optional width specifier.
4477 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4478 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4479 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4480 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4481 pred:$p, cc_out:$s)>;
4483 // Aliases for ADD without the ".w" optional width specifier.
4484 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4485 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4487 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4488 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4489 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4490 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4491 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4492 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4493 pred:$p, cc_out:$s)>;
4494 // ... and with the destination and source register combined.
4495 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4496 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4497 def : t2InstAlias<"add${p} $Rdn, $imm",
4498 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4499 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4500 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4501 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4502 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4503 pred:$p, cc_out:$s)>;
4505 // add w/ negative immediates is just a sub.
4506 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4507 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4509 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
4510 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4511 def : t2InstSubst<"add${s}${p} $Rdn, $imm",
4512 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4514 def : t2InstSubst<"add${p} $Rdn, $imm",
4515 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4517 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4518 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4520 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
4521 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4522 def : t2InstSubst<"add${s}${p}.w $Rdn, $imm",
4523 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4525 def : t2InstSubst<"addw${p} $Rdn, $imm",
4526 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4529 // Aliases for SUB without the ".w" optional width specifier.
4530 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4531 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4532 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4533 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4534 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4535 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4536 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4537 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4538 pred:$p, cc_out:$s)>;
4539 // ... and with the destination and source register combined.
4540 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4541 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4542 def : t2InstAlias<"sub${p} $Rdn, $imm",
4543 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4544 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4545 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4546 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4547 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4548 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4549 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4550 pred:$p, cc_out:$s)>;
4552 // Alias for compares without the ".w" optional width specifier.
4553 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4554 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4555 def : t2InstAlias<"teq${p} $Rn, $Rm",
4556 (t2TEQrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
4557 def : t2InstAlias<"tst${p} $Rn, $Rm",
4558 (t2TSTrr rGPR:$Rn, rGPR:$Rm, pred:$p)>;
4561 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4562 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4563 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4565 // Non-predicable aliases of a predicable DSB: the predicate is (14, 0) where
4566 // 14 = AL (always execute) and 0 = "instruction doesn't read the CPSR".
4567 def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
4568 def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
4570 // Armv8-R 'Data Full Barrier'
4571 def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
4573 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4575 def : t2InstAlias<"ldr${p} $Rt, $addr",
4576 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4577 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4578 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4579 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4580 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4581 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4582 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4583 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4584 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4586 def : t2InstAlias<"ldr${p} $Rt, $addr",
4587 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4588 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4589 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4590 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4591 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4592 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4593 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4594 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4595 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4597 def : t2InstAlias<"ldr${p} $Rt, $addr",
4598 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4599 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4600 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4601 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4602 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4603 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4604 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4605 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4606 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4608 // Alias for MVN with(out) the ".w" optional width specifier.
4609 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4610 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4611 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4612 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4613 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4614 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4616 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
4617 // input operands swapped when the shift amount is zero (i.e., unspecified).
4618 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4619 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4620 Requires<[HasDSP, IsThumb2]>;
4621 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4622 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
4623 Requires<[HasDSP, IsThumb2]>;
4625 // PUSH/POP aliases for STM/LDM
4626 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4627 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4628 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4629 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4631 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4632 def : t2InstAlias<"stm${p} $Rn, $regs",
4633 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4634 def : t2InstAlias<"stm${p} $Rn!, $regs",
4635 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4637 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4638 def : t2InstAlias<"ldm${p} $Rn, $regs",
4639 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4640 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4641 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4643 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4644 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4645 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4646 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4647 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4649 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4650 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4651 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4652 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4653 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4655 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4656 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4657 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4658 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4661 // Alias for RSB without the ".w" optional width specifier, and with optional
4662 // implied destination register.
4663 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4664 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4665 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4666 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4667 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4668 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4669 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4670 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4673 // SSAT/USAT optional shift operand.
4674 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4675 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4676 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4677 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4679 // STM w/o the .w suffix.
4680 def : t2InstAlias<"stm${p} $Rn, $regs",
4681 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4683 // Alias for STR, STRB, and STRH without the ".w" optional
4685 def : t2InstAlias<"str${p} $Rt, $addr",
4686 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4687 def : t2InstAlias<"strb${p} $Rt, $addr",
4688 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4689 def : t2InstAlias<"strh${p} $Rt, $addr",
4690 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4692 def : t2InstAlias<"str${p} $Rt, $addr",
4693 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4694 def : t2InstAlias<"strb${p} $Rt, $addr",
4695 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4696 def : t2InstAlias<"strh${p} $Rt, $addr",
4697 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4699 // Extend instruction optional rotate operand.
4700 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4701 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4702 Requires<[HasDSP, IsThumb2]>;
4703 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4704 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4705 Requires<[HasDSP, IsThumb2]>;
4706 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4707 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4708 Requires<[HasDSP, IsThumb2]>;
4709 def : InstAlias<"sxtb16${p} $Rd, $Rm",
4710 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4711 Requires<[HasDSP, IsThumb2]>;
4713 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4714 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4715 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4716 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4717 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4718 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4719 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4720 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4722 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4723 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4724 Requires<[HasDSP, IsThumb2]>;
4725 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4726 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4727 Requires<[HasDSP, IsThumb2]>;
4728 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4729 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4730 Requires<[HasDSP, IsThumb2]>;
4731 def : InstAlias<"uxtb16${p} $Rd, $Rm",
4732 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
4733 Requires<[HasDSP, IsThumb2]>;
4735 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4736 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4737 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4738 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4739 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4740 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4741 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4742 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4744 // Extend instruction w/o the ".w" optional width specifier.
4745 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4746 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4747 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4748 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4749 Requires<[HasDSP, IsThumb2]>;
4750 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4751 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4753 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4754 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4755 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4756 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
4757 Requires<[HasDSP, IsThumb2]>;
4758 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4759 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4762 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4764 def : t2InstSubst<"mov${p} $Rd, $imm",
4765 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4766 def : t2InstSubst<"mvn${s}${p} $Rd, $imm",
4767 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
4768 // Same for AND <--> BIC
4769 def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm",
4770 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4771 pred:$p, cc_out:$s)>;
4772 def : t2InstSubst<"bic${s}${p} $Rdn, $imm",
4773 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4774 pred:$p, cc_out:$s)>;
4775 def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",
4776 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4777 pred:$p, cc_out:$s)>;
4778 def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm",
4779 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4780 pred:$p, cc_out:$s)>;
4781 def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",
4782 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4783 pred:$p, cc_out:$s)>;
4784 def : t2InstSubst<"and${s}${p} $Rdn, $imm",
4785 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4786 pred:$p, cc_out:$s)>;
4787 def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",
4788 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4789 pred:$p, cc_out:$s)>;
4790 def : t2InstSubst<"and${s}${p}.w $Rdn, $imm",
4791 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4792 pred:$p, cc_out:$s)>;
4794 def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm",
4795 (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4796 pred:$p, cc_out:$s)>;
4797 def : t2InstSubst<"orn${s}${p} $Rdn, $imm",
4798 (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4799 pred:$p, cc_out:$s)>;
4800 def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm",
4801 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4802 pred:$p, cc_out:$s)>;
4803 def : t2InstSubst<"orr${s}${p} $Rdn, $imm",
4804 (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4805 pred:$p, cc_out:$s)>;
4806 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4807 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4808 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4809 pred:$p, cc_out:$s)>;
4810 def : t2InstSubst<"add${s}${p} $Rd, $imm",
4811 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4812 pred:$p, cc_out:$s)>;
4813 // Same for CMP <--> CMN via t2_so_imm_neg
4814 def : t2InstSubst<"cmp${p} $Rd, $imm",
4815 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4816 def : t2InstSubst<"cmn${p} $Rd, $imm",
4817 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4820 // Wide 'mul' encoding can be specified with only two operands.
4821 def : t2InstAlias<"mul${p} $Rn, $Rm",
4822 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4824 // "neg" is and alias for "rsb rd, rn, #0"
4825 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4826 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4828 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4829 // these, unfortunately.
4830 // FIXME: LSL #0 in the shift should allow SP to be used as either the
4831 // source or destination (but not both).
4832 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4833 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4834 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4835 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4837 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4838 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4839 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4840 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4842 // Aliases for the above with the .w qualifier
4843 def : t2InstAlias<"mov${p}.w $Rd, $shift",
4844 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4845 def : t2InstAlias<"movs${p}.w $Rd, $shift",
4846 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4847 def : t2InstAlias<"mov${p}.w $Rd, $shift",
4848 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4849 def : t2InstAlias<"movs${p}.w $Rd, $shift",
4850 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4852 // ADR w/o the .w suffix
4853 def : t2InstAlias<"adr${p} $Rd, $addr",
4854 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4856 // LDR(literal) w/ alternate [pc, #imm] syntax.
4857 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4858 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4859 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4860 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4861 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4862 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4863 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4864 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4865 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4866 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4867 // Version w/ the .w suffix.
4868 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4869 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>;
4870 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4871 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4872 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4873 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4874 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4875 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4876 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4877 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4879 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4880 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
4882 // Pseudo instruction ldr Rt, =immediate
4884 : t2AsmPseudo<"ldr${p} $Rt, $immediate",
4885 (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
4886 // Version w/ the .w suffix.
4887 def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
4888 (t2LDRConstPool GPRnopc:$Rt,
4889 const_pool_asm_imm:$immediate, pred:$p)>;
4891 // PLD/PLDW/PLI with alternate literal form.
4892 def : t2InstAlias<"pld${p} $addr",
4893 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
4894 def : InstAlias<"pli${p} $addr",
4895 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
4896 Requires<[IsThumb2,HasV7]>;