1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12 : Operand<i32>,
105 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
106 let PrintMethod = "printAddrModeImm12Operand";
107 let EncoderMethod = "getAddrModeImm12OpValue";
108 let DecoderMethod = "DecodeT2AddrModeImm12";
109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
112 // t2ldrlabel := imm12
113 def t2ldrlabel : Operand<i32> {
114 let EncoderMethod = "getAddrModeImm12OpValue";
118 // ADR instruction labels.
119 def t2adrlabel : Operand<i32> {
120 let EncoderMethod = "getT2AdrLabelOpValue";
124 // t2addrmode_imm8 := reg +/- imm8
125 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
126 def t2addrmode_imm8 : Operand<i32>,
127 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
128 let PrintMethod = "printT2AddrModeImm8Operand";
129 let EncoderMethod = "getT2AddrModeImm8OpValue";
130 let DecoderMethod = "DecodeT2AddrModeImm8";
131 let ParserMatchClass = MemImm8OffsetAsmOperand;
132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
135 def t2am_imm8_offset : Operand<i32>,
136 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
137 [], [SDNPWantRoot]> {
138 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
139 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
140 let DecoderMethod = "DecodeT2Imm8";
143 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
144 def t2addrmode_imm8s4 : Operand<i32> {
145 let PrintMethod = "printT2AddrModeImm8s4Operand";
146 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
147 let DecoderMethod = "DecodeT2AddrModeImm8s4";
148 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
151 def t2am_imm8s4_offset : Operand<i32> {
152 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
153 let DecoderMethod = "DecodeT2Imm8S4";
156 // t2addrmode_so_reg := reg + (reg << imm2)
157 def t2addrmode_so_reg : Operand<i32>,
158 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
159 let PrintMethod = "printT2AddrModeSoRegOperand";
160 let EncoderMethod = "getT2AddrModeSORegOpValue";
161 let DecoderMethod = "DecodeT2AddrModeSOReg";
162 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
165 // t2addrmode_reg := reg
166 // Used by load/store exclusive instructions. Useful to enable right assembly
167 // parsing and printing. Not used for any codegen matching.
169 def t2addrmode_reg : Operand<i32> {
170 let PrintMethod = "printAddrMode7Operand";
171 let DecoderMethod = "DecodeGPRRegisterClass";
172 let MIOperandInfo = (ops GPR);
175 //===----------------------------------------------------------------------===//
176 // Multiclass helpers...
180 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
181 string opc, string asm, list<dag> pattern>
182 : T2I<oops, iops, itin, opc, asm, pattern> {
187 let Inst{26} = imm{11};
188 let Inst{14-12} = imm{10-8};
189 let Inst{7-0} = imm{7-0};
193 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
194 string opc, string asm, list<dag> pattern>
195 : T2sI<oops, iops, itin, opc, asm, pattern> {
201 let Inst{26} = imm{11};
202 let Inst{14-12} = imm{10-8};
203 let Inst{7-0} = imm{7-0};
206 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
207 string opc, string asm, list<dag> pattern>
208 : T2I<oops, iops, itin, opc, asm, pattern> {
212 let Inst{19-16} = Rn;
213 let Inst{26} = imm{11};
214 let Inst{14-12} = imm{10-8};
215 let Inst{7-0} = imm{7-0};
219 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
220 string opc, string asm, list<dag> pattern>
221 : T2I<oops, iops, itin, opc, asm, pattern> {
226 let Inst{3-0} = ShiftedRm{3-0};
227 let Inst{5-4} = ShiftedRm{6-5};
228 let Inst{14-12} = ShiftedRm{11-9};
229 let Inst{7-6} = ShiftedRm{8-7};
232 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
233 string opc, string asm, list<dag> pattern>
234 : T2sI<oops, iops, itin, opc, asm, pattern> {
239 let Inst{3-0} = ShiftedRm{3-0};
240 let Inst{5-4} = ShiftedRm{6-5};
241 let Inst{14-12} = ShiftedRm{11-9};
242 let Inst{7-6} = ShiftedRm{8-7};
245 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
246 string opc, string asm, list<dag> pattern>
247 : T2I<oops, iops, itin, opc, asm, pattern> {
251 let Inst{19-16} = Rn;
252 let Inst{3-0} = ShiftedRm{3-0};
253 let Inst{5-4} = ShiftedRm{6-5};
254 let Inst{14-12} = ShiftedRm{11-9};
255 let Inst{7-6} = ShiftedRm{8-7};
258 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
259 string opc, string asm, list<dag> pattern>
260 : T2I<oops, iops, itin, opc, asm, pattern> {
268 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
269 string opc, string asm, list<dag> pattern>
270 : T2sI<oops, iops, itin, opc, asm, pattern> {
278 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
279 string opc, string asm, list<dag> pattern>
280 : T2I<oops, iops, itin, opc, asm, pattern> {
284 let Inst{19-16} = Rn;
289 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
290 string opc, string asm, list<dag> pattern>
291 : T2I<oops, iops, itin, opc, asm, pattern> {
297 let Inst{19-16} = Rn;
298 let Inst{26} = imm{11};
299 let Inst{14-12} = imm{10-8};
300 let Inst{7-0} = imm{7-0};
303 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
304 string opc, string asm, list<dag> pattern>
305 : T2sI<oops, iops, itin, opc, asm, pattern> {
311 let Inst{19-16} = Rn;
312 let Inst{26} = imm{11};
313 let Inst{14-12} = imm{10-8};
314 let Inst{7-0} = imm{7-0};
317 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
318 string opc, string asm, list<dag> pattern>
319 : T2I<oops, iops, itin, opc, asm, pattern> {
326 let Inst{14-12} = imm{4-2};
327 let Inst{7-6} = imm{1-0};
330 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
331 string opc, string asm, list<dag> pattern>
332 : T2sI<oops, iops, itin, opc, asm, pattern> {
339 let Inst{14-12} = imm{4-2};
340 let Inst{7-6} = imm{1-0};
343 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
344 string opc, string asm, list<dag> pattern>
345 : T2I<oops, iops, itin, opc, asm, pattern> {
351 let Inst{19-16} = Rn;
355 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
356 string opc, string asm, list<dag> pattern>
357 : T2sI<oops, iops, itin, opc, asm, pattern> {
363 let Inst{19-16} = Rn;
367 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
368 string opc, string asm, list<dag> pattern>
369 : T2I<oops, iops, itin, opc, asm, pattern> {
375 let Inst{19-16} = Rn;
376 let Inst{3-0} = ShiftedRm{3-0};
377 let Inst{5-4} = ShiftedRm{6-5};
378 let Inst{14-12} = ShiftedRm{11-9};
379 let Inst{7-6} = ShiftedRm{8-7};
382 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
383 string opc, string asm, list<dag> pattern>
384 : T2sI<oops, iops, itin, opc, asm, pattern> {
390 let Inst{19-16} = Rn;
391 let Inst{3-0} = ShiftedRm{3-0};
392 let Inst{5-4} = ShiftedRm{6-5};
393 let Inst{14-12} = ShiftedRm{11-9};
394 let Inst{7-6} = ShiftedRm{8-7};
397 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
398 string opc, string asm, list<dag> pattern>
399 : T2I<oops, iops, itin, opc, asm, pattern> {
405 let Inst{19-16} = Rn;
406 let Inst{15-12} = Ra;
411 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
412 dag oops, dag iops, InstrItinClass itin,
413 string opc, string asm, list<dag> pattern>
414 : T2I<oops, iops, itin, opc, asm, pattern> {
420 let Inst{31-23} = 0b111110111;
421 let Inst{22-20} = opc22_20;
422 let Inst{19-16} = Rn;
423 let Inst{15-12} = RdLo;
424 let Inst{11-8} = RdHi;
425 let Inst{7-4} = opc7_4;
430 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
431 /// unary operation that produces a value. These are predicable and can be
432 /// changed to modify CPSR.
433 multiclass T2I_un_irs<bits<4> opcod, string opc,
434 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
435 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
437 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
439 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
440 let isAsCheapAsAMove = Cheap;
441 let isReMaterializable = ReMat;
442 let Inst{31-27} = 0b11110;
444 let Inst{24-21} = opcod;
445 let Inst{19-16} = 0b1111; // Rn
449 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
451 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
452 let Inst{31-27} = 0b11101;
453 let Inst{26-25} = 0b01;
454 let Inst{24-21} = opcod;
455 let Inst{19-16} = 0b1111; // Rn
456 let Inst{14-12} = 0b000; // imm3
457 let Inst{7-6} = 0b00; // imm2
458 let Inst{5-4} = 0b00; // type
461 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
462 opc, ".w\t$Rd, $ShiftedRm",
463 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
464 let Inst{31-27} = 0b11101;
465 let Inst{26-25} = 0b01;
466 let Inst{24-21} = opcod;
467 let Inst{19-16} = 0b1111; // Rn
471 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
472 /// binary operation that produces a value. These are predicable and can be
473 /// changed to modify CPSR.
474 multiclass T2I_bin_irs<bits<4> opcod, string opc,
475 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
476 PatFrag opnode, string baseOpc, bit Commutable = 0,
479 def ri : T2sTwoRegImm<
480 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
481 opc, "\t$Rd, $Rn, $imm",
482 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
483 let Inst{31-27} = 0b11110;
485 let Inst{24-21} = opcod;
489 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
490 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
491 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
492 let isCommutable = Commutable;
493 let Inst{31-27} = 0b11101;
494 let Inst{26-25} = 0b01;
495 let Inst{24-21} = opcod;
496 let Inst{14-12} = 0b000; // imm3
497 let Inst{7-6} = 0b00; // imm2
498 let Inst{5-4} = 0b00; // type
501 def rs : T2sTwoRegShiftedReg<
502 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
503 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
504 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
505 let Inst{31-27} = 0b11101;
506 let Inst{26-25} = 0b01;
507 let Inst{24-21} = opcod;
509 // Assembly aliases for optional destination operand when it's the same
510 // as the source operand.
511 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
512 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
513 t2_so_imm:$imm, pred:$p,
515 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
516 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
519 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
520 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
521 t2_so_reg:$shift, pred:$p,
525 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
526 // the ".w" suffix to indicate that they are wide.
527 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
528 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
529 PatFrag opnode, string baseOpc, bit Commutable = 0> :
530 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
531 // Assembler aliases w/o the ".w" suffix.
532 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
533 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
536 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
537 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
538 t2_so_reg:$shift, pred:$p,
541 // and with the optional destination operand, too.
542 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
543 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
546 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
547 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
548 t2_so_reg:$shift, pred:$p,
552 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
553 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
554 /// it is equivalent to the T2I_bin_irs counterpart.
555 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
557 def ri : T2sTwoRegImm<
558 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
559 opc, ".w\t$Rd, $Rn, $imm",
560 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
561 let Inst{31-27} = 0b11110;
563 let Inst{24-21} = opcod;
567 def rr : T2sThreeReg<
568 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
569 opc, "\t$Rd, $Rn, $Rm",
570 [/* For disassembly only; pattern left blank */]> {
571 let Inst{31-27} = 0b11101;
572 let Inst{26-25} = 0b01;
573 let Inst{24-21} = opcod;
574 let Inst{14-12} = 0b000; // imm3
575 let Inst{7-6} = 0b00; // imm2
576 let Inst{5-4} = 0b00; // type
579 def rs : T2sTwoRegShiftedReg<
580 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
581 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
582 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
583 let Inst{31-27} = 0b11101;
584 let Inst{26-25} = 0b01;
585 let Inst{24-21} = opcod;
589 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
590 /// instruction modifies the CPSR register.
591 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
592 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
593 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
594 PatFrag opnode, bit Commutable = 0> {
596 def ri : T2sTwoRegImm<
597 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
598 opc, ".w\t$Rd, $Rn, $imm",
599 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
600 let Inst{31-27} = 0b11110;
602 let Inst{24-21} = opcod;
606 def rr : T2sThreeReg<
607 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
608 opc, ".w\t$Rd, $Rn, $Rm",
609 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
610 let isCommutable = Commutable;
611 let Inst{31-27} = 0b11101;
612 let Inst{26-25} = 0b01;
613 let Inst{24-21} = opcod;
614 let Inst{14-12} = 0b000; // imm3
615 let Inst{7-6} = 0b00; // imm2
616 let Inst{5-4} = 0b00; // type
619 def rs : T2sTwoRegShiftedReg<
620 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
621 opc, ".w\t$Rd, $Rn, $ShiftedRm",
622 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
623 let Inst{31-27} = 0b11101;
624 let Inst{26-25} = 0b01;
625 let Inst{24-21} = opcod;
630 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
631 /// patterns for a binary operation that produces a value.
632 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
633 bit Commutable = 0> {
635 // The register-immediate version is re-materializable. This is useful
636 // in particular for taking the address of a local.
637 let isReMaterializable = 1 in {
638 def ri : T2sTwoRegImm<
639 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
640 opc, ".w\t$Rd, $Rn, $imm",
641 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
642 let Inst{31-27} = 0b11110;
645 let Inst{23-21} = op23_21;
651 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
652 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
653 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
657 let Inst{31-27} = 0b11110;
658 let Inst{26} = imm{11};
659 let Inst{25-24} = 0b10;
660 let Inst{23-21} = op23_21;
661 let Inst{20} = 0; // The S bit.
662 let Inst{19-16} = Rn;
664 let Inst{14-12} = imm{10-8};
666 let Inst{7-0} = imm{7-0};
669 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
670 opc, ".w\t$Rd, $Rn, $Rm",
671 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
672 let isCommutable = Commutable;
673 let Inst{31-27} = 0b11101;
674 let Inst{26-25} = 0b01;
676 let Inst{23-21} = op23_21;
677 let Inst{14-12} = 0b000; // imm3
678 let Inst{7-6} = 0b00; // imm2
679 let Inst{5-4} = 0b00; // type
682 def rs : T2sTwoRegShiftedReg<
683 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
684 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
685 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
686 let Inst{31-27} = 0b11101;
687 let Inst{26-25} = 0b01;
689 let Inst{23-21} = op23_21;
693 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
694 /// for a binary operation that produces a value and use the carry
695 /// bit. It's not predicable.
696 let Defs = [CPSR], Uses = [CPSR] in {
697 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
698 bit Commutable = 0> {
700 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
701 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
702 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
703 Requires<[IsThumb2]> {
704 let Inst{31-27} = 0b11110;
706 let Inst{24-21} = opcod;
710 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
711 opc, ".w\t$Rd, $Rn, $Rm",
712 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
713 Requires<[IsThumb2]> {
714 let isCommutable = Commutable;
715 let Inst{31-27} = 0b11101;
716 let Inst{26-25} = 0b01;
717 let Inst{24-21} = opcod;
718 let Inst{14-12} = 0b000; // imm3
719 let Inst{7-6} = 0b00; // imm2
720 let Inst{5-4} = 0b00; // type
723 def rs : T2sTwoRegShiftedReg<
724 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
725 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
726 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
727 Requires<[IsThumb2]> {
728 let Inst{31-27} = 0b11101;
729 let Inst{26-25} = 0b01;
730 let Inst{24-21} = opcod;
735 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
736 /// version is not needed since this is only for codegen.
737 let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
738 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
740 def ri : T2sTwoRegImm<
741 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
742 opc, ".w\t$Rd, $Rn, $imm",
743 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
744 let Inst{31-27} = 0b11110;
746 let Inst{24-21} = opcod;
750 def rs : T2sTwoRegShiftedReg<
751 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
752 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
753 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
754 let Inst{31-27} = 0b11101;
755 let Inst{26-25} = 0b01;
756 let Inst{24-21} = opcod;
761 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
762 // rotate operation that produces a value.
763 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
766 def ri : T2sTwoRegShiftImm<
767 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
768 opc, ".w\t$Rd, $Rm, $imm",
769 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
770 let Inst{31-27} = 0b11101;
771 let Inst{26-21} = 0b010010;
772 let Inst{19-16} = 0b1111; // Rn
773 let Inst{5-4} = opcod;
776 def rr : T2sThreeReg<
777 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
778 opc, ".w\t$Rd, $Rn, $Rm",
779 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
780 let Inst{31-27} = 0b11111;
781 let Inst{26-23} = 0b0100;
782 let Inst{22-21} = opcod;
783 let Inst{15-12} = 0b1111;
784 let Inst{7-4} = 0b0000;
787 // Optional destination register
788 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
789 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
792 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
793 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
797 // Assembler aliases w/o the ".w" suffix.
798 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
799 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
802 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
803 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
807 // and with the optional destination operand, too.
808 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
809 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
812 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
813 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
818 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
819 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
820 /// a explicit result, only implicitly set CPSR.
821 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
822 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
823 PatFrag opnode, string baseOpc> {
824 let isCompare = 1, Defs = [CPSR] in {
826 def ri : T2OneRegCmpImm<
827 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
828 opc, ".w\t$Rn, $imm",
829 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
830 let Inst{31-27} = 0b11110;
832 let Inst{24-21} = opcod;
833 let Inst{20} = 1; // The S bit.
835 let Inst{11-8} = 0b1111; // Rd
838 def rr : T2TwoRegCmp<
839 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
841 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
842 let Inst{31-27} = 0b11101;
843 let Inst{26-25} = 0b01;
844 let Inst{24-21} = opcod;
845 let Inst{20} = 1; // The S bit.
846 let Inst{14-12} = 0b000; // imm3
847 let Inst{11-8} = 0b1111; // Rd
848 let Inst{7-6} = 0b00; // imm2
849 let Inst{5-4} = 0b00; // type
852 def rs : T2OneRegCmpShiftedReg<
853 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
854 opc, ".w\t$Rn, $ShiftedRm",
855 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
856 let Inst{31-27} = 0b11101;
857 let Inst{26-25} = 0b01;
858 let Inst{24-21} = opcod;
859 let Inst{20} = 1; // The S bit.
860 let Inst{11-8} = 0b1111; // Rd
864 // Assembler aliases w/o the ".w" suffix.
865 // No alias here for 'rr' version as not all instantiations of this
866 // multiclass want one (CMP in particular, does not).
867 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
868 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
869 t2_so_imm:$imm, pred:$p)>;
870 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
871 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
876 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
877 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
878 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
880 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
881 opc, ".w\t$Rt, $addr",
882 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
883 let Inst{31-27} = 0b11111;
884 let Inst{26-25} = 0b00;
885 let Inst{24} = signed;
887 let Inst{22-21} = opcod;
888 let Inst{20} = 1; // load
891 let Inst{15-12} = Rt;
894 let addr{12} = 1; // add = TRUE
895 let Inst{19-16} = addr{16-13}; // Rn
896 let Inst{23} = addr{12}; // U
897 let Inst{11-0} = addr{11-0}; // imm
899 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
901 [(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
902 let Inst{31-27} = 0b11111;
903 let Inst{26-25} = 0b00;
904 let Inst{24} = signed;
906 let Inst{22-21} = opcod;
907 let Inst{20} = 1; // load
909 // Offset: index==TRUE, wback==FALSE
910 let Inst{10} = 1; // The P bit.
911 let Inst{8} = 0; // The W bit.
914 let Inst{15-12} = Rt;
917 let Inst{19-16} = addr{12-9}; // Rn
918 let Inst{9} = addr{8}; // U
919 let Inst{7-0} = addr{7-0}; // imm
921 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
922 opc, ".w\t$Rt, $addr",
923 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
924 let Inst{31-27} = 0b11111;
925 let Inst{26-25} = 0b00;
926 let Inst{24} = signed;
928 let Inst{22-21} = opcod;
929 let Inst{20} = 1; // load
930 let Inst{11-6} = 0b000000;
933 let Inst{15-12} = Rt;
936 let Inst{19-16} = addr{9-6}; // Rn
937 let Inst{3-0} = addr{5-2}; // Rm
938 let Inst{5-4} = addr{1-0}; // imm
940 let DecoderMethod = "DecodeT2LoadShift";
943 // FIXME: Is the pci variant actually needed?
944 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
945 opc, ".w\t$Rt, $addr",
946 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
947 let isReMaterializable = 1;
948 let Inst{31-27} = 0b11111;
949 let Inst{26-25} = 0b00;
950 let Inst{24} = signed;
951 let Inst{23} = ?; // add = (U == '1')
952 let Inst{22-21} = opcod;
953 let Inst{20} = 1; // load
954 let Inst{19-16} = 0b1111; // Rn
957 let Inst{15-12} = Rt{3-0};
958 let Inst{11-0} = addr{11-0};
962 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
963 multiclass T2I_st<bits<2> opcod, string opc,
964 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
966 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
967 opc, ".w\t$Rt, $addr",
968 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
969 let Inst{31-27} = 0b11111;
970 let Inst{26-23} = 0b0001;
971 let Inst{22-21} = opcod;
972 let Inst{20} = 0; // !load
975 let Inst{15-12} = Rt;
978 let addr{12} = 1; // add = TRUE
979 let Inst{19-16} = addr{16-13}; // Rn
980 let Inst{23} = addr{12}; // U
981 let Inst{11-0} = addr{11-0}; // imm
983 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
985 [(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
986 let Inst{31-27} = 0b11111;
987 let Inst{26-23} = 0b0000;
988 let Inst{22-21} = opcod;
989 let Inst{20} = 0; // !load
991 // Offset: index==TRUE, wback==FALSE
992 let Inst{10} = 1; // The P bit.
993 let Inst{8} = 0; // The W bit.
996 let Inst{15-12} = Rt;
999 let Inst{19-16} = addr{12-9}; // Rn
1000 let Inst{9} = addr{8}; // U
1001 let Inst{7-0} = addr{7-0}; // imm
1003 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1004 opc, ".w\t$Rt, $addr",
1005 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1006 let Inst{31-27} = 0b11111;
1007 let Inst{26-23} = 0b0000;
1008 let Inst{22-21} = opcod;
1009 let Inst{20} = 0; // !load
1010 let Inst{11-6} = 0b000000;
1013 let Inst{15-12} = Rt;
1016 let Inst{19-16} = addr{9-6}; // Rn
1017 let Inst{3-0} = addr{5-2}; // Rm
1018 let Inst{5-4} = addr{1-0}; // imm
1022 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1023 /// register and one whose operand is a register rotated by 8/16/24.
1024 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1025 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1026 opc, ".w\t$Rd, $Rm$rot",
1027 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1028 Requires<[IsThumb2]> {
1029 let Inst{31-27} = 0b11111;
1030 let Inst{26-23} = 0b0100;
1031 let Inst{22-20} = opcod;
1032 let Inst{19-16} = 0b1111; // Rn
1033 let Inst{15-12} = 0b1111;
1037 let Inst{5-4} = rot{1-0}; // rotate
1040 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1041 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1042 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1043 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1044 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1045 Requires<[HasT2ExtractPack, IsThumb2]> {
1047 let Inst{31-27} = 0b11111;
1048 let Inst{26-23} = 0b0100;
1049 let Inst{22-20} = opcod;
1050 let Inst{19-16} = 0b1111; // Rn
1051 let Inst{15-12} = 0b1111;
1053 let Inst{5-4} = rot;
1056 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1058 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1059 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1060 opc, "\t$Rd, $Rm$rot", []>,
1061 Requires<[IsThumb2, HasT2ExtractPack]> {
1063 let Inst{31-27} = 0b11111;
1064 let Inst{26-23} = 0b0100;
1065 let Inst{22-20} = opcod;
1066 let Inst{19-16} = 0b1111; // Rn
1067 let Inst{15-12} = 0b1111;
1069 let Inst{5-4} = rot;
1072 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1073 /// register and one whose operand is a register rotated by 8/16/24.
1074 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1075 : T2ThreeReg<(outs rGPR:$Rd),
1076 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1077 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1078 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1079 Requires<[HasT2ExtractPack, IsThumb2]> {
1081 let Inst{31-27} = 0b11111;
1082 let Inst{26-23} = 0b0100;
1083 let Inst{22-20} = opcod;
1084 let Inst{15-12} = 0b1111;
1086 let Inst{5-4} = rot;
1089 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1090 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1091 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1093 let Inst{31-27} = 0b11111;
1094 let Inst{26-23} = 0b0100;
1095 let Inst{22-20} = opcod;
1096 let Inst{15-12} = 0b1111;
1098 let Inst{5-4} = rot;
1101 //===----------------------------------------------------------------------===//
1103 //===----------------------------------------------------------------------===//
1105 //===----------------------------------------------------------------------===//
1106 // Miscellaneous Instructions.
1109 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1110 string asm, list<dag> pattern>
1111 : T2XI<oops, iops, itin, asm, pattern> {
1115 let Inst{11-8} = Rd;
1116 let Inst{26} = label{11};
1117 let Inst{14-12} = label{10-8};
1118 let Inst{7-0} = label{7-0};
1121 // LEApcrel - Load a pc-relative address into a register without offending the
1123 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1124 (ins t2adrlabel:$addr, pred:$p),
1125 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1126 let Inst{31-27} = 0b11110;
1127 let Inst{25-24} = 0b10;
1128 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1131 let Inst{19-16} = 0b1111; // Rn
1136 let Inst{11-8} = Rd;
1137 let Inst{23} = addr{12};
1138 let Inst{21} = addr{12};
1139 let Inst{26} = addr{11};
1140 let Inst{14-12} = addr{10-8};
1141 let Inst{7-0} = addr{7-0};
1144 let neverHasSideEffects = 1, isReMaterializable = 1 in
1145 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1147 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1148 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1153 //===----------------------------------------------------------------------===//
1154 // Load / store Instructions.
1158 let canFoldAsLoad = 1, isReMaterializable = 1 in
1159 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1160 UnOpFrag<(load node:$Src)>>;
1162 // Loads with zero extension
1163 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1164 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1165 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1166 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1168 // Loads with sign extension
1169 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1170 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1171 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1172 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1174 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1176 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1177 (ins t2addrmode_imm8s4:$addr),
1178 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1179 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1181 // zextload i1 -> zextload i8
1182 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1183 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1184 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1185 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1186 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1187 (t2LDRBs t2addrmode_so_reg:$addr)>;
1188 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1189 (t2LDRBpci tconstpool:$addr)>;
1191 // extload -> zextload
1192 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1194 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1195 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1196 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
1197 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1198 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1199 (t2LDRBs t2addrmode_so_reg:$addr)>;
1200 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1201 (t2LDRBpci tconstpool:$addr)>;
1203 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1204 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1205 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
1206 (t2LDRBi8 t2addrmode_imm8:$addr)>;
1207 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1208 (t2LDRBs t2addrmode_so_reg:$addr)>;
1209 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1210 (t2LDRBpci tconstpool:$addr)>;
1212 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1213 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1214 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1215 (t2LDRHi8 t2addrmode_imm8:$addr)>;
1216 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1217 (t2LDRHs t2addrmode_so_reg:$addr)>;
1218 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1219 (t2LDRHpci tconstpool:$addr)>;
1221 // FIXME: The destination register of the loads and stores can't be PC, but
1222 // can be SP. We need another regclass (similar to rGPR) to represent
1223 // that. Not a pressing issue since these are selected manually,
1228 let mayLoad = 1, neverHasSideEffects = 1 in {
1229 def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1230 (ins t2addrmode_imm8:$addr),
1231 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1232 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1235 def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1236 (ins GPR:$base, t2am_imm8_offset:$addr),
1237 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1238 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1241 def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1242 (ins t2addrmode_imm8:$addr),
1243 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1244 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1246 def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1247 (ins GPR:$base, t2am_imm8_offset:$addr),
1248 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1249 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1252 def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1253 (ins t2addrmode_imm8:$addr),
1254 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1255 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1257 def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1258 (ins GPR:$base, t2am_imm8_offset:$addr),
1259 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1260 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1263 def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1264 (ins t2addrmode_imm8:$addr),
1265 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1266 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1268 def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1269 (ins GPR:$base, t2am_imm8_offset:$addr),
1270 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1271 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1274 def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1275 (ins t2addrmode_imm8:$addr),
1276 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1277 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1279 def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1280 (ins GPR:$base, t2am_imm8_offset:$addr),
1281 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1282 "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1284 } // mayLoad = 1, neverHasSideEffects = 1
1286 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1287 // for disassembly only.
1288 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1289 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1290 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1291 "\t$Rt, $addr", []> {
1292 let Inst{31-27} = 0b11111;
1293 let Inst{26-25} = 0b00;
1294 let Inst{24} = signed;
1296 let Inst{22-21} = type;
1297 let Inst{20} = 1; // load
1299 let Inst{10-8} = 0b110; // PUW.
1303 let Inst{15-12} = Rt;
1304 let Inst{19-16} = addr{12-9};
1305 let Inst{7-0} = addr{7-0};
1308 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1309 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1310 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1311 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1312 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1315 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1316 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1317 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1318 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1319 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1320 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1323 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1324 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1325 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1326 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1329 def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
1330 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1331 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1332 "str", "\t$Rt, [$Rn, $addr]!",
1333 "$Rn = $base_wb,@earlyclobber $base_wb",
1334 [(set GPRnopc:$base_wb,
1335 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1337 def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
1338 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1339 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1340 "str", "\t$Rt, [$Rn], $addr",
1341 "$Rn = $base_wb,@earlyclobber $base_wb",
1342 [(set GPRnopc:$base_wb,
1343 (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1345 def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
1346 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1347 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1348 "strh", "\t$Rt, [$Rn, $addr]!",
1349 "$Rn = $base_wb,@earlyclobber $base_wb",
1350 [(set GPRnopc:$base_wb,
1351 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1353 def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
1354 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1355 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1356 "strh", "\t$Rt, [$Rn], $addr",
1357 "$Rn = $base_wb,@earlyclobber $base_wb",
1358 [(set GPRnopc:$base_wb,
1359 (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1361 def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
1362 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1363 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1364 "strb", "\t$Rt, [$Rn, $addr]!",
1365 "$Rn = $base_wb,@earlyclobber $base_wb",
1366 [(set GPRnopc:$base_wb,
1367 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1369 def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
1370 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1371 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1372 "strb", "\t$Rt, [$Rn], $addr",
1373 "$Rn = $base_wb,@earlyclobber $base_wb",
1374 [(set GPRnopc:$base_wb,
1375 (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1377 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1379 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1380 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1381 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1382 "\t$Rt, $addr", []> {
1383 let Inst{31-27} = 0b11111;
1384 let Inst{26-25} = 0b00;
1385 let Inst{24} = 0; // not signed
1387 let Inst{22-21} = type;
1388 let Inst{20} = 0; // store
1390 let Inst{10-8} = 0b110; // PUW
1394 let Inst{15-12} = Rt;
1395 let Inst{19-16} = addr{12-9};
1396 let Inst{7-0} = addr{7-0};
1399 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1400 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1401 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1403 // ldrd / strd pre / post variants
1404 // For disassembly only.
1406 def t2LDRD_PRE : T2Ii8s4Tied<1, 1, 1,
1407 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1408 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1409 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1411 def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1,
1412 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1413 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1414 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1416 def t2STRD_PRE : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb),
1417 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1418 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1420 def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb),
1421 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1422 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1424 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1425 // data/instruction access. These are for disassembly only.
1426 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1427 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1428 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1430 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1432 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1433 let Inst{31-25} = 0b1111100;
1434 let Inst{24} = instr;
1436 let Inst{21} = write;
1438 let Inst{15-12} = 0b1111;
1441 let addr{12} = 1; // add = TRUE
1442 let Inst{19-16} = addr{16-13}; // Rn
1443 let Inst{23} = addr{12}; // U
1444 let Inst{11-0} = addr{11-0}; // imm12
1447 def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1449 [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1450 let Inst{31-25} = 0b1111100;
1451 let Inst{24} = instr;
1452 let Inst{23} = 0; // U = 0
1454 let Inst{21} = write;
1456 let Inst{15-12} = 0b1111;
1457 let Inst{11-8} = 0b1100;
1460 let Inst{19-16} = addr{12-9}; // Rn
1461 let Inst{7-0} = addr{7-0}; // imm8
1464 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1466 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1467 let Inst{31-25} = 0b1111100;
1468 let Inst{24} = instr;
1469 let Inst{23} = 0; // add = TRUE for T1
1471 let Inst{21} = write;
1473 let Inst{15-12} = 0b1111;
1474 let Inst{11-6} = 0000000;
1477 let Inst{19-16} = addr{9-6}; // Rn
1478 let Inst{3-0} = addr{5-2}; // Rm
1479 let Inst{5-4} = addr{1-0}; // imm2
1481 let DecoderMethod = "DecodeT2LoadShift";
1485 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1486 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1487 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1489 //===----------------------------------------------------------------------===//
1490 // Load / store multiple Instructions.
1493 multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1494 InstrItinClass itin_upd, bit L_bit> {
1496 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1497 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1501 let Inst{31-27} = 0b11101;
1502 let Inst{26-25} = 0b00;
1503 let Inst{24-23} = 0b01; // Increment After
1505 let Inst{21} = 0; // No writeback
1506 let Inst{20} = L_bit;
1507 let Inst{19-16} = Rn;
1508 let Inst{15-0} = regs;
1511 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1512 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1516 let Inst{31-27} = 0b11101;
1517 let Inst{26-25} = 0b00;
1518 let Inst{24-23} = 0b01; // Increment After
1520 let Inst{21} = 1; // Writeback
1521 let Inst{20} = L_bit;
1522 let Inst{19-16} = Rn;
1523 let Inst{15-0} = regs;
1526 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1527 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1531 let Inst{31-27} = 0b11101;
1532 let Inst{26-25} = 0b00;
1533 let Inst{24-23} = 0b10; // Decrement Before
1535 let Inst{21} = 0; // No writeback
1536 let Inst{20} = L_bit;
1537 let Inst{19-16} = Rn;
1538 let Inst{15-0} = regs;
1541 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1542 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1546 let Inst{31-27} = 0b11101;
1547 let Inst{26-25} = 0b00;
1548 let Inst{24-23} = 0b10; // Decrement Before
1550 let Inst{21} = 1; // Writeback
1551 let Inst{20} = L_bit;
1552 let Inst{19-16} = Rn;
1553 let Inst{15-0} = regs;
1557 let neverHasSideEffects = 1 in {
1559 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1560 defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1562 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1563 defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1565 } // neverHasSideEffects
1568 //===----------------------------------------------------------------------===//
1569 // Move Instructions.
1572 let neverHasSideEffects = 1 in
1573 def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1574 "mov", ".w\t$Rd, $Rm", []> {
1575 let Inst{31-27} = 0b11101;
1576 let Inst{26-25} = 0b01;
1577 let Inst{24-21} = 0b0010;
1578 let Inst{19-16} = 0b1111; // Rn
1579 let Inst{14-12} = 0b000;
1580 let Inst{7-4} = 0b0000;
1583 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1584 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1585 AddedComplexity = 1 in
1586 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1587 "mov", ".w\t$Rd, $imm",
1588 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1589 let Inst{31-27} = 0b11110;
1591 let Inst{24-21} = 0b0010;
1592 let Inst{19-16} = 0b1111; // Rn
1596 def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1597 pred:$p, cc_out:$s)>;
1599 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1600 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1601 "movw", "\t$Rd, $imm",
1602 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1603 let Inst{31-27} = 0b11110;
1605 let Inst{24-21} = 0b0010;
1606 let Inst{20} = 0; // The S bit.
1612 let Inst{11-8} = Rd;
1613 let Inst{19-16} = imm{15-12};
1614 let Inst{26} = imm{11};
1615 let Inst{14-12} = imm{10-8};
1616 let Inst{7-0} = imm{7-0};
1619 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1620 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1622 let Constraints = "$src = $Rd" in {
1623 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1624 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1625 "movt", "\t$Rd, $imm",
1627 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1628 let Inst{31-27} = 0b11110;
1630 let Inst{24-21} = 0b0110;
1631 let Inst{20} = 0; // The S bit.
1637 let Inst{11-8} = Rd;
1638 let Inst{19-16} = imm{15-12};
1639 let Inst{26} = imm{11};
1640 let Inst{14-12} = imm{10-8};
1641 let Inst{7-0} = imm{7-0};
1644 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1645 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1648 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1650 //===----------------------------------------------------------------------===//
1651 // Extend Instructions.
1656 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1657 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1658 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1659 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1660 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1662 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1663 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1664 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1665 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1666 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1668 // TODO: SXT(A){B|H}16
1672 let AddedComplexity = 16 in {
1673 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1674 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1675 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1676 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1677 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1678 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1680 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1681 // The transformation should probably be done as a combiner action
1682 // instead so we can include a check for masking back in the upper
1683 // eight bits of the source into the lower eight bits of the result.
1684 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1685 // (t2UXTB16 rGPR:$Src, 3)>,
1686 // Requires<[HasT2ExtractPack, IsThumb2]>;
1687 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1688 (t2UXTB16 rGPR:$Src, 1)>,
1689 Requires<[HasT2ExtractPack, IsThumb2]>;
1691 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1692 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1693 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1694 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1695 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1698 //===----------------------------------------------------------------------===//
1699 // Arithmetic Instructions.
1702 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1703 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1704 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1705 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1707 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1708 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1709 // CPSR and the implicit def of CPSR is not needed.
1710 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1711 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1712 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1713 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1714 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1715 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1717 let hasPostISelHook = 1 in {
1718 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1719 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1720 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1721 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1725 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1726 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1728 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1729 // CPSR and the implicit def of CPSR is not needed.
1730 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1731 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1733 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1734 // The assume-no-carry-in form uses the negation of the input since add/sub
1735 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1736 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1738 // The AddedComplexity preferences the first variant over the others since
1739 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1740 let AddedComplexity = 1 in
1741 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1742 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1743 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1744 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1745 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1746 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1747 let AddedComplexity = 1 in
1748 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1749 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1750 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1751 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1752 // The with-carry-in form matches bitwise not instead of the negation.
1753 // Effectively, the inverse interpretation of the carry flag already accounts
1754 // for part of the negation.
1755 let AddedComplexity = 1 in
1756 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1757 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1758 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1759 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1761 // Select Bytes -- for disassembly only
1763 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1764 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1765 Requires<[IsThumb2, HasThumb2DSP]> {
1766 let Inst{31-27} = 0b11111;
1767 let Inst{26-24} = 0b010;
1769 let Inst{22-20} = 0b010;
1770 let Inst{15-12} = 0b1111;
1772 let Inst{6-4} = 0b000;
1775 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1776 // And Miscellaneous operations -- for disassembly only
1777 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1778 list<dag> pat = [/* For disassembly only; pattern left blank */],
1779 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1780 string asm = "\t$Rd, $Rn, $Rm">
1781 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1782 Requires<[IsThumb2, HasThumb2DSP]> {
1783 let Inst{31-27} = 0b11111;
1784 let Inst{26-23} = 0b0101;
1785 let Inst{22-20} = op22_20;
1786 let Inst{15-12} = 0b1111;
1787 let Inst{7-4} = op7_4;
1793 let Inst{11-8} = Rd;
1794 let Inst{19-16} = Rn;
1798 // Saturating add/subtract -- for disassembly only
1800 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1801 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1802 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1803 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1804 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1805 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1806 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1807 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1808 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1809 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1810 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1811 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1812 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1813 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1814 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1815 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1816 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1817 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1818 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1819 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1820 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1821 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1823 // Signed/Unsigned add/subtract -- for disassembly only
1825 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1826 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1827 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1828 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1829 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1830 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1831 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1832 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1833 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1834 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1835 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1836 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1838 // Signed/Unsigned halving add/subtract -- for disassembly only
1840 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1841 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1842 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1843 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1844 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1845 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1846 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1847 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1848 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1849 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1850 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1851 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1853 // Helper class for disassembly only
1854 // A6.3.16 & A6.3.17
1855 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1856 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1857 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1858 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1859 let Inst{31-27} = 0b11111;
1860 let Inst{26-24} = 0b011;
1861 let Inst{23} = long;
1862 let Inst{22-20} = op22_20;
1863 let Inst{7-4} = op7_4;
1866 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1867 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1868 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1869 let Inst{31-27} = 0b11111;
1870 let Inst{26-24} = 0b011;
1871 let Inst{23} = long;
1872 let Inst{22-20} = op22_20;
1873 let Inst{7-4} = op7_4;
1876 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1878 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1879 (ins rGPR:$Rn, rGPR:$Rm),
1880 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1881 Requires<[IsThumb2, HasThumb2DSP]> {
1882 let Inst{15-12} = 0b1111;
1884 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1885 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1886 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1887 Requires<[IsThumb2, HasThumb2DSP]>;
1889 // Signed/Unsigned saturate -- for disassembly only
1891 class T2SatI<dag oops, dag iops, InstrItinClass itin,
1892 string opc, string asm, list<dag> pattern>
1893 : T2I<oops, iops, itin, opc, asm, pattern> {
1899 let Inst{11-8} = Rd;
1900 let Inst{19-16} = Rn;
1901 let Inst{4-0} = sat_imm;
1902 let Inst{21} = sh{5};
1903 let Inst{14-12} = sh{4-2};
1904 let Inst{7-6} = sh{1-0};
1908 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1909 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1910 [/* For disassembly only; pattern left blank */]> {
1911 let Inst{31-27} = 0b11110;
1912 let Inst{25-22} = 0b1100;
1917 def t2SSAT16: T2SatI<
1918 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1919 "ssat16", "\t$Rd, $sat_imm, $Rn",
1920 [/* For disassembly only; pattern left blank */]>,
1921 Requires<[IsThumb2, HasThumb2DSP]> {
1922 let Inst{31-27} = 0b11110;
1923 let Inst{25-22} = 0b1100;
1926 let Inst{21} = 1; // sh = '1'
1927 let Inst{14-12} = 0b000; // imm3 = '000'
1928 let Inst{7-6} = 0b00; // imm2 = '00'
1932 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1933 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1934 [/* For disassembly only; pattern left blank */]> {
1935 let Inst{31-27} = 0b11110;
1936 let Inst{25-22} = 0b1110;
1941 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1943 "usat16", "\t$Rd, $sat_imm, $Rn",
1944 [/* For disassembly only; pattern left blank */]>,
1945 Requires<[IsThumb2, HasThumb2DSP]> {
1946 let Inst{31-27} = 0b11110;
1947 let Inst{25-22} = 0b1110;
1950 let Inst{21} = 1; // sh = '1'
1951 let Inst{14-12} = 0b000; // imm3 = '000'
1952 let Inst{7-6} = 0b00; // imm2 = '00'
1955 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1956 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1958 //===----------------------------------------------------------------------===//
1959 // Shift and rotate Instructions.
1962 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
1963 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
1964 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
1965 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
1966 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
1967 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
1968 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
1969 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
1971 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1972 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1973 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1975 let Uses = [CPSR] in {
1976 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1977 "rrx", "\t$Rd, $Rm",
1978 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1979 let Inst{31-27} = 0b11101;
1980 let Inst{26-25} = 0b01;
1981 let Inst{24-21} = 0b0010;
1982 let Inst{19-16} = 0b1111; // Rn
1983 let Inst{14-12} = 0b000;
1984 let Inst{7-4} = 0b0011;
1988 let isCodeGenOnly = 1, Defs = [CPSR] in {
1989 def t2MOVsrl_flag : T2TwoRegShiftImm<
1990 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1991 "lsrs", ".w\t$Rd, $Rm, #1",
1992 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
1993 let Inst{31-27} = 0b11101;
1994 let Inst{26-25} = 0b01;
1995 let Inst{24-21} = 0b0010;
1996 let Inst{20} = 1; // The S bit.
1997 let Inst{19-16} = 0b1111; // Rn
1998 let Inst{5-4} = 0b01; // Shift type.
1999 // Shift amount = Inst{14-12:7-6} = 1.
2000 let Inst{14-12} = 0b000;
2001 let Inst{7-6} = 0b01;
2003 def t2MOVsra_flag : T2TwoRegShiftImm<
2004 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2005 "asrs", ".w\t$Rd, $Rm, #1",
2006 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2007 let Inst{31-27} = 0b11101;
2008 let Inst{26-25} = 0b01;
2009 let Inst{24-21} = 0b0010;
2010 let Inst{20} = 1; // The S bit.
2011 let Inst{19-16} = 0b1111; // Rn
2012 let Inst{5-4} = 0b10; // Shift type.
2013 // Shift amount = Inst{14-12:7-6} = 1.
2014 let Inst{14-12} = 0b000;
2015 let Inst{7-6} = 0b01;
2019 //===----------------------------------------------------------------------===//
2020 // Bitwise Instructions.
2023 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2024 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2025 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2026 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2027 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2028 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2029 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2030 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2031 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2033 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2034 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2035 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2038 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2039 string opc, string asm, list<dag> pattern>
2040 : T2I<oops, iops, itin, opc, asm, pattern> {
2045 let Inst{11-8} = Rd;
2046 let Inst{4-0} = msb{4-0};
2047 let Inst{14-12} = lsb{4-2};
2048 let Inst{7-6} = lsb{1-0};
2051 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2052 string opc, string asm, list<dag> pattern>
2053 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2056 let Inst{19-16} = Rn;
2059 let Constraints = "$src = $Rd" in
2060 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2061 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2062 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2063 let Inst{31-27} = 0b11110;
2064 let Inst{26} = 0; // should be 0.
2066 let Inst{24-20} = 0b10110;
2067 let Inst{19-16} = 0b1111; // Rn
2069 let Inst{5} = 0; // should be 0.
2072 let msb{4-0} = imm{9-5};
2073 let lsb{4-0} = imm{4-0};
2076 def t2SBFX: T2TwoRegBitFI<
2077 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2078 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2079 let Inst{31-27} = 0b11110;
2081 let Inst{24-20} = 0b10100;
2085 def t2UBFX: T2TwoRegBitFI<
2086 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2087 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2088 let Inst{31-27} = 0b11110;
2090 let Inst{24-20} = 0b11100;
2094 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2095 let Constraints = "$src = $Rd" in {
2096 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2097 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2098 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2099 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2100 bf_inv_mask_imm:$imm))]> {
2101 let Inst{31-27} = 0b11110;
2102 let Inst{26} = 0; // should be 0.
2104 let Inst{24-20} = 0b10110;
2106 let Inst{5} = 0; // should be 0.
2109 let msb{4-0} = imm{9-5};
2110 let lsb{4-0} = imm{4-0};
2113 // GNU as only supports this form of bfi (w/ 4 arguments)
2114 let isAsmParserOnly = 1 in
2115 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2116 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2118 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2120 let Inst{31-27} = 0b11110;
2121 let Inst{26} = 0; // should be 0.
2123 let Inst{24-20} = 0b10110;
2125 let Inst{5} = 0; // should be 0.
2129 let msb{4-0} = width; // Custom encoder => lsb+width-1
2130 let lsb{4-0} = lsbit;
2134 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2135 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2136 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2139 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2140 let AddedComplexity = 1 in
2141 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2142 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2143 UnOpFrag<(not node:$Src)>, 1, 1>;
2146 let AddedComplexity = 1 in
2147 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2148 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2150 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2151 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2152 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2153 Requires<[IsThumb2]>;
2155 def : T2Pat<(t2_so_imm_not:$src),
2156 (t2MVNi t2_so_imm_not:$src)>;
2158 //===----------------------------------------------------------------------===//
2159 // Multiply Instructions.
2161 let isCommutable = 1 in
2162 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2163 "mul", "\t$Rd, $Rn, $Rm",
2164 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2165 let Inst{31-27} = 0b11111;
2166 let Inst{26-23} = 0b0110;
2167 let Inst{22-20} = 0b000;
2168 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2169 let Inst{7-4} = 0b0000; // Multiply
2172 def t2MLA: T2FourReg<
2173 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2174 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2175 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2176 let Inst{31-27} = 0b11111;
2177 let Inst{26-23} = 0b0110;
2178 let Inst{22-20} = 0b000;
2179 let Inst{7-4} = 0b0000; // Multiply
2182 def t2MLS: T2FourReg<
2183 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2184 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2185 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2186 let Inst{31-27} = 0b11111;
2187 let Inst{26-23} = 0b0110;
2188 let Inst{22-20} = 0b000;
2189 let Inst{7-4} = 0b0001; // Multiply and Subtract
2192 // Extra precision multiplies with low / high results
2193 let neverHasSideEffects = 1 in {
2194 let isCommutable = 1 in {
2195 def t2SMULL : T2MulLong<0b000, 0b0000,
2196 (outs rGPR:$RdLo, rGPR:$RdHi),
2197 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2198 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2200 def t2UMULL : T2MulLong<0b010, 0b0000,
2201 (outs rGPR:$RdLo, rGPR:$RdHi),
2202 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2203 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2206 // Multiply + accumulate
2207 def t2SMLAL : T2MulLong<0b100, 0b0000,
2208 (outs rGPR:$RdLo, rGPR:$RdHi),
2209 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2210 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2212 def t2UMLAL : T2MulLong<0b110, 0b0000,
2213 (outs rGPR:$RdLo, rGPR:$RdHi),
2214 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2215 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2217 def t2UMAAL : T2MulLong<0b110, 0b0110,
2218 (outs rGPR:$RdLo, rGPR:$RdHi),
2219 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2220 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2221 Requires<[IsThumb2, HasThumb2DSP]>;
2222 } // neverHasSideEffects
2224 // Rounding variants of the below included for disassembly only
2226 // Most significant word multiply
2227 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2228 "smmul", "\t$Rd, $Rn, $Rm",
2229 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2230 Requires<[IsThumb2, HasThumb2DSP]> {
2231 let Inst{31-27} = 0b11111;
2232 let Inst{26-23} = 0b0110;
2233 let Inst{22-20} = 0b101;
2234 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2235 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2238 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2239 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2240 Requires<[IsThumb2, HasThumb2DSP]> {
2241 let Inst{31-27} = 0b11111;
2242 let Inst{26-23} = 0b0110;
2243 let Inst{22-20} = 0b101;
2244 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2245 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2248 def t2SMMLA : T2FourReg<
2249 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2250 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2251 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2252 Requires<[IsThumb2, HasThumb2DSP]> {
2253 let Inst{31-27} = 0b11111;
2254 let Inst{26-23} = 0b0110;
2255 let Inst{22-20} = 0b101;
2256 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2259 def t2SMMLAR: T2FourReg<
2260 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2261 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2262 Requires<[IsThumb2, HasThumb2DSP]> {
2263 let Inst{31-27} = 0b11111;
2264 let Inst{26-23} = 0b0110;
2265 let Inst{22-20} = 0b101;
2266 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2269 def t2SMMLS: T2FourReg<
2270 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2271 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2272 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2273 Requires<[IsThumb2, HasThumb2DSP]> {
2274 let Inst{31-27} = 0b11111;
2275 let Inst{26-23} = 0b0110;
2276 let Inst{22-20} = 0b110;
2277 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2280 def t2SMMLSR:T2FourReg<
2281 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2282 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2283 Requires<[IsThumb2, HasThumb2DSP]> {
2284 let Inst{31-27} = 0b11111;
2285 let Inst{26-23} = 0b0110;
2286 let Inst{22-20} = 0b110;
2287 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2290 multiclass T2I_smul<string opc, PatFrag opnode> {
2291 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2292 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2293 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2294 (sext_inreg rGPR:$Rm, i16)))]>,
2295 Requires<[IsThumb2, HasThumb2DSP]> {
2296 let Inst{31-27} = 0b11111;
2297 let Inst{26-23} = 0b0110;
2298 let Inst{22-20} = 0b001;
2299 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2300 let Inst{7-6} = 0b00;
2301 let Inst{5-4} = 0b00;
2304 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2305 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2306 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2307 (sra rGPR:$Rm, (i32 16))))]>,
2308 Requires<[IsThumb2, HasThumb2DSP]> {
2309 let Inst{31-27} = 0b11111;
2310 let Inst{26-23} = 0b0110;
2311 let Inst{22-20} = 0b001;
2312 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2313 let Inst{7-6} = 0b00;
2314 let Inst{5-4} = 0b01;
2317 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2318 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2319 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2320 (sext_inreg rGPR:$Rm, i16)))]>,
2321 Requires<[IsThumb2, HasThumb2DSP]> {
2322 let Inst{31-27} = 0b11111;
2323 let Inst{26-23} = 0b0110;
2324 let Inst{22-20} = 0b001;
2325 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2326 let Inst{7-6} = 0b00;
2327 let Inst{5-4} = 0b10;
2330 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2331 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2332 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2333 (sra rGPR:$Rm, (i32 16))))]>,
2334 Requires<[IsThumb2, HasThumb2DSP]> {
2335 let Inst{31-27} = 0b11111;
2336 let Inst{26-23} = 0b0110;
2337 let Inst{22-20} = 0b001;
2338 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2339 let Inst{7-6} = 0b00;
2340 let Inst{5-4} = 0b11;
2343 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2344 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2345 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2346 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2347 Requires<[IsThumb2, HasThumb2DSP]> {
2348 let Inst{31-27} = 0b11111;
2349 let Inst{26-23} = 0b0110;
2350 let Inst{22-20} = 0b011;
2351 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2352 let Inst{7-6} = 0b00;
2353 let Inst{5-4} = 0b00;
2356 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2357 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2358 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2359 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2360 Requires<[IsThumb2, HasThumb2DSP]> {
2361 let Inst{31-27} = 0b11111;
2362 let Inst{26-23} = 0b0110;
2363 let Inst{22-20} = 0b011;
2364 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2365 let Inst{7-6} = 0b00;
2366 let Inst{5-4} = 0b01;
2371 multiclass T2I_smla<string opc, PatFrag opnode> {
2373 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2374 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2375 [(set rGPR:$Rd, (add rGPR:$Ra,
2376 (opnode (sext_inreg rGPR:$Rn, i16),
2377 (sext_inreg rGPR:$Rm, i16))))]>,
2378 Requires<[IsThumb2, HasThumb2DSP]> {
2379 let Inst{31-27} = 0b11111;
2380 let Inst{26-23} = 0b0110;
2381 let Inst{22-20} = 0b001;
2382 let Inst{7-6} = 0b00;
2383 let Inst{5-4} = 0b00;
2387 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2388 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2389 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2390 (sra rGPR:$Rm, (i32 16)))))]>,
2391 Requires<[IsThumb2, HasThumb2DSP]> {
2392 let Inst{31-27} = 0b11111;
2393 let Inst{26-23} = 0b0110;
2394 let Inst{22-20} = 0b001;
2395 let Inst{7-6} = 0b00;
2396 let Inst{5-4} = 0b01;
2400 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2401 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2402 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2403 (sext_inreg rGPR:$Rm, i16))))]>,
2404 Requires<[IsThumb2, HasThumb2DSP]> {
2405 let Inst{31-27} = 0b11111;
2406 let Inst{26-23} = 0b0110;
2407 let Inst{22-20} = 0b001;
2408 let Inst{7-6} = 0b00;
2409 let Inst{5-4} = 0b10;
2413 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2414 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2415 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2416 (sra rGPR:$Rm, (i32 16)))))]>,
2417 Requires<[IsThumb2, HasThumb2DSP]> {
2418 let Inst{31-27} = 0b11111;
2419 let Inst{26-23} = 0b0110;
2420 let Inst{22-20} = 0b001;
2421 let Inst{7-6} = 0b00;
2422 let Inst{5-4} = 0b11;
2426 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2427 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2428 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2429 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2430 Requires<[IsThumb2, HasThumb2DSP]> {
2431 let Inst{31-27} = 0b11111;
2432 let Inst{26-23} = 0b0110;
2433 let Inst{22-20} = 0b011;
2434 let Inst{7-6} = 0b00;
2435 let Inst{5-4} = 0b00;
2439 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2440 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2441 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2442 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2443 Requires<[IsThumb2, HasThumb2DSP]> {
2444 let Inst{31-27} = 0b11111;
2445 let Inst{26-23} = 0b0110;
2446 let Inst{22-20} = 0b011;
2447 let Inst{7-6} = 0b00;
2448 let Inst{5-4} = 0b01;
2452 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2453 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2455 // Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2456 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2457 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2458 [/* For disassembly only; pattern left blank */]>,
2459 Requires<[IsThumb2, HasThumb2DSP]>;
2460 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2461 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2462 [/* For disassembly only; pattern left blank */]>,
2463 Requires<[IsThumb2, HasThumb2DSP]>;
2464 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2465 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2466 [/* For disassembly only; pattern left blank */]>,
2467 Requires<[IsThumb2, HasThumb2DSP]>;
2468 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2469 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2470 [/* For disassembly only; pattern left blank */]>,
2471 Requires<[IsThumb2, HasThumb2DSP]>;
2473 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2474 // These are for disassembly only.
2476 def t2SMUAD: T2ThreeReg_mac<
2477 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2478 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2479 Requires<[IsThumb2, HasThumb2DSP]> {
2480 let Inst{15-12} = 0b1111;
2482 def t2SMUADX:T2ThreeReg_mac<
2483 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2484 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2485 Requires<[IsThumb2, HasThumb2DSP]> {
2486 let Inst{15-12} = 0b1111;
2488 def t2SMUSD: T2ThreeReg_mac<
2489 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2490 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2491 Requires<[IsThumb2, HasThumb2DSP]> {
2492 let Inst{15-12} = 0b1111;
2494 def t2SMUSDX:T2ThreeReg_mac<
2495 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2496 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2497 Requires<[IsThumb2, HasThumb2DSP]> {
2498 let Inst{15-12} = 0b1111;
2500 def t2SMLAD : T2FourReg_mac<
2501 0, 0b010, 0b0000, (outs rGPR:$Rd),
2502 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2503 "\t$Rd, $Rn, $Rm, $Ra", []>,
2504 Requires<[IsThumb2, HasThumb2DSP]>;
2505 def t2SMLADX : T2FourReg_mac<
2506 0, 0b010, 0b0001, (outs rGPR:$Rd),
2507 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2508 "\t$Rd, $Rn, $Rm, $Ra", []>,
2509 Requires<[IsThumb2, HasThumb2DSP]>;
2510 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2511 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2512 "\t$Rd, $Rn, $Rm, $Ra", []>,
2513 Requires<[IsThumb2, HasThumb2DSP]>;
2514 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2515 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2516 "\t$Rd, $Rn, $Rm, $Ra", []>,
2517 Requires<[IsThumb2, HasThumb2DSP]>;
2518 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2519 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2520 "\t$Ra, $Rd, $Rm, $Rn", []>,
2521 Requires<[IsThumb2, HasThumb2DSP]>;
2522 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2523 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2524 "\t$Ra, $Rd, $Rm, $Rn", []>,
2525 Requires<[IsThumb2, HasThumb2DSP]>;
2526 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2527 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2528 "\t$Ra, $Rd, $Rm, $Rn", []>,
2529 Requires<[IsThumb2, HasThumb2DSP]>;
2530 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2531 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2532 "\t$Ra, $Rd, $Rm, $Rn", []>,
2533 Requires<[IsThumb2, HasThumb2DSP]>;
2535 //===----------------------------------------------------------------------===//
2536 // Division Instructions.
2537 // Signed and unsigned division on v7-M
2539 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2540 "sdiv", "\t$Rd, $Rn, $Rm",
2541 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2542 Requires<[HasDivide, IsThumb2]> {
2543 let Inst{31-27} = 0b11111;
2544 let Inst{26-21} = 0b011100;
2546 let Inst{15-12} = 0b1111;
2547 let Inst{7-4} = 0b1111;
2550 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2551 "udiv", "\t$Rd, $Rn, $Rm",
2552 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2553 Requires<[HasDivide, IsThumb2]> {
2554 let Inst{31-27} = 0b11111;
2555 let Inst{26-21} = 0b011101;
2557 let Inst{15-12} = 0b1111;
2558 let Inst{7-4} = 0b1111;
2561 //===----------------------------------------------------------------------===//
2562 // Misc. Arithmetic Instructions.
2565 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2566 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2567 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2568 let Inst{31-27} = 0b11111;
2569 let Inst{26-22} = 0b01010;
2570 let Inst{21-20} = op1;
2571 let Inst{15-12} = 0b1111;
2572 let Inst{7-6} = 0b10;
2573 let Inst{5-4} = op2;
2577 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2578 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2580 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2581 "rbit", "\t$Rd, $Rm",
2582 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2584 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2585 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2587 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2588 "rev16", ".w\t$Rd, $Rm",
2589 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2591 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2592 "revsh", ".w\t$Rd, $Rm",
2593 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2595 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2596 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2597 (t2REVSH rGPR:$Rm)>;
2599 def t2PKHBT : T2ThreeReg<
2600 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2601 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2602 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2603 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2605 Requires<[HasT2ExtractPack, IsThumb2]> {
2606 let Inst{31-27} = 0b11101;
2607 let Inst{26-25} = 0b01;
2608 let Inst{24-20} = 0b01100;
2609 let Inst{5} = 0; // BT form
2613 let Inst{14-12} = sh{4-2};
2614 let Inst{7-6} = sh{1-0};
2617 // Alternate cases for PKHBT where identities eliminate some nodes.
2618 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2619 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2620 Requires<[HasT2ExtractPack, IsThumb2]>;
2621 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2622 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2623 Requires<[HasT2ExtractPack, IsThumb2]>;
2625 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2626 // will match the pattern below.
2627 def t2PKHTB : T2ThreeReg<
2628 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2629 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2630 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2631 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2633 Requires<[HasT2ExtractPack, IsThumb2]> {
2634 let Inst{31-27} = 0b11101;
2635 let Inst{26-25} = 0b01;
2636 let Inst{24-20} = 0b01100;
2637 let Inst{5} = 1; // TB form
2641 let Inst{14-12} = sh{4-2};
2642 let Inst{7-6} = sh{1-0};
2645 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2646 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2647 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2648 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2649 Requires<[HasT2ExtractPack, IsThumb2]>;
2650 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2651 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2652 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2653 Requires<[HasT2ExtractPack, IsThumb2]>;
2655 //===----------------------------------------------------------------------===//
2656 // Comparison Instructions...
2658 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2659 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2660 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2662 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2663 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2664 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2665 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2666 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2667 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2669 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2670 // Compare-to-zero still works out, just not the relationals
2671 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2672 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2673 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2674 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2675 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2678 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2679 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2681 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2682 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2684 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2685 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2686 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2688 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2689 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2690 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2693 // Conditional moves
2694 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2695 // a two-value operand where a dag node expects two operands. :(
2696 let neverHasSideEffects = 1 in {
2697 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2698 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2700 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2701 RegConstraint<"$false = $Rd">;
2703 let isMoveImm = 1 in
2704 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2705 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2707 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2708 RegConstraint<"$false = $Rd">;
2710 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2711 let isCodeGenOnly = 1 in {
2712 let isMoveImm = 1 in
2713 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2715 "movw", "\t$Rd, $imm", []>,
2716 RegConstraint<"$false = $Rd"> {
2717 let Inst{31-27} = 0b11110;
2719 let Inst{24-21} = 0b0010;
2720 let Inst{20} = 0; // The S bit.
2726 let Inst{11-8} = Rd;
2727 let Inst{19-16} = imm{15-12};
2728 let Inst{26} = imm{11};
2729 let Inst{14-12} = imm{10-8};
2730 let Inst{7-0} = imm{7-0};
2733 let isMoveImm = 1 in
2734 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2735 (ins rGPR:$false, i32imm:$src, pred:$p),
2736 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2738 let isMoveImm = 1 in
2739 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2740 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2741 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2742 imm:$cc, CCR:$ccr))*/]>,
2743 RegConstraint<"$false = $Rd"> {
2744 let Inst{31-27} = 0b11110;
2746 let Inst{24-21} = 0b0011;
2747 let Inst{20} = 0; // The S bit.
2748 let Inst{19-16} = 0b1111; // Rn
2752 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2753 string opc, string asm, list<dag> pattern>
2754 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2755 let Inst{31-27} = 0b11101;
2756 let Inst{26-25} = 0b01;
2757 let Inst{24-21} = 0b0010;
2758 let Inst{20} = 0; // The S bit.
2759 let Inst{19-16} = 0b1111; // Rn
2760 let Inst{5-4} = opcod; // Shift type.
2762 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2763 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2764 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2765 RegConstraint<"$false = $Rd">;
2766 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2767 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2768 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2769 RegConstraint<"$false = $Rd">;
2770 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2771 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2772 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2773 RegConstraint<"$false = $Rd">;
2774 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2775 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2776 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2777 RegConstraint<"$false = $Rd">;
2778 } // isCodeGenOnly = 1
2779 } // neverHasSideEffects
2781 //===----------------------------------------------------------------------===//
2782 // Atomic operations intrinsics
2785 // memory barriers protect the atomic sequences
2786 let hasSideEffects = 1 in {
2787 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2788 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2789 Requires<[IsThumb, HasDB]> {
2791 let Inst{31-4} = 0xf3bf8f5;
2792 let Inst{3-0} = opt;
2796 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2797 "dsb", "\t$opt", []>,
2798 Requires<[IsThumb, HasDB]> {
2800 let Inst{31-4} = 0xf3bf8f4;
2801 let Inst{3-0} = opt;
2804 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2806 []>, Requires<[IsThumb2, HasDB]> {
2808 let Inst{31-4} = 0xf3bf8f6;
2809 let Inst{3-0} = opt;
2812 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2813 InstrItinClass itin, string opc, string asm, string cstr,
2814 list<dag> pattern, bits<4> rt2 = 0b1111>
2815 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2816 let Inst{31-27} = 0b11101;
2817 let Inst{26-20} = 0b0001101;
2818 let Inst{11-8} = rt2;
2819 let Inst{7-6} = 0b01;
2820 let Inst{5-4} = opcod;
2821 let Inst{3-0} = 0b1111;
2825 let Inst{19-16} = addr;
2826 let Inst{15-12} = Rt;
2828 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2829 InstrItinClass itin, string opc, string asm, string cstr,
2830 list<dag> pattern, bits<4> rt2 = 0b1111>
2831 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2832 let Inst{31-27} = 0b11101;
2833 let Inst{26-20} = 0b0001100;
2834 let Inst{11-8} = rt2;
2835 let Inst{7-6} = 0b01;
2836 let Inst{5-4} = opcod;
2842 let Inst{19-16} = addr;
2843 let Inst{15-12} = Rt;
2846 let mayLoad = 1 in {
2847 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2848 AddrModeNone, 4, NoItinerary,
2849 "ldrexb", "\t$Rt, $addr", "", []>;
2850 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2851 AddrModeNone, 4, NoItinerary,
2852 "ldrexh", "\t$Rt, $addr", "", []>;
2853 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2854 AddrModeNone, 4, NoItinerary,
2855 "ldrex", "\t$Rt, $addr", "", []> {
2856 let Inst{31-27} = 0b11101;
2857 let Inst{26-20} = 0b0000101;
2858 let Inst{11-8} = 0b1111;
2859 let Inst{7-0} = 0b00000000; // imm8 = 0
2863 let Inst{19-16} = addr;
2864 let Inst{15-12} = Rt;
2866 let hasExtraDefRegAllocReq = 1 in
2867 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2868 (ins t2addrmode_reg:$addr),
2869 AddrModeNone, 4, NoItinerary,
2870 "ldrexd", "\t$Rt, $Rt2, $addr", "",
2873 let Inst{11-8} = Rt2;
2877 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2878 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2879 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2880 AddrModeNone, 4, NoItinerary,
2881 "strexb", "\t$Rd, $Rt, $addr", "", []>;
2882 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2883 (ins rGPR:$Rt, t2addrmode_reg:$addr),
2884 AddrModeNone, 4, NoItinerary,
2885 "strexh", "\t$Rd, $Rt, $addr", "", []>;
2886 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2887 AddrModeNone, 4, NoItinerary,
2888 "strex", "\t$Rd, $Rt, $addr", "",
2890 let Inst{31-27} = 0b11101;
2891 let Inst{26-20} = 0b0000100;
2892 let Inst{7-0} = 0b00000000; // imm8 = 0
2897 let Inst{11-8} = Rd;
2898 let Inst{19-16} = addr;
2899 let Inst{15-12} = Rt;
2903 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2904 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2905 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2906 AddrModeNone, 4, NoItinerary,
2907 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2910 let Inst{11-8} = Rt2;
2913 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
2914 Requires<[IsThumb2, HasV7]> {
2915 let Inst{31-16} = 0xf3bf;
2916 let Inst{15-14} = 0b10;
2919 let Inst{11-8} = 0b1111;
2920 let Inst{7-4} = 0b0010;
2921 let Inst{3-0} = 0b1111;
2924 //===----------------------------------------------------------------------===//
2925 // SJLJ Exception handling intrinsics
2926 // eh_sjlj_setjmp() is an instruction sequence to store the return
2927 // address and save #0 in R0 for the non-longjmp case.
2928 // Since by its nature we may be coming from some other function to get
2929 // here, and we're using the stack frame for the containing function to
2930 // save/restore registers, we can't keep anything live in regs across
2931 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2932 // when we get here from a longjmp(). We force everything out of registers
2933 // except for our own input by listing the relevant registers in Defs. By
2934 // doing so, we also cause the prologue/epilogue code to actively preserve
2935 // all of the callee-saved resgisters, which is exactly what we want.
2936 // $val is a scratch register for our use.
2938 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
2939 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2940 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2941 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2942 AddrModeNone, 0, NoItinerary, "", "",
2943 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2944 Requires<[IsThumb2, HasVFP2]>;
2948 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
2949 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2950 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2951 AddrModeNone, 0, NoItinerary, "", "",
2952 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2953 Requires<[IsThumb2, NoVFP]>;
2957 //===----------------------------------------------------------------------===//
2958 // Control-Flow Instructions
2961 // FIXME: remove when we have a way to marking a MI with these properties.
2962 // FIXME: Should pc be an implicit operand like PICADD, etc?
2963 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2964 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2965 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2966 reglist:$regs, variable_ops),
2967 4, IIC_iLoad_mBr, [],
2968 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2969 RegConstraint<"$Rn = $wb">;
2971 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2972 let isPredicable = 1 in
2973 def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2975 [(br bb:$target)]> {
2976 let Inst{31-27} = 0b11110;
2977 let Inst{15-14} = 0b10;
2981 let Inst{26} = target{19};
2982 let Inst{11} = target{18};
2983 let Inst{13} = target{17};
2984 let Inst{21-16} = target{16-11};
2985 let Inst{10-0} = target{10-0};
2988 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2989 def t2BR_JT : t2PseudoInst<(outs),
2990 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2992 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2994 // FIXME: Add a non-pc based case that can be predicated.
2995 def t2TBB_JT : t2PseudoInst<(outs),
2996 (ins GPR:$index, i32imm:$jt, i32imm:$id),
2999 def t2TBH_JT : t2PseudoInst<(outs),
3000 (ins GPR:$index, i32imm:$jt, i32imm:$id),
3003 def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3004 "tbb", "\t[$Rn, $Rm]", []> {
3007 let Inst{31-20} = 0b111010001101;
3008 let Inst{19-16} = Rn;
3009 let Inst{15-5} = 0b11110000000;
3010 let Inst{4} = 0; // B form
3014 def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3015 "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3018 let Inst{31-20} = 0b111010001101;
3019 let Inst{19-16} = Rn;
3020 let Inst{15-5} = 0b11110000000;
3021 let Inst{4} = 1; // H form
3024 } // isNotDuplicable, isIndirectBranch
3026 } // isBranch, isTerminator, isBarrier
3028 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3029 // a two-value operand where a dag node expects two operands. :(
3030 let isBranch = 1, isTerminator = 1 in
3031 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3033 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3034 let Inst{31-27} = 0b11110;
3035 let Inst{15-14} = 0b10;
3039 let Inst{25-22} = p;
3042 let Inst{26} = target{20};
3043 let Inst{11} = target{19};
3044 let Inst{13} = target{18};
3045 let Inst{21-16} = target{17-12};
3046 let Inst{10-0} = target{11-1};
3048 let DecoderMethod = "DecodeThumb2BCCInstruction";
3051 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3053 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3055 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3057 def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3059 (t2B uncondbrtarget:$dst)>,
3060 Requires<[IsThumb2, IsDarwin]>;
3064 let Defs = [ITSTATE] in
3065 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3066 AddrModeNone, 2, IIC_iALUx,
3067 "it$mask\t$cc", "", []> {
3068 // 16-bit instruction.
3069 let Inst{31-16} = 0x0000;
3070 let Inst{15-8} = 0b10111111;
3075 let Inst{3-0} = mask;
3077 let DecoderMethod = "DecodeIT";
3080 // Branch and Exchange Jazelle -- for disassembly only
3082 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3084 let Inst{31-27} = 0b11110;
3086 let Inst{25-20} = 0b111100;
3087 let Inst{19-16} = func;
3088 let Inst{15-0} = 0b1000111100000000;
3091 // Compare and branch on zero / non-zero
3092 let isBranch = 1, isTerminator = 1 in {
3093 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3094 "cbz\t$Rn, $target", []>,
3095 T1Misc<{0,0,?,1,?,?,?}>,
3096 Requires<[IsThumb2]> {
3100 let Inst{9} = target{5};
3101 let Inst{7-3} = target{4-0};
3105 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3106 "cbnz\t$Rn, $target", []>,
3107 T1Misc<{1,0,?,1,?,?,?}>,
3108 Requires<[IsThumb2]> {
3112 let Inst{9} = target{5};
3113 let Inst{7-3} = target{4-0};
3119 // Change Processor State is a system instruction -- for disassembly and
3121 // FIXME: Since the asm parser has currently no clean way to handle optional
3122 // operands, create 3 versions of the same instruction. Once there's a clean
3123 // framework to represent optional operands, change this behavior.
3124 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3125 !strconcat("cps", asm_op),
3126 [/* For disassembly only; pattern left blank */]> {
3132 let Inst{31-27} = 0b11110;
3134 let Inst{25-20} = 0b111010;
3135 let Inst{19-16} = 0b1111;
3136 let Inst{15-14} = 0b10;
3138 let Inst{10-9} = imod;
3140 let Inst{7-5} = iflags;
3141 let Inst{4-0} = mode;
3142 let DecoderMethod = "DecodeT2CPSInstruction";
3146 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3147 "$imod.w\t$iflags, $mode">;
3148 let mode = 0, M = 0 in
3149 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3150 "$imod.w\t$iflags">;
3151 let imod = 0, iflags = 0, M = 1 in
3152 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3154 // A6.3.4 Branches and miscellaneous control
3155 // Table A6-14 Change Processor State, and hint instructions
3156 // Helper class for disassembly only.
3157 class T2I_hint<bits<8> op7_0, string opc, string asm>
3158 : T2I<(outs), (ins), NoItinerary, opc, asm,
3159 [/* For disassembly only; pattern left blank */]> {
3160 let Inst{31-20} = 0xf3a;
3161 let Inst{19-16} = 0b1111;
3162 let Inst{15-14} = 0b10;
3164 let Inst{10-8} = 0b000;
3165 let Inst{7-0} = op7_0;
3168 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3169 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3170 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3171 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3172 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3174 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3176 let Inst{31-20} = 0b111100111010;
3177 let Inst{19-16} = 0b1111;
3178 let Inst{15-8} = 0b10000000;
3179 let Inst{7-4} = 0b1111;
3180 let Inst{3-0} = opt;
3183 // Secure Monitor Call is a system instruction -- for disassembly only
3184 // Option = Inst{19-16}
3185 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3186 [/* For disassembly only; pattern left blank */]> {
3187 let Inst{31-27} = 0b11110;
3188 let Inst{26-20} = 0b1111111;
3189 let Inst{15-12} = 0b1000;
3192 let Inst{19-16} = opt;
3195 class T2SRS<bits<12> op31_20,
3196 dag oops, dag iops, InstrItinClass itin,
3197 string opc, string asm, list<dag> pattern>
3198 : T2I<oops, iops, itin, opc, asm, pattern> {
3199 let Inst{31-20} = op31_20{11-0};
3202 let Inst{4-0} = mode{4-0};
3205 // Store Return State is a system instruction -- for disassembly only
3206 def t2SRSDBW : T2SRS<0b111010000010,
3207 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3208 [/* For disassembly only; pattern left blank */]>;
3209 def t2SRSDB : T2SRS<0b111010000000,
3210 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3211 [/* For disassembly only; pattern left blank */]>;
3212 def t2SRSIAW : T2SRS<0b111010011010,
3213 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3214 [/* For disassembly only; pattern left blank */]>;
3215 def t2SRSIA : T2SRS<0b111010011000,
3216 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3217 [/* For disassembly only; pattern left blank */]>;
3219 // Return From Exception is a system instruction -- for disassembly only
3221 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3222 string opc, string asm, list<dag> pattern>
3223 : T2I<oops, iops, itin, opc, asm, pattern> {
3224 let Inst{31-20} = op31_20{11-0};
3227 let Inst{19-16} = Rn;
3228 let Inst{15-0} = 0xc000;
3231 def t2RFEDBW : T2RFE<0b111010000011,
3232 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3233 [/* For disassembly only; pattern left blank */]>;
3234 def t2RFEDB : T2RFE<0b111010000001,
3235 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3236 [/* For disassembly only; pattern left blank */]>;
3237 def t2RFEIAW : T2RFE<0b111010011011,
3238 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3239 [/* For disassembly only; pattern left blank */]>;
3240 def t2RFEIA : T2RFE<0b111010011001,
3241 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3242 [/* For disassembly only; pattern left blank */]>;
3244 //===----------------------------------------------------------------------===//
3245 // Non-Instruction Patterns
3248 // 32-bit immediate using movw + movt.
3249 // This is a single pseudo instruction to make it re-materializable.
3250 // FIXME: Remove this when we can do generalized remat.
3251 let isReMaterializable = 1, isMoveImm = 1 in
3252 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3253 [(set rGPR:$dst, (i32 imm:$src))]>,
3254 Requires<[IsThumb, HasV6T2]>;
3256 // Pseudo instruction that combines movw + movt + add pc (if pic).
3257 // It also makes it possible to rematerialize the instructions.
3258 // FIXME: Remove this when we can do generalized remat and when machine licm
3259 // can properly the instructions.
3260 let isReMaterializable = 1 in {
3261 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3263 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3264 Requires<[IsThumb2, UseMovt]>;
3266 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3268 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3269 Requires<[IsThumb2, UseMovt]>;
3272 // ConstantPool, GlobalAddress, and JumpTable
3273 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3274 Requires<[IsThumb2, DontUseMovt]>;
3275 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3276 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3277 Requires<[IsThumb2, UseMovt]>;
3279 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3280 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3282 // Pseudo instruction that combines ldr from constpool and add pc. This should
3283 // be expanded into two instructions late to allow if-conversion and
3285 let canFoldAsLoad = 1, isReMaterializable = 1 in
3286 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3288 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3290 Requires<[IsThumb2]>;
3292 //===----------------------------------------------------------------------===//
3293 // Move between special register and ARM core register -- for disassembly only
3296 class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3297 dag oops, dag iops, InstrItinClass itin,
3298 string opc, string asm, list<dag> pattern>
3299 : T2I<oops, iops, itin, opc, asm, pattern> {
3300 let Inst{31-20} = op31_20{11-0};
3301 let Inst{15-14} = op15_14{1-0};
3303 let Inst{12} = op12{0};
3307 class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3308 dag oops, dag iops, InstrItinClass itin,
3309 string opc, string asm, list<dag> pattern>
3310 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3312 let Inst{11-8} = Rd;
3313 let Inst{19-16} = 0b1111;
3316 def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3317 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3318 [/* For disassembly only; pattern left blank */]>;
3319 def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3320 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3321 [/* For disassembly only; pattern left blank */]>;
3323 // Move from ARM core register to Special Register
3325 // No need to have both system and application versions, the encodings are the
3326 // same and the assembly parser has no way to distinguish between them. The mask
3327 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3328 // the mask with the fields to be accessed in the special register.
3329 def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3330 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3331 NoItinerary, "msr", "\t$mask, $Rn",
3332 [/* For disassembly only; pattern left blank */]> {
3335 let Inst{19-16} = Rn;
3336 let Inst{20} = mask{4}; // R Bit
3337 let Inst{11-8} = mask{3-0};
3340 //===----------------------------------------------------------------------===//
3341 // Move between coprocessor and ARM core register
3344 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3346 : T2Cop<Op, oops, iops,
3347 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3349 let Inst{27-24} = 0b1110;
3350 let Inst{20} = direction;
3360 let Inst{15-12} = Rt;
3361 let Inst{11-8} = cop;
3362 let Inst{23-21} = opc1;
3363 let Inst{7-5} = opc2;
3364 let Inst{3-0} = CRm;
3365 let Inst{19-16} = CRn;
3368 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3369 list<dag> pattern = []>
3371 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3372 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3373 let Inst{27-24} = 0b1100;
3374 let Inst{23-21} = 0b010;
3375 let Inst{20} = direction;
3383 let Inst{15-12} = Rt;
3384 let Inst{19-16} = Rt2;
3385 let Inst{11-8} = cop;
3386 let Inst{7-4} = opc1;
3387 let Inst{3-0} = CRm;
3390 /* from ARM core register to coprocessor */
3391 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3393 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3394 c_imm:$CRm, imm0_7:$opc2),
3395 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3396 imm:$CRm, imm:$opc2)]>;
3397 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3398 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3399 c_imm:$CRm, imm0_7:$opc2),
3400 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3401 imm:$CRm, imm:$opc2)]>;
3403 /* from coprocessor to ARM core register */
3404 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3405 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3406 c_imm:$CRm, imm0_7:$opc2), []>;
3408 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3409 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3410 c_imm:$CRm, imm0_7:$opc2), []>;
3412 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3413 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3415 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3416 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3419 /* from ARM core register to coprocessor */
3420 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3421 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3423 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3424 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3425 GPR:$Rt2, imm:$CRm)]>;
3426 /* from coprocessor to ARM core register */
3427 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3429 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3431 //===----------------------------------------------------------------------===//
3432 // Other Coprocessor Instructions.
3435 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3436 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3437 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3438 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3439 imm:$CRm, imm:$opc2)]> {
3440 let Inst{27-24} = 0b1110;
3449 let Inst{3-0} = CRm;
3451 let Inst{7-5} = opc2;
3452 let Inst{11-8} = cop;
3453 let Inst{15-12} = CRd;
3454 let Inst{19-16} = CRn;
3455 let Inst{23-20} = opc1;
3458 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3459 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3460 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3461 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3462 imm:$CRm, imm:$opc2)]> {
3463 let Inst{27-24} = 0b1110;
3472 let Inst{3-0} = CRm;
3474 let Inst{7-5} = opc2;
3475 let Inst{11-8} = cop;
3476 let Inst{15-12} = CRd;
3477 let Inst{19-16} = CRn;
3478 let Inst{23-20} = opc1;
3483 //===----------------------------------------------------------------------===//
3484 // Non-Instruction Patterns
3487 // SXT/UXT with no rotate
3488 let AddedComplexity = 16 in {
3489 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3490 Requires<[IsThumb2]>;
3491 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3492 Requires<[IsThumb2]>;
3493 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3494 Requires<[HasT2ExtractPack, IsThumb2]>;
3495 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3496 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3497 Requires<[HasT2ExtractPack, IsThumb2]>;
3498 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3499 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3500 Requires<[HasT2ExtractPack, IsThumb2]>;
3503 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3504 Requires<[IsThumb2]>;
3505 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3506 Requires<[IsThumb2]>;
3507 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3508 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3509 Requires<[HasT2ExtractPack, IsThumb2]>;
3510 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3511 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3512 Requires<[HasT2ExtractPack, IsThumb2]>;
3514 // Atomic load/store patterns
3515 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3516 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3517 def : T2Pat<(atomic_load_8 t2addrmode_imm8:$addr),
3518 (t2LDRBi8 t2addrmode_imm8:$addr)>;
3519 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3520 (t2LDRBs t2addrmode_so_reg:$addr)>;
3521 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3522 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3523 def : T2Pat<(atomic_load_16 t2addrmode_imm8:$addr),
3524 (t2LDRHi8 t2addrmode_imm8:$addr)>;
3525 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3526 (t2LDRHs t2addrmode_so_reg:$addr)>;
3527 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3528 (t2LDRi12 t2addrmode_imm12:$addr)>;
3529 def : T2Pat<(atomic_load_32 t2addrmode_imm8:$addr),
3530 (t2LDRi8 t2addrmode_imm8:$addr)>;
3531 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3532 (t2LDRs t2addrmode_so_reg:$addr)>;
3533 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3534 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3535 def : T2Pat<(atomic_store_8 t2addrmode_imm8:$addr, GPR:$val),
3536 (t2STRBi8 GPR:$val, t2addrmode_imm8:$addr)>;
3537 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3538 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3539 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3540 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3541 def : T2Pat<(atomic_store_16 t2addrmode_imm8:$addr, GPR:$val),
3542 (t2STRHi8 GPR:$val, t2addrmode_imm8:$addr)>;
3543 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3544 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3545 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3546 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3547 def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val),
3548 (t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>;
3549 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3550 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3553 //===----------------------------------------------------------------------===//
3554 // Assembler aliases
3557 // Aliases for ADC without the ".w" optional width specifier.
3558 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3559 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3560 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3561 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3562 pred:$p, cc_out:$s)>;
3564 // Aliases for SBC without the ".w" optional width specifier.
3565 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3566 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3567 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3568 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3569 pred:$p, cc_out:$s)>;
3571 // Aliases for ADD without the ".w" optional width specifier.
3572 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3573 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3574 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3575 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3576 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3577 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3578 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3579 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3580 pred:$p, cc_out:$s)>;
3582 // Alias for compares without the ".w" optional width specifier.
3583 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3584 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3585 def : t2InstAlias<"teq${p} $Rn, $Rm",
3586 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3587 def : t2InstAlias<"tst${p} $Rn, $Rm",
3588 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3591 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3592 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3593 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;