1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements the targeting of the InstructionSelector class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
14 #include "ARMRegisterBankInfo.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetMachine.h"
17 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/Debug.h"
23 #define DEBUG_TYPE "arm-isel"
29 #define GET_GLOBALISEL_PREDICATE_BITSET
30 #include "ARMGenGlobalISel.inc"
31 #undef GET_GLOBALISEL_PREDICATE_BITSET
33 class ARMInstructionSelector : public InstructionSelector {
35 ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
36 const ARMRegisterBankInfo &RBI);
38 bool select(MachineInstr &I) const override;
39 static const char *getName() { return DEBUG_TYPE; }
42 bool selectImpl(MachineInstr &I) const;
47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
48 MachineRegisterInfo &MRI) const;
50 // Helper for inserting a comparison sequence that sets \p ResReg to either 1
51 // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
52 // \p PrevRes otherwise. In essence, it computes PrevRes OR (LHS Cond RHS).
53 bool insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg,
54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
55 unsigned PrevRes) const;
57 // Set \p DestReg to \p Constant.
58 void putConstant(InsertInfo I, unsigned DestReg, unsigned Constant) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
64 // Check if the types match and both operands have the expected size and
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
67 unsigned ExpectedSize, unsigned ExpectedRegBankID) const;
69 // Check if the register has the expected size and register bank.
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
71 unsigned ExpectedRegBankID) const;
73 const ARMBaseInstrInfo &TII;
74 const ARMBaseRegisterInfo &TRI;
75 const ARMBaseTargetMachine &TM;
76 const ARMRegisterBankInfo &RBI;
77 const ARMSubtarget &STI;
79 #define GET_GLOBALISEL_PREDICATES_DECL
80 #include "ARMGenGlobalISel.inc"
81 #undef GET_GLOBALISEL_PREDICATES_DECL
83 // We declare the temporaries used by selectImpl() in the class to minimize the
84 // cost of constructing placeholder values.
85 #define GET_GLOBALISEL_TEMPORARIES_DECL
86 #include "ARMGenGlobalISel.inc"
87 #undef GET_GLOBALISEL_TEMPORARIES_DECL
89 } // end anonymous namespace
93 createARMInstructionSelector(const ARMBaseTargetMachine &TM,
94 const ARMSubtarget &STI,
95 const ARMRegisterBankInfo &RBI) {
96 return new ARMInstructionSelector(TM, STI, RBI);
100 const unsigned zero_reg = 0;
102 #define GET_GLOBALISEL_IMPL
103 #include "ARMGenGlobalISel.inc"
104 #undef GET_GLOBALISEL_IMPL
106 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,
107 const ARMSubtarget &STI,
108 const ARMRegisterBankInfo &RBI)
109 : InstructionSelector(), TII(*STI.getInstrInfo()),
110 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI),
111 #define GET_GLOBALISEL_PREDICATES_INIT
112 #include "ARMGenGlobalISel.inc"
113 #undef GET_GLOBALISEL_PREDICATES_INIT
114 #define GET_GLOBALISEL_TEMPORARIES_INIT
115 #include "ARMGenGlobalISel.inc"
116 #undef GET_GLOBALISEL_TEMPORARIES_INIT
120 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
121 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
122 const RegisterBankInfo &RBI) {
123 unsigned DstReg = I.getOperand(0).getReg();
124 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
127 const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
129 assert(RegBank && "Can't get reg bank for virtual register");
131 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
132 assert((RegBank->getID() == ARM::GPRRegBankID ||
133 RegBank->getID() == ARM::FPRRegBankID) &&
134 "Unsupported reg bank");
136 const TargetRegisterClass *RC = &ARM::GPRRegClass;
138 if (RegBank->getID() == ARM::FPRRegBankID) {
140 RC = &ARM::SPRRegClass;
141 else if (DstSize == 64)
142 RC = &ARM::DPRRegClass;
144 llvm_unreachable("Unsupported destination size");
147 // No need to constrain SrcReg. It will get constrained when
148 // we hit another of its uses or its defs.
149 // Copies do not have constraints.
150 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
151 DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
158 static bool selectMergeValues(MachineInstrBuilder &MIB,
159 const ARMBaseInstrInfo &TII,
160 MachineRegisterInfo &MRI,
161 const TargetRegisterInfo &TRI,
162 const RegisterBankInfo &RBI) {
163 assert(TII.getSubtarget().hasVFP2() && "Can't select merge without VFP");
165 // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
167 unsigned VReg0 = MIB->getOperand(0).getReg();
169 assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
170 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
171 "Unsupported operand for G_MERGE_VALUES");
172 unsigned VReg1 = MIB->getOperand(1).getReg();
174 assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
175 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
176 "Unsupported operand for G_MERGE_VALUES");
177 unsigned VReg2 = MIB->getOperand(2).getReg();
179 assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
180 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
181 "Unsupported operand for G_MERGE_VALUES");
183 MIB->setDesc(TII.get(ARM::VMOVDRR));
184 MIB.add(predOps(ARMCC::AL));
189 static bool selectUnmergeValues(MachineInstrBuilder &MIB,
190 const ARMBaseInstrInfo &TII,
191 MachineRegisterInfo &MRI,
192 const TargetRegisterInfo &TRI,
193 const RegisterBankInfo &RBI) {
194 assert(TII.getSubtarget().hasVFP2() && "Can't select unmerge without VFP");
196 // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
198 unsigned VReg0 = MIB->getOperand(0).getReg();
200 assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
201 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
202 "Unsupported operand for G_UNMERGE_VALUES");
203 unsigned VReg1 = MIB->getOperand(1).getReg();
205 assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
206 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
207 "Unsupported operand for G_UNMERGE_VALUES");
208 unsigned VReg2 = MIB->getOperand(2).getReg();
210 assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
211 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
212 "Unsupported operand for G_UNMERGE_VALUES");
214 MIB->setDesc(TII.get(ARM::VMOVRRD));
215 MIB.add(predOps(ARMCC::AL));
220 /// Select the opcode for simple extensions (that translate to a single SXT/UXT
221 /// instruction). Extension operations more complicated than that should not
222 /// invoke this. Returns the original opcode if it doesn't know how to select a
224 static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
225 using namespace TargetOpcode;
227 if (Size != 8 && Size != 16)
231 return Size == 8 ? ARM::SXTB : ARM::SXTH;
234 return Size == 8 ? ARM::UXTB : ARM::UXTH;
239 /// Select the opcode for simple loads and stores. For types smaller than 32
240 /// bits, the value will be zero extended. Returns the original opcode if it
241 /// doesn't know how to select a better one.
242 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
244 bool isStore = Opc == TargetOpcode::G_STORE;
246 if (RegBank == ARM::GPRRegBankID) {
250 return isStore ? ARM::STRBi12 : ARM::LDRBi12;
252 return isStore ? ARM::STRH : ARM::LDRH;
254 return isStore ? ARM::STRi12 : ARM::LDRi12;
260 if (RegBank == ARM::FPRRegBankID) {
263 return isStore ? ARM::VSTRS : ARM::VLDRS;
265 return isStore ? ARM::VSTRD : ARM::VLDRD;
274 // When lowering comparisons, we sometimes need to perform two compares instead
275 // of just one. Get the condition codes for both comparisons. If only one is
276 // needed, the second member of the pair is ARMCC::AL.
277 static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
278 getComparePreds(CmpInst::Predicate Pred) {
279 std::pair<ARMCC::CondCodes, ARMCC::CondCodes> Preds = {ARMCC::AL, ARMCC::AL};
281 case CmpInst::FCMP_ONE:
282 Preds = {ARMCC::GT, ARMCC::MI};
284 case CmpInst::FCMP_UEQ:
285 Preds = {ARMCC::EQ, ARMCC::VS};
287 case CmpInst::ICMP_EQ:
288 case CmpInst::FCMP_OEQ:
289 Preds.first = ARMCC::EQ;
291 case CmpInst::ICMP_SGT:
292 case CmpInst::FCMP_OGT:
293 Preds.first = ARMCC::GT;
295 case CmpInst::ICMP_SGE:
296 case CmpInst::FCMP_OGE:
297 Preds.first = ARMCC::GE;
299 case CmpInst::ICMP_UGT:
300 case CmpInst::FCMP_UGT:
301 Preds.first = ARMCC::HI;
303 case CmpInst::FCMP_OLT:
304 Preds.first = ARMCC::MI;
306 case CmpInst::ICMP_ULE:
307 case CmpInst::FCMP_OLE:
308 Preds.first = ARMCC::LS;
310 case CmpInst::FCMP_ORD:
311 Preds.first = ARMCC::VC;
313 case CmpInst::FCMP_UNO:
314 Preds.first = ARMCC::VS;
316 case CmpInst::FCMP_UGE:
317 Preds.first = ARMCC::PL;
319 case CmpInst::ICMP_SLT:
320 case CmpInst::FCMP_ULT:
321 Preds.first = ARMCC::LT;
323 case CmpInst::ICMP_SLE:
324 case CmpInst::FCMP_ULE:
325 Preds.first = ARMCC::LE;
327 case CmpInst::FCMP_UNE:
328 case CmpInst::ICMP_NE:
329 Preds.first = ARMCC::NE;
331 case CmpInst::ICMP_UGE:
332 Preds.first = ARMCC::HS;
334 case CmpInst::ICMP_ULT:
335 Preds.first = ARMCC::LO;
340 assert(Preds.first != ARMCC::AL && "No comparisons needed?");
344 struct ARMInstructionSelector::CmpConstants {
345 CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned OpRegBank,
347 : ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
348 OperandRegBankID(OpRegBank), OperandSize(OpSize) {}
350 // The opcode used for performing the comparison.
351 const unsigned ComparisonOpcode;
353 // The opcode used for reading the flags set by the comparison. May be
354 // ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
355 const unsigned ReadFlagsOpcode;
357 // The assumed register bank ID for the operands.
358 const unsigned OperandRegBankID;
360 // The assumed size in bits for the operands.
361 const unsigned OperandSize;
364 struct ARMInstructionSelector::InsertInfo {
365 InsertInfo(MachineInstrBuilder &MIB)
366 : MBB(*MIB->getParent()), InsertBefore(std::next(MIB->getIterator())),
367 DbgLoc(MIB->getDebugLoc()) {}
369 MachineBasicBlock &MBB;
370 const MachineBasicBlock::instr_iterator InsertBefore;
371 const DebugLoc &DbgLoc;
374 void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
375 unsigned Constant) const {
376 (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVi))
379 .add(predOps(ARMCC::AL))
383 bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
384 unsigned LHSReg, unsigned RHSReg,
385 unsigned ExpectedSize,
386 unsigned ExpectedRegBankID) const {
387 return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
388 validReg(MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
389 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
392 bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
393 unsigned ExpectedSize,
394 unsigned ExpectedRegBankID) const {
395 if (MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
396 DEBUG(dbgs() << "Unexpected size for register");
400 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
401 DEBUG(dbgs() << "Unexpected register bank for register");
408 bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
409 MachineInstrBuilder &MIB,
410 MachineRegisterInfo &MRI) const {
411 const InsertInfo I(MIB);
413 auto ResReg = MIB->getOperand(0).getReg();
414 if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
418 static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
419 if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
420 putConstant(I, ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
421 MIB->eraseFromParent();
425 auto LHSReg = MIB->getOperand(2).getReg();
426 auto RHSReg = MIB->getOperand(3).getReg();
427 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
428 Helper.OperandRegBankID))
431 auto ARMConds = getComparePreds(Cond);
432 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
433 putConstant(I, ZeroReg, 0);
435 if (ARMConds.second == ARMCC::AL) {
436 // Simple case, we only need one comparison and we're done.
437 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
441 // Not so simple, we need two successive comparisons.
442 auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
443 if (!insertComparison(Helper, I, IntermediateRes, ARMConds.first, LHSReg,
446 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg,
451 MIB->eraseFromParent();
455 bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
457 ARMCC::CondCodes Cond,
458 unsigned LHSReg, unsigned RHSReg,
459 unsigned PrevRes) const {
460 // Perform the comparison.
462 BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode))
465 .add(predOps(ARMCC::AL));
466 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
469 // Read the comparison flags (if necessary).
470 if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
471 auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
472 TII.get(Helper.ReadFlagsOpcode))
473 .add(predOps(ARMCC::AL));
474 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI))
478 // Select either 1 or the previous result based on the value of the flags.
479 auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVCCi))
483 .add(predOps(Cond, ARM::CPSR));
484 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
490 bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
491 MachineRegisterInfo &MRI) const {
492 if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) {
493 DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n");
497 auto GV = MIB->getOperand(1).getGlobal();
498 if (GV->isThreadLocal()) {
499 DEBUG(dbgs() << "TLS variables not supported yet\n");
503 auto &MBB = *MIB->getParent();
504 auto &MF = *MBB.getParent();
506 bool UseMovt = STI.useMovt(MF);
508 unsigned Size = TM.getPointerSize();
509 unsigned Alignment = 4;
511 auto addOpsForConstantPoolLoad = [&MF, Alignment,
512 Size](MachineInstrBuilder &MIB,
513 const GlobalValue *GV, bool IsSBREL) {
514 assert(MIB->getOpcode() == ARM::LDRi12 && "Unsupported instruction");
515 auto ConstPool = MF.getConstantPool();
517 // For SB relative entries we need a target-specific constant pool.
518 // Otherwise, just use a regular constant pool entry.
520 ? ConstPool->getConstantPoolIndex(
521 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL), Alignment)
522 : ConstPool->getConstantPoolIndex(GV, Alignment);
523 MIB.addConstantPoolIndex(CPIndex, /*Offset*/ 0, /*TargetFlags*/ 0)
525 MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
526 MachineMemOperand::MOLoad, Size, Alignment))
528 .add(predOps(ARMCC::AL));
531 if (TM.isPositionIndependent()) {
532 bool Indirect = STI.isGVIndirectSymbol(GV);
533 // FIXME: Taking advantage of MOVT for ELF is pretty involved, so we don't
534 // support it yet. See PR28229.
536 UseMovt && !STI.isTargetELF()
537 ? (Indirect ? ARM::MOV_ga_pcrel_ldr : ARM::MOV_ga_pcrel)
538 : (Indirect ? ARM::LDRLIT_ga_pcrel_ldr : ARM::LDRLIT_ga_pcrel);
539 MIB->setDesc(TII.get(Opc));
541 int TargetFlags = ARMII::MO_NO_FLAG;
542 if (STI.isTargetDarwin())
543 TargetFlags |= ARMII::MO_NONLAZY;
544 if (STI.isGVInGOT(GV))
545 TargetFlags |= ARMII::MO_GOT;
546 MIB->getOperand(1).setTargetFlags(TargetFlags);
549 MIB.addMemOperand(MF.getMachineMemOperand(
550 MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad,
551 TM.getPointerSize(), Alignment));
553 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
556 bool isReadOnly = STI.getTargetLowering()->isReadOnly(GV);
557 if (STI.isROPI() && isReadOnly) {
558 unsigned Opc = UseMovt ? ARM::MOV_ga_pcrel : ARM::LDRLIT_ga_pcrel;
559 MIB->setDesc(TII.get(Opc));
560 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
562 if (STI.isRWPI() && !isReadOnly) {
563 auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
564 MachineInstrBuilder OffsetMIB;
566 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
567 TII.get(ARM::MOVi32imm), Offset);
568 OffsetMIB.addGlobalAddress(GV, /*Offset*/ 0, ARMII::MO_SBREL);
570 // Load the offset from the constant pool.
572 BuildMI(MBB, *MIB, MIB->getDebugLoc(), TII.get(ARM::LDRi12), Offset);
573 addOpsForConstantPoolLoad(OffsetMIB, GV, /*IsSBREL*/ true);
575 if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI))
578 // Add the offset to the SB register.
579 MIB->setDesc(TII.get(ARM::ADDrr));
580 MIB->RemoveOperand(1);
581 MIB.addReg(ARM::R9) // FIXME: don't hardcode R9
583 .add(predOps(ARMCC::AL))
586 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
589 if (STI.isTargetELF()) {
591 MIB->setDesc(TII.get(ARM::MOVi32imm));
593 // Load the global's address from the constant pool.
594 MIB->setDesc(TII.get(ARM::LDRi12));
595 MIB->RemoveOperand(1);
596 addOpsForConstantPoolLoad(MIB, GV, /*IsSBREL*/ false);
598 } else if (STI.isTargetMachO()) {
600 MIB->setDesc(TII.get(ARM::MOVi32imm));
602 MIB->setDesc(TII.get(ARM::LDRLIT_ga_abs));
604 DEBUG(dbgs() << "Object format not supported yet\n");
608 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
611 bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
612 MachineRegisterInfo &MRI) const {
613 auto &MBB = *MIB->getParent();
614 auto InsertBefore = std::next(MIB->getIterator());
615 auto &DbgLoc = MIB->getDebugLoc();
617 // Compare the condition to 0.
618 auto CondReg = MIB->getOperand(1).getReg();
619 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
620 "Unsupported types for select operation");
621 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::CMPri))
624 .add(predOps(ARMCC::AL));
625 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
628 // Move a value into the result register based on the result of the
630 auto ResReg = MIB->getOperand(0).getReg();
631 auto TrueReg = MIB->getOperand(2).getReg();
632 auto FalseReg = MIB->getOperand(3).getReg();
633 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
634 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
635 "Unsupported types for select operation");
636 auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(ARM::MOVCCr))
640 .add(predOps(ARMCC::EQ, ARM::CPSR));
641 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI))
644 MIB->eraseFromParent();
648 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc,
649 MachineInstrBuilder &MIB) const {
650 MIB->setDesc(TII.get(ARM::MOVsr));
651 MIB.addImm(ShiftOpc);
652 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
653 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
656 bool ARMInstructionSelector::select(MachineInstr &I) const {
657 assert(I.getParent() && "Instruction should be in a basic block!");
658 assert(I.getParent()->getParent() && "Instruction should be in a function!");
660 auto &MBB = *I.getParent();
661 auto &MF = *MBB.getParent();
662 auto &MRI = MF.getRegInfo();
664 if (!isPreISelGenericOpcode(I.getOpcode())) {
666 return selectCopy(I, TII, MRI, TRI, RBI);
674 MachineInstrBuilder MIB{MF, I};
677 using namespace TargetOpcode;
678 switch (I.getOpcode()) {
683 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
684 // FIXME: Smaller destination sizes coming soon!
685 if (DstTy.getSizeInBits() != 32) {
686 DEBUG(dbgs() << "Unsupported destination size for extension");
690 LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
691 unsigned SrcSize = SrcTy.getSizeInBits();
694 // ZExt boils down to & 0x1; for SExt we also subtract that from 0
695 I.setDesc(TII.get(ARM::ANDri));
696 MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
699 unsigned SExtResult = I.getOperand(0).getReg();
701 // Use a new virtual register for the result of the AND
702 unsigned AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
703 I.getOperand(0).setReg(AndResult);
705 auto InsertBefore = std::next(I.getIterator());
707 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::RSBri))
711 .add(predOps(ARMCC::AL))
713 if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
720 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
721 if (NewOpc == I.getOpcode())
723 I.setDesc(TII.get(NewOpc));
724 MIB.addImm(0).add(predOps(ARMCC::AL));
728 DEBUG(dbgs() << "Unsupported source size for extension");
735 // The high bits are undefined, so there's nothing special to do, just
736 // treat it as a copy.
737 auto SrcReg = I.getOperand(1).getReg();
738 auto DstReg = I.getOperand(0).getReg();
740 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
741 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
743 if (SrcRegBank.getID() != DstRegBank.getID()) {
744 DEBUG(dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
748 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
749 DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
753 I.setDesc(TII.get(COPY));
754 return selectCopy(I, TII, MRI, TRI, RBI);
757 return selectSelect(MIB, MRI);
759 CmpConstants Helper(ARM::CMPrr, ARM::INSTRUCTION_LIST_END,
760 ARM::GPRRegBankID, 32);
761 return selectCmp(Helper, MIB, MRI);
764 assert(STI.hasVFP2() && "Can't select fcmp without VFP");
766 unsigned OpReg = I.getOperand(2).getReg();
767 unsigned Size = MRI.getType(OpReg).getSizeInBits();
769 if (Size == 64 && STI.isFPOnlySP()) {
770 DEBUG(dbgs() << "Subtarget only supports single precision");
773 if (Size != 32 && Size != 64) {
774 DEBUG(dbgs() << "Unsupported size for G_FCMP operand");
778 CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
779 ARM::FPRRegBankID, Size);
780 return selectCmp(Helper, MIB, MRI);
783 return selectShift(ARM_AM::ShiftOpc::lsr, MIB);
785 return selectShift(ARM_AM::ShiftOpc::asr, MIB);
787 return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
790 I.setDesc(TII.get(ARM::ADDrr));
791 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
794 // Add 0 to the given frame index and hope it will eventually be folded into
796 I.setDesc(TII.get(ARM::ADDri));
797 MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
800 return selectGlobal(MIB, MRI);
803 const auto &MemOp = **I.memoperands_begin();
804 if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
805 DEBUG(dbgs() << "Atomic load/store not supported yet\n");
809 unsigned Reg = I.getOperand(0).getReg();
810 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
812 LLT ValTy = MRI.getType(Reg);
813 const auto ValSize = ValTy.getSizeInBits();
815 assert((ValSize != 64 || STI.hasVFP2()) &&
816 "Don't know how to load/store 64-bit value without VFP");
818 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
819 if (NewOpc == G_LOAD || NewOpc == G_STORE)
822 I.setDesc(TII.get(NewOpc));
824 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
825 // LDRH has a funny addressing mode (there's already a FIXME for it).
827 MIB.addImm(0).add(predOps(ARMCC::AL));
830 case G_MERGE_VALUES: {
831 if (!selectMergeValues(MIB, TII, MRI, TRI, RBI))
835 case G_UNMERGE_VALUES: {
836 if (!selectUnmergeValues(MIB, TII, MRI, TRI, RBI))
841 if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
842 DEBUG(dbgs() << "Unsupported condition register for G_BRCOND");
847 auto Test = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::TSTri))
848 .addReg(I.getOperand(0).getReg())
850 .add(predOps(ARMCC::AL));
851 if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI))
854 // Branch conditionally.
855 auto Branch = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::Bcc))
856 .add(I.getOperand(1))
857 .add(predOps(ARMCC::EQ, ARM::CPSR));
858 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
867 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);