1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMAsmBackend.h"
13 #include "MCTargetDesc/ARMAsmBackendDarwin.h"
14 #include "MCTargetDesc/ARMAsmBackendELF.h"
15 #include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMFixupKinds.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDirectives.h"
23 #include "llvm/MC/MCELFObjectWriter.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixupKindInfo.h"
26 #include "llvm/MC/MCMachObjectWriter.h"
27 #include "llvm/MC/MCObjectWriter.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSectionELF.h"
30 #include "llvm/MC/MCSectionMachO.h"
31 #include "llvm/MC/MCSubtargetInfo.h"
32 #include "llvm/MC/MCValue.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ELF.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/Format.h"
37 #include "llvm/Support/MachO.h"
38 #include "llvm/Support/TargetParser.h"
39 #include "llvm/Support/raw_ostream.h"
43 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
45 ARMELFObjectWriter(uint8_t OSABI)
46 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
47 /*HasRelocationAddend*/ false) {}
49 } // end anonymous namespace
51 const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
52 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
53 // This table *must* be in the order that the fixup_* kinds are defined in
56 // Name Offset (bits) Size (bits) Flags
57 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
58 {"fixup_t2_ldst_pcrel_12", 0, 32,
59 MCFixupKindInfo::FKF_IsPCRel |
60 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
61 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
62 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
63 {"fixup_t2_pcrel_10", 0, 32,
64 MCFixupKindInfo::FKF_IsPCRel |
65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
66 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
67 {"fixup_t2_pcrel_9", 0, 32,
68 MCFixupKindInfo::FKF_IsPCRel |
69 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
70 {"fixup_thumb_adr_pcrel_10", 0, 8,
71 MCFixupKindInfo::FKF_IsPCRel |
72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
73 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
74 {"fixup_t2_adr_pcrel_12", 0, 32,
75 MCFixupKindInfo::FKF_IsPCRel |
76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
77 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
78 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
79 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
80 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
81 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
82 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
83 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
84 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
85 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
86 {"fixup_arm_thumb_blx", 0, 32,
87 MCFixupKindInfo::FKF_IsPCRel |
88 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
89 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
90 {"fixup_arm_thumb_cp", 0, 8,
91 MCFixupKindInfo::FKF_IsPCRel |
92 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
93 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
94 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
96 {"fixup_arm_movt_hi16", 0, 20, 0},
97 {"fixup_arm_movw_lo16", 0, 20, 0},
98 {"fixup_t2_movt_hi16", 0, 20, 0},
99 {"fixup_t2_movw_lo16", 0, 20, 0},
100 {"fixup_arm_mod_imm", 0, 12, 0},
102 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
103 // This table *must* be in the order that the fixup_* kinds are defined in
106 // Name Offset (bits) Size (bits) Flags
107 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
108 {"fixup_t2_ldst_pcrel_12", 0, 32,
109 MCFixupKindInfo::FKF_IsPCRel |
110 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
111 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
112 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
113 {"fixup_t2_pcrel_10", 0, 32,
114 MCFixupKindInfo::FKF_IsPCRel |
115 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
116 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
117 {"fixup_t2_pcrel_9", 0, 32,
118 MCFixupKindInfo::FKF_IsPCRel |
119 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
120 {"fixup_thumb_adr_pcrel_10", 8, 8,
121 MCFixupKindInfo::FKF_IsPCRel |
122 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
123 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
124 {"fixup_t2_adr_pcrel_12", 0, 32,
125 MCFixupKindInfo::FKF_IsPCRel |
126 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
127 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
128 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
129 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
130 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
131 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
132 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
133 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
134 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
135 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
136 {"fixup_arm_thumb_blx", 0, 32,
137 MCFixupKindInfo::FKF_IsPCRel |
138 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
139 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
140 {"fixup_arm_thumb_cp", 8, 8,
141 MCFixupKindInfo::FKF_IsPCRel |
142 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
143 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
144 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
146 {"fixup_arm_movt_hi16", 12, 20, 0},
147 {"fixup_arm_movw_lo16", 12, 20, 0},
148 {"fixup_t2_movt_hi16", 12, 20, 0},
149 {"fixup_t2_movw_lo16", 12, 20, 0},
150 {"fixup_arm_mod_imm", 20, 12, 0},
153 if (Kind < FirstTargetFixupKind)
154 return MCAsmBackend::getFixupKindInfo(Kind);
156 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
158 return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
161 void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
174 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
175 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2];
176 bool HasV8MBaselineOps = STI->getFeatureBits()[ARM::HasV8MBaselineOps];
182 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
184 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
186 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
188 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
196 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
197 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
202 const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
203 uint64_t Value) const {
204 switch ((unsigned)Fixup.getKind()) {
205 case ARM::fixup_arm_thumb_br: {
206 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
207 // low bit being an implied zero. There's an implied +4 offset for the
208 // branch, so we adjust the other way here to determine what's
211 // Relax if the value is too big for a (signed) i8.
212 int64_t Offset = int64_t(Value) - 4;
213 if (Offset > 2046 || Offset < -2048)
214 return "out of range pc-relative fixup value";
217 case ARM::fixup_arm_thumb_bcc: {
218 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
219 // low bit being an implied zero. There's an implied +4 offset for the
220 // branch, so we adjust the other way here to determine what's
223 // Relax if the value is too big for a (signed) i8.
224 int64_t Offset = int64_t(Value) - 4;
225 if (Offset > 254 || Offset < -256)
226 return "out of range pc-relative fixup value";
229 case ARM::fixup_thumb_adr_pcrel_10:
230 case ARM::fixup_arm_thumb_cp: {
231 // If the immediate is negative, greater than 1020, or not a multiple
232 // of four, the wide version of the instruction must be used.
233 int64_t Offset = int64_t(Value) - 4;
235 return "misaligned pc-relative fixup value";
236 else if (Offset > 1020 || Offset < 0)
237 return "out of range pc-relative fixup value";
240 case ARM::fixup_arm_thumb_cb: {
241 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
242 // instruction it is is actually out of range for the instruction.
243 // It will be changed to a NOP.
244 int64_t Offset = (Value & ~1);
246 return "will be converted to nop";
250 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
255 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
256 const MCRelaxableFragment *DF,
257 const MCAsmLayout &Layout) const {
258 return reasonForFixupRelaxation(Fixup, Value);
261 void ARMAsmBackend::relaxInstruction(const MCInst &Inst,
262 const MCSubtargetInfo &STI,
264 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
266 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
267 if (RelaxedOp == Inst.getOpcode()) {
268 SmallString<256> Tmp;
269 raw_svector_ostream OS(Tmp);
270 Inst.dump_pretty(OS);
272 report_fatal_error("unexpected instruction to relax: " + OS.str());
275 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
276 // have to change the operands too.
277 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
278 RelaxedOp == ARM::tHINT) {
279 Res.setOpcode(RelaxedOp);
280 Res.addOperand(MCOperand::createImm(0));
281 Res.addOperand(MCOperand::createImm(14));
282 Res.addOperand(MCOperand::createReg(0));
286 // The rest of instructions we're relaxing have the same operands.
287 // We just need to update to the proper opcode.
289 Res.setOpcode(RelaxedOp);
292 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
293 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
294 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
295 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
296 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
298 const uint16_t nopEncoding =
299 hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
300 uint64_t NumNops = Count / 2;
301 for (uint64_t i = 0; i != NumNops; ++i)
302 OW->write16(nopEncoding);
308 const uint32_t nopEncoding =
309 hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
310 uint64_t NumNops = Count / 4;
311 for (uint64_t i = 0; i != NumNops; ++i)
312 OW->write32(nopEncoding);
313 // FIXME: should this function return false when unable to write exactly
314 // 'Count' bytes with NOP encodings?
317 break; // No leftover bytes to write
333 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
334 if (IsLittleEndian) {
335 // Note that the halfwords are stored high first and low second in thumb;
336 // so we need to swap the fixup value here to map properly.
337 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
338 Swapped |= (Value & 0x0000FFFF) << 16;
344 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
345 bool IsLittleEndian) {
348 if (IsLittleEndian) {
349 Value = (SecondHalf & 0xFFFF) << 16;
350 Value |= (FirstHalf & 0xFFFF);
352 Value = (SecondHalf & 0xFFFF);
353 Value |= (FirstHalf & 0xFFFF) << 16;
359 unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
360 bool IsPCRel, MCContext *Ctx,
362 bool IsResolved) const {
363 unsigned Kind = Fixup.getKind();
366 llvm_unreachable("Unknown fixup kind!");
375 case ARM::fixup_arm_movt_hi16:
379 case ARM::fixup_arm_movw_lo16: {
380 unsigned Hi4 = (Value & 0xF000) >> 12;
381 unsigned Lo12 = Value & 0x0FFF;
382 // inst{19-16} = Hi4;
383 // inst{11-0} = Lo12;
384 Value = (Hi4 << 16) | (Lo12);
387 case ARM::fixup_t2_movt_hi16:
391 case ARM::fixup_t2_movw_lo16: {
392 unsigned Hi4 = (Value & 0xF000) >> 12;
393 unsigned i = (Value & 0x800) >> 11;
394 unsigned Mid3 = (Value & 0x700) >> 8;
395 unsigned Lo8 = Value & 0x0FF;
396 // inst{19-16} = Hi4;
398 // inst{14-12} = Mid3;
400 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
401 return swapHalfWords(Value, IsLittleEndian);
403 case ARM::fixup_arm_ldst_pcrel_12:
404 // ARM PC-relative values are offset by 8.
407 case ARM::fixup_t2_ldst_pcrel_12: {
408 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
411 if ((int64_t)Value < 0) {
415 if (Ctx && Value >= 4096) {
416 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
419 Value |= isAdd << 23;
421 // Same addressing mode as fixup_arm_pcrel_10,
422 // but with 16-bit halfwords swapped.
423 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
424 return swapHalfWords(Value, IsLittleEndian);
428 case ARM::fixup_arm_adr_pcrel_12: {
429 // ARM PC-relative values are offset by 8.
431 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
432 if ((int64_t)Value < 0) {
436 if (Ctx && ARM_AM::getSOImmVal(Value) == -1) {
437 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
440 // Encode the immediate and shift the opcode into place.
441 return ARM_AM::getSOImmVal(Value) | (opc << 21);
444 case ARM::fixup_t2_adr_pcrel_12: {
447 if ((int64_t)Value < 0) {
452 uint32_t out = (opc << 21);
453 out |= (Value & 0x800) << 15;
454 out |= (Value & 0x700) << 4;
455 out |= (Value & 0x0FF);
457 return swapHalfWords(out, IsLittleEndian);
460 case ARM::fixup_arm_condbranch:
461 case ARM::fixup_arm_uncondbranch:
462 case ARM::fixup_arm_uncondbl:
463 case ARM::fixup_arm_condbl:
464 case ARM::fixup_arm_blx:
465 // These values don't encode the low two bits since they're always zero.
466 // Offset by 8 just as above.
467 if (const MCSymbolRefExpr *SRE =
468 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
469 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
471 return 0xffffff & ((Value - 8) >> 2);
472 case ARM::fixup_t2_uncondbranch: {
474 Value >>= 1; // Low bit is not encoded.
477 bool I = Value & 0x800000;
478 bool J1 = Value & 0x400000;
479 bool J2 = Value & 0x200000;
483 out |= I << 26; // S bit
484 out |= !J1 << 13; // J1 bit
485 out |= !J2 << 11; // J2 bit
486 out |= (Value & 0x1FF800) << 5; // imm6 field
487 out |= (Value & 0x0007FF); // imm11 field
489 return swapHalfWords(out, IsLittleEndian);
491 case ARM::fixup_t2_condbranch: {
493 Value >>= 1; // Low bit is not encoded.
496 out |= (Value & 0x80000) << 7; // S bit
497 out |= (Value & 0x40000) >> 7; // J2 bit
498 out |= (Value & 0x20000) >> 4; // J1 bit
499 out |= (Value & 0x1F800) << 5; // imm6 field
500 out |= (Value & 0x007FF); // imm11 field
502 return swapHalfWords(out, IsLittleEndian);
504 case ARM::fixup_arm_thumb_bl: {
505 // The value doesn't encode the low bit (always zero) and is offset by
506 // four. The 32-bit immediate value is encoded as
507 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
508 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
509 // The value is encoded into disjoint bit positions in the destination
510 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
511 // J = either J1 or J2 bit
513 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
515 // Note that the halfwords are stored high first, low second; so we need
516 // to transpose the fixup value here to map properly.
517 uint32_t offset = (Value - 4) >> 1;
518 uint32_t signBit = (offset & 0x800000) >> 23;
519 uint32_t I1Bit = (offset & 0x400000) >> 22;
520 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
521 uint32_t I2Bit = (offset & 0x200000) >> 21;
522 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
523 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
524 uint32_t imm11Bits = (offset & 0x000007FF);
526 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
527 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
528 (uint16_t)imm11Bits);
529 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
531 case ARM::fixup_arm_thumb_blx: {
532 // The value doesn't encode the low two bits (always zero) and is offset by
533 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
534 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
535 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
536 // The value is encoded into disjoint bit positions in the destination
537 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
538 // J = either J1 or J2 bit, 0 = zero.
540 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
542 // Note that the halfwords are stored high first, low second; so we need
543 // to transpose the fixup value here to map properly.
544 if (Ctx && Value % 4 != 0) {
545 Ctx->reportError(Fixup.getLoc(), "misaligned ARM call destination");
549 uint32_t offset = (Value - 4) >> 2;
550 if (const MCSymbolRefExpr *SRE =
551 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
552 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
554 uint32_t signBit = (offset & 0x400000) >> 22;
555 uint32_t I1Bit = (offset & 0x200000) >> 21;
556 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
557 uint32_t I2Bit = (offset & 0x100000) >> 20;
558 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
559 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
560 uint32_t imm10LBits = (offset & 0x3FF);
562 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
563 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
564 ((uint16_t)imm10LBits) << 1);
565 return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
567 case ARM::fixup_thumb_adr_pcrel_10:
568 case ARM::fixup_arm_thumb_cp:
569 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
570 // could have an error on our hands.
571 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
572 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
573 if (FixupDiagnostic) {
574 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic);
578 // Offset by 4, and don't encode the low two bits.
579 return ((Value - 4) >> 2) & 0xff;
580 case ARM::fixup_arm_thumb_cb: {
581 // Offset by 4 and don't encode the lower bit, which is always 0.
582 // FIXME: diagnose if no Thumb2
583 uint32_t Binary = (Value - 4) >> 1;
584 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
586 case ARM::fixup_arm_thumb_br:
587 // Offset by 4 and don't encode the lower bit, which is always 0.
588 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] &&
589 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
590 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
591 if (FixupDiagnostic) {
592 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic);
596 return ((Value - 4) >> 1) & 0x7ff;
597 case ARM::fixup_arm_thumb_bcc:
598 // Offset by 4 and don't encode the lower bit, which is always 0.
599 if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) {
600 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
601 if (FixupDiagnostic) {
602 Ctx->reportError(Fixup.getLoc(), FixupDiagnostic);
606 return ((Value - 4) >> 1) & 0xff;
607 case ARM::fixup_arm_pcrel_10_unscaled: {
608 Value = Value - 8; // ARM fixups offset by an additional word and don't
609 // need to adjust for the half-word ordering.
611 if ((int64_t)Value < 0) {
615 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
616 if (Ctx && Value >= 256) {
617 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
620 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
621 return Value | (isAdd << 23);
623 case ARM::fixup_arm_pcrel_10:
624 Value = Value - 4; // ARM fixups offset by an additional word and don't
625 // need to adjust for the half-word ordering.
627 case ARM::fixup_t2_pcrel_10: {
628 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
631 if ((int64_t)Value < 0) {
635 // These values don't encode the low two bits since they're always zero.
637 if (Ctx && Value >= 256) {
638 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
641 Value |= isAdd << 23;
643 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
645 if (Kind == ARM::fixup_t2_pcrel_10)
646 return swapHalfWords(Value, IsLittleEndian);
650 case ARM::fixup_arm_pcrel_9:
651 Value = Value - 4; // ARM fixups offset by an additional word and don't
652 // need to adjust for the half-word ordering.
654 case ARM::fixup_t2_pcrel_9: {
655 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
658 if ((int64_t)Value < 0) {
662 // These values don't encode the low bit since it's always zero.
663 if (Ctx && (Value & 1)) {
664 Ctx->reportError(Fixup.getLoc(), "invalid value for this fixup");
668 if (Ctx && Value >= 256) {
669 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
672 Value |= isAdd << 23;
674 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
676 if (Kind == ARM::fixup_t2_pcrel_9)
677 return swapHalfWords(Value, IsLittleEndian);
681 case ARM::fixup_arm_mod_imm:
682 Value = ARM_AM::getSOImmVal(Value);
683 if (Ctx && Value >> 12) {
684 Ctx->reportError(Fixup.getLoc(), "out of range immediate fixup value");
691 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
692 const MCAsmLayout &Layout,
693 const MCFixup &Fixup,
694 const MCFragment *DF,
695 const MCValue &Target, uint64_t &Value,
697 const MCSymbolRefExpr *A = Target.getSymA();
698 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
699 // Some fixups to thumb function symbols need the low bit (thumb bit)
701 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
702 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
703 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
704 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
705 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
706 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
708 if (Asm.isThumbFunc(Sym))
712 if (IsResolved && (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
713 assert(Sym && "How did we resolve this?");
715 // If the symbol is external the linker will handle it.
716 // FIXME: Should we handle it as an optimization?
718 // If the symbol is out of range, produce a relocation and hope the
719 // linker can handle it. GNU AS produces an error in this case.
720 if (Sym->isExternal() || Value >= 0x400004)
723 // We must always generate a relocation for BL/BLX instructions if we have
724 // a symbol to reference, as the linker relies on knowing the destination
725 // symbol's thumb-ness to get interworking right.
726 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
727 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
728 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
729 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
732 // Try to get the encoded value for the fixup as-if we're mapping it into
733 // the instruction. This allows adjustFixupValue() to issue a diagnostic
734 // if the value aren't invalid.
735 (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(),
736 IsLittleEndian, IsResolved);
739 /// getFixupKindNumBytes - The number of bytes the fixup may change.
740 static unsigned getFixupKindNumBytes(unsigned Kind) {
743 llvm_unreachable("Unknown fixup kind!");
746 case ARM::fixup_arm_thumb_bcc:
747 case ARM::fixup_arm_thumb_cp:
748 case ARM::fixup_thumb_adr_pcrel_10:
752 case ARM::fixup_arm_thumb_br:
753 case ARM::fixup_arm_thumb_cb:
754 case ARM::fixup_arm_mod_imm:
757 case ARM::fixup_arm_pcrel_10_unscaled:
758 case ARM::fixup_arm_ldst_pcrel_12:
759 case ARM::fixup_arm_pcrel_10:
760 case ARM::fixup_arm_pcrel_9:
761 case ARM::fixup_arm_adr_pcrel_12:
762 case ARM::fixup_arm_uncondbl:
763 case ARM::fixup_arm_condbl:
764 case ARM::fixup_arm_blx:
765 case ARM::fixup_arm_condbranch:
766 case ARM::fixup_arm_uncondbranch:
770 case ARM::fixup_t2_ldst_pcrel_12:
771 case ARM::fixup_t2_condbranch:
772 case ARM::fixup_t2_uncondbranch:
773 case ARM::fixup_t2_pcrel_10:
774 case ARM::fixup_t2_pcrel_9:
775 case ARM::fixup_t2_adr_pcrel_12:
776 case ARM::fixup_arm_thumb_bl:
777 case ARM::fixup_arm_thumb_blx:
778 case ARM::fixup_arm_movt_hi16:
779 case ARM::fixup_arm_movw_lo16:
780 case ARM::fixup_t2_movt_hi16:
781 case ARM::fixup_t2_movw_lo16:
791 /// getFixupKindContainerSizeBytes - The number of bytes of the
792 /// container involved in big endian.
793 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
796 llvm_unreachable("Unknown fixup kind!");
805 case ARM::fixup_arm_thumb_bcc:
806 case ARM::fixup_arm_thumb_cp:
807 case ARM::fixup_thumb_adr_pcrel_10:
808 case ARM::fixup_arm_thumb_br:
809 case ARM::fixup_arm_thumb_cb:
810 // Instruction size is 2 bytes.
813 case ARM::fixup_arm_pcrel_10_unscaled:
814 case ARM::fixup_arm_ldst_pcrel_12:
815 case ARM::fixup_arm_pcrel_10:
816 case ARM::fixup_arm_adr_pcrel_12:
817 case ARM::fixup_arm_uncondbl:
818 case ARM::fixup_arm_condbl:
819 case ARM::fixup_arm_blx:
820 case ARM::fixup_arm_condbranch:
821 case ARM::fixup_arm_uncondbranch:
822 case ARM::fixup_t2_ldst_pcrel_12:
823 case ARM::fixup_t2_condbranch:
824 case ARM::fixup_t2_uncondbranch:
825 case ARM::fixup_t2_pcrel_10:
826 case ARM::fixup_t2_adr_pcrel_12:
827 case ARM::fixup_arm_thumb_bl:
828 case ARM::fixup_arm_thumb_blx:
829 case ARM::fixup_arm_movt_hi16:
830 case ARM::fixup_arm_movw_lo16:
831 case ARM::fixup_t2_movt_hi16:
832 case ARM::fixup_t2_movw_lo16:
833 case ARM::fixup_arm_mod_imm:
834 // Instruction size is 4 bytes.
839 void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
840 unsigned DataSize, uint64_t Value,
841 bool IsPCRel) const {
842 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
844 adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian, true);
846 return; // Doesn't change encoding.
848 unsigned Offset = Fixup.getOffset();
849 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
851 // Used to point to big endian bytes.
852 unsigned FullSizeBytes;
853 if (!IsLittleEndian) {
854 FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
855 assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!");
856 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
859 // For each byte of the fragment that the fixup touches, mask in the bits from
860 // the fixup value. The Value has been "split up" into the appropriate
862 for (unsigned i = 0; i != NumBytes; ++i) {
863 unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
864 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
870 /// \brief Compact unwind encoding values.
871 enum CompactUnwindEncodings {
872 UNWIND_ARM_MODE_MASK = 0x0F000000,
873 UNWIND_ARM_MODE_FRAME = 0x01000000,
874 UNWIND_ARM_MODE_FRAME_D = 0x02000000,
875 UNWIND_ARM_MODE_DWARF = 0x04000000,
877 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000,
879 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001,
880 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002,
881 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004,
883 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008,
884 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010,
885 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020,
886 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040,
887 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080,
889 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00,
891 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF
894 } // end CU namespace
896 /// Generate compact unwind encoding for the function based on the CFI
897 /// instructions. If the CFI instructions describe a frame that cannot be
898 /// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
899 /// tells the runtime to fallback and unwind using dwarf.
900 uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
901 ArrayRef<MCCFIInstruction> Instrs) const {
902 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
903 // Only armv7k uses CFI based unwinding.
904 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
906 // No .cfi directives means no frame.
909 // Start off assuming CFA is at SP+0.
910 int CFARegister = ARM::SP;
911 int CFARegisterOffset = 0;
912 // Mark savable registers as initially unsaved
913 DenseMap<unsigned, int> RegOffsets;
914 int FloatRegCount = 0;
915 // Process each .cfi directive and build up compact unwind info.
916 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
918 const MCCFIInstruction &Inst = Instrs[i];
919 switch (Inst.getOperation()) {
920 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
921 CFARegisterOffset = -Inst.getOffset();
922 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
924 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
925 CFARegisterOffset = -Inst.getOffset();
927 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
928 CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
930 case MCCFIInstruction::OpOffset: // DW_CFA_offset
931 Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
932 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
933 RegOffsets[Reg] = Inst.getOffset();
934 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
935 RegOffsets[Reg] = Inst.getOffset();
938 DEBUG_WITH_TYPE("compact-unwind",
939 llvm::dbgs() << ".cfi_offset on unknown register="
940 << Inst.getRegister() << "\n");
941 return CU::UNWIND_ARM_MODE_DWARF;
944 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
948 // Directive not convertable to compact unwind, bail out.
949 DEBUG_WITH_TYPE("compact-unwind",
951 << "CFI directive not compatiable with comact "
952 "unwind encoding, opcode=" << Inst.getOperation()
954 return CU::UNWIND_ARM_MODE_DWARF;
959 // If no frame set up, return no unwind info.
960 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
963 // Verify standard frame (lr/r7) was used.
964 if (CFARegister != ARM::R7) {
965 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
967 << " instead of r7\n");
968 return CU::UNWIND_ARM_MODE_DWARF;
970 int StackAdjust = CFARegisterOffset - 8;
971 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
972 DEBUG_WITH_TYPE("compact-unwind",
974 << "LR not saved as standard frame, StackAdjust="
976 << ", CFARegisterOffset=" << CFARegisterOffset
977 << ", lr save at offset=" << RegOffsets[14] << "\n");
978 return CU::UNWIND_ARM_MODE_DWARF;
980 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
981 DEBUG_WITH_TYPE("compact-unwind",
982 llvm::dbgs() << "r7 not saved as standard frame\n");
983 return CU::UNWIND_ARM_MODE_DWARF;
985 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
987 // If var-args are used, there may be a stack adjust required.
988 switch (StackAdjust) {
992 CompactUnwindEncoding |= 0x00400000;
995 CompactUnwindEncoding |= 0x00800000;
998 CompactUnwindEncoding |= 0x00C00000;
1001 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1002 << ".cfi_def_cfa stack adjust ("
1003 << StackAdjust << ") out of range\n");
1004 return CU::UNWIND_ARM_MODE_DWARF;
1007 // If r6 is saved, it must be right below r7.
1011 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1012 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5},
1013 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4},
1014 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12},
1015 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11},
1016 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10},
1017 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9},
1018 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}};
1020 int CurOffset = -8 - StackAdjust;
1021 for (auto CSReg : GPRCSRegs) {
1022 auto Offset = RegOffsets.find(CSReg.Reg);
1023 if (Offset == RegOffsets.end())
1026 int RegOffset = Offset->second;
1027 if (RegOffset != CurOffset - 4) {
1028 DEBUG_WITH_TYPE("compact-unwind",
1029 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1030 << RegOffset << " but only supported at "
1031 << CurOffset << "\n");
1032 return CU::UNWIND_ARM_MODE_DWARF;
1034 CompactUnwindEncoding |= CSReg.Encoding;
1038 // If no floats saved, we are done.
1039 if (FloatRegCount == 0)
1040 return CompactUnwindEncoding;
1042 // Switch mode to include D register saving.
1043 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1044 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1046 // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1047 // but needs coordination with the linker and libunwind.
1048 if (FloatRegCount > 4) {
1049 DEBUG_WITH_TYPE("compact-unwind",
1050 llvm::dbgs() << "unsupported number of D registers saved ("
1051 << FloatRegCount << ")\n");
1052 return CU::UNWIND_ARM_MODE_DWARF;
1055 // Floating point registers must either be saved sequentially, or we defer to
1056 // DWARF. No gaps allowed here so check that each saved d-register is
1057 // precisely where it should be.
1058 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1059 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1060 auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1061 if (Offset == RegOffsets.end()) {
1062 DEBUG_WITH_TYPE("compact-unwind",
1063 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1064 << MRI.getName(FPRCSRegs[Idx])
1066 return CU::UNWIND_ARM_MODE_DWARF;
1067 } else if (Offset->second != CurOffset - 8) {
1068 DEBUG_WITH_TYPE("compact-unwind",
1069 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1070 << MRI.getName(FPRCSRegs[Idx])
1071 << " saved at " << Offset->second
1072 << ", expected at " << CurOffset - 8
1074 return CU::UNWIND_ARM_MODE_DWARF;
1079 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1082 static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
1083 unsigned AK = ARM::parseArch(Arch);
1086 return MachO::CPU_SUBTYPE_ARM_V7;
1087 case ARM::AK_ARMV4T:
1088 return MachO::CPU_SUBTYPE_ARM_V4T;
1089 case ARM::AK_ARMV5T:
1090 case ARM::AK_ARMV5TE:
1091 case ARM::AK_ARMV5TEJ:
1092 return MachO::CPU_SUBTYPE_ARM_V5;
1094 case ARM::AK_ARMV6K:
1095 return MachO::CPU_SUBTYPE_ARM_V6;
1096 case ARM::AK_ARMV7A:
1097 return MachO::CPU_SUBTYPE_ARM_V7;
1098 case ARM::AK_ARMV7S:
1099 return MachO::CPU_SUBTYPE_ARM_V7S;
1100 case ARM::AK_ARMV7K:
1101 return MachO::CPU_SUBTYPE_ARM_V7K;
1102 case ARM::AK_ARMV6M:
1103 return MachO::CPU_SUBTYPE_ARM_V6M;
1104 case ARM::AK_ARMV7M:
1105 return MachO::CPU_SUBTYPE_ARM_V7M;
1106 case ARM::AK_ARMV7EM:
1107 return MachO::CPU_SUBTYPE_ARM_V7EM;
1111 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
1112 const MCRegisterInfo &MRI,
1113 const Triple &TheTriple, StringRef CPU,
1115 switch (TheTriple.getObjectFormat()) {
1117 llvm_unreachable("unsupported object format");
1118 case Triple::MachO: {
1119 MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
1120 return new ARMAsmBackendDarwin(T, TheTriple, MRI, CS);
1123 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1124 return new ARMAsmBackendWinCOFF(T, TheTriple);
1126 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1127 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
1128 return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
1132 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
1133 const MCRegisterInfo &MRI,
1134 const Triple &TT, StringRef CPU) {
1135 return createARMAsmBackend(T, MRI, TT, CPU, true);
1138 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
1139 const MCRegisterInfo &MRI,
1140 const Triple &TT, StringRef CPU) {
1141 return createARMAsmBackend(T, MRI, TT, CPU, false);
1144 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
1145 const MCRegisterInfo &MRI,
1146 const Triple &TT, StringRef CPU) {
1147 return createARMAsmBackend(T, MRI, TT, CPU, true);
1150 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
1151 const MCRegisterInfo &MRI,
1152 const Triple &TT, StringRef CPU) {
1153 return createARMAsmBackend(T, MRI, TT, CPU, false);