1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMMCTargetDesc.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMFixupKinds.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCFixupKindInfo.h"
20 #include "llvm/MC/MCMachObjectWriter.h"
21 #include "llvm/MC/MCObjectWriter.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSectionMachO.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCValue.h"
27 #include "llvm/Object/MachOFormat.h"
28 #include "llvm/Support/ELF.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
34 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
36 ARMELFObjectWriter(uint8_t OSABI)
37 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
38 /*HasRelocationAddend*/ false) {}
41 class ARMAsmBackend : public MCAsmBackend {
42 const MCSubtargetInfo* STI;
43 bool isThumbMode; // Currently emitting Thumb code.
45 ARMAsmBackend(const Target &T, const StringRef TT)
46 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
47 isThumbMode(TT.startswith("thumb")) {}
53 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
56 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
59 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
60 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
61 // This table *must* be in the order that the fixup_* kinds are defined in
64 // Name Offset (bits) Size (bits) Flags
65 { "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
66 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
67 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
68 { "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
71 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
72 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
74 { "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
75 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
76 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
77 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
78 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
79 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
80 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
81 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
82 { "fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
83 { "fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
84 { "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
85 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
86 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
87 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
88 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel |
89 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
90 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
91 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19.
92 { "fixup_arm_movt_hi16", 0, 20, 0 },
93 { "fixup_arm_movw_lo16", 0, 20, 0 },
94 { "fixup_t2_movt_hi16", 0, 20, 0 },
95 { "fixup_t2_movw_lo16", 0, 20, 0 },
96 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
97 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
98 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
99 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel },
102 if (Kind < FirstTargetFixupKind)
103 return MCAsmBackend::getFixupKindInfo(Kind);
105 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
107 return Infos[Kind - FirstTargetFixupKind];
110 /// processFixupValue - Target hook to process the literal value of a fixup
112 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
113 const MCFixup &Fixup, const MCFragment *DF,
114 MCValue &Target, uint64_t &Value,
117 bool mayNeedRelaxation(const MCInst &Inst) const;
119 bool fixupNeedsRelaxation(const MCFixup &Fixup,
121 const MCInstFragment *DF,
122 const MCAsmLayout &Layout) const;
124 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
126 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
128 void handleAssemblerFlag(MCAssemblerFlag Flag) {
140 unsigned getPointerSize() const { return 4; }
141 bool isThumb() const { return isThumbMode; }
142 void setIsThumb(bool it) { isThumbMode = it; }
144 } // end anonymous namespace
146 static unsigned getRelaxedOpcode(unsigned Op) {
149 case ARM::tBcc: return ARM::t2Bcc;
150 case ARM::tLDRpciASM: return ARM::t2LDRpci;
151 case ARM::tADR: return ARM::t2ADR;
152 case ARM::tB: return ARM::t2B;
156 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
157 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
162 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
164 const MCInstFragment *DF,
165 const MCAsmLayout &Layout) const {
166 switch ((unsigned)Fixup.getKind()) {
167 case ARM::fixup_arm_thumb_br: {
168 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
169 // low bit being an implied zero. There's an implied +4 offset for the
170 // branch, so we adjust the other way here to determine what's
173 // Relax if the value is too big for a (signed) i8.
174 int64_t Offset = int64_t(Value) - 4;
175 return Offset > 2046 || Offset < -2048;
177 case ARM::fixup_arm_thumb_bcc: {
178 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
179 // low bit being an implied zero. There's an implied +4 offset for the
180 // branch, so we adjust the other way here to determine what's
183 // Relax if the value is too big for a (signed) i8.
184 int64_t Offset = int64_t(Value) - 4;
185 return Offset > 254 || Offset < -256;
187 case ARM::fixup_thumb_adr_pcrel_10:
188 case ARM::fixup_arm_thumb_cp: {
189 // If the immediate is negative, greater than 1020, or not a multiple
190 // of four, the wide version of the instruction must be used.
191 int64_t Offset = int64_t(Value) - 4;
192 return Offset > 1020 || Offset < 0 || Offset & 3;
195 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!");
198 void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
199 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
201 // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
202 if (RelaxedOp == Inst.getOpcode()) {
203 SmallString<256> Tmp;
204 raw_svector_ostream OS(Tmp);
205 Inst.dump_pretty(OS);
207 report_fatal_error("unexpected instruction to relax: " + OS.str());
210 // The instructions we're relaxing have (so far) the same operands.
211 // We just need to update to the proper opcode.
213 Res.setOpcode(RelaxedOp);
216 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
217 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
218 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
219 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0
220 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
222 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding
223 : Thumb1_16bitNopEncoding;
224 uint64_t NumNops = Count / 2;
225 for (uint64_t i = 0; i != NumNops; ++i)
226 OW->Write16(nopEncoding);
232 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding
234 uint64_t NumNops = Count / 4;
235 for (uint64_t i = 0; i != NumNops; ++i)
236 OW->Write32(nopEncoding);
237 // FIXME: should this function return false when unable to write exactly
238 // 'Count' bytes with NOP encodings?
240 default: break; // No leftover bytes to write
241 case 1: OW->Write8(0); break;
242 case 2: OW->Write16(0); break;
243 case 3: OW->Write16(0); OW->Write8(0xa0); break;
249 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
250 MCContext *Ctx = NULL) {
251 unsigned Kind = Fixup.getKind();
254 llvm_unreachable("Unknown fixup kind!");
259 case ARM::fixup_arm_movt_hi16:
262 case ARM::fixup_arm_movw_lo16:
263 case ARM::fixup_arm_movt_hi16_pcrel:
264 case ARM::fixup_arm_movw_lo16_pcrel: {
265 unsigned Hi4 = (Value & 0xF000) >> 12;
266 unsigned Lo12 = Value & 0x0FFF;
267 // inst{19-16} = Hi4;
268 // inst{11-0} = Lo12;
269 Value = (Hi4 << 16) | (Lo12);
272 case ARM::fixup_t2_movt_hi16:
275 case ARM::fixup_t2_movw_lo16:
276 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like
277 // the other hi16 fixup?
278 case ARM::fixup_t2_movw_lo16_pcrel: {
279 unsigned Hi4 = (Value & 0xF000) >> 12;
280 unsigned i = (Value & 0x800) >> 11;
281 unsigned Mid3 = (Value & 0x700) >> 8;
282 unsigned Lo8 = Value & 0x0FF;
283 // inst{19-16} = Hi4;
285 // inst{14-12} = Mid3;
287 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
288 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
289 swapped |= (Value & 0x0000FFFF) << 16;
292 case ARM::fixup_arm_ldst_pcrel_12:
293 // ARM PC-relative values are offset by 8.
296 case ARM::fixup_t2_ldst_pcrel_12: {
297 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
300 if ((int64_t)Value < 0) {
304 if (Ctx && Value >= 4096)
305 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
306 Value |= isAdd << 23;
308 // Same addressing mode as fixup_arm_pcrel_10,
309 // but with 16-bit halfwords swapped.
310 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
311 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
312 swapped |= (Value & 0x0000FFFF) << 16;
318 case ARM::fixup_thumb_adr_pcrel_10:
319 return ((Value - 4) >> 2) & 0xff;
320 case ARM::fixup_arm_adr_pcrel_12: {
321 // ARM PC-relative values are offset by 8.
323 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
324 if ((int64_t)Value < 0) {
328 if (Ctx && ARM_AM::getSOImmVal(Value) == -1)
329 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
330 // Encode the immediate and shift the opcode into place.
331 return ARM_AM::getSOImmVal(Value) | (opc << 21);
334 case ARM::fixup_t2_adr_pcrel_12: {
337 if ((int64_t)Value < 0) {
342 uint32_t out = (opc << 21);
343 out |= (Value & 0x800) << 15;
344 out |= (Value & 0x700) << 4;
345 out |= (Value & 0x0FF);
347 uint64_t swapped = (out & 0xFFFF0000) >> 16;
348 swapped |= (out & 0x0000FFFF) << 16;
352 case ARM::fixup_arm_condbranch:
353 case ARM::fixup_arm_uncondbranch:
354 case ARM::fixup_arm_uncondbl:
355 case ARM::fixup_arm_condbl:
356 case ARM::fixup_arm_blx:
357 // These values don't encode the low two bits since they're always zero.
358 // Offset by 8 just as above.
359 return 0xffffff & ((Value - 8) >> 2);
360 case ARM::fixup_t2_uncondbranch: {
362 Value >>= 1; // Low bit is not encoded.
365 bool I = Value & 0x800000;
366 bool J1 = Value & 0x400000;
367 bool J2 = Value & 0x200000;
371 out |= I << 26; // S bit
372 out |= !J1 << 13; // J1 bit
373 out |= !J2 << 11; // J2 bit
374 out |= (Value & 0x1FF800) << 5; // imm6 field
375 out |= (Value & 0x0007FF); // imm11 field
377 uint64_t swapped = (out & 0xFFFF0000) >> 16;
378 swapped |= (out & 0x0000FFFF) << 16;
381 case ARM::fixup_t2_condbranch: {
383 Value >>= 1; // Low bit is not encoded.
386 out |= (Value & 0x80000) << 7; // S bit
387 out |= (Value & 0x40000) >> 7; // J2 bit
388 out |= (Value & 0x20000) >> 4; // J1 bit
389 out |= (Value & 0x1F800) << 5; // imm6 field
390 out |= (Value & 0x007FF); // imm11 field
392 uint32_t swapped = (out & 0xFFFF0000) >> 16;
393 swapped |= (out & 0x0000FFFF) << 16;
396 case ARM::fixup_arm_thumb_bl: {
397 // The value doesn't encode the low bit (always zero) and is offset by
398 // four. The value is encoded into disjoint bit positions in the destination
399 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
401 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
403 // Note that the halfwords are stored high first, low second; so we need
404 // to transpose the fixup value here to map properly.
405 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0;
407 Value = 0x3fffff & ((Value - 4) >> 1);
408 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
409 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
410 Binary |= isNeg << 10; // Sign bit.
413 case ARM::fixup_arm_thumb_blx: {
414 // The value doesn't encode the low two bits (always zero) and is offset by
415 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
416 // positions in the destination opcode. x = unchanged, I = immediate value
417 // bit, S = sign extension bit, 0 = zero.
419 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
421 // Note that the halfwords are stored high first, low second; so we need
422 // to transpose the fixup value here to map properly.
423 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0;
425 Value = 0xfffff & ((Value - 2) >> 2);
426 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
427 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
428 Binary |= isNeg << 10; // Sign bit.
431 case ARM::fixup_arm_thumb_cp:
432 // Offset by 4, and don't encode the low two bits. Two bytes of that
433 // 'off by 4' is implicitly handled by the half-word ordering of the
434 // Thumb encoding, so we only need to adjust by 2 here.
435 return ((Value - 2) >> 2) & 0xff;
436 case ARM::fixup_arm_thumb_cb: {
437 // Offset by 4 and don't encode the lower bit, which is always 0.
438 uint32_t Binary = (Value - 4) >> 1;
439 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
441 case ARM::fixup_arm_thumb_br:
442 // Offset by 4 and don't encode the lower bit, which is always 0.
443 return ((Value - 4) >> 1) & 0x7ff;
444 case ARM::fixup_arm_thumb_bcc:
445 // Offset by 4 and don't encode the lower bit, which is always 0.
446 return ((Value - 4) >> 1) & 0xff;
447 case ARM::fixup_arm_pcrel_10_unscaled: {
448 Value = Value - 8; // ARM fixups offset by an additional word and don't
449 // need to adjust for the half-word ordering.
451 if ((int64_t)Value < 0) {
455 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
456 if (Ctx && Value >= 256)
457 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
458 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
459 return Value | (isAdd << 23);
461 case ARM::fixup_arm_pcrel_10:
462 Value = Value - 4; // ARM fixups offset by an additional word and don't
463 // need to adjust for the half-word ordering.
465 case ARM::fixup_t2_pcrel_10: {
466 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
469 if ((int64_t)Value < 0) {
473 // These values don't encode the low two bits since they're always zero.
475 if (Ctx && Value >= 256)
476 Ctx->FatalError(Fixup.getLoc(), "out of range pc-relative fixup value");
477 Value |= isAdd << 23;
479 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
481 if (Kind == ARM::fixup_t2_pcrel_10) {
482 uint32_t swapped = (Value & 0xFFFF0000) >> 16;
483 swapped |= (Value & 0x0000FFFF) << 16;
492 void ARMAsmBackend::processFixupValue(const MCAssembler &Asm,
493 const MCAsmLayout &Layout,
494 const MCFixup &Fixup,
495 const MCFragment *DF,
496 MCValue &Target, uint64_t &Value,
498 const MCSymbolRefExpr *A = Target.getSymA();
499 // Some fixups to thumb function symbols need the low bit (thumb bit)
501 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&
502 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&
503 (unsigned)Fixup.getKind() != ARM::fixup_arm_adr_pcrel_12 &&
504 (unsigned)Fixup.getKind() != ARM::fixup_thumb_adr_pcrel_10 &&
505 (unsigned)Fixup.getKind() != ARM::fixup_t2_adr_pcrel_12 &&
506 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {
508 const MCSymbol &Sym = A->getSymbol().AliasedSymbol();
509 if (Asm.isThumbFunc(&Sym))
513 // We must always generate a relocation for BL/BLX instructions if we have
514 // a symbol to reference, as the linker relies on knowing the destination
515 // symbol's thumb-ness to get interworking right.
516 if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||
517 (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||
518 (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||
519 (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
520 (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
523 // Try to get the encoded value for the fixup as-if we're mapping it into
524 // the instruction. This allows adjustFixupValue() to issue a diagnostic
525 // if the value aren't invalid.
526 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
531 // FIXME: This should be in a separate file.
532 // ELF is an ELF of course...
533 class ELFARMAsmBackend : public ARMAsmBackend {
536 ELFARMAsmBackend(const Target &T, const StringRef TT,
538 : ARMAsmBackend(T, TT), OSABI(_OSABI) { }
540 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
541 uint64_t Value) const;
543 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
544 return createARMELFObjectWriter(OS, OSABI);
548 // FIXME: Raise this to share code between Darwin and ELF.
549 void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
550 unsigned DataSize, uint64_t Value) const {
551 unsigned NumBytes = 4; // FIXME: 2 for Thumb
552 Value = adjustFixupValue(Fixup, Value);
553 if (!Value) return; // Doesn't change encoding.
555 unsigned Offset = Fixup.getOffset();
557 // For each byte of the fragment that the fixup touches, mask in the bits from
558 // the fixup value. The Value has been "split up" into the appropriate
560 for (unsigned i = 0; i != NumBytes; ++i)
561 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
564 // FIXME: This should be in a separate file.
565 class DarwinARMAsmBackend : public ARMAsmBackend {
567 const object::mach::CPUSubtypeARM Subtype;
568 DarwinARMAsmBackend(const Target &T, const StringRef TT,
569 object::mach::CPUSubtypeARM st)
570 : ARMAsmBackend(T, TT), Subtype(st) { }
572 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
573 return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
574 object::mach::CTM_ARM,
578 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
579 uint64_t Value) const;
581 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
586 /// getFixupKindNumBytes - The number of bytes the fixup may change.
587 static unsigned getFixupKindNumBytes(unsigned Kind) {
590 llvm_unreachable("Unknown fixup kind!");
593 case ARM::fixup_arm_thumb_bcc:
594 case ARM::fixup_arm_thumb_cp:
595 case ARM::fixup_thumb_adr_pcrel_10:
599 case ARM::fixup_arm_thumb_br:
600 case ARM::fixup_arm_thumb_cb:
603 case ARM::fixup_arm_pcrel_10_unscaled:
604 case ARM::fixup_arm_ldst_pcrel_12:
605 case ARM::fixup_arm_pcrel_10:
606 case ARM::fixup_arm_adr_pcrel_12:
607 case ARM::fixup_arm_uncondbl:
608 case ARM::fixup_arm_condbl:
609 case ARM::fixup_arm_blx:
610 case ARM::fixup_arm_condbranch:
611 case ARM::fixup_arm_uncondbranch:
615 case ARM::fixup_t2_ldst_pcrel_12:
616 case ARM::fixup_t2_condbranch:
617 case ARM::fixup_t2_uncondbranch:
618 case ARM::fixup_t2_pcrel_10:
619 case ARM::fixup_t2_adr_pcrel_12:
620 case ARM::fixup_arm_thumb_bl:
621 case ARM::fixup_arm_thumb_blx:
622 case ARM::fixup_arm_movt_hi16:
623 case ARM::fixup_arm_movw_lo16:
624 case ARM::fixup_arm_movt_hi16_pcrel:
625 case ARM::fixup_arm_movw_lo16_pcrel:
626 case ARM::fixup_t2_movt_hi16:
627 case ARM::fixup_t2_movw_lo16:
628 case ARM::fixup_t2_movt_hi16_pcrel:
629 case ARM::fixup_t2_movw_lo16_pcrel:
634 void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
635 unsigned DataSize, uint64_t Value) const {
636 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
637 Value = adjustFixupValue(Fixup, Value);
638 if (!Value) return; // Doesn't change encoding.
640 unsigned Offset = Fixup.getOffset();
641 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
643 // For each byte of the fragment that the fixup touches, mask in the
644 // bits from the fixup value.
645 for (unsigned i = 0; i != NumBytes; ++i)
646 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
649 } // end anonymous namespace
651 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
652 Triple TheTriple(TT);
654 if (TheTriple.isOSDarwin()) {
655 if (TheTriple.getArchName() == "armv4t" ||
656 TheTriple.getArchName() == "thumbv4t")
657 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T);
658 else if (TheTriple.getArchName() == "armv5e" ||
659 TheTriple.getArchName() == "thumbv5e")
660 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ);
661 else if (TheTriple.getArchName() == "armv6" ||
662 TheTriple.getArchName() == "thumbv6")
663 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6);
664 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7);
667 if (TheTriple.isOSWindows())
668 assert(0 && "Windows not supported on ARM");
670 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
671 return new ELFARMAsmBackend(T, TT, OSABI);