lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

   1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides ARM specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMMCTargetDesc.h"
  15 #include "ARMBaseInfo.h"
  16 #include "ARMELFStreamer.h"
  17 #include "ARMMCAsmInfo.h"
  18 #include "InstPrinter/ARMInstPrinter.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCInstrAnalysis.h"
  21 #include "llvm/MC/MCInstrInfo.h"
  22 #include "llvm/MC/MCRegisterInfo.h"
  23 #include "llvm/MC/MCStreamer.h"
  24 #include "llvm/MC/MCSubtargetInfo.h"
  25 #include "llvm/Support/ErrorHandling.h"
  26 #include "llvm/Support/TargetRegistry.h"
  27
  28 #define GET_REGINFO_MC_DESC
  29 #include "ARMGenRegisterInfo.inc"
  30
  31 #define GET_INSTRINFO_MC_DESC
  32 #include "ARMGenInstrInfo.inc"
  33
  34 #define GET_SUBTARGETINFO_MC_DESC
  35 #include "ARMGenSubtargetInfo.inc"
  36
  37 using namespace llvm;
  38
  39 std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
  40   // Set the boolean corresponding to the current target triple, or the default
  41   // if one cannot be determined, to true.
  42   unsigned Len = TT.size();
  43   unsigned Idx = 0;
  44
  45   // FIXME: Enhance Triple helper class to extract ARM version.
  46   bool isThumb = false;
  47   if (Len >= 5 && TT.substr(0, 4) == "armv")
  48     Idx = 4;
  49   else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
  50     isThumb = true;
  51     if (Len >= 7 && TT[5] == 'v')
  52       Idx = 6;
  53   }
  54
  55   bool NoCPU = CPU == "generic" || CPU.empty();
  56   std::string ARMArchFeature;
  57   if (Idx) {
  58     unsigned SubVer = TT[Idx];
  59     if (SubVer >= '7' && SubVer <= '9') {
  60       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
  61         if (NoCPU)
  62           // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
  63           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
  64         else
  65           // Use CPU to figure out the exact features.
  66           ARMArchFeature = "+v7";
  67       } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
  68         if (NoCPU)
  69           // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
  70           //       FeatureT2XtPk, FeatureMClass
  71           ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
  72         else
  73           // Use CPU to figure out the exact features.
  74           ARMArchFeature = "+v7";
  75       } else if (Len >= Idx+2 && TT[Idx+1] == 's') {
  76         if (NoCPU)
  77           // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
  78           //      Swift
  79           ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+t2xtpk";
  80         else
  81           // Use CPU to figure out the exact features.
  82           ARMArchFeature = "+v7";
  83       } else {
  84         // v7 CPUs have lots of different feature sets. If no CPU is specified,
  85         // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
  86         // the "minimum" feature set and use CPU string to figure out the exact
  87         // features.
  88         if (NoCPU)
  89           // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
  90           ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
  91         else
  92           // Use CPU to figure out the exact features.
  93           ARMArchFeature = "+v7";
  94       }
  95     } else if (SubVer == '6') {
  96       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
  97         ARMArchFeature = "+v6t2";
  98       else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
  99         if (NoCPU)
 100           // v6m: FeatureNoARM, FeatureMClass
 101           ARMArchFeature = "+v6,+noarm,+mclass";
 102         else
 103           ARMArchFeature = "+v6";
 104       } else
 105         ARMArchFeature = "+v6";
 106     } else if (SubVer == '5') {
 107       if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
 108         ARMArchFeature = "+v5te";
 109       else
 110         ARMArchFeature = "+v5t";
 111     } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
 112       ARMArchFeature = "+v4t";
 113   }
 114
 115   if (isThumb) {
 116     if (ARMArchFeature.empty())
 117       ARMArchFeature = "+thumb-mode";
 118     else
 119       ARMArchFeature += ",+thumb-mode";
 120   }
 121
 122   return ARMArchFeature;
 123 }
 124
 125 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
 126                                                   StringRef FS) {
 127   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
 128   if (!FS.empty()) {
 129     if (!ArchFS.empty())
 130       ArchFS = ArchFS + "," + FS.str();
 131     else
 132       ArchFS = FS;
 133   }
 134
 135   MCSubtargetInfo *X = new MCSubtargetInfo();
 136   InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
 137   return X;
 138 }
 139
 140 static MCInstrInfo *createARMMCInstrInfo() {
 141   MCInstrInfo *X = new MCInstrInfo();
 142   InitARMMCInstrInfo(X);
 143   return X;
 144 }
 145
 146 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
 147   MCRegisterInfo *X = new MCRegisterInfo();
 148   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
 149   return X;
 150 }
 151
 152 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
 153   Triple TheTriple(TT);
 154
 155   if (TheTriple.isOSDarwin())
 156     return new ARMMCAsmInfoDarwin();
 157
 158   return new ARMELFMCAsmInfo();
 159 }
 160
 161 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 162                                              CodeModel::Model CM,
 163                                              CodeGenOpt::Level OL) {
 164   MCCodeGenInfo *X = new MCCodeGenInfo();
 165   if (RM == Reloc::Default) {
 166     Triple TheTriple(TT);
 167     // Default relocation model on Darwin is PIC, not DynamicNoPIC.
 168     RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
 169   }
 170   X->InitMCCodeGenInfo(RM, CM, OL);
 171   return X;
 172 }
 173
 174 // This is duplicated code. Refactor this.
 175 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
 176                                     MCContext &Ctx, MCAsmBackend &MAB,
 177                                     raw_ostream &OS,
 178                                     MCCodeEmitter *Emitter,
 179                                     bool RelaxAll,
 180                                     bool NoExecStack) {
 181   Triple TheTriple(TT);
 182
 183   if (TheTriple.isOSDarwin())
 184     return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
 185
 186   if (TheTriple.isOSWindows()) {
 187     llvm_unreachable("ARM does not support Windows COFF format");
 188   }
 189
 190   return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
 191                               TheTriple.getArch() == Triple::thumb);
 192 }
 193
 194 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
 195                                              unsigned SyntaxVariant,
 196                                              const MCAsmInfo &MAI,
 197                                              const MCInstrInfo &MII,
 198                                              const MCRegisterInfo &MRI,
 199                                              const MCSubtargetInfo &STI) {
 200   if (SyntaxVariant == 0)
 201     return new ARMInstPrinter(MAI, MII, MRI, STI);
 202   return 0;
 203 }
 204
 205 namespace {
 206
 207 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 208 public:
 209   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 210
 211   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
 212     // BCCs with the "always" predicate are unconditional branches.
 213     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 214       return true;
 215     return MCInstrAnalysis::isUnconditionalBranch(Inst);
 216   }
 217
 218   virtual bool isConditionalBranch(const MCInst &Inst) const {
 219     // BCCs with the "always" predicate are unconditional branches.
 220     if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
 221       return false;
 222     return MCInstrAnalysis::isConditionalBranch(Inst);
 223   }
 224
 225   uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
 226                           uint64_t Size) const {
 227     // We only handle PCRel branches for now.
 228     if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
 229       return -1ULL;
 230
 231     int64_t Imm = Inst.getOperand(0).getImm();
 232     // FIXME: This is not right for thumb.
 233     return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
 234   }
 235 };
 236
 237 }
 238
 239 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
 240   return new ARMMCInstrAnalysis(Info);
 241 }
 242
 243 // Force static initialization.
 244 extern "C" void LLVMInitializeARMTargetMC() {
 245   // Register the MC asm info.
 246   RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
 247   RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
 248
 249   // Register the MC codegen info.
 250   TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
 251   TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
 252
 253   // Register the MC instruction info.
 254   TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
 255   TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
 256
 257   // Register the MC register info.
 258   TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
 259   TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
 260
 261   // Register the MC subtarget info.
 262   TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
 263                                           ARM_MC::createARMMCSubtargetInfo);
 264   TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
 265                                           ARM_MC::createARMMCSubtargetInfo);
 266
 267   // Register the MC instruction analyzer.
 268   TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
 269                                           createARMMCInstrAnalysis);
 270   TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
 271                                           createARMMCInstrAnalysis);
 272
 273   // Register the MC Code Emitter
 274   TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
 275   TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
 276
 277   // Register the asm backend.
 278   TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
 279   TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
 280
 281   // Register the object streamer.
 282   TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
 283   TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
 284
 285   // Register the MCInstPrinter.
 286   TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
 287   TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
 288 }