1 //===- ARMTargetStreamer.cpp - ARMTargetStreamer class --*- C++ -*---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMTargetStreamer class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "llvm/MC/ConstantPools.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/Support/ARMBuildAttributes.h"
20 #include "llvm/Support/TargetParser.h"
25 // ARMTargetStreamer Implemenation
28 ARMTargetStreamer::ARMTargetStreamer(MCStreamer &S)
29 : MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()) {}
31 ARMTargetStreamer::~ARMTargetStreamer() = default;
33 // The constant pool handling is shared by all ARMTargetStreamer
35 const MCExpr *ARMTargetStreamer::addConstantPoolEntry(const MCExpr *Expr, SMLoc Loc) {
36 return ConstantPools->addEntry(Streamer, Expr, 4, Loc);
39 void ARMTargetStreamer::emitCurrentConstantPool() {
40 ConstantPools->emitForCurrentSection(Streamer);
41 ConstantPools->clearCacheForCurrentSection(Streamer);
44 // finish() - write out any non-empty assembler constant pools.
45 void ARMTargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
47 // reset() - Reset any state
48 void ARMTargetStreamer::reset() {}
50 // The remaining callbacks should be handled separately by each
52 void ARMTargetStreamer::emitFnStart() {}
53 void ARMTargetStreamer::emitFnEnd() {}
54 void ARMTargetStreamer::emitCantUnwind() {}
55 void ARMTargetStreamer::emitPersonality(const MCSymbol *Personality) {}
56 void ARMTargetStreamer::emitPersonalityIndex(unsigned Index) {}
57 void ARMTargetStreamer::emitHandlerData() {}
58 void ARMTargetStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
60 void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {}
61 void ARMTargetStreamer::emitPad(int64_t Offset) {}
62 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
64 void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset,
65 const SmallVectorImpl<uint8_t> &Opcodes) {
67 void ARMTargetStreamer::switchVendor(StringRef Vendor) {}
68 void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
69 void ARMTargetStreamer::emitTextAttribute(unsigned Attribute,
71 void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute,
73 StringRef StringValue) {}
74 void ARMTargetStreamer::emitArch(unsigned Arch) {}
75 void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {}
76 void ARMTargetStreamer::emitObjectArch(unsigned Arch) {}
77 void ARMTargetStreamer::emitFPU(unsigned FPU) {}
78 void ARMTargetStreamer::finishAttributeSection() {}
79 void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {}
81 ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
82 void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
84 static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
85 if (STI.getCPU() == "xscale")
86 return ARMBuildAttrs::v5TEJ;
88 if (STI.hasFeature(ARM::HasV8Ops)) {
89 if (STI.hasFeature(ARM::FeatureRClass))
90 return ARMBuildAttrs::v8_R;
91 return ARMBuildAttrs::v8_A;
92 } else if (STI.hasFeature(ARM::HasV8MMainlineOps))
93 return ARMBuildAttrs::v8_M_Main;
94 else if (STI.hasFeature(ARM::HasV7Ops)) {
95 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
96 return ARMBuildAttrs::v7E_M;
97 return ARMBuildAttrs::v7;
98 } else if (STI.hasFeature(ARM::HasV6T2Ops))
99 return ARMBuildAttrs::v6T2;
100 else if (STI.hasFeature(ARM::HasV8MBaselineOps))
101 return ARMBuildAttrs::v8_M_Base;
102 else if (STI.hasFeature(ARM::HasV6MOps))
103 return ARMBuildAttrs::v6S_M;
104 else if (STI.hasFeature(ARM::HasV6Ops))
105 return ARMBuildAttrs::v6;
106 else if (STI.hasFeature(ARM::HasV5TEOps))
107 return ARMBuildAttrs::v5TE;
108 else if (STI.hasFeature(ARM::HasV5TOps))
109 return ARMBuildAttrs::v5T;
110 else if (STI.hasFeature(ARM::HasV4TOps))
111 return ARMBuildAttrs::v4T;
113 return ARMBuildAttrs::v4;
116 static bool isV8M(const MCSubtargetInfo &STI) {
117 // Note that v8M Baseline is a subset of v6T2!
118 return (STI.hasFeature(ARM::HasV8MBaselineOps) &&
119 !STI.hasFeature(ARM::HasV6T2Ops)) ||
120 STI.hasFeature(ARM::HasV8MMainlineOps);
123 /// Emit the build attributes that only depend on the hardware that we expect
124 // /to be available, and not on the ABI, or any source-language choices.
125 void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
126 switchVendor("aeabi");
128 const StringRef CPUString = STI.getCPU();
129 if (!CPUString.empty() && !CPUString.startswith("generic")) {
130 // FIXME: remove krait check when GNU tools support krait cpu
131 if (STI.hasFeature(ARM::ProcKrait)) {
132 emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
133 // We consider krait as a "cortex-a9" + hwdiv CPU
134 // Enable hwdiv through ".arch_extension idiv"
135 if (STI.hasFeature(ARM::FeatureHWDivThumb) ||
136 STI.hasFeature(ARM::FeatureHWDivARM))
137 emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM);
139 emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
143 emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(STI));
145 if (STI.hasFeature(ARM::FeatureAClass)) {
146 emitAttribute(ARMBuildAttrs::CPU_arch_profile,
147 ARMBuildAttrs::ApplicationProfile);
148 } else if (STI.hasFeature(ARM::FeatureRClass)) {
149 emitAttribute(ARMBuildAttrs::CPU_arch_profile,
150 ARMBuildAttrs::RealTimeProfile);
151 } else if (STI.hasFeature(ARM::FeatureMClass)) {
152 emitAttribute(ARMBuildAttrs::CPU_arch_profile,
153 ARMBuildAttrs::MicroControllerProfile);
156 emitAttribute(ARMBuildAttrs::ARM_ISA_use, STI.hasFeature(ARM::FeatureNoARM)
157 ? ARMBuildAttrs::Not_Allowed
158 : ARMBuildAttrs::Allowed);
161 emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
162 ARMBuildAttrs::AllowThumbDerived);
163 } else if (STI.hasFeature(ARM::FeatureThumb2)) {
164 emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
165 ARMBuildAttrs::AllowThumb32);
166 } else if (STI.hasFeature(ARM::HasV4TOps)) {
167 emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
170 if (STI.hasFeature(ARM::FeatureNEON)) {
171 /* NEON is not exactly a VFP architecture, but GAS emit one of
172 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
173 if (STI.hasFeature(ARM::FeatureFPARMv8)) {
174 if (STI.hasFeature(ARM::FeatureCrypto))
175 emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
177 emitFPU(ARM::FK_NEON_FP_ARMV8);
178 } else if (STI.hasFeature(ARM::FeatureVFP4))
179 emitFPU(ARM::FK_NEON_VFPV4);
181 emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16
183 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
184 if (STI.hasFeature(ARM::HasV8Ops))
185 emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
186 STI.hasFeature(ARM::HasV8_1aOps)
187 ? ARMBuildAttrs::AllowNeonARMv8_1a
188 : ARMBuildAttrs::AllowNeonARMv8);
190 if (STI.hasFeature(ARM::FeatureFPARMv8))
191 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
192 // FPU, but there are two different names for it depending on the CPU.
193 emitFPU(STI.hasFeature(ARM::FeatureD16)
194 ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV5_SP_D16
197 else if (STI.hasFeature(ARM::FeatureVFP4))
198 emitFPU(STI.hasFeature(ARM::FeatureD16)
199 ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV4_SP_D16
202 else if (STI.hasFeature(ARM::FeatureVFP3))
204 STI.hasFeature(ARM::FeatureD16)
206 ? (STI.hasFeature(ARM::FeatureVFPOnlySP)
207 ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
209 : (STI.hasFeature(ARM::FeatureFP16)
210 ? ARM::FK_VFPV3_D16_FP16
211 : ARM::FK_VFPV3_D16))
213 : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16
215 else if (STI.hasFeature(ARM::FeatureVFP2))
216 emitFPU(ARM::FK_VFPV2);
219 // ABI_HardFP_use attribute to indicate single precision FP.
220 if (STI.hasFeature(ARM::FeatureVFPOnlySP))
221 emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
222 ARMBuildAttrs::HardFPSinglePrecision);
224 if (STI.hasFeature(ARM::FeatureFP16))
225 emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
227 if (STI.hasFeature(ARM::FeatureMP))
228 emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
230 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
231 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
232 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
233 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
234 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
235 // otherwise, the default value (AllowDIVIfExists) applies.
236 if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops))
237 emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
239 if (STI.hasFeature(ARM::FeatureDSP) && isV8M(STI))
240 emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
242 if (STI.hasFeature(ARM::FeatureStrictAlign))
243 emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
244 ARMBuildAttrs::Not_Allowed);
246 emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
247 ARMBuildAttrs::Allowed);
249 if (STI.hasFeature(ARM::FeatureTrustZone) &&
250 STI.hasFeature(ARM::FeatureVirtualization))
251 emitAttribute(ARMBuildAttrs::Virtualization_use,
252 ARMBuildAttrs::AllowTZVirtualization);
253 else if (STI.hasFeature(ARM::FeatureTrustZone))
254 emitAttribute(ARMBuildAttrs::Virtualization_use, ARMBuildAttrs::AllowTZ);
255 else if (STI.hasFeature(ARM::FeatureVirtualization))
256 emitAttribute(ARMBuildAttrs::Virtualization_use,
257 ARMBuildAttrs::AllowVirtualization);