1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 #define DEBUG_TYPE "hexagon-instrinfo"
34 #define GET_INSTRINFO_CTOR_DTOR
35 #define GET_INSTRMAP_INFO
36 #include "HexagonGenInstrInfo.inc"
37 #include "HexagonGenDFAPacketizer.inc"
40 /// Constants for Hexagon instructions.
42 const int Hexagon_MEMW_OFFSET_MAX = 4095;
43 const int Hexagon_MEMW_OFFSET_MIN = -4096;
44 const int Hexagon_MEMD_OFFSET_MAX = 8191;
45 const int Hexagon_MEMD_OFFSET_MIN = -8192;
46 const int Hexagon_MEMH_OFFSET_MAX = 2047;
47 const int Hexagon_MEMH_OFFSET_MIN = -2048;
48 const int Hexagon_MEMB_OFFSET_MAX = 1023;
49 const int Hexagon_MEMB_OFFSET_MIN = -1024;
50 const int Hexagon_ADDI_OFFSET_MAX = 32767;
51 const int Hexagon_ADDI_OFFSET_MIN = -32768;
52 const int Hexagon_MEMD_AUTOINC_MAX = 56;
53 const int Hexagon_MEMD_AUTOINC_MIN = -64;
54 const int Hexagon_MEMW_AUTOINC_MAX = 28;
55 const int Hexagon_MEMW_AUTOINC_MIN = -32;
56 const int Hexagon_MEMH_AUTOINC_MAX = 14;
57 const int Hexagon_MEMH_AUTOINC_MIN = -16;
58 const int Hexagon_MEMB_AUTOINC_MAX = 7;
59 const int Hexagon_MEMB_AUTOINC_MIN = -8;
61 // Pin the vtable to this file.
62 void HexagonInstrInfo::anchor() {}
64 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
65 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
66 RI(), Subtarget(ST) {}
68 /// isLoadFromStackSlot - If the specified machine instruction is a direct
69 /// load from a stack slot, return the virtual or physical register number of
70 /// the destination along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than loading from the stack slot.
73 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
74 int &FrameIndex) const {
77 switch (MI->getOpcode()) {
79 case Hexagon::L2_loadri_io:
80 case Hexagon::L2_loadrd_io:
81 case Hexagon::L2_loadrh_io:
82 case Hexagon::L2_loadrb_io:
83 case Hexagon::L2_loadrub_io:
84 if (MI->getOperand(2).isFI() &&
85 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
86 FrameIndex = MI->getOperand(2).getIndex();
87 return MI->getOperand(0).getReg();
95 /// isStoreToStackSlot - If the specified machine instruction is a direct
96 /// store to a stack slot, return the virtual or physical register number of
97 /// the source reg along with the FrameIndex of the loaded stack slot. If
98 /// not, return 0. This predicate must return 0 if the instruction has
99 /// any side effects other than storing to the stack slot.
100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
104 case Hexagon::S2_storeri_io:
105 case Hexagon::S2_storerd_io:
106 case Hexagon::S2_storerh_io:
107 case Hexagon::S2_storerb_io:
108 if (MI->getOperand(2).isFI() &&
109 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
110 FrameIndex = MI->getOperand(0).getIndex();
111 return MI->getOperand(2).getReg();
120 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
121 MachineBasicBlock *FBB,
122 const SmallVectorImpl<MachineOperand> &Cond,
125 int BOpc = Hexagon::J2_jump;
126 int BccOpc = Hexagon::J2_jumpt;
128 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
131 // Check if ReverseBranchCondition has asked to reverse this branch
132 // If we want to reverse the branch an odd number of times, we want
134 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
135 BccOpc = Hexagon::J2_jumpf;
141 // Due to a bug in TailMerging/CFG Optimization, we need to add a
142 // special case handling of a predicated jump followed by an
143 // unconditional jump. If not, Tail Merging and CFG Optimization go
144 // into an infinite loop.
145 MachineBasicBlock *NewTBB, *NewFBB;
146 SmallVector<MachineOperand, 4> Cond;
147 MachineInstr *Term = MBB.getFirstTerminator();
148 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
150 MachineBasicBlock *NextBB =
151 std::next(MachineFunction::iterator(&MBB));
152 if (NewTBB == NextBB) {
153 ReverseBranchCondition(Cond);
155 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
158 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
160 // If Cond[0] is a basic block, insert ENDLOOP0.
162 BuildMI(&MBB, DL, get(Hexagon::ENDLOOP0)).addMBB(Cond[0].getMBB());
165 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
170 // We don't handle ENDLOOP0 with a conditional branch in AnalyzeBranch.
171 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
172 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
177 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
178 MachineBasicBlock *&TBB,
179 MachineBasicBlock *&FBB,
180 SmallVectorImpl<MachineOperand> &Cond,
181 bool AllowModify) const {
185 // If the block has no terminators, it just falls into the block after it.
186 MachineBasicBlock::instr_iterator I = MBB.instr_end();
187 if (I == MBB.instr_begin())
190 // A basic block may looks like this:
200 // It has two succs but does not have a terminator
201 // Don't know how to handle it.
206 } while (I != MBB.instr_begin());
211 while (I->isDebugValue()) {
212 if (I == MBB.instr_begin())
217 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
218 I->getOperand(0).isMBB();
219 // Delete the JMP if it's equivalent to a fall-through.
220 if (AllowModify && JumpToBlock &&
221 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
222 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
223 I->eraseFromParent();
225 if (I == MBB.instr_begin())
229 if (!isUnpredicatedTerminator(I))
232 // Get the last instruction in the block.
233 MachineInstr *LastInst = I;
234 MachineInstr *SecondLastInst = nullptr;
235 // Find one more terminator if present.
237 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
241 // This is a third branch.
244 if (I == MBB.instr_begin())
249 int LastOpcode = LastInst->getOpcode();
250 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
251 // If the branch target is not a basic block, it could be a tail call.
252 // (It is, if the target is a function.)
253 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
255 if (SecLastOpcode == Hexagon::J2_jump &&
256 !SecondLastInst->getOperand(0).isMBB())
259 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
260 bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
262 // If there is only one terminator instruction, process it.
263 if (LastInst && !SecondLastInst) {
264 if (LastOpcode == Hexagon::J2_jump) {
265 TBB = LastInst->getOperand(0).getMBB();
268 if (LastOpcode == Hexagon::ENDLOOP0) {
269 TBB = LastInst->getOperand(0).getMBB();
270 Cond.push_back(LastInst->getOperand(0));
273 if (LastOpcodeHasJMP_c) {
274 TBB = LastInst->getOperand(1).getMBB();
275 if (LastOpcodeHasNot) {
276 Cond.push_back(MachineOperand::CreateImm(0));
278 Cond.push_back(LastInst->getOperand(0));
281 // Otherwise, don't know what this is.
285 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
286 bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
287 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
288 TBB = SecondLastInst->getOperand(1).getMBB();
289 if (SecLastOpcodeHasNot)
290 Cond.push_back(MachineOperand::CreateImm(0));
291 Cond.push_back(SecondLastInst->getOperand(0));
292 FBB = LastInst->getOperand(0).getMBB();
296 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
297 // executed, so remove it.
298 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
299 TBB = SecondLastInst->getOperand(0).getMBB();
302 I->eraseFromParent();
306 // If the block ends with an ENDLOOP, and JMP, handle it.
307 if (SecLastOpcode == Hexagon::ENDLOOP0 &&
308 LastOpcode == Hexagon::J2_jump) {
309 TBB = SecondLastInst->getOperand(0).getMBB();
310 Cond.push_back(SecondLastInst->getOperand(0));
311 FBB = LastInst->getOperand(0).getMBB();
315 // Otherwise, can't handle this.
320 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321 MachineBasicBlock::iterator I = MBB.end();
322 if (I == MBB.begin()) return 0;
324 unsigned Opc1 = I->getOpcode();
326 case Hexagon::J2_jump:
327 case Hexagon::J2_jumpt:
328 case Hexagon::J2_jumpf:
329 case Hexagon::ENDLOOP0:
330 I->eraseFromParent();
338 if (I == MBB.begin()) return 1;
340 unsigned Opc2 = I->getOpcode();
342 case Hexagon::J2_jumpt:
343 case Hexagon::J2_jumpf:
344 case Hexagon::ENDLOOP0:
345 I->eraseFromParent();
353 /// \brief For a comparison instruction, return the source registers in
354 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
355 /// compares against in CmpValue. Return true if the comparison instruction
357 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
358 unsigned &SrcReg, unsigned &SrcReg2,
359 int &Mask, int &Value) const {
360 unsigned Opc = MI->getOpcode();
362 // Set mask and the first source register.
364 case Hexagon::C2_cmpeqp:
365 case Hexagon::C2_cmpeqi:
366 case Hexagon::C2_cmpeq:
367 case Hexagon::C2_cmpgtp:
368 case Hexagon::C2_cmpgtup:
369 case Hexagon::C2_cmpgtui:
370 case Hexagon::C2_cmpgtu:
371 case Hexagon::C2_cmpgti:
372 case Hexagon::C2_cmpgt:
373 SrcReg = MI->getOperand(1).getReg();
376 case Hexagon::A4_cmpbeqi:
377 case Hexagon::A4_cmpbeq:
378 case Hexagon::A4_cmpbgtui:
379 case Hexagon::A4_cmpbgtu:
380 case Hexagon::A4_cmpbgt:
381 SrcReg = MI->getOperand(1).getReg();
384 case Hexagon::A4_cmpheqi:
385 case Hexagon::A4_cmpheq:
386 case Hexagon::A4_cmphgtui:
387 case Hexagon::A4_cmphgtu:
388 case Hexagon::A4_cmphgt:
389 SrcReg = MI->getOperand(1).getReg();
394 // Set the value/second source register.
396 case Hexagon::C2_cmpeqp:
397 case Hexagon::C2_cmpeq:
398 case Hexagon::C2_cmpgtp:
399 case Hexagon::C2_cmpgtup:
400 case Hexagon::C2_cmpgtu:
401 case Hexagon::C2_cmpgt:
402 case Hexagon::A4_cmpbeq:
403 case Hexagon::A4_cmpbgtu:
404 case Hexagon::A4_cmpbgt:
405 case Hexagon::A4_cmpheq:
406 case Hexagon::A4_cmphgtu:
407 case Hexagon::A4_cmphgt:
408 SrcReg2 = MI->getOperand(2).getReg();
411 case Hexagon::C2_cmpeqi:
412 case Hexagon::C2_cmpgtui:
413 case Hexagon::C2_cmpgti:
414 case Hexagon::A4_cmpbeqi:
415 case Hexagon::A4_cmpbgtui:
416 case Hexagon::A4_cmpheqi:
417 case Hexagon::A4_cmphgtui:
419 Value = MI->getOperand(2).getImm();
427 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator I, DebugLoc DL,
429 unsigned DestReg, unsigned SrcReg,
430 bool KillSrc) const {
431 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
432 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
435 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
436 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
439 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
440 // Map Pd = Ps to Pd = or(Ps, Ps).
441 BuildMI(MBB, I, DL, get(Hexagon::C2_or),
442 DestReg).addReg(SrcReg).addReg(SrcReg);
445 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
446 Hexagon::IntRegsRegClass.contains(SrcReg)) {
447 // We can have an overlap between single and double reg: r1:0 = r0.
448 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
450 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
451 Hexagon::subreg_hireg))).addImm(0);
453 // r1:0 = r1 or no overlap.
454 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
455 Hexagon::subreg_loreg))).addReg(SrcReg);
456 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
457 Hexagon::subreg_hireg))).addImm(0);
461 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
462 Hexagon::IntRegsRegClass.contains(SrcReg)) {
463 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
466 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
467 Hexagon::IntRegsRegClass.contains(DestReg)) {
468 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
469 addReg(SrcReg, getKillRegState(KillSrc));
472 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
473 Hexagon::PredRegsRegClass.contains(DestReg)) {
474 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
475 addReg(SrcReg, getKillRegState(KillSrc));
479 llvm_unreachable("Unimplemented");
483 void HexagonInstrInfo::
484 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
485 unsigned SrcReg, bool isKill, int FI,
486 const TargetRegisterClass *RC,
487 const TargetRegisterInfo *TRI) const {
489 DebugLoc DL = MBB.findDebugLoc(I);
490 MachineFunction &MF = *MBB.getParent();
491 MachineFrameInfo &MFI = *MF.getFrameInfo();
492 unsigned Align = MFI.getObjectAlignment(FI);
494 MachineMemOperand *MMO =
495 MF.getMachineMemOperand(
496 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
497 MachineMemOperand::MOStore,
498 MFI.getObjectSize(FI),
501 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
502 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
503 .addFrameIndex(FI).addImm(0)
504 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
505 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
506 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
507 .addFrameIndex(FI).addImm(0)
508 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
509 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
510 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
511 .addFrameIndex(FI).addImm(0)
512 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
514 llvm_unreachable("Unimplemented");
519 void HexagonInstrInfo::storeRegToAddr(
520 MachineFunction &MF, unsigned SrcReg,
522 SmallVectorImpl<MachineOperand> &Addr,
523 const TargetRegisterClass *RC,
524 SmallVectorImpl<MachineInstr*> &NewMIs) const
526 llvm_unreachable("Unimplemented");
530 void HexagonInstrInfo::
531 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
532 unsigned DestReg, int FI,
533 const TargetRegisterClass *RC,
534 const TargetRegisterInfo *TRI) const {
535 DebugLoc DL = MBB.findDebugLoc(I);
536 MachineFunction &MF = *MBB.getParent();
537 MachineFrameInfo &MFI = *MF.getFrameInfo();
538 unsigned Align = MFI.getObjectAlignment(FI);
540 MachineMemOperand *MMO =
541 MF.getMachineMemOperand(
542 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
543 MachineMemOperand::MOLoad,
544 MFI.getObjectSize(FI),
546 if (RC == &Hexagon::IntRegsRegClass) {
547 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
548 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
549 } else if (RC == &Hexagon::DoubleRegsRegClass) {
550 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
551 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
552 } else if (RC == &Hexagon::PredRegsRegClass) {
553 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
554 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
556 llvm_unreachable("Can't store this register to stack slot");
561 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
562 SmallVectorImpl<MachineOperand> &Addr,
563 const TargetRegisterClass *RC,
564 SmallVectorImpl<MachineInstr*> &NewMIs) const {
565 llvm_unreachable("Unimplemented");
568 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
569 const HexagonRegisterInfo &TRI = getRegisterInfo();
570 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
571 MachineBasicBlock &MBB = *MI->getParent();
572 DebugLoc DL = MI->getDebugLoc();
573 unsigned Opc = MI->getOpcode();
576 case Hexagon::TFR_PdTrue: {
577 unsigned Reg = MI->getOperand(0).getReg();
578 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
579 .addReg(Reg, RegState::Undef)
580 .addReg(Reg, RegState::Undef);
584 case Hexagon::TFR_PdFalse: {
585 unsigned Reg = MI->getOperand(0).getReg();
586 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
587 .addReg(Reg, RegState::Undef)
588 .addReg(Reg, RegState::Undef);
592 case Hexagon::VMULW: {
593 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
594 unsigned DstReg = MI->getOperand(0).getReg();
595 unsigned Src1Reg = MI->getOperand(1).getReg();
596 unsigned Src2Reg = MI->getOperand(2).getReg();
597 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
598 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
599 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
600 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
601 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
602 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
604 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
605 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
608 MRI.clearKillFlags(Src1SubHi);
609 MRI.clearKillFlags(Src1SubLo);
610 MRI.clearKillFlags(Src2SubHi);
611 MRI.clearKillFlags(Src2SubLo);
614 case Hexagon::VMULW_ACC: {
615 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
616 unsigned DstReg = MI->getOperand(0).getReg();
617 unsigned Src1Reg = MI->getOperand(1).getReg();
618 unsigned Src2Reg = MI->getOperand(2).getReg();
619 unsigned Src3Reg = MI->getOperand(3).getReg();
620 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
621 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
622 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
623 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
624 unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
625 unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
626 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
627 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
628 .addReg(Src2SubHi).addReg(Src3SubHi);
629 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
630 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
631 .addReg(Src2SubLo).addReg(Src3SubLo);
633 MRI.clearKillFlags(Src1SubHi);
634 MRI.clearKillFlags(Src1SubLo);
635 MRI.clearKillFlags(Src2SubHi);
636 MRI.clearKillFlags(Src2SubLo);
637 MRI.clearKillFlags(Src3SubHi);
638 MRI.clearKillFlags(Src3SubLo);
641 case Hexagon::TCRETURNi:
642 MI->setDesc(get(Hexagon::J2_jump));
644 case Hexagon::TCRETURNr:
645 MI->setDesc(get(Hexagon::J2_jumpr));
652 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
654 ArrayRef<unsigned> Ops,
656 // Hexagon_TODO: Implement.
660 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
662 MachineRegisterInfo &RegInfo = MF->getRegInfo();
663 const TargetRegisterClass *TRC;
665 TRC = &Hexagon::PredRegsRegClass;
666 } else if (VT == MVT::i32 || VT == MVT::f32) {
667 TRC = &Hexagon::IntRegsRegClass;
668 } else if (VT == MVT::i64 || VT == MVT::f64) {
669 TRC = &Hexagon::DoubleRegsRegClass;
671 llvm_unreachable("Cannot handle this register class");
674 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
678 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
679 const MCInstrDesc &MID = MI->getDesc();
680 const uint64_t F = MID.TSFlags;
681 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
684 // TODO: This is largely obsolete now. Will need to be removed
685 // in consecutive patches.
686 switch(MI->getOpcode()) {
687 // TFR_FI Remains a special case.
688 case Hexagon::TFR_FI:
696 // This returns true in two cases:
697 // - The OP code itself indicates that this is an extended instruction.
698 // - One of MOs has been marked with HMOTF_ConstExtended flag.
699 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
700 // First check if this is permanently extended op code.
701 const uint64_t F = MI->getDesc().TSFlags;
702 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
704 // Use MO operand flags to determine if one of MI's operands
705 // has HMOTF_ConstExtended flag set.
706 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
707 E = MI->operands_end(); I != E; ++I) {
708 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
714 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
715 return MI->getDesc().isBranch();
718 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
719 if (isNewValueJump(MI))
722 if (isNewValueStore(MI))
728 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
729 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
732 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
733 bool isPred = MI->getDesc().isPredicable();
738 const int Opc = MI->getOpcode();
741 case Hexagon::A2_tfrsi:
742 return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
744 case Hexagon::S2_storerd_io:
745 return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
747 case Hexagon::S2_storeri_io:
748 case Hexagon::S2_storerinew_io:
749 return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
751 case Hexagon::S2_storerh_io:
752 case Hexagon::S2_storerhnew_io:
753 return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
755 case Hexagon::S2_storerb_io:
756 case Hexagon::S2_storerbnew_io:
757 return isUInt<6>(MI->getOperand(1).getImm());
759 case Hexagon::L2_loadrd_io:
760 return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
762 case Hexagon::L2_loadri_io:
763 return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
765 case Hexagon::L2_loadrh_io:
766 case Hexagon::L2_loadruh_io:
767 return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
769 case Hexagon::L2_loadrb_io:
770 case Hexagon::L2_loadrub_io:
771 return isUInt<6>(MI->getOperand(2).getImm());
773 case Hexagon::L2_loadrd_pi:
774 return isShiftedInt<4,3>(MI->getOperand(3).getImm());
776 case Hexagon::L2_loadri_pi:
777 return isShiftedInt<4,2>(MI->getOperand(3).getImm());
779 case Hexagon::L2_loadrh_pi:
780 case Hexagon::L2_loadruh_pi:
781 return isShiftedInt<4,1>(MI->getOperand(3).getImm());
783 case Hexagon::L2_loadrb_pi:
784 case Hexagon::L2_loadrub_pi:
785 return isInt<4>(MI->getOperand(3).getImm());
787 case Hexagon::S4_storeirb_io:
788 case Hexagon::S4_storeirh_io:
789 case Hexagon::S4_storeiri_io:
790 return (isUInt<6>(MI->getOperand(1).getImm()) &&
791 isInt<6>(MI->getOperand(2).getImm()));
793 case Hexagon::A2_addi:
794 return isInt<8>(MI->getOperand(2).getImm());
796 case Hexagon::A2_aslh:
797 case Hexagon::A2_asrh:
798 case Hexagon::A2_sxtb:
799 case Hexagon::A2_sxth:
800 case Hexagon::A2_zxtb:
801 case Hexagon::A2_zxth:
808 // This function performs the following inversiones:
813 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
815 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
816 : Hexagon::getTruePredOpcode(Opc);
817 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
818 return InvPredOpcode;
821 default: llvm_unreachable("Unexpected predicated instruction");
822 case Hexagon::C2_ccombinewt:
823 return Hexagon::C2_ccombinewf;
824 case Hexagon::C2_ccombinewf:
825 return Hexagon::C2_ccombinewt;
828 case Hexagon::L4_return_t:
829 return Hexagon::L4_return_f;
830 case Hexagon::L4_return_f:
831 return Hexagon::L4_return_t;
835 // New Value Store instructions.
836 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
837 const uint64_t F = MI->getDesc().TSFlags;
839 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
842 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
843 const uint64_t F = get(Opcode).TSFlags;
845 return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
848 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
849 enum Hexagon::PredSense inPredSense;
850 inPredSense = invertPredicate ? Hexagon::PredSense_false :
851 Hexagon::PredSense_true;
852 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
853 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
856 // This switch case will be removed once all the instructions have been
857 // modified to use relation maps.
859 case Hexagon::TFRI_f:
860 return !invertPredicate ? Hexagon::TFRI_cPt_f :
861 Hexagon::TFRI_cNotPt_f;
862 case Hexagon::A2_combinew:
863 return !invertPredicate ? Hexagon::C2_ccombinewt :
864 Hexagon::C2_ccombinewf;
867 case Hexagon::L4_return:
868 return !invertPredicate ? Hexagon::L4_return_t:
869 Hexagon::L4_return_f;
871 llvm_unreachable("Unexpected predicable instruction");
875 bool HexagonInstrInfo::
876 PredicateInstruction(MachineInstr *MI,
877 const SmallVectorImpl<MachineOperand> &Cond) const {
878 int Opc = MI->getOpcode();
879 assert (isPredicable(MI) && "Expected predicable instruction");
880 bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
881 (Cond[0].getImm() == 0));
883 // This will change MI's opcode to its predicate version.
884 // However, its operand list is still the old one, i.e. the
885 // non-predicate one.
886 MI->setDesc(get(getCondOpcode(Opc, invertJump)));
889 unsigned int GAIdx = 0;
891 // Indicates whether the current MI has a GlobalAddress operand
892 bool hasGAOpnd = false;
893 std::vector<MachineOperand> tmpOpnds;
895 // Indicates whether we need to shift operands to right.
896 bool needShift = true;
898 // The predicate is ALWAYS the FIRST input operand !!!
899 if (MI->getNumOperands() == 0) {
900 // The non-predicate version of MI does not take any operands,
901 // i.e. no outs and no ins. In this condition, the predicate
902 // operand will be directly placed at Operands[0]. No operand
908 else if ( MI->getOperand(MI->getNumOperands()-1).isReg()
909 && MI->getOperand(MI->getNumOperands()-1).isDef()
910 && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
911 // The non-predicate version of MI does not have any input operands.
912 // In this condition, we extend the length of Operands[] by one and
913 // copy the original last operand to the newly allocated slot.
914 // At this moment, it is just a place holder. Later, we will put
915 // predicate operand directly into it. No operand shift is needed.
916 // Example: r0=BARRIER (this is a faked insn used here for illustration)
917 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
919 oper = MI->getNumOperands() - 2;
922 // We need to right shift all input operands by one. Duplicate the
923 // last operand into the newly allocated slot.
924 MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
929 // Operands[ MI->getNumOperands() - 2 ] has been copied into
930 // Operands[ MI->getNumOperands() - 1 ], so we start from
931 // Operands[ MI->getNumOperands() - 3 ].
932 // oper is a signed int.
933 // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
934 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
936 MachineOperand &MO = MI->getOperand(oper);
938 // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4] Opnd[5] Opnd[6] Opnd[7]
939 // <Def0> <Def1> <Use0> <Use1> <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
943 // Predicate Operand here
944 if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
948 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
949 MO.isImplicit(), MO.isKill(),
950 MO.isDead(), MO.isUndef(),
953 else if (MO.isImm()) {
954 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
956 else if (MO.isGlobal()) {
957 // MI can not have more than one GlobalAddress operand.
958 assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
960 // There is no member function called "ChangeToGlobalAddress" in the
961 // MachineOperand class (not like "ChangeToRegister" and
962 // "ChangeToImmediate"). So we have to remove them from Operands[] list
963 // first, and then add them back after we have inserted the predicate
964 // operand. tmpOpnds[] is to remember these operands before we remove
966 tmpOpnds.push_back(MO);
968 // Operands[oper] is a GlobalAddress operand;
969 // Operands[oper+1] has been copied into Operands[oper+2];
975 llvm_unreachable("Unexpected operand type");
980 int regPos = invertJump ? 1 : 0;
981 MachineOperand PredMO = Cond[regPos];
983 // [oper] now points to the last explicit Def. Predicate operand must be
984 // located at [oper+1]. See diagram above.
985 // This assumes that the predicate is always the first operand,
986 // i.e. Operands[0+numResults], in the set of inputs
987 // It is better to have an assert here to check this. But I don't know how
988 // to write this assert because findFirstPredOperandIdx() would return -1
989 if (oper < -1) oper = -1;
991 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
992 PredMO.isImplicit(), false,
993 PredMO.isDead(), PredMO.isUndef(),
996 MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
997 RegInfo.clearKillFlags(PredMO.getReg());
1003 // Operands[GAIdx] is the original GlobalAddress operand, which is
1004 // already copied into tmpOpnds[0].
1005 // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
1006 // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
1007 // so we start from [GAIdx+2]
1008 for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
1009 tmpOpnds.push_back(MI->getOperand(i));
1011 // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
1012 // It is very important that we always remove from the end of Operands[]
1013 // MI->getNumOperands() is at least 2 if program goes to here.
1014 for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
1015 MI->RemoveOperand(i);
1017 for (i = 0; i < tmpOpnds.size(); ++i)
1018 MI->addOperand(tmpOpnds[i]);
1027 isProfitableToIfCvt(MachineBasicBlock &MBB,
1029 unsigned ExtraPredCycles,
1030 const BranchProbability &Probability) const {
1037 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1038 unsigned NumTCycles,
1039 unsigned ExtraTCycles,
1040 MachineBasicBlock &FMBB,
1041 unsigned NumFCycles,
1042 unsigned ExtraFCycles,
1043 const BranchProbability &Probability) const {
1047 // Returns true if an instruction is predicated irrespective of the predicate
1048 // sense. For example, all of the following will return true.
1049 // if (p0) R1 = add(R2, R3)
1050 // if (!p0) R1 = add(R2, R3)
1051 // if (p0.new) R1 = add(R2, R3)
1052 // if (!p0.new) R1 = add(R2, R3)
1053 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1054 const uint64_t F = MI->getDesc().TSFlags;
1056 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1059 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
1060 const uint64_t F = get(Opcode).TSFlags;
1062 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1065 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
1066 const uint64_t F = MI->getDesc().TSFlags;
1068 assert(isPredicated(MI));
1069 return (!((F >> HexagonII::PredicatedFalsePos) &
1070 HexagonII::PredicatedFalseMask));
1073 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
1074 const uint64_t F = get(Opcode).TSFlags;
1076 // Make sure that the instruction is predicated.
1077 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1078 return (!((F >> HexagonII::PredicatedFalsePos) &
1079 HexagonII::PredicatedFalseMask));
1082 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1083 const uint64_t F = MI->getDesc().TSFlags;
1085 assert(isPredicated(MI));
1086 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1089 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
1090 const uint64_t F = get(Opcode).TSFlags;
1092 assert(isPredicated(Opcode));
1093 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1096 // Returns true, if a ST insn can be promoted to a new-value store.
1097 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
1098 const uint64_t F = MI->getDesc().TSFlags;
1100 return ((F >> HexagonII::mayNVStorePos) &
1101 HexagonII::mayNVStoreMask);
1105 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1106 std::vector<MachineOperand> &Pred) const {
1107 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1108 MachineOperand MO = MI->getOperand(oper);
1109 if (MO.isReg() && MO.isDef()) {
1110 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1111 if (RC == &Hexagon::PredRegsRegClass) {
1123 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1124 const SmallVectorImpl<MachineOperand> &Pred2) const {
1131 // We indicate that we want to reverse the branch by
1132 // inserting a 0 at the beginning of the Cond vector.
1134 bool HexagonInstrInfo::
1135 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1136 if (!Cond.empty() && Cond[0].isMBB())
1138 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1139 Cond.erase(Cond.begin());
1141 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1147 bool HexagonInstrInfo::
1148 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1149 const BranchProbability &Probability) const {
1150 return (NumInstrs <= 4);
1153 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1154 switch (MI->getOpcode()) {
1155 default: return false;
1156 case Hexagon::L4_return:
1157 case Hexagon::L4_return_t:
1158 case Hexagon::L4_return_f:
1159 case Hexagon::L4_return_tnew_pnt:
1160 case Hexagon::L4_return_fnew_pnt:
1161 case Hexagon::L4_return_tnew_pt:
1162 case Hexagon::L4_return_fnew_pt:
1168 bool HexagonInstrInfo::
1169 isValidOffset(const int Opcode, const int Offset) const {
1170 // This function is to check whether the "Offset" is in the correct range of
1171 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1172 // inserted to calculate the final address. Due to this reason, the function
1173 // assumes that the "Offset" has correct alignment.
1174 // We used to assert if the offset was not properly aligned, however,
1175 // there are cases where a misaligned pointer recast can cause this
1176 // problem, and we need to allow for it. The front end warns of such
1177 // misaligns with respect to load size.
1181 case Hexagon::L2_loadri_io:
1182 case Hexagon::S2_storeri_io:
1183 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1184 (Offset <= Hexagon_MEMW_OFFSET_MAX);
1186 case Hexagon::L2_loadrd_io:
1187 case Hexagon::S2_storerd_io:
1188 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1189 (Offset <= Hexagon_MEMD_OFFSET_MAX);
1191 case Hexagon::L2_loadrh_io:
1192 case Hexagon::L2_loadruh_io:
1193 case Hexagon::S2_storerh_io:
1194 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1195 (Offset <= Hexagon_MEMH_OFFSET_MAX);
1197 case Hexagon::L2_loadrb_io:
1198 case Hexagon::S2_storerb_io:
1199 case Hexagon::L2_loadrub_io:
1200 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1201 (Offset <= Hexagon_MEMB_OFFSET_MAX);
1203 case Hexagon::A2_addi:
1204 case Hexagon::TFR_FI:
1205 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1206 (Offset <= Hexagon_ADDI_OFFSET_MAX);
1208 case Hexagon::L4_iadd_memopw_io:
1209 case Hexagon::L4_isub_memopw_io:
1210 case Hexagon::L4_add_memopw_io:
1211 case Hexagon::L4_sub_memopw_io:
1212 case Hexagon::L4_and_memopw_io:
1213 case Hexagon::L4_or_memopw_io:
1214 return (0 <= Offset && Offset <= 255);
1216 case Hexagon::L4_iadd_memoph_io:
1217 case Hexagon::L4_isub_memoph_io:
1218 case Hexagon::L4_add_memoph_io:
1219 case Hexagon::L4_sub_memoph_io:
1220 case Hexagon::L4_and_memoph_io:
1221 case Hexagon::L4_or_memoph_io:
1222 return (0 <= Offset && Offset <= 127);
1224 case Hexagon::L4_iadd_memopb_io:
1225 case Hexagon::L4_isub_memopb_io:
1226 case Hexagon::L4_add_memopb_io:
1227 case Hexagon::L4_sub_memopb_io:
1228 case Hexagon::L4_and_memopb_io:
1229 case Hexagon::L4_or_memopb_io:
1230 return (0 <= Offset && Offset <= 63);
1232 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
1233 // any size. Later pass knows how to handle it.
1234 case Hexagon::STriw_pred:
1235 case Hexagon::LDriw_pred:
1238 case Hexagon::J2_loop0i:
1239 return isUInt<10>(Offset);
1241 // INLINEASM is very special.
1242 case Hexagon::INLINEASM:
1246 llvm_unreachable("No offset range is defined for this opcode. "
1247 "Please define it in the above switch statement!");
1252 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
1254 bool HexagonInstrInfo::
1255 isValidAutoIncImm(const EVT VT, const int Offset) const {
1257 if (VT == MVT::i64) {
1258 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
1259 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
1260 (Offset & 0x7) == 0);
1262 if (VT == MVT::i32) {
1263 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
1264 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
1265 (Offset & 0x3) == 0);
1267 if (VT == MVT::i16) {
1268 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
1269 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
1270 (Offset & 0x1) == 0);
1272 if (VT == MVT::i8) {
1273 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
1274 Offset <= Hexagon_MEMB_AUTOINC_MAX);
1276 llvm_unreachable("Not an auto-inc opc!");
1280 bool HexagonInstrInfo::
1281 isMemOp(const MachineInstr *MI) const {
1282 // return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
1284 switch (MI->getOpcode())
1286 default: return false;
1287 case Hexagon::L4_iadd_memopw_io:
1288 case Hexagon::L4_isub_memopw_io:
1289 case Hexagon::L4_add_memopw_io:
1290 case Hexagon::L4_sub_memopw_io:
1291 case Hexagon::L4_and_memopw_io:
1292 case Hexagon::L4_or_memopw_io:
1293 case Hexagon::L4_iadd_memoph_io:
1294 case Hexagon::L4_isub_memoph_io:
1295 case Hexagon::L4_add_memoph_io:
1296 case Hexagon::L4_sub_memoph_io:
1297 case Hexagon::L4_and_memoph_io:
1298 case Hexagon::L4_or_memoph_io:
1299 case Hexagon::L4_iadd_memopb_io:
1300 case Hexagon::L4_isub_memopb_io:
1301 case Hexagon::L4_add_memopb_io:
1302 case Hexagon::L4_sub_memopb_io:
1303 case Hexagon::L4_and_memopb_io:
1304 case Hexagon::L4_or_memopb_io:
1305 case Hexagon::L4_ior_memopb_io:
1306 case Hexagon::L4_ior_memoph_io:
1307 case Hexagon::L4_ior_memopw_io:
1308 case Hexagon::L4_iand_memopb_io:
1309 case Hexagon::L4_iand_memoph_io:
1310 case Hexagon::L4_iand_memopw_io:
1317 bool HexagonInstrInfo::
1318 isSpillPredRegOp(const MachineInstr *MI) const {
1319 switch (MI->getOpcode()) {
1320 default: return false;
1321 case Hexagon::STriw_pred :
1322 case Hexagon::LDriw_pred :
1327 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
1328 switch (MI->getOpcode()) {
1329 default: return false;
1330 case Hexagon::C2_cmpeq:
1331 case Hexagon::C2_cmpeqi:
1332 case Hexagon::C2_cmpgt:
1333 case Hexagon::C2_cmpgti:
1334 case Hexagon::C2_cmpgtu:
1335 case Hexagon::C2_cmpgtui:
1340 bool HexagonInstrInfo::
1341 isConditionalTransfer (const MachineInstr *MI) const {
1342 switch (MI->getOpcode()) {
1343 default: return false;
1344 case Hexagon::A2_tfrt:
1345 case Hexagon::A2_tfrf:
1346 case Hexagon::C2_cmoveit:
1347 case Hexagon::C2_cmoveif:
1348 case Hexagon::A2_tfrtnew:
1349 case Hexagon::A2_tfrfnew:
1350 case Hexagon::C2_cmovenewit:
1351 case Hexagon::C2_cmovenewif:
1356 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
1357 switch (MI->getOpcode())
1359 default: return false;
1360 case Hexagon::A2_paddf:
1361 case Hexagon::A2_paddfnew:
1362 case Hexagon::A2_paddt:
1363 case Hexagon::A2_paddtnew:
1364 case Hexagon::A2_pandf:
1365 case Hexagon::A2_pandfnew:
1366 case Hexagon::A2_pandt:
1367 case Hexagon::A2_pandtnew:
1368 case Hexagon::A4_paslhf:
1369 case Hexagon::A4_paslhfnew:
1370 case Hexagon::A4_paslht:
1371 case Hexagon::A4_paslhtnew:
1372 case Hexagon::A4_pasrhf:
1373 case Hexagon::A4_pasrhfnew:
1374 case Hexagon::A4_pasrht:
1375 case Hexagon::A4_pasrhtnew:
1376 case Hexagon::A2_porf:
1377 case Hexagon::A2_porfnew:
1378 case Hexagon::A2_port:
1379 case Hexagon::A2_portnew:
1380 case Hexagon::A2_psubf:
1381 case Hexagon::A2_psubfnew:
1382 case Hexagon::A2_psubt:
1383 case Hexagon::A2_psubtnew:
1384 case Hexagon::A2_pxorf:
1385 case Hexagon::A2_pxorfnew:
1386 case Hexagon::A2_pxort:
1387 case Hexagon::A2_pxortnew:
1388 case Hexagon::A4_psxthf:
1389 case Hexagon::A4_psxthfnew:
1390 case Hexagon::A4_psxtht:
1391 case Hexagon::A4_psxthtnew:
1392 case Hexagon::A4_psxtbf:
1393 case Hexagon::A4_psxtbfnew:
1394 case Hexagon::A4_psxtbt:
1395 case Hexagon::A4_psxtbtnew:
1396 case Hexagon::A4_pzxtbf:
1397 case Hexagon::A4_pzxtbfnew:
1398 case Hexagon::A4_pzxtbt:
1399 case Hexagon::A4_pzxtbtnew:
1400 case Hexagon::A4_pzxthf:
1401 case Hexagon::A4_pzxthfnew:
1402 case Hexagon::A4_pzxtht:
1403 case Hexagon::A4_pzxthtnew:
1404 case Hexagon::A2_paddit:
1405 case Hexagon::A2_paddif:
1406 case Hexagon::C2_ccombinewt:
1407 case Hexagon::C2_ccombinewf:
1412 bool HexagonInstrInfo::
1413 isConditionalLoad (const MachineInstr* MI) const {
1414 switch (MI->getOpcode())
1416 default: return false;
1417 case Hexagon::L2_ploadrdt_io :
1418 case Hexagon::L2_ploadrdf_io:
1419 case Hexagon::L2_ploadrit_io:
1420 case Hexagon::L2_ploadrif_io:
1421 case Hexagon::L2_ploadrht_io:
1422 case Hexagon::L2_ploadrhf_io:
1423 case Hexagon::L2_ploadrbt_io:
1424 case Hexagon::L2_ploadrbf_io:
1425 case Hexagon::L2_ploadruht_io:
1426 case Hexagon::L2_ploadruhf_io:
1427 case Hexagon::L2_ploadrubt_io:
1428 case Hexagon::L2_ploadrubf_io:
1429 case Hexagon::L2_ploadrdt_pi:
1430 case Hexagon::L2_ploadrdf_pi:
1431 case Hexagon::L2_ploadrit_pi:
1432 case Hexagon::L2_ploadrif_pi:
1433 case Hexagon::L2_ploadrht_pi:
1434 case Hexagon::L2_ploadrhf_pi:
1435 case Hexagon::L2_ploadrbt_pi:
1436 case Hexagon::L2_ploadrbf_pi:
1437 case Hexagon::L2_ploadruht_pi:
1438 case Hexagon::L2_ploadruhf_pi:
1439 case Hexagon::L2_ploadrubt_pi:
1440 case Hexagon::L2_ploadrubf_pi:
1441 case Hexagon::L4_ploadrdt_rr:
1442 case Hexagon::L4_ploadrdf_rr:
1443 case Hexagon::L4_ploadrbt_rr:
1444 case Hexagon::L4_ploadrbf_rr:
1445 case Hexagon::L4_ploadrubt_rr:
1446 case Hexagon::L4_ploadrubf_rr:
1447 case Hexagon::L4_ploadrht_rr:
1448 case Hexagon::L4_ploadrhf_rr:
1449 case Hexagon::L4_ploadruht_rr:
1450 case Hexagon::L4_ploadruhf_rr:
1451 case Hexagon::L4_ploadrit_rr:
1452 case Hexagon::L4_ploadrif_rr:
1457 // Returns true if an instruction is a conditional store.
1459 // Note: It doesn't include conditional new-value stores as they can't be
1460 // converted to .new predicate.
1462 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
1464 // / \ (not OK. it will cause new-value store to be
1465 // / X conditional on p0.new while R2 producer is
1468 // p.new store p.old NV store
1469 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
1475 // [if (p0)memw(R0+#0)=R2]
1477 // The above diagram shows the steps involoved in the conversion of a predicated
1478 // store instruction to its .new predicated new-value form.
1480 // The following set of instructions further explains the scenario where
1481 // conditional new-value store becomes invalid when promoted to .new predicate
1484 // { 1) if (p0) r0 = add(r1, r2)
1485 // 2) p0 = cmp.eq(r3, #0) }
1487 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
1488 // the first two instructions because in instr 1, r0 is conditional on old value
1489 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
1490 // is not valid for new-value stores.
1491 bool HexagonInstrInfo::
1492 isConditionalStore (const MachineInstr* MI) const {
1493 switch (MI->getOpcode())
1495 default: return false;
1496 case Hexagon::S4_storeirbt_io:
1497 case Hexagon::S4_storeirbf_io:
1498 case Hexagon::S4_pstorerbt_rr:
1499 case Hexagon::S4_pstorerbf_rr:
1500 case Hexagon::S2_pstorerbt_io:
1501 case Hexagon::S2_pstorerbf_io:
1502 case Hexagon::S2_pstorerbt_pi:
1503 case Hexagon::S2_pstorerbf_pi:
1504 case Hexagon::S2_pstorerdt_io:
1505 case Hexagon::S2_pstorerdf_io:
1506 case Hexagon::S4_pstorerdt_rr:
1507 case Hexagon::S4_pstorerdf_rr:
1508 case Hexagon::S2_pstorerdt_pi:
1509 case Hexagon::S2_pstorerdf_pi:
1510 case Hexagon::S2_pstorerht_io:
1511 case Hexagon::S2_pstorerhf_io:
1512 case Hexagon::S4_storeirht_io:
1513 case Hexagon::S4_storeirhf_io:
1514 case Hexagon::S4_pstorerht_rr:
1515 case Hexagon::S4_pstorerhf_rr:
1516 case Hexagon::S2_pstorerht_pi:
1517 case Hexagon::S2_pstorerhf_pi:
1518 case Hexagon::S2_pstorerit_io:
1519 case Hexagon::S2_pstorerif_io:
1520 case Hexagon::S4_storeirit_io:
1521 case Hexagon::S4_storeirif_io:
1522 case Hexagon::S4_pstorerit_rr:
1523 case Hexagon::S4_pstorerif_rr:
1524 case Hexagon::S2_pstorerit_pi:
1525 case Hexagon::S2_pstorerif_pi:
1527 // V4 global address store before promoting to dot new.
1528 case Hexagon::S4_pstorerdt_abs:
1529 case Hexagon::S4_pstorerdf_abs:
1530 case Hexagon::S4_pstorerbt_abs:
1531 case Hexagon::S4_pstorerbf_abs:
1532 case Hexagon::S4_pstorerht_abs:
1533 case Hexagon::S4_pstorerhf_abs:
1534 case Hexagon::S4_pstorerit_abs:
1535 case Hexagon::S4_pstorerif_abs:
1538 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1539 // from the "Conditional Store" list. Because a predicated new value store
1540 // would NOT be promoted to a double dot new store. See diagram below:
1541 // This function returns yes for those stores that are predicated but not
1542 // yet promoted to predicate dot new instructions.
1544 // +---------------------+
1545 // /-----| if (p0) memw(..)=r0 |---------\~
1546 // || +---------------------+ ||
1547 // promote || /\ /\ || promote
1549 // \||/ demote || \||/
1551 // +-------------------------+ || +-------------------------+
1552 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
1553 // +-------------------------+ || +-------------------------+
1556 // promote || \/ NOT possible
1560 // +-----------------------------+
1561 // | if (p0.new) memw(..)=r0.new |
1562 // +-----------------------------+
1563 // Double Dot New Store
1569 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
1570 if (isNewValue(MI) && isBranch(MI))
1575 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1576 return (getAddrMode(MI) == HexagonII::PostInc);
1579 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
1580 const uint64_t F = MI->getDesc().TSFlags;
1581 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
1584 // Returns true, if any one of the operands is a dot new
1585 // insn, whether it is predicated dot new or register dot new.
1586 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
1587 return (isNewValueInst(MI) ||
1588 (isPredicated(MI) && isPredicatedNew(MI)));
1591 // Returns the most basic instruction for the .new predicated instructions and
1592 // new-value stores.
1593 // For example, all of the following instructions will be converted back to the
1594 // same instruction:
1595 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1596 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1597 // 3) if (p0.new) memw(R0+#0) = R1 --->
1600 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
1602 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
1603 NewOp = Hexagon::getPredOldOpcode(NewOp);
1604 assert(NewOp >= 0 &&
1605 "Couldn't change predicate new instruction to its old form.");
1608 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
1609 NewOp = Hexagon::getNonNVStore(NewOp);
1610 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
1615 // Return the new value instruction for a given store.
1616 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
1617 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
1618 if (NVOpcode >= 0) // Valid new-value store instruction.
1621 switch (MI->getOpcode()) {
1622 default: llvm_unreachable("Unknown .new type");
1623 case Hexagon::S4_storerb_ur:
1624 return Hexagon::S4_storerbnew_ur;
1626 case Hexagon::S4_storerh_ur:
1627 return Hexagon::S4_storerhnew_ur;
1629 case Hexagon::S4_storeri_ur:
1630 return Hexagon::S4_storerinew_ur;
1632 case Hexagon::S2_storerb_pci:
1633 return Hexagon::S2_storerb_pci;
1635 case Hexagon::S2_storeri_pci:
1636 return Hexagon::S2_storeri_pci;
1638 case Hexagon::S2_storerh_pci:
1639 return Hexagon::S2_storerh_pci;
1641 case Hexagon::S2_storerd_pci:
1642 return Hexagon::S2_storerd_pci;
1644 case Hexagon::S2_storerf_pci:
1645 return Hexagon::S2_storerf_pci;
1650 // Return .new predicate version for an instruction.
1651 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
1652 const MachineBranchProbabilityInfo
1655 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1656 if (NewOpcode >= 0) // Valid predicate new instruction
1659 switch (MI->getOpcode()) {
1660 default: llvm_unreachable("Unknown .new type");
1662 case Hexagon::J2_jumpt:
1663 case Hexagon::J2_jumpf:
1664 return getDotNewPredJumpOp(MI, MBPI);
1666 case Hexagon::J2_jumprt:
1667 return Hexagon::J2_jumptnewpt;
1669 case Hexagon::J2_jumprf:
1670 return Hexagon::J2_jumprfnewpt;
1672 case Hexagon::JMPrett:
1673 return Hexagon::J2_jumprtnewpt;
1675 case Hexagon::JMPretf:
1676 return Hexagon::J2_jumprfnewpt;
1679 // Conditional combine
1680 case Hexagon::C2_ccombinewt:
1681 return Hexagon::C2_ccombinewnewt;
1682 case Hexagon::C2_ccombinewf:
1683 return Hexagon::C2_ccombinewnewf;
1688 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
1689 const uint64_t F = MI->getDesc().TSFlags;
1691 return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
1694 /// immediateExtend - Changes the instruction in place to one using an immediate
1696 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
1697 assert((isExtendable(MI)||isConstExtended(MI)) &&
1698 "Instruction must be extendable");
1699 // Find which operand is extendable.
1700 short ExtOpNum = getCExtOpNum(MI);
1701 MachineOperand &MO = MI->getOperand(ExtOpNum);
1702 // This needs to be something we understand.
1703 assert((MO.isMBB() || MO.isImm()) &&
1704 "Branch with unknown extendable field type");
1705 // Mark given operand as extended.
1706 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
1709 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1710 const TargetSubtargetInfo &STI) const {
1711 const InstrItineraryData *II = STI.getInstrItineraryData();
1712 return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
1715 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1716 const MachineBasicBlock *MBB,
1717 const MachineFunction &MF) const {
1718 // Debug info is never a scheduling boundary. It's necessary to be explicit
1719 // due to the special treatment of IT instructions below, otherwise a
1720 // dbg_value followed by an IT will result in the IT instruction being
1721 // considered a scheduling hazard, which is wrong. It should be the actual
1722 // instruction preceding the dbg_value instruction(s), just like it is
1723 // when debug info is not present.
1724 if (MI->isDebugValue())
1727 // Terminators and labels can't be scheduled around.
1728 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
1734 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
1735 const uint64_t F = MI->getDesc().TSFlags;
1736 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1737 if (isExtended) // Instruction must be extended.
1740 unsigned isExtendable = (F >> HexagonII::ExtendablePos)
1741 & HexagonII::ExtendableMask;
1745 short ExtOpNum = getCExtOpNum(MI);
1746 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1747 // Use MO operand flags to determine if MO
1748 // has the HMOTF_ConstExtended flag set.
1749 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1751 // If this is a Machine BB address we are talking about, and it is
1752 // not marked as extended, say so.
1756 // We could be using an instruction with an extendable immediate and shoehorn
1757 // a global address into it. If it is a global address it will be constant
1758 // extended. We do this for COMBINE.
1759 // We currently only handle isGlobal() because it is the only kind of
1760 // object we are going to end up with here for now.
1761 // In the future we probably should add isSymbol(), etc.
1762 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress())
1765 // If the extendable operand is not 'Immediate' type, the instruction should
1766 // have 'isExtended' flag set.
1767 assert(MO.isImm() && "Extendable operand must be Immediate type");
1769 int MinValue = getMinValue(MI);
1770 int MaxValue = getMaxValue(MI);
1771 int ImmValue = MO.getImm();
1773 return (ImmValue < MinValue || ImmValue > MaxValue);
1776 // Returns the opcode to use when converting MI, which is a conditional jump,
1777 // into a conditional instruction which uses the .new value of the predicate.
1778 // We also use branch probabilities to add a hint to the jump.
1780 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
1782 MachineBranchProbabilityInfo *MBPI) const {
1784 // We assume that block can have at most two successors.
1786 MachineBasicBlock *Src = MI->getParent();
1787 MachineOperand *BrTarget = &MI->getOperand(1);
1788 MachineBasicBlock *Dst = BrTarget->getMBB();
1790 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
1791 if (Prediction >= BranchProbability(1,2))
1794 switch (MI->getOpcode()) {
1795 case Hexagon::J2_jumpt:
1796 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
1797 case Hexagon::J2_jumpf:
1798 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
1801 llvm_unreachable("Unexpected jump instruction.");
1804 // Returns true if a particular operand is extendable for an instruction.
1805 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
1806 unsigned short OperandNum) const {
1807 const uint64_t F = MI->getDesc().TSFlags;
1809 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
1813 // Returns Operand Index for the constant extended instruction.
1814 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
1815 const uint64_t F = MI->getDesc().TSFlags;
1816 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
1819 // Returns the min value that doesn't need to be extended.
1820 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
1821 const uint64_t F = MI->getDesc().TSFlags;
1822 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1823 & HexagonII::ExtentSignedMask;
1824 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1825 & HexagonII::ExtentBitsMask;
1827 if (isSigned) // if value is signed
1828 return -1U << (bits - 1);
1833 // Returns the max value that doesn't need to be extended.
1834 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
1835 const uint64_t F = MI->getDesc().TSFlags;
1836 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
1837 & HexagonII::ExtentSignedMask;
1838 unsigned bits = (F >> HexagonII::ExtentBitsPos)
1839 & HexagonII::ExtentBitsMask;
1841 if (isSigned) // if value is signed
1842 return ~(-1U << (bits - 1));
1844 return ~(-1U << bits);
1847 // Returns true if an instruction can be converted into a non-extended
1848 // equivalent instruction.
1849 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
1852 // Check if the instruction has a register form that uses register in place
1853 // of the extended operand, if so return that as the non-extended form.
1854 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
1857 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1858 // Check addressing mode and retrieve non-ext equivalent instruction.
1860 switch (getAddrMode(MI)) {
1861 case HexagonII::Absolute :
1862 // Load/store with absolute addressing mode can be converted into
1863 // base+offset mode.
1864 NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
1866 case HexagonII::BaseImmOffset :
1867 // Load/store with base+offset addressing mode can be converted into
1868 // base+register offset addressing mode. However left shift operand should
1870 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
1875 if (NonExtOpcode < 0)
1882 // Returns opcode of the non-extended equivalent instruction.
1883 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
1885 // Check if the instruction has a register form that uses register in place
1886 // of the extended operand, if so return that as the non-extended form.
1887 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
1888 if (NonExtOpcode >= 0)
1889 return NonExtOpcode;
1891 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1892 // Check addressing mode and retrieve non-ext equivalent instruction.
1893 switch (getAddrMode(MI)) {
1894 case HexagonII::Absolute :
1895 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
1896 case HexagonII::BaseImmOffset :
1897 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
1905 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
1906 return (Opcode == Hexagon::J2_jumpt) ||
1907 (Opcode == Hexagon::J2_jumpf) ||
1908 (Opcode == Hexagon::J2_jumptnewpt) ||
1909 (Opcode == Hexagon::J2_jumpfnewpt) ||
1910 (Opcode == Hexagon::J2_jumpt) ||
1911 (Opcode == Hexagon::J2_jumpf);
1914 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
1915 return (Opcode == Hexagon::J2_jumpf) ||
1916 (Opcode == Hexagon::J2_jumpfnewpt) ||
1917 (Opcode == Hexagon::J2_jumpfnew);