1 //===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
16 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/Support/DataTypes.h"
30 class MCSubtargetInfo;
33 class MipsMCCodeEmitter : public MCCodeEmitter {
34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
36 const MCInstrInfo &MCII;
40 bool isMicroMips(const MCSubtargetInfo &STI) const;
43 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)
44 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
46 ~MipsMCCodeEmitter() {}
48 void EmitByte(unsigned char C, raw_ostream &OS) const;
50 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
51 raw_ostream &OS) const;
53 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
54 SmallVectorImpl<MCFixup> &Fixups,
55 const MCSubtargetInfo &STI) const override;
57 // getBinaryCodeForInstr - TableGen'erated function for getting the
58 // binary encoding for an instruction.
59 uint64_t getBinaryCodeForInstr(const MCInst &MI,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const;
63 // getJumpTargetOpValue - Return binary encoding of the jump
64 // target operand. If the machine operand requires relocation,
65 // record the relocation and return zero.
66 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
70 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
71 // target operand. If the machine operand requires relocation,
72 // record the relocation and return zero.
73 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
74 SmallVectorImpl<MCFixup> &Fixups,
75 const MCSubtargetInfo &STI) const;
77 // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump
79 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
83 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
84 SmallVectorImpl<MCFixup> &Fixups,
85 const MCSubtargetInfo &STI) const;
87 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups,
89 const MCSubtargetInfo &STI) const;
91 // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp
92 // instruction immediate operand.
93 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI) const;
97 // getBranchTargetOpValue - Return binary encoding of the branch
98 // target operand. If the machine operand requires relocation,
99 // record the relocation and return zero.
100 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
101 SmallVectorImpl<MCFixup> &Fixups,
102 const MCSubtargetInfo &STI) const;
104 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
105 // target operand. If the machine operand requires relocation,
106 // record the relocation and return zero.
107 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
108 SmallVectorImpl<MCFixup> &Fixups,
109 const MCSubtargetInfo &STI) const;
111 // getBranchTarget21OpValue - Return binary encoding of the branch
112 // offset operand. If the machine operand requires relocation,
113 // record the relocation and return zero.
114 unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
115 SmallVectorImpl<MCFixup> &Fixups,
116 const MCSubtargetInfo &STI) const;
118 // getBranchTarget26OpValue - Return binary encoding of the branch
119 // offset operand. If the machine operand requires relocation,
120 // record the relocation and return zero.
121 unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
122 SmallVectorImpl<MCFixup> &Fixups,
123 const MCSubtargetInfo &STI) const;
125 // getJumpOffset16OpValue - Return binary encoding of the jump
126 // offset operand. If the machine operand requires relocation,
127 // record the relocation and return zero.
128 unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
129 SmallVectorImpl<MCFixup> &Fixups,
130 const MCSubtargetInfo &STI) const;
132 // getMachineOpValue - Return binary encoding of operand. If the machin
133 // operand requires relocation, record the relocation and return zero.
134 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
135 SmallVectorImpl<MCFixup> &Fixups,
136 const MCSubtargetInfo &STI) const;
138 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
139 SmallVectorImpl<MCFixup> &Fixups,
140 const MCSubtargetInfo &STI) const;
142 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
143 SmallVectorImpl<MCFixup> &Fixups,
144 const MCSubtargetInfo &STI) const;
145 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
146 SmallVectorImpl<MCFixup> &Fixups,
147 const MCSubtargetInfo &STI) const;
148 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const;
151 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
152 SmallVectorImpl<MCFixup> &Fixups,
153 const MCSubtargetInfo &STI) const;
155 // getLSAImmEncoding - Return binary encoding of LSA immediate.
156 unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
157 SmallVectorImpl<MCFixup> &Fixups,
158 const MCSubtargetInfo &STI) const;
160 unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
161 SmallVectorImpl<MCFixup> &Fixups,
162 const MCSubtargetInfo &STI) const;
164 unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
165 SmallVectorImpl<MCFixup> &Fixups,
166 const MCSubtargetInfo &STI) const;
168 unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
169 SmallVectorImpl<MCFixup> &Fixups,
170 const MCSubtargetInfo &STI) const;
171 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo,
172 SmallVectorImpl<MCFixup> &Fixups,
173 const MCSubtargetInfo &STI) const;
175 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
176 const MCSubtargetInfo &STI) const;
178 unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
179 SmallVectorImpl<MCFixup> &Fixups,
180 const MCSubtargetInfo &STI) const;
181 }; // class MipsMCCodeEmitter