1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target streamer methods.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetStreamer.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsABIInfo.h"
17 #include "MipsELFStreamer.h"
18 #include "MipsMCExpr.h"
19 #include "MipsMCTargetDesc.h"
20 #include "MipsTargetObjectFile.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbolELF.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ELF.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/FormattedStream.h"
33 static cl::opt<bool> RoundSectionSizes(
34 "mips-round-section-sizes", cl::init(false),
35 cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
36 } // end anonymous namespace
38 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
39 : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
40 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
42 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
43 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
44 void MipsTargetStreamer::setUsesMicroMips() {}
45 void MipsTargetStreamer::emitDirectiveSetMips16() {}
46 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
47 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
48 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
49 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
51 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
52 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
53 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
54 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
55 forbidModuleDirective();
57 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
58 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
59 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
60 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
61 void MipsTargetStreamer::emitDirectiveNaN2008() {}
62 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
63 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
64 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
65 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
66 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
67 unsigned ReturnReg) {}
68 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
69 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
71 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
72 forbidModuleDirective();
74 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
75 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
76 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
77 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
78 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
79 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
80 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
81 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
84 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
85 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
87 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
93 forbidModuleDirective();
95 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
96 forbidModuleDirective();
98 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
99 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
100 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
101 bool MipsTargetStreamer::emitDirectiveCpRestore(
102 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
103 const MCSubtargetInfo *STI) {
104 forbidModuleDirective();
107 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
108 const MCSymbol &Sym, bool IsReg) {
110 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
111 bool SaveLocationIsRegister) {}
113 void MipsTargetStreamer::emitDirectiveModuleFP() {}
115 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
116 if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
117 report_fatal_error("+nooddspreg is only valid for O32");
119 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
120 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
121 void MipsTargetStreamer::emitDirectiveSetFp(
122 MipsABIFlagsSection::FpABIKind Value) {
123 forbidModuleDirective();
125 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
126 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
127 forbidModuleDirective();
130 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
131 const MCSubtargetInfo *STI) {
133 TmpInst.setOpcode(Opcode);
134 TmpInst.addOperand(MCOperand::createReg(Reg0));
135 TmpInst.setLoc(IDLoc);
136 getStreamer().EmitInstruction(TmpInst, *STI);
139 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
140 SMLoc IDLoc, const MCSubtargetInfo *STI) {
142 TmpInst.setOpcode(Opcode);
143 TmpInst.addOperand(MCOperand::createReg(Reg0));
144 TmpInst.addOperand(Op1);
145 TmpInst.setLoc(IDLoc);
146 getStreamer().EmitInstruction(TmpInst, *STI);
149 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
150 SMLoc IDLoc, const MCSubtargetInfo *STI) {
151 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
154 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
155 SMLoc IDLoc, const MCSubtargetInfo *STI) {
156 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
159 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
160 SMLoc IDLoc, const MCSubtargetInfo *STI) {
162 TmpInst.setOpcode(Opcode);
163 TmpInst.addOperand(MCOperand::createImm(Imm1));
164 TmpInst.addOperand(MCOperand::createImm(Imm2));
165 TmpInst.setLoc(IDLoc);
166 getStreamer().EmitInstruction(TmpInst, *STI);
169 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
170 MCOperand Op2, SMLoc IDLoc,
171 const MCSubtargetInfo *STI) {
173 TmpInst.setOpcode(Opcode);
174 TmpInst.addOperand(MCOperand::createReg(Reg0));
175 TmpInst.addOperand(MCOperand::createReg(Reg1));
176 TmpInst.addOperand(Op2);
177 TmpInst.setLoc(IDLoc);
178 getStreamer().EmitInstruction(TmpInst, *STI);
181 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
182 unsigned Reg2, SMLoc IDLoc,
183 const MCSubtargetInfo *STI) {
184 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
187 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
188 int16_t Imm, SMLoc IDLoc,
189 const MCSubtargetInfo *STI) {
190 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
193 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
194 unsigned TrgReg, bool Is64Bit,
195 const MCSubtargetInfo *STI) {
196 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
200 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
201 int16_t ShiftAmount, SMLoc IDLoc,
202 const MCSubtargetInfo *STI) {
203 if (ShiftAmount >= 32) {
204 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
208 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
211 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
212 const MCSubtargetInfo *STI) {
213 if (hasShortDelaySlot)
214 emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
216 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
219 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
220 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
223 /// Emit the $gp restore operation for .cprestore.
224 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
225 const MCSubtargetInfo *STI) {
226 emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
230 /// Emit a store instruction with an immediate offset.
231 void MipsTargetStreamer::emitStoreWithImmOffset(
232 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
233 function_ref<unsigned()> GetATReg, SMLoc IDLoc,
234 const MCSubtargetInfo *STI) {
235 if (isInt<16>(Offset)) {
236 emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
240 // sw $8, offset($8) => lui $at, %hi(offset)
242 // sw $8, %lo(offset)($at)
244 unsigned ATReg = GetATReg();
248 unsigned LoOffset = Offset & 0x0000ffff;
249 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
251 // If msb of LoOffset is 1(negative number) we must increment HiOffset
252 // to account for the sign-extension of the low part.
253 if (LoOffset & 0x8000)
256 // Generate the base address in ATReg.
257 emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
258 if (BaseReg != Mips::ZERO)
259 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
260 // Emit the store with the adjusted base and offset.
261 emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
264 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
265 /// out of range for a simm16 will be expanded to appropriate instructions.
266 void MipsTargetStreamer::emitStoreWithSymOffset(
267 unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
268 MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
269 const MCSubtargetInfo *STI) {
270 // sw $8, sym => lui $at, %hi(sym)
271 // sw $8, %lo(sym)($at)
273 // Generate the base address in ATReg.
274 emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
275 if (BaseReg != Mips::ZERO)
276 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
277 // Emit the store with the adjusted base and offset.
278 emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
281 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
282 /// permitted to be the same register iff DstReg is distinct from BaseReg and
283 /// DstReg is a GPR. It is the callers responsibility to identify such cases
284 /// and pass the appropriate register in TmpReg.
285 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
286 unsigned BaseReg, int64_t Offset,
287 unsigned TmpReg, SMLoc IDLoc,
288 const MCSubtargetInfo *STI) {
289 if (isInt<16>(Offset)) {
290 emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
294 // 1) lw $8, offset($9) => lui $8, %hi(offset)
296 // lw $8, %lo(offset)($9)
297 // 2) lw $8, offset($8) => lui $at, %hi(offset)
299 // lw $8, %lo(offset)($at)
301 unsigned LoOffset = Offset & 0x0000ffff;
302 unsigned HiOffset = (Offset & 0xffff0000) >> 16;
304 // If msb of LoOffset is 1(negative number) we must increment HiOffset
305 // to account for the sign-extension of the low part.
306 if (LoOffset & 0x8000)
309 // Generate the base address in TmpReg.
310 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
311 if (BaseReg != Mips::ZERO)
312 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
313 // Emit the load with the adjusted base and offset.
314 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
317 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
318 /// out of range for a simm16 will be expanded to appropriate instructions.
319 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
320 /// GPR. It is the callers responsibility to identify such cases and pass the
321 /// appropriate register in TmpReg.
322 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
324 MCOperand &HiOperand,
325 MCOperand &LoOperand,
326 unsigned TmpReg, SMLoc IDLoc,
327 const MCSubtargetInfo *STI) {
328 // 1) lw $8, sym => lui $8, %hi(sym)
329 // lw $8, %lo(sym)($8)
330 // 2) ldc1 $f0, sym => lui $at, %hi(sym)
331 // ldc1 $f0, %lo(sym)($at)
333 // Generate the base address in TmpReg.
334 emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
335 if (BaseReg != Mips::ZERO)
336 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
337 // Emit the load with the adjusted base and offset.
338 emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
341 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
342 formatted_raw_ostream &OS)
343 : MipsTargetStreamer(S), OS(OS) {}
345 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
346 OS << "\t.set\tmicromips\n";
347 forbidModuleDirective();
350 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
351 OS << "\t.set\tnomicromips\n";
352 forbidModuleDirective();
355 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
356 OS << "\t.set\tmips16\n";
357 forbidModuleDirective();
360 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
361 OS << "\t.set\tnomips16\n";
362 MipsTargetStreamer::emitDirectiveSetNoMips16();
365 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
366 OS << "\t.set\treorder\n";
367 MipsTargetStreamer::emitDirectiveSetReorder();
370 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
371 OS << "\t.set\tnoreorder\n";
372 forbidModuleDirective();
375 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
376 OS << "\t.set\tmacro\n";
377 MipsTargetStreamer::emitDirectiveSetMacro();
380 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
381 OS << "\t.set\tnomacro\n";
382 MipsTargetStreamer::emitDirectiveSetNoMacro();
385 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
386 OS << "\t.set\tmsa\n";
387 MipsTargetStreamer::emitDirectiveSetMsa();
390 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
391 OS << "\t.set\tnomsa\n";
392 MipsTargetStreamer::emitDirectiveSetNoMsa();
395 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
396 OS << "\t.set\tat\n";
397 MipsTargetStreamer::emitDirectiveSetAt();
400 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
401 OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
402 MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
405 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
406 OS << "\t.set\tnoat\n";
407 MipsTargetStreamer::emitDirectiveSetNoAt();
410 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
411 OS << "\t.end\t" << Name << '\n';
414 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
415 OS << "\t.ent\t" << Symbol.getName() << '\n';
418 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
420 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
422 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
423 OS << "\t.nan\tlegacy\n";
426 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
427 OS << "\t.option\tpic0\n";
430 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
431 OS << "\t.option\tpic2\n";
434 void MipsTargetAsmStreamer::emitDirectiveInsn() {
435 MipsTargetStreamer::emitDirectiveInsn();
439 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
440 unsigned ReturnReg) {
442 << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
444 << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
447 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
448 OS << "\t.set arch=" << Arch << "\n";
449 MipsTargetStreamer::emitDirectiveSetArch(Arch);
452 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
453 OS << "\t.set\tmips0\n";
454 MipsTargetStreamer::emitDirectiveSetMips0();
457 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
458 OS << "\t.set\tmips1\n";
459 MipsTargetStreamer::emitDirectiveSetMips1();
462 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
463 OS << "\t.set\tmips2\n";
464 MipsTargetStreamer::emitDirectiveSetMips2();
467 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
468 OS << "\t.set\tmips3\n";
469 MipsTargetStreamer::emitDirectiveSetMips3();
472 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
473 OS << "\t.set\tmips4\n";
474 MipsTargetStreamer::emitDirectiveSetMips4();
477 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
478 OS << "\t.set\tmips5\n";
479 MipsTargetStreamer::emitDirectiveSetMips5();
482 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
483 OS << "\t.set\tmips32\n";
484 MipsTargetStreamer::emitDirectiveSetMips32();
487 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
488 OS << "\t.set\tmips32r2\n";
489 MipsTargetStreamer::emitDirectiveSetMips32R2();
492 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
493 OS << "\t.set\tmips32r3\n";
494 MipsTargetStreamer::emitDirectiveSetMips32R3();
497 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
498 OS << "\t.set\tmips32r5\n";
499 MipsTargetStreamer::emitDirectiveSetMips32R5();
502 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
503 OS << "\t.set\tmips32r6\n";
504 MipsTargetStreamer::emitDirectiveSetMips32R6();
507 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
508 OS << "\t.set\tmips64\n";
509 MipsTargetStreamer::emitDirectiveSetMips64();
512 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
513 OS << "\t.set\tmips64r2\n";
514 MipsTargetStreamer::emitDirectiveSetMips64R2();
517 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
518 OS << "\t.set\tmips64r3\n";
519 MipsTargetStreamer::emitDirectiveSetMips64R3();
522 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
523 OS << "\t.set\tmips64r5\n";
524 MipsTargetStreamer::emitDirectiveSetMips64R5();
527 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
528 OS << "\t.set\tmips64r6\n";
529 MipsTargetStreamer::emitDirectiveSetMips64R6();
532 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
533 OS << "\t.set\tdsp\n";
534 MipsTargetStreamer::emitDirectiveSetDsp();
537 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
538 OS << "\t.set\tnodsp\n";
539 MipsTargetStreamer::emitDirectiveSetNoDsp();
542 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
543 OS << "\t.set\tpop\n";
544 MipsTargetStreamer::emitDirectiveSetPop();
547 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
548 OS << "\t.set\tpush\n";
549 MipsTargetStreamer::emitDirectiveSetPush();
552 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
553 OS << "\t.set\tsoftfloat\n";
554 MipsTargetStreamer::emitDirectiveSetSoftFloat();
557 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
558 OS << "\t.set\thardfloat\n";
559 MipsTargetStreamer::emitDirectiveSetHardFloat();
562 // Print a 32 bit hex number with all numbers.
563 static void printHex32(unsigned Value, raw_ostream &OS) {
565 for (int i = 7; i >= 0; i--)
566 OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
569 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
570 int CPUTopSavedRegOff) {
572 printHex32(CPUBitmask, OS);
573 OS << ',' << CPUTopSavedRegOff << '\n';
576 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
577 int FPUTopSavedRegOff) {
579 printHex32(FPUBitmask, OS);
580 OS << "," << FPUTopSavedRegOff << '\n';
583 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
585 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
586 forbidModuleDirective();
589 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
590 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
591 const MCSubtargetInfo *STI) {
592 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
593 OS << "\t.cprestore\t" << Offset << "\n";
597 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
601 OS << "\t.cpsetup\t$"
602 << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
606 << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
613 forbidModuleDirective();
616 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
617 bool SaveLocationIsRegister) {
619 forbidModuleDirective();
622 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
623 OS << "\t.module\tfp=";
624 OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
627 void MipsTargetAsmStreamer::emitDirectiveSetFp(
628 MipsABIFlagsSection::FpABIKind Value) {
629 MipsTargetStreamer::emitDirectiveSetFp(Value);
632 OS << ABIFlagsSection.getFpABIString(Value) << "\n";
635 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
636 MipsTargetStreamer::emitDirectiveModuleOddSPReg();
638 OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
641 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
642 MipsTargetStreamer::emitDirectiveSetOddSPReg();
643 OS << "\t.set\toddspreg\n";
646 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
647 MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
648 OS << "\t.set\tnooddspreg\n";
651 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
652 OS << "\t.module\tsoftfloat\n";
655 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
656 OS << "\t.module\thardfloat\n";
659 // This part is for ELF object output.
660 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
661 const MCSubtargetInfo &STI)
662 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
663 MCAssembler &MCA = getStreamer().getAssembler();
665 // It's possible that MCObjectFileInfo isn't fully initialized at this point
666 // due to an initialization order problem where LLVMTargetMachine creates the
667 // target streamer before TargetLoweringObjectFile calls
668 // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
669 // covers all cases so this statement covers most cases and direct object
670 // emission must call setPic() once MCObjectFileInfo has been initialized. The
671 // cases we don't handle here are covered by MipsAsmPrinter.
672 Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
674 const FeatureBitset &Features = STI.getFeatureBits();
676 // Set the header flags that we can in the constructor.
677 // FIXME: This is a fairly terrible hack. We set the rest
678 // of these in the destructor. The problem here is two-fold:
680 // a: Some of the eflags can be set/reset by directives.
681 // b: There aren't any usage paths that initialize the ABI
682 // pointer until after we initialize either an assembler
683 // or the target machine.
684 // We can fix this by making the target streamer construct
685 // the ABI, but this is fraught with wide ranging dependency
687 unsigned EFlags = MCA.getELFHeaderEFlags();
689 // FIXME: Fix a dependency issue by instantiating the ABI object to some
690 // default based off the triple. The triple doesn't describe the target
691 // fully, but any external user of the API that uses the MCTargetStreamer
692 // would otherwise crash on assertion failure.
695 STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
696 STI.getTargetTriple().getArch() == Triple::ArchType::mips
698 : MipsABIInfo::N64());
701 if (Features[Mips::FeatureMips64r6])
702 EFlags |= ELF::EF_MIPS_ARCH_64R6;
703 else if (Features[Mips::FeatureMips64r2] ||
704 Features[Mips::FeatureMips64r3] ||
705 Features[Mips::FeatureMips64r5])
706 EFlags |= ELF::EF_MIPS_ARCH_64R2;
707 else if (Features[Mips::FeatureMips64])
708 EFlags |= ELF::EF_MIPS_ARCH_64;
709 else if (Features[Mips::FeatureMips5])
710 EFlags |= ELF::EF_MIPS_ARCH_5;
711 else if (Features[Mips::FeatureMips4])
712 EFlags |= ELF::EF_MIPS_ARCH_4;
713 else if (Features[Mips::FeatureMips3])
714 EFlags |= ELF::EF_MIPS_ARCH_3;
715 else if (Features[Mips::FeatureMips32r6])
716 EFlags |= ELF::EF_MIPS_ARCH_32R6;
717 else if (Features[Mips::FeatureMips32r2] ||
718 Features[Mips::FeatureMips32r3] ||
719 Features[Mips::FeatureMips32r5])
720 EFlags |= ELF::EF_MIPS_ARCH_32R2;
721 else if (Features[Mips::FeatureMips32])
722 EFlags |= ELF::EF_MIPS_ARCH_32;
723 else if (Features[Mips::FeatureMips2])
724 EFlags |= ELF::EF_MIPS_ARCH_2;
726 EFlags |= ELF::EF_MIPS_ARCH_1;
729 if (Features[Mips::FeatureCnMips])
730 EFlags |= ELF::EF_MIPS_MACH_OCTEON;
733 if (Features[Mips::FeatureNaN2008])
734 EFlags |= ELF::EF_MIPS_NAN2008;
736 MCA.setELFHeaderEFlags(EFlags);
739 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
740 auto *Symbol = cast<MCSymbolELF>(S);
741 getStreamer().getAssembler().registerSymbol(*Symbol);
742 uint8_t Type = Symbol->getType();
743 if (Type != ELF::STT_FUNC)
746 if (isMicroMipsEnabled())
747 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
750 void MipsTargetELFStreamer::finish() {
751 MCAssembler &MCA = getStreamer().getAssembler();
752 const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
754 // .bss, .text and .data are always at least 16-byte aligned.
755 MCSection &TextSection = *OFI.getTextSection();
756 MCA.registerSection(TextSection);
757 MCSection &DataSection = *OFI.getDataSection();
758 MCA.registerSection(DataSection);
759 MCSection &BSSSection = *OFI.getBSSSection();
760 MCA.registerSection(BSSSection);
762 TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
763 DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
764 BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
766 if (RoundSectionSizes) {
767 // Make sections sizes a multiple of the alignment. This is useful for
768 // verifying the output of IAS against the output of other assemblers but
769 // it's not necessary to produce a correct object and increases section
771 MCStreamer &OS = getStreamer();
772 for (MCSection &S : MCA) {
773 MCSectionELF &Section = static_cast<MCSectionELF &>(S);
775 unsigned Alignment = Section.getAlignment();
777 OS.SwitchSection(&Section);
778 if (Section.UseCodeAlign())
779 OS.EmitCodeAlignment(Alignment, Alignment);
781 OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
786 const FeatureBitset &Features = STI.getFeatureBits();
788 // Update e_header flags. See the FIXME and comment above in
789 // the constructor for a full rundown on this.
790 unsigned EFlags = MCA.getELFHeaderEFlags();
793 // N64 does not require any ABI bits.
794 if (getABI().IsO32())
795 EFlags |= ELF::EF_MIPS_ABI_O32;
796 else if (getABI().IsN32())
797 EFlags |= ELF::EF_MIPS_ABI2;
799 if (Features[Mips::FeatureGP64Bit]) {
800 if (getABI().IsO32())
801 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
802 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
803 EFlags |= ELF::EF_MIPS_32BITMODE;
805 // -mplt is not implemented but we should act as if it was
807 if (!Features[Mips::FeatureNoABICalls])
808 EFlags |= ELF::EF_MIPS_CPIC;
811 EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
813 MCA.setELFHeaderEFlags(EFlags);
815 // Emit all the option records.
816 // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
818 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
819 MEF.EmitMipsOptionRecords();
824 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
825 auto *Symbol = cast<MCSymbolELF>(S);
826 // If on rhs is micromips symbol then mark Symbol as microMips.
827 if (Value->getKind() != MCExpr::SymbolRef)
829 const auto &RhsSym = cast<MCSymbolELF>(
830 static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
832 if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
835 Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
838 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
839 return static_cast<MCELFStreamer &>(Streamer);
842 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
843 MicroMipsEnabled = true;
844 forbidModuleDirective();
847 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
848 MicroMipsEnabled = false;
849 forbidModuleDirective();
852 void MipsTargetELFStreamer::setUsesMicroMips() {
853 MCAssembler &MCA = getStreamer().getAssembler();
854 unsigned Flags = MCA.getELFHeaderEFlags();
855 Flags |= ELF::EF_MIPS_MICROMIPS;
856 MCA.setELFHeaderEFlags(Flags);
859 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
860 MCAssembler &MCA = getStreamer().getAssembler();
861 unsigned Flags = MCA.getELFHeaderEFlags();
862 Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
863 MCA.setELFHeaderEFlags(Flags);
864 forbidModuleDirective();
867 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
868 MCAssembler &MCA = getStreamer().getAssembler();
869 unsigned Flags = MCA.getELFHeaderEFlags();
870 Flags |= ELF::EF_MIPS_NOREORDER;
871 MCA.setELFHeaderEFlags(Flags);
872 forbidModuleDirective();
875 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
876 MCAssembler &MCA = getStreamer().getAssembler();
877 MCContext &Context = MCA.getContext();
878 MCStreamer &OS = getStreamer();
880 MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
882 MCSymbol *Sym = Context.getOrCreateSymbol(Name);
883 const MCSymbolRefExpr *ExprRef =
884 MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
886 MCA.registerSection(*Sec);
887 Sec->setAlignment(4);
891 OS.SwitchSection(Sec);
893 OS.EmitValueImpl(ExprRef, 4);
895 OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
896 OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
898 OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
899 OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
901 OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
902 OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
903 OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
905 // The .end directive marks the end of a procedure. Invalidate
906 // the information gathered up until this point.
907 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
911 // .end also implicitly sets the size.
912 MCSymbol *CurPCSym = Context.createTempSymbol();
913 OS.EmitLabel(CurPCSym);
914 const MCExpr *Size = MCBinaryExpr::createSub(
915 MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
918 // The ELFObjectWriter can determine the absolute size as it has access to
919 // the layout information of the assembly file, so a size expression rather
920 // than an absolute value is ok here.
921 static_cast<MCSymbolELF *>(Sym)->setSize(Size);
924 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
925 GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
927 // .ent also acts like an implicit '.type symbol, STT_FUNC'
928 static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
931 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
932 MCAssembler &MCA = getStreamer().getAssembler();
933 unsigned Flags = MCA.getELFHeaderEFlags();
934 Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
935 MCA.setELFHeaderEFlags(Flags);
938 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
939 MCAssembler &MCA = getStreamer().getAssembler();
940 unsigned Flags = MCA.getELFHeaderEFlags();
941 Flags |= ELF::EF_MIPS_NAN2008;
942 MCA.setELFHeaderEFlags(Flags);
945 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
946 MCAssembler &MCA = getStreamer().getAssembler();
947 unsigned Flags = MCA.getELFHeaderEFlags();
948 Flags &= ~ELF::EF_MIPS_NAN2008;
949 MCA.setELFHeaderEFlags(Flags);
952 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
953 MCAssembler &MCA = getStreamer().getAssembler();
954 unsigned Flags = MCA.getELFHeaderEFlags();
955 // This option overrides other PIC options like -KPIC.
957 Flags &= ~ELF::EF_MIPS_PIC;
958 MCA.setELFHeaderEFlags(Flags);
961 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
962 MCAssembler &MCA = getStreamer().getAssembler();
963 unsigned Flags = MCA.getELFHeaderEFlags();
965 // NOTE: We are following the GAS behaviour here which means the directive
966 // 'pic2' also sets the CPIC bit in the ELF header. This is different from
967 // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
968 // EF_MIPS_CPIC to be mutually exclusive.
969 Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
970 MCA.setELFHeaderEFlags(Flags);
973 void MipsTargetELFStreamer::emitDirectiveInsn() {
974 MipsTargetStreamer::emitDirectiveInsn();
975 MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
976 MEF.createPendingLabelRelocs();
979 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
980 unsigned ReturnReg_) {
981 MCContext &Context = getStreamer().getAssembler().getContext();
982 const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
985 FrameReg = RegInfo->getEncodingValue(StackReg);
986 FrameOffset = StackSize;
987 ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
990 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
991 int CPUTopSavedRegOff) {
993 GPRBitMask = CPUBitmask;
994 GPROffset = CPUTopSavedRegOff;
997 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
998 int FPUTopSavedRegOff) {
1000 FPRBitMask = FPUBitmask;
1001 FPROffset = FPUTopSavedRegOff;
1004 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1006 // This directive expands to:
1007 // lui $gp, %hi(_gp_disp)
1008 // addui $gp, $gp, %lo(_gp_disp)
1009 // addu $gp, $gp, $reg
1010 // when support for position independent code is enabled.
1011 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1014 // There's a GNU extension controlled by -mno-shared that allows
1015 // locally-binding symbols to be accessed using absolute addresses.
1016 // This is currently not supported. When supported -mno-shared makes
1017 // .cpload expand to:
1018 // lui $gp, %hi(__gnu_local_gp)
1019 // addiu $gp, $gp, %lo(__gnu_local_gp)
1021 StringRef SymName("_gp_disp");
1022 MCAssembler &MCA = getStreamer().getAssembler();
1023 MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1024 MCA.registerSymbol(*GP_Disp);
1027 TmpInst.setOpcode(Mips::LUi);
1028 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1029 const MCExpr *HiSym = MipsMCExpr::create(
1031 MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1034 TmpInst.addOperand(MCOperand::createExpr(HiSym));
1035 getStreamer().EmitInstruction(TmpInst, STI);
1039 TmpInst.setOpcode(Mips::ADDiu);
1040 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1041 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1042 const MCExpr *LoSym = MipsMCExpr::create(
1044 MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1047 TmpInst.addOperand(MCOperand::createExpr(LoSym));
1048 getStreamer().EmitInstruction(TmpInst, STI);
1052 TmpInst.setOpcode(Mips::ADDu);
1053 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1054 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1055 TmpInst.addOperand(MCOperand::createReg(RegNo));
1056 getStreamer().EmitInstruction(TmpInst, STI);
1058 forbidModuleDirective();
1061 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1062 int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1063 const MCSubtargetInfo *STI) {
1064 MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1065 // .cprestore offset
1066 // When PIC mode is enabled and the O32 ABI is used, this directive expands
1068 // sw $gp, offset($sp)
1069 // and adds a corresponding LW after every JAL.
1071 // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1072 // is used in non-PIC mode.
1073 if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1076 // Store the $gp on the stack.
1077 emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
1082 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1084 const MCSymbol &Sym,
1086 // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1087 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1090 forbidModuleDirective();
1092 MCAssembler &MCA = getStreamer().getAssembler();
1095 // Either store the old $gp in a register or on the stack
1097 // move $save, $gpreg
1098 emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
1100 // sd $gpreg, offset($sp)
1101 emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
1104 if (getABI().IsN32()) {
1105 MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1106 const MipsMCExpr *HiExpr = MipsMCExpr::create(
1107 MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1109 const MipsMCExpr *LoExpr = MipsMCExpr::create(
1110 MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1113 // lui $gp, %hi(__gnu_local_gp)
1114 emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1116 // addiu $gp, $gp, %lo(__gnu_local_gp)
1117 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1123 const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1124 MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1126 const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1127 MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1130 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1131 emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1133 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1134 emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1137 // daddu $gp, $gp, $funcreg
1138 emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
1141 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1142 bool SaveLocationIsRegister) {
1143 // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1144 if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1148 // Either restore the old $gp from a register or on the stack
1149 if (SaveLocationIsRegister) {
1150 Inst.setOpcode(Mips::OR);
1151 Inst.addOperand(MCOperand::createReg(Mips::GP));
1152 Inst.addOperand(MCOperand::createReg(SaveLocation));
1153 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1155 Inst.setOpcode(Mips::LD);
1156 Inst.addOperand(MCOperand::createReg(Mips::GP));
1157 Inst.addOperand(MCOperand::createReg(Mips::SP));
1158 Inst.addOperand(MCOperand::createImm(SaveLocation));
1160 getStreamer().EmitInstruction(Inst, STI);
1162 forbidModuleDirective();
1165 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1166 MCAssembler &MCA = getStreamer().getAssembler();
1167 MCContext &Context = MCA.getContext();
1168 MCStreamer &OS = getStreamer();
1169 MCSectionELF *Sec = Context.getELFSection(
1170 ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1171 MCA.registerSection(*Sec);
1172 Sec->setAlignment(8);
1173 OS.SwitchSection(Sec);
1175 OS << ABIFlagsSection;